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ARM: at91: fix board-rm9200-dt after sys_timer conversion
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_display.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35
36 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
37 {
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
39 struct drm_device *dev = crtc->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 int i;
42
43 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
44 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
45
46 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
47 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
49
50 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
51 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
53
54 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
55 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
56 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
57
58 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
59 for (i = 0; i < 256; i++) {
60 WREG32(AVIVO_DC_LUT_30_COLOR,
61 (radeon_crtc->lut_r[i] << 20) |
62 (radeon_crtc->lut_g[i] << 10) |
63 (radeon_crtc->lut_b[i] << 0));
64 }
65
66 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
67 }
68
69 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
70 {
71 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
72 struct drm_device *dev = crtc->dev;
73 struct radeon_device *rdev = dev->dev_private;
74 int i;
75
76 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
77 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
78
79 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
80 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
82
83 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
84 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
86
87 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
88 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
89
90 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
91 for (i = 0; i < 256; i++) {
92 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
93 (radeon_crtc->lut_r[i] << 20) |
94 (radeon_crtc->lut_g[i] << 10) |
95 (radeon_crtc->lut_b[i] << 0));
96 }
97 }
98
99 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
100 {
101 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
102 struct drm_device *dev = crtc->dev;
103 struct radeon_device *rdev = dev->dev_private;
104 int i;
105
106 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
107
108 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
109 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
110 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
111 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
112 NI_GRPH_PRESCALE_BYPASS);
113 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
114 NI_OVL_PRESCALE_BYPASS);
115 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
116 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
117 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
118
119 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
120
121 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
122 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
124
125 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
126 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
128
129 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
130 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
131
132 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
133 for (i = 0; i < 256; i++) {
134 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
135 (radeon_crtc->lut_r[i] << 20) |
136 (radeon_crtc->lut_g[i] << 10) |
137 (radeon_crtc->lut_b[i] << 0));
138 }
139
140 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
141 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
142 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
143 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
145 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
146 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
147 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
148 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
150 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
151 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
152 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
153 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
154 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
155 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
156
157 }
158
159 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
160 {
161 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
162 struct drm_device *dev = crtc->dev;
163 struct radeon_device *rdev = dev->dev_private;
164 int i;
165 uint32_t dac2_cntl;
166
167 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
168 if (radeon_crtc->crtc_id == 0)
169 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
170 else
171 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
172 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
173
174 WREG8(RADEON_PALETTE_INDEX, 0);
175 for (i = 0; i < 256; i++) {
176 WREG32(RADEON_PALETTE_30_DATA,
177 (radeon_crtc->lut_r[i] << 20) |
178 (radeon_crtc->lut_g[i] << 10) |
179 (radeon_crtc->lut_b[i] << 0));
180 }
181 }
182
183 void radeon_crtc_load_lut(struct drm_crtc *crtc)
184 {
185 struct drm_device *dev = crtc->dev;
186 struct radeon_device *rdev = dev->dev_private;
187
188 if (!crtc->enabled)
189 return;
190
191 if (ASIC_IS_DCE5(rdev))
192 dce5_crtc_load_lut(crtc);
193 else if (ASIC_IS_DCE4(rdev))
194 dce4_crtc_load_lut(crtc);
195 else if (ASIC_IS_AVIVO(rdev))
196 avivo_crtc_load_lut(crtc);
197 else
198 legacy_crtc_load_lut(crtc);
199 }
200
201 /** Sets the color ramps on behalf of fbcon */
202 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
203 u16 blue, int regno)
204 {
205 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
206
207 radeon_crtc->lut_r[regno] = red >> 6;
208 radeon_crtc->lut_g[regno] = green >> 6;
209 radeon_crtc->lut_b[regno] = blue >> 6;
210 }
211
212 /** Gets the color ramps on behalf of fbcon */
213 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
214 u16 *blue, int regno)
215 {
216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
217
218 *red = radeon_crtc->lut_r[regno] << 6;
219 *green = radeon_crtc->lut_g[regno] << 6;
220 *blue = radeon_crtc->lut_b[regno] << 6;
221 }
222
223 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
224 u16 *blue, uint32_t start, uint32_t size)
225 {
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 int end = (start + size > 256) ? 256 : start + size, i;
228
229 /* userspace palettes are always correct as is */
230 for (i = start; i < end; i++) {
231 radeon_crtc->lut_r[i] = red[i] >> 6;
232 radeon_crtc->lut_g[i] = green[i] >> 6;
233 radeon_crtc->lut_b[i] = blue[i] >> 6;
234 }
235 radeon_crtc_load_lut(crtc);
236 }
237
238 static void radeon_crtc_destroy(struct drm_crtc *crtc)
239 {
240 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
241
242 drm_crtc_cleanup(crtc);
243 kfree(radeon_crtc);
244 }
245
246 /*
247 * Handle unpin events outside the interrupt handler proper.
248 */
249 static void radeon_unpin_work_func(struct work_struct *__work)
250 {
251 struct radeon_unpin_work *work =
252 container_of(__work, struct radeon_unpin_work, work);
253 int r;
254
255 /* unpin of the old buffer */
256 r = radeon_bo_reserve(work->old_rbo, false);
257 if (likely(r == 0)) {
258 r = radeon_bo_unpin(work->old_rbo);
259 if (unlikely(r != 0)) {
260 DRM_ERROR("failed to unpin buffer after flip\n");
261 }
262 radeon_bo_unreserve(work->old_rbo);
263 } else
264 DRM_ERROR("failed to reserve buffer after flip\n");
265
266 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
267 kfree(work);
268 }
269
270 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
271 {
272 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
273 struct radeon_unpin_work *work;
274 struct drm_pending_vblank_event *e;
275 struct timeval now;
276 unsigned long flags;
277 u32 update_pending;
278 int vpos, hpos;
279
280 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
281 work = radeon_crtc->unpin_work;
282 if (work == NULL ||
283 (work->fence && !radeon_fence_signaled(work->fence))) {
284 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
285 return;
286 }
287 /* New pageflip, or just completion of a previous one? */
288 if (!radeon_crtc->deferred_flip_completion) {
289 /* do the flip (mmio) */
290 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
291 } else {
292 /* This is just a completion of a flip queued in crtc
293 * at last invocation. Make sure we go directly to
294 * completion routine.
295 */
296 update_pending = 0;
297 radeon_crtc->deferred_flip_completion = 0;
298 }
299
300 /* Has the pageflip already completed in crtc, or is it certain
301 * to complete in this vblank?
302 */
303 if (update_pending &&
304 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
305 &vpos, &hpos)) &&
306 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
307 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
308 /* crtc didn't flip in this target vblank interval,
309 * but flip is pending in crtc. Based on the current
310 * scanout position we know that the current frame is
311 * (nearly) complete and the flip will (likely)
312 * complete before the start of the next frame.
313 */
314 update_pending = 0;
315 }
316 if (update_pending) {
317 /* crtc didn't flip in this target vblank interval,
318 * but flip is pending in crtc. It will complete it
319 * in next vblank interval, so complete the flip at
320 * next vblank irq.
321 */
322 radeon_crtc->deferred_flip_completion = 1;
323 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
324 return;
325 }
326
327 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
328 radeon_crtc->unpin_work = NULL;
329
330 /* wakeup userspace */
331 if (work->event) {
332 e = work->event;
333 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
334 e->event.tv_sec = now.tv_sec;
335 e->event.tv_usec = now.tv_usec;
336 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
337 wake_up_interruptible(&e->base.file_priv->event_wait);
338 }
339 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
340
341 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
342 radeon_fence_unref(&work->fence);
343 radeon_post_page_flip(work->rdev, work->crtc_id);
344 schedule_work(&work->work);
345 }
346
347 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
348 struct drm_framebuffer *fb,
349 struct drm_pending_vblank_event *event)
350 {
351 struct drm_device *dev = crtc->dev;
352 struct radeon_device *rdev = dev->dev_private;
353 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
354 struct radeon_framebuffer *old_radeon_fb;
355 struct radeon_framebuffer *new_radeon_fb;
356 struct drm_gem_object *obj;
357 struct radeon_bo *rbo;
358 struct radeon_unpin_work *work;
359 unsigned long flags;
360 u32 tiling_flags, pitch_pixels;
361 u64 base;
362 int r;
363
364 work = kzalloc(sizeof *work, GFP_KERNEL);
365 if (work == NULL)
366 return -ENOMEM;
367
368 work->event = event;
369 work->rdev = rdev;
370 work->crtc_id = radeon_crtc->crtc_id;
371 old_radeon_fb = to_radeon_framebuffer(crtc->fb);
372 new_radeon_fb = to_radeon_framebuffer(fb);
373 /* schedule unpin of the old buffer */
374 obj = old_radeon_fb->obj;
375 /* take a reference to the old object */
376 drm_gem_object_reference(obj);
377 rbo = gem_to_radeon_bo(obj);
378 work->old_rbo = rbo;
379 obj = new_radeon_fb->obj;
380 rbo = gem_to_radeon_bo(obj);
381
382 spin_lock(&rbo->tbo.bdev->fence_lock);
383 if (rbo->tbo.sync_obj)
384 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
385 spin_unlock(&rbo->tbo.bdev->fence_lock);
386
387 INIT_WORK(&work->work, radeon_unpin_work_func);
388
389 /* We borrow the event spin lock for protecting unpin_work */
390 spin_lock_irqsave(&dev->event_lock, flags);
391 if (radeon_crtc->unpin_work) {
392 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
393 r = -EBUSY;
394 goto unlock_free;
395 }
396 radeon_crtc->unpin_work = work;
397 radeon_crtc->deferred_flip_completion = 0;
398 spin_unlock_irqrestore(&dev->event_lock, flags);
399
400 /* pin the new buffer */
401 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
402 work->old_rbo, rbo);
403
404 r = radeon_bo_reserve(rbo, false);
405 if (unlikely(r != 0)) {
406 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
407 goto pflip_cleanup;
408 }
409 /* Only 27 bit offset for legacy CRTC */
410 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
411 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
412 if (unlikely(r != 0)) {
413 radeon_bo_unreserve(rbo);
414 r = -EINVAL;
415 DRM_ERROR("failed to pin new rbo buffer before flip\n");
416 goto pflip_cleanup;
417 }
418 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
419 radeon_bo_unreserve(rbo);
420
421 if (!ASIC_IS_AVIVO(rdev)) {
422 /* crtc offset is from display base addr not FB location */
423 base -= radeon_crtc->legacy_display_base_addr;
424 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
425
426 if (tiling_flags & RADEON_TILING_MACRO) {
427 if (ASIC_IS_R300(rdev)) {
428 base &= ~0x7ff;
429 } else {
430 int byteshift = fb->bits_per_pixel >> 4;
431 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
432 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
433 }
434 } else {
435 int offset = crtc->y * pitch_pixels + crtc->x;
436 switch (fb->bits_per_pixel) {
437 case 8:
438 default:
439 offset *= 1;
440 break;
441 case 15:
442 case 16:
443 offset *= 2;
444 break;
445 case 24:
446 offset *= 3;
447 break;
448 case 32:
449 offset *= 4;
450 break;
451 }
452 base += offset;
453 }
454 base &= ~7;
455 }
456
457 spin_lock_irqsave(&dev->event_lock, flags);
458 work->new_crtc_base = base;
459 spin_unlock_irqrestore(&dev->event_lock, flags);
460
461 /* update crtc fb */
462 crtc->fb = fb;
463
464 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
465 if (r) {
466 DRM_ERROR("failed to get vblank before flip\n");
467 goto pflip_cleanup1;
468 }
469
470 /* set the proper interrupt */
471 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
472
473 return 0;
474
475 pflip_cleanup1:
476 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
477 DRM_ERROR("failed to reserve new rbo in error path\n");
478 goto pflip_cleanup;
479 }
480 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
481 DRM_ERROR("failed to unpin new rbo in error path\n");
482 }
483 radeon_bo_unreserve(rbo);
484
485 pflip_cleanup:
486 spin_lock_irqsave(&dev->event_lock, flags);
487 radeon_crtc->unpin_work = NULL;
488 unlock_free:
489 spin_unlock_irqrestore(&dev->event_lock, flags);
490 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
491 radeon_fence_unref(&work->fence);
492 kfree(work);
493
494 return r;
495 }
496
497 static const struct drm_crtc_funcs radeon_crtc_funcs = {
498 .cursor_set = radeon_crtc_cursor_set,
499 .cursor_move = radeon_crtc_cursor_move,
500 .gamma_set = radeon_crtc_gamma_set,
501 .set_config = drm_crtc_helper_set_config,
502 .destroy = radeon_crtc_destroy,
503 .page_flip = radeon_crtc_page_flip,
504 };
505
506 static void radeon_crtc_init(struct drm_device *dev, int index)
507 {
508 struct radeon_device *rdev = dev->dev_private;
509 struct radeon_crtc *radeon_crtc;
510 int i;
511
512 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
513 if (radeon_crtc == NULL)
514 return;
515
516 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
517
518 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
519 radeon_crtc->crtc_id = index;
520 rdev->mode_info.crtcs[index] = radeon_crtc;
521
522 #if 0
523 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
524 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
525 radeon_crtc->mode_set.num_connectors = 0;
526 #endif
527
528 for (i = 0; i < 256; i++) {
529 radeon_crtc->lut_r[i] = i << 2;
530 radeon_crtc->lut_g[i] = i << 2;
531 radeon_crtc->lut_b[i] = i << 2;
532 }
533
534 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
535 radeon_atombios_init_crtc(dev, radeon_crtc);
536 else
537 radeon_legacy_init_crtc(dev, radeon_crtc);
538 }
539
540 static const char *encoder_names[37] = {
541 "NONE",
542 "INTERNAL_LVDS",
543 "INTERNAL_TMDS1",
544 "INTERNAL_TMDS2",
545 "INTERNAL_DAC1",
546 "INTERNAL_DAC2",
547 "INTERNAL_SDVOA",
548 "INTERNAL_SDVOB",
549 "SI170B",
550 "CH7303",
551 "CH7301",
552 "INTERNAL_DVO1",
553 "EXTERNAL_SDVOA",
554 "EXTERNAL_SDVOB",
555 "TITFP513",
556 "INTERNAL_LVTM1",
557 "VT1623",
558 "HDMI_SI1930",
559 "HDMI_INTERNAL",
560 "INTERNAL_KLDSCP_TMDS1",
561 "INTERNAL_KLDSCP_DVO1",
562 "INTERNAL_KLDSCP_DAC1",
563 "INTERNAL_KLDSCP_DAC2",
564 "SI178",
565 "MVPU_FPGA",
566 "INTERNAL_DDI",
567 "VT1625",
568 "HDMI_SI1932",
569 "DP_AN9801",
570 "DP_DP501",
571 "INTERNAL_UNIPHY",
572 "INTERNAL_KLDSCP_LVTMA",
573 "INTERNAL_UNIPHY1",
574 "INTERNAL_UNIPHY2",
575 "NUTMEG",
576 "TRAVIS",
577 "INTERNAL_VCE"
578 };
579
580 static const char *hpd_names[6] = {
581 "HPD1",
582 "HPD2",
583 "HPD3",
584 "HPD4",
585 "HPD5",
586 "HPD6",
587 };
588
589 static void radeon_print_display_setup(struct drm_device *dev)
590 {
591 struct drm_connector *connector;
592 struct radeon_connector *radeon_connector;
593 struct drm_encoder *encoder;
594 struct radeon_encoder *radeon_encoder;
595 uint32_t devices;
596 int i = 0;
597
598 DRM_INFO("Radeon Display Connectors\n");
599 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
600 radeon_connector = to_radeon_connector(connector);
601 DRM_INFO("Connector %d:\n", i);
602 DRM_INFO(" %s\n", drm_get_connector_name(connector));
603 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
604 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
605 if (radeon_connector->ddc_bus) {
606 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
607 radeon_connector->ddc_bus->rec.mask_clk_reg,
608 radeon_connector->ddc_bus->rec.mask_data_reg,
609 radeon_connector->ddc_bus->rec.a_clk_reg,
610 radeon_connector->ddc_bus->rec.a_data_reg,
611 radeon_connector->ddc_bus->rec.en_clk_reg,
612 radeon_connector->ddc_bus->rec.en_data_reg,
613 radeon_connector->ddc_bus->rec.y_clk_reg,
614 radeon_connector->ddc_bus->rec.y_data_reg);
615 if (radeon_connector->router.ddc_valid)
616 DRM_INFO(" DDC Router 0x%x/0x%x\n",
617 radeon_connector->router.ddc_mux_control_pin,
618 radeon_connector->router.ddc_mux_state);
619 if (radeon_connector->router.cd_valid)
620 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
621 radeon_connector->router.cd_mux_control_pin,
622 radeon_connector->router.cd_mux_state);
623 } else {
624 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
625 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
626 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
627 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
628 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
629 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
630 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
631 }
632 DRM_INFO(" Encoders:\n");
633 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
634 radeon_encoder = to_radeon_encoder(encoder);
635 devices = radeon_encoder->devices & radeon_connector->devices;
636 if (devices) {
637 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
638 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
639 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
640 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
641 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
642 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
643 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
644 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
645 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
646 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
647 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
648 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
649 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
650 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
651 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
652 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
653 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
654 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
655 if (devices & ATOM_DEVICE_TV1_SUPPORT)
656 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
657 if (devices & ATOM_DEVICE_CV_SUPPORT)
658 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
659 }
660 }
661 i++;
662 }
663 }
664
665 static bool radeon_setup_enc_conn(struct drm_device *dev)
666 {
667 struct radeon_device *rdev = dev->dev_private;
668 bool ret = false;
669
670 if (rdev->bios) {
671 if (rdev->is_atom_bios) {
672 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
673 if (ret == false)
674 ret = radeon_get_atom_connector_info_from_object_table(dev);
675 } else {
676 ret = radeon_get_legacy_connector_info_from_bios(dev);
677 if (ret == false)
678 ret = radeon_get_legacy_connector_info_from_table(dev);
679 }
680 } else {
681 if (!ASIC_IS_AVIVO(rdev))
682 ret = radeon_get_legacy_connector_info_from_table(dev);
683 }
684 if (ret) {
685 radeon_setup_encoder_clones(dev);
686 radeon_print_display_setup(dev);
687 }
688
689 return ret;
690 }
691
692 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
693 {
694 struct drm_device *dev = radeon_connector->base.dev;
695 struct radeon_device *rdev = dev->dev_private;
696 int ret = 0;
697
698 /* on hw with routers, select right port */
699 if (radeon_connector->router.ddc_valid)
700 radeon_router_select_ddc_port(radeon_connector);
701
702 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
703 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) ||
704 (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
705 ENCODER_OBJECT_ID_NONE)) {
706 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
707
708 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
709 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
710 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
711 &dig->dp_i2c_bus->adapter);
712 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
713 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
714 &radeon_connector->ddc_bus->adapter);
715 } else {
716 if (radeon_connector->ddc_bus && !radeon_connector->edid)
717 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
718 &radeon_connector->ddc_bus->adapter);
719 }
720
721 if (!radeon_connector->edid) {
722 if (rdev->is_atom_bios) {
723 /* some laptops provide a hardcoded edid in rom for LCDs */
724 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
725 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
726 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
727 } else
728 /* some servers provide a hardcoded edid in rom for KVMs */
729 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
730 }
731 if (radeon_connector->edid) {
732 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
733 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
734 return ret;
735 }
736 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
737 return 0;
738 }
739
740 /* avivo */
741 static void avivo_get_fb_div(struct radeon_pll *pll,
742 u32 target_clock,
743 u32 post_div,
744 u32 ref_div,
745 u32 *fb_div,
746 u32 *frac_fb_div)
747 {
748 u32 tmp = post_div * ref_div;
749
750 tmp *= target_clock;
751 *fb_div = tmp / pll->reference_freq;
752 *frac_fb_div = tmp % pll->reference_freq;
753
754 if (*fb_div > pll->max_feedback_div)
755 *fb_div = pll->max_feedback_div;
756 else if (*fb_div < pll->min_feedback_div)
757 *fb_div = pll->min_feedback_div;
758 }
759
760 static u32 avivo_get_post_div(struct radeon_pll *pll,
761 u32 target_clock)
762 {
763 u32 vco, post_div, tmp;
764
765 if (pll->flags & RADEON_PLL_USE_POST_DIV)
766 return pll->post_div;
767
768 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
769 if (pll->flags & RADEON_PLL_IS_LCD)
770 vco = pll->lcd_pll_out_min;
771 else
772 vco = pll->pll_out_min;
773 } else {
774 if (pll->flags & RADEON_PLL_IS_LCD)
775 vco = pll->lcd_pll_out_max;
776 else
777 vco = pll->pll_out_max;
778 }
779
780 post_div = vco / target_clock;
781 tmp = vco % target_clock;
782
783 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
784 if (tmp)
785 post_div++;
786 } else {
787 if (!tmp)
788 post_div--;
789 }
790
791 if (post_div > pll->max_post_div)
792 post_div = pll->max_post_div;
793 else if (post_div < pll->min_post_div)
794 post_div = pll->min_post_div;
795
796 return post_div;
797 }
798
799 #define MAX_TOLERANCE 10
800
801 void radeon_compute_pll_avivo(struct radeon_pll *pll,
802 u32 freq,
803 u32 *dot_clock_p,
804 u32 *fb_div_p,
805 u32 *frac_fb_div_p,
806 u32 *ref_div_p,
807 u32 *post_div_p)
808 {
809 u32 target_clock = freq / 10;
810 u32 post_div = avivo_get_post_div(pll, target_clock);
811 u32 ref_div = pll->min_ref_div;
812 u32 fb_div = 0, frac_fb_div = 0, tmp;
813
814 if (pll->flags & RADEON_PLL_USE_REF_DIV)
815 ref_div = pll->reference_div;
816
817 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
818 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
819 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
820 if (frac_fb_div >= 5) {
821 frac_fb_div -= 5;
822 frac_fb_div = frac_fb_div / 10;
823 frac_fb_div++;
824 }
825 if (frac_fb_div >= 10) {
826 fb_div++;
827 frac_fb_div = 0;
828 }
829 } else {
830 while (ref_div <= pll->max_ref_div) {
831 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
832 &fb_div, &frac_fb_div);
833 if (frac_fb_div >= (pll->reference_freq / 2))
834 fb_div++;
835 frac_fb_div = 0;
836 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
837 tmp = (tmp * 10000) / target_clock;
838
839 if (tmp > (10000 + MAX_TOLERANCE))
840 ref_div++;
841 else if (tmp >= (10000 - MAX_TOLERANCE))
842 break;
843 else
844 ref_div++;
845 }
846 }
847
848 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
849 (ref_div * post_div * 10);
850 *fb_div_p = fb_div;
851 *frac_fb_div_p = frac_fb_div;
852 *ref_div_p = ref_div;
853 *post_div_p = post_div;
854 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
855 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
856 }
857
858 /* pre-avivo */
859 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
860 {
861 uint64_t mod;
862
863 n += d / 2;
864
865 mod = do_div(n, d);
866 return n;
867 }
868
869 void radeon_compute_pll_legacy(struct radeon_pll *pll,
870 uint64_t freq,
871 uint32_t *dot_clock_p,
872 uint32_t *fb_div_p,
873 uint32_t *frac_fb_div_p,
874 uint32_t *ref_div_p,
875 uint32_t *post_div_p)
876 {
877 uint32_t min_ref_div = pll->min_ref_div;
878 uint32_t max_ref_div = pll->max_ref_div;
879 uint32_t min_post_div = pll->min_post_div;
880 uint32_t max_post_div = pll->max_post_div;
881 uint32_t min_fractional_feed_div = 0;
882 uint32_t max_fractional_feed_div = 0;
883 uint32_t best_vco = pll->best_vco;
884 uint32_t best_post_div = 1;
885 uint32_t best_ref_div = 1;
886 uint32_t best_feedback_div = 1;
887 uint32_t best_frac_feedback_div = 0;
888 uint32_t best_freq = -1;
889 uint32_t best_error = 0xffffffff;
890 uint32_t best_vco_diff = 1;
891 uint32_t post_div;
892 u32 pll_out_min, pll_out_max;
893
894 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
895 freq = freq * 1000;
896
897 if (pll->flags & RADEON_PLL_IS_LCD) {
898 pll_out_min = pll->lcd_pll_out_min;
899 pll_out_max = pll->lcd_pll_out_max;
900 } else {
901 pll_out_min = pll->pll_out_min;
902 pll_out_max = pll->pll_out_max;
903 }
904
905 if (pll_out_min > 64800)
906 pll_out_min = 64800;
907
908 if (pll->flags & RADEON_PLL_USE_REF_DIV)
909 min_ref_div = max_ref_div = pll->reference_div;
910 else {
911 while (min_ref_div < max_ref_div-1) {
912 uint32_t mid = (min_ref_div + max_ref_div) / 2;
913 uint32_t pll_in = pll->reference_freq / mid;
914 if (pll_in < pll->pll_in_min)
915 max_ref_div = mid;
916 else if (pll_in > pll->pll_in_max)
917 min_ref_div = mid;
918 else
919 break;
920 }
921 }
922
923 if (pll->flags & RADEON_PLL_USE_POST_DIV)
924 min_post_div = max_post_div = pll->post_div;
925
926 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
927 min_fractional_feed_div = pll->min_frac_feedback_div;
928 max_fractional_feed_div = pll->max_frac_feedback_div;
929 }
930
931 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
932 uint32_t ref_div;
933
934 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
935 continue;
936
937 /* legacy radeons only have a few post_divs */
938 if (pll->flags & RADEON_PLL_LEGACY) {
939 if ((post_div == 5) ||
940 (post_div == 7) ||
941 (post_div == 9) ||
942 (post_div == 10) ||
943 (post_div == 11) ||
944 (post_div == 13) ||
945 (post_div == 14) ||
946 (post_div == 15))
947 continue;
948 }
949
950 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
951 uint32_t feedback_div, current_freq = 0, error, vco_diff;
952 uint32_t pll_in = pll->reference_freq / ref_div;
953 uint32_t min_feed_div = pll->min_feedback_div;
954 uint32_t max_feed_div = pll->max_feedback_div + 1;
955
956 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
957 continue;
958
959 while (min_feed_div < max_feed_div) {
960 uint32_t vco;
961 uint32_t min_frac_feed_div = min_fractional_feed_div;
962 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
963 uint32_t frac_feedback_div;
964 uint64_t tmp;
965
966 feedback_div = (min_feed_div + max_feed_div) / 2;
967
968 tmp = (uint64_t)pll->reference_freq * feedback_div;
969 vco = radeon_div(tmp, ref_div);
970
971 if (vco < pll_out_min) {
972 min_feed_div = feedback_div + 1;
973 continue;
974 } else if (vco > pll_out_max) {
975 max_feed_div = feedback_div;
976 continue;
977 }
978
979 while (min_frac_feed_div < max_frac_feed_div) {
980 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
981 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
982 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
983 current_freq = radeon_div(tmp, ref_div * post_div);
984
985 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
986 if (freq < current_freq)
987 error = 0xffffffff;
988 else
989 error = freq - current_freq;
990 } else
991 error = abs(current_freq - freq);
992 vco_diff = abs(vco - best_vco);
993
994 if ((best_vco == 0 && error < best_error) ||
995 (best_vco != 0 &&
996 ((best_error > 100 && error < best_error - 100) ||
997 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
998 best_post_div = post_div;
999 best_ref_div = ref_div;
1000 best_feedback_div = feedback_div;
1001 best_frac_feedback_div = frac_feedback_div;
1002 best_freq = current_freq;
1003 best_error = error;
1004 best_vco_diff = vco_diff;
1005 } else if (current_freq == freq) {
1006 if (best_freq == -1) {
1007 best_post_div = post_div;
1008 best_ref_div = ref_div;
1009 best_feedback_div = feedback_div;
1010 best_frac_feedback_div = frac_feedback_div;
1011 best_freq = current_freq;
1012 best_error = error;
1013 best_vco_diff = vco_diff;
1014 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1015 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1016 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1017 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1018 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1019 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1020 best_post_div = post_div;
1021 best_ref_div = ref_div;
1022 best_feedback_div = feedback_div;
1023 best_frac_feedback_div = frac_feedback_div;
1024 best_freq = current_freq;
1025 best_error = error;
1026 best_vco_diff = vco_diff;
1027 }
1028 }
1029 if (current_freq < freq)
1030 min_frac_feed_div = frac_feedback_div + 1;
1031 else
1032 max_frac_feed_div = frac_feedback_div;
1033 }
1034 if (current_freq < freq)
1035 min_feed_div = feedback_div + 1;
1036 else
1037 max_feed_div = feedback_div;
1038 }
1039 }
1040 }
1041
1042 *dot_clock_p = best_freq / 10000;
1043 *fb_div_p = best_feedback_div;
1044 *frac_fb_div_p = best_frac_feedback_div;
1045 *ref_div_p = best_ref_div;
1046 *post_div_p = best_post_div;
1047 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1048 (long long)freq,
1049 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1050 best_ref_div, best_post_div);
1051
1052 }
1053
1054 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1055 {
1056 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1057
1058 if (radeon_fb->obj) {
1059 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1060 }
1061 drm_framebuffer_cleanup(fb);
1062 kfree(radeon_fb);
1063 }
1064
1065 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1066 struct drm_file *file_priv,
1067 unsigned int *handle)
1068 {
1069 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1070
1071 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1072 }
1073
1074 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1075 .destroy = radeon_user_framebuffer_destroy,
1076 .create_handle = radeon_user_framebuffer_create_handle,
1077 };
1078
1079 int
1080 radeon_framebuffer_init(struct drm_device *dev,
1081 struct radeon_framebuffer *rfb,
1082 struct drm_mode_fb_cmd2 *mode_cmd,
1083 struct drm_gem_object *obj)
1084 {
1085 int ret;
1086 rfb->obj = obj;
1087 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1088 if (ret) {
1089 rfb->obj = NULL;
1090 return ret;
1091 }
1092 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1093 return 0;
1094 }
1095
1096 static struct drm_framebuffer *
1097 radeon_user_framebuffer_create(struct drm_device *dev,
1098 struct drm_file *file_priv,
1099 struct drm_mode_fb_cmd2 *mode_cmd)
1100 {
1101 struct drm_gem_object *obj;
1102 struct radeon_framebuffer *radeon_fb;
1103 int ret;
1104
1105 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1106 if (obj == NULL) {
1107 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1108 "can't create framebuffer\n", mode_cmd->handles[0]);
1109 return ERR_PTR(-ENOENT);
1110 }
1111
1112 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1113 if (radeon_fb == NULL)
1114 return ERR_PTR(-ENOMEM);
1115
1116 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1117 if (ret) {
1118 kfree(radeon_fb);
1119 drm_gem_object_unreference_unlocked(obj);
1120 return NULL;
1121 }
1122
1123 return &radeon_fb->base;
1124 }
1125
1126 static void radeon_output_poll_changed(struct drm_device *dev)
1127 {
1128 struct radeon_device *rdev = dev->dev_private;
1129 radeon_fb_output_poll_changed(rdev);
1130 }
1131
1132 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1133 .fb_create = radeon_user_framebuffer_create,
1134 .output_poll_changed = radeon_output_poll_changed
1135 };
1136
1137 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1138 { { 0, "driver" },
1139 { 1, "bios" },
1140 };
1141
1142 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1143 { { TV_STD_NTSC, "ntsc" },
1144 { TV_STD_PAL, "pal" },
1145 { TV_STD_PAL_M, "pal-m" },
1146 { TV_STD_PAL_60, "pal-60" },
1147 { TV_STD_NTSC_J, "ntsc-j" },
1148 { TV_STD_SCART_PAL, "scart-pal" },
1149 { TV_STD_PAL_CN, "pal-cn" },
1150 { TV_STD_SECAM, "secam" },
1151 };
1152
1153 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1154 { { UNDERSCAN_OFF, "off" },
1155 { UNDERSCAN_ON, "on" },
1156 { UNDERSCAN_AUTO, "auto" },
1157 };
1158
1159 static int radeon_modeset_create_props(struct radeon_device *rdev)
1160 {
1161 int sz;
1162
1163 if (rdev->is_atom_bios) {
1164 rdev->mode_info.coherent_mode_property =
1165 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1166 if (!rdev->mode_info.coherent_mode_property)
1167 return -ENOMEM;
1168 }
1169
1170 if (!ASIC_IS_AVIVO(rdev)) {
1171 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1172 rdev->mode_info.tmds_pll_property =
1173 drm_property_create_enum(rdev->ddev, 0,
1174 "tmds_pll",
1175 radeon_tmds_pll_enum_list, sz);
1176 }
1177
1178 rdev->mode_info.load_detect_property =
1179 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1180 if (!rdev->mode_info.load_detect_property)
1181 return -ENOMEM;
1182
1183 drm_mode_create_scaling_mode_property(rdev->ddev);
1184
1185 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1186 rdev->mode_info.tv_std_property =
1187 drm_property_create_enum(rdev->ddev, 0,
1188 "tv standard",
1189 radeon_tv_std_enum_list, sz);
1190
1191 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1192 rdev->mode_info.underscan_property =
1193 drm_property_create_enum(rdev->ddev, 0,
1194 "underscan",
1195 radeon_underscan_enum_list, sz);
1196
1197 rdev->mode_info.underscan_hborder_property =
1198 drm_property_create_range(rdev->ddev, 0,
1199 "underscan hborder", 0, 128);
1200 if (!rdev->mode_info.underscan_hborder_property)
1201 return -ENOMEM;
1202
1203 rdev->mode_info.underscan_vborder_property =
1204 drm_property_create_range(rdev->ddev, 0,
1205 "underscan vborder", 0, 128);
1206 if (!rdev->mode_info.underscan_vborder_property)
1207 return -ENOMEM;
1208
1209 return 0;
1210 }
1211
1212 void radeon_update_display_priority(struct radeon_device *rdev)
1213 {
1214 /* adjustment options for the display watermarks */
1215 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1216 /* set display priority to high for r3xx, rv515 chips
1217 * this avoids flickering due to underflow to the
1218 * display controllers during heavy acceleration.
1219 * Don't force high on rs4xx igp chips as it seems to
1220 * affect the sound card. See kernel bug 15982.
1221 */
1222 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1223 !(rdev->flags & RADEON_IS_IGP))
1224 rdev->disp_priority = 2;
1225 else
1226 rdev->disp_priority = 0;
1227 } else
1228 rdev->disp_priority = radeon_disp_priority;
1229
1230 }
1231
1232 /*
1233 * Allocate hdmi structs and determine register offsets
1234 */
1235 static void radeon_afmt_init(struct radeon_device *rdev)
1236 {
1237 int i;
1238
1239 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1240 rdev->mode_info.afmt[i] = NULL;
1241
1242 if (ASIC_IS_DCE6(rdev)) {
1243 /* todo */
1244 } else if (ASIC_IS_DCE4(rdev)) {
1245 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1246 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1247 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1248 if (rdev->mode_info.afmt[0]) {
1249 rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1250 rdev->mode_info.afmt[0]->id = 0;
1251 }
1252 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1253 if (rdev->mode_info.afmt[1]) {
1254 rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1255 rdev->mode_info.afmt[1]->id = 1;
1256 }
1257 if (!ASIC_IS_DCE41(rdev)) {
1258 rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1259 if (rdev->mode_info.afmt[2]) {
1260 rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1261 rdev->mode_info.afmt[2]->id = 2;
1262 }
1263 rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1264 if (rdev->mode_info.afmt[3]) {
1265 rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1266 rdev->mode_info.afmt[3]->id = 3;
1267 }
1268 rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1269 if (rdev->mode_info.afmt[4]) {
1270 rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1271 rdev->mode_info.afmt[4]->id = 4;
1272 }
1273 rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1274 if (rdev->mode_info.afmt[5]) {
1275 rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1276 rdev->mode_info.afmt[5]->id = 5;
1277 }
1278 }
1279 } else if (ASIC_IS_DCE3(rdev)) {
1280 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1281 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1282 if (rdev->mode_info.afmt[0]) {
1283 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1284 rdev->mode_info.afmt[0]->id = 0;
1285 }
1286 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1287 if (rdev->mode_info.afmt[1]) {
1288 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1289 rdev->mode_info.afmt[1]->id = 1;
1290 }
1291 } else if (ASIC_IS_DCE2(rdev)) {
1292 /* DCE2 has at least 1 routable audio block */
1293 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1294 if (rdev->mode_info.afmt[0]) {
1295 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1296 rdev->mode_info.afmt[0]->id = 0;
1297 }
1298 /* r6xx has 2 routable audio blocks */
1299 if (rdev->family >= CHIP_R600) {
1300 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1301 if (rdev->mode_info.afmt[1]) {
1302 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1303 rdev->mode_info.afmt[1]->id = 1;
1304 }
1305 }
1306 }
1307 }
1308
1309 static void radeon_afmt_fini(struct radeon_device *rdev)
1310 {
1311 int i;
1312
1313 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1314 kfree(rdev->mode_info.afmt[i]);
1315 rdev->mode_info.afmt[i] = NULL;
1316 }
1317 }
1318
1319 int radeon_modeset_init(struct radeon_device *rdev)
1320 {
1321 int i;
1322 int ret;
1323
1324 drm_mode_config_init(rdev->ddev);
1325 rdev->mode_info.mode_config_initialized = true;
1326
1327 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1328
1329 if (ASIC_IS_DCE5(rdev)) {
1330 rdev->ddev->mode_config.max_width = 16384;
1331 rdev->ddev->mode_config.max_height = 16384;
1332 } else if (ASIC_IS_AVIVO(rdev)) {
1333 rdev->ddev->mode_config.max_width = 8192;
1334 rdev->ddev->mode_config.max_height = 8192;
1335 } else {
1336 rdev->ddev->mode_config.max_width = 4096;
1337 rdev->ddev->mode_config.max_height = 4096;
1338 }
1339
1340 rdev->ddev->mode_config.preferred_depth = 24;
1341 rdev->ddev->mode_config.prefer_shadow = 1;
1342
1343 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1344
1345 ret = radeon_modeset_create_props(rdev);
1346 if (ret) {
1347 return ret;
1348 }
1349
1350 /* init i2c buses */
1351 radeon_i2c_init(rdev);
1352
1353 /* check combios for a valid hardcoded EDID - Sun servers */
1354 if (!rdev->is_atom_bios) {
1355 /* check for hardcoded EDID in BIOS */
1356 radeon_combios_check_hardcoded_edid(rdev);
1357 }
1358
1359 /* allocate crtcs */
1360 for (i = 0; i < rdev->num_crtc; i++) {
1361 radeon_crtc_init(rdev->ddev, i);
1362 }
1363
1364 /* okay we should have all the bios connectors */
1365 ret = radeon_setup_enc_conn(rdev->ddev);
1366 if (!ret) {
1367 return ret;
1368 }
1369
1370 /* init dig PHYs, disp eng pll */
1371 if (rdev->is_atom_bios) {
1372 radeon_atom_encoder_init(rdev);
1373 radeon_atom_disp_eng_pll_init(rdev);
1374 }
1375
1376 /* initialize hpd */
1377 radeon_hpd_init(rdev);
1378
1379 /* setup afmt */
1380 radeon_afmt_init(rdev);
1381
1382 /* Initialize power management */
1383 radeon_pm_init(rdev);
1384
1385 radeon_fbdev_init(rdev);
1386 drm_kms_helper_poll_init(rdev->ddev);
1387
1388 return 0;
1389 }
1390
1391 void radeon_modeset_fini(struct radeon_device *rdev)
1392 {
1393 radeon_fbdev_fini(rdev);
1394 kfree(rdev->mode_info.bios_hardcoded_edid);
1395 radeon_pm_fini(rdev);
1396
1397 if (rdev->mode_info.mode_config_initialized) {
1398 radeon_afmt_fini(rdev);
1399 drm_kms_helper_poll_fini(rdev->ddev);
1400 radeon_hpd_fini(rdev);
1401 drm_mode_config_cleanup(rdev->ddev);
1402 rdev->mode_info.mode_config_initialized = false;
1403 }
1404 /* free i2c buses */
1405 radeon_i2c_fini(rdev);
1406 }
1407
1408 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1409 {
1410 /* try and guess if this is a tv or a monitor */
1411 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1412 (mode->vdisplay == 576) || /* 576p */
1413 (mode->vdisplay == 720) || /* 720p */
1414 (mode->vdisplay == 1080)) /* 1080p */
1415 return true;
1416 else
1417 return false;
1418 }
1419
1420 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1421 const struct drm_display_mode *mode,
1422 struct drm_display_mode *adjusted_mode)
1423 {
1424 struct drm_device *dev = crtc->dev;
1425 struct radeon_device *rdev = dev->dev_private;
1426 struct drm_encoder *encoder;
1427 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1428 struct radeon_encoder *radeon_encoder;
1429 struct drm_connector *connector;
1430 struct radeon_connector *radeon_connector;
1431 bool first = true;
1432 u32 src_v = 1, dst_v = 1;
1433 u32 src_h = 1, dst_h = 1;
1434
1435 radeon_crtc->h_border = 0;
1436 radeon_crtc->v_border = 0;
1437
1438 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1439 if (encoder->crtc != crtc)
1440 continue;
1441 radeon_encoder = to_radeon_encoder(encoder);
1442 connector = radeon_get_connector_for_encoder(encoder);
1443 radeon_connector = to_radeon_connector(connector);
1444
1445 if (first) {
1446 /* set scaling */
1447 if (radeon_encoder->rmx_type == RMX_OFF)
1448 radeon_crtc->rmx_type = RMX_OFF;
1449 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1450 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1451 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1452 else
1453 radeon_crtc->rmx_type = RMX_OFF;
1454 /* copy native mode */
1455 memcpy(&radeon_crtc->native_mode,
1456 &radeon_encoder->native_mode,
1457 sizeof(struct drm_display_mode));
1458 src_v = crtc->mode.vdisplay;
1459 dst_v = radeon_crtc->native_mode.vdisplay;
1460 src_h = crtc->mode.hdisplay;
1461 dst_h = radeon_crtc->native_mode.hdisplay;
1462
1463 /* fix up for overscan on hdmi */
1464 if (ASIC_IS_AVIVO(rdev) &&
1465 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1466 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1467 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1468 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1469 is_hdtv_mode(mode)))) {
1470 if (radeon_encoder->underscan_hborder != 0)
1471 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1472 else
1473 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1474 if (radeon_encoder->underscan_vborder != 0)
1475 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1476 else
1477 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1478 radeon_crtc->rmx_type = RMX_FULL;
1479 src_v = crtc->mode.vdisplay;
1480 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1481 src_h = crtc->mode.hdisplay;
1482 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1483 }
1484 first = false;
1485 } else {
1486 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1487 /* WARNING: Right now this can't happen but
1488 * in the future we need to check that scaling
1489 * are consistent across different encoder
1490 * (ie all encoder can work with the same
1491 * scaling).
1492 */
1493 DRM_ERROR("Scaling not consistent across encoder.\n");
1494 return false;
1495 }
1496 }
1497 }
1498 if (radeon_crtc->rmx_type != RMX_OFF) {
1499 fixed20_12 a, b;
1500 a.full = dfixed_const(src_v);
1501 b.full = dfixed_const(dst_v);
1502 radeon_crtc->vsc.full = dfixed_div(a, b);
1503 a.full = dfixed_const(src_h);
1504 b.full = dfixed_const(dst_h);
1505 radeon_crtc->hsc.full = dfixed_div(a, b);
1506 } else {
1507 radeon_crtc->vsc.full = dfixed_const(1);
1508 radeon_crtc->hsc.full = dfixed_const(1);
1509 }
1510 return true;
1511 }
1512
1513 /*
1514 * Retrieve current video scanout position of crtc on a given gpu.
1515 *
1516 * \param dev Device to query.
1517 * \param crtc Crtc to query.
1518 * \param *vpos Location where vertical scanout position should be stored.
1519 * \param *hpos Location where horizontal scanout position should go.
1520 *
1521 * Returns vpos as a positive number while in active scanout area.
1522 * Returns vpos as a negative number inside vblank, counting the number
1523 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1524 * until start of active scanout / end of vblank."
1525 *
1526 * \return Flags, or'ed together as follows:
1527 *
1528 * DRM_SCANOUTPOS_VALID = Query successful.
1529 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1530 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1531 * this flag means that returned position may be offset by a constant but
1532 * unknown small number of scanlines wrt. real scanout position.
1533 *
1534 */
1535 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1536 {
1537 u32 stat_crtc = 0, vbl = 0, position = 0;
1538 int vbl_start, vbl_end, vtotal, ret = 0;
1539 bool in_vbl = true;
1540
1541 struct radeon_device *rdev = dev->dev_private;
1542
1543 if (ASIC_IS_DCE4(rdev)) {
1544 if (crtc == 0) {
1545 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1546 EVERGREEN_CRTC0_REGISTER_OFFSET);
1547 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1548 EVERGREEN_CRTC0_REGISTER_OFFSET);
1549 ret |= DRM_SCANOUTPOS_VALID;
1550 }
1551 if (crtc == 1) {
1552 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1553 EVERGREEN_CRTC1_REGISTER_OFFSET);
1554 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1555 EVERGREEN_CRTC1_REGISTER_OFFSET);
1556 ret |= DRM_SCANOUTPOS_VALID;
1557 }
1558 if (crtc == 2) {
1559 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1560 EVERGREEN_CRTC2_REGISTER_OFFSET);
1561 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1562 EVERGREEN_CRTC2_REGISTER_OFFSET);
1563 ret |= DRM_SCANOUTPOS_VALID;
1564 }
1565 if (crtc == 3) {
1566 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1567 EVERGREEN_CRTC3_REGISTER_OFFSET);
1568 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1569 EVERGREEN_CRTC3_REGISTER_OFFSET);
1570 ret |= DRM_SCANOUTPOS_VALID;
1571 }
1572 if (crtc == 4) {
1573 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1574 EVERGREEN_CRTC4_REGISTER_OFFSET);
1575 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1576 EVERGREEN_CRTC4_REGISTER_OFFSET);
1577 ret |= DRM_SCANOUTPOS_VALID;
1578 }
1579 if (crtc == 5) {
1580 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1581 EVERGREEN_CRTC5_REGISTER_OFFSET);
1582 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1583 EVERGREEN_CRTC5_REGISTER_OFFSET);
1584 ret |= DRM_SCANOUTPOS_VALID;
1585 }
1586 } else if (ASIC_IS_AVIVO(rdev)) {
1587 if (crtc == 0) {
1588 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1589 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1590 ret |= DRM_SCANOUTPOS_VALID;
1591 }
1592 if (crtc == 1) {
1593 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1594 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1595 ret |= DRM_SCANOUTPOS_VALID;
1596 }
1597 } else {
1598 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1599 if (crtc == 0) {
1600 /* Assume vbl_end == 0, get vbl_start from
1601 * upper 16 bits.
1602 */
1603 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1604 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1605 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1606 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1607 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1608 if (!(stat_crtc & 1))
1609 in_vbl = false;
1610
1611 ret |= DRM_SCANOUTPOS_VALID;
1612 }
1613 if (crtc == 1) {
1614 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1615 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1616 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1617 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1618 if (!(stat_crtc & 1))
1619 in_vbl = false;
1620
1621 ret |= DRM_SCANOUTPOS_VALID;
1622 }
1623 }
1624
1625 /* Decode into vertical and horizontal scanout position. */
1626 *vpos = position & 0x1fff;
1627 *hpos = (position >> 16) & 0x1fff;
1628
1629 /* Valid vblank area boundaries from gpu retrieved? */
1630 if (vbl > 0) {
1631 /* Yes: Decode. */
1632 ret |= DRM_SCANOUTPOS_ACCURATE;
1633 vbl_start = vbl & 0x1fff;
1634 vbl_end = (vbl >> 16) & 0x1fff;
1635 }
1636 else {
1637 /* No: Fake something reasonable which gives at least ok results. */
1638 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1639 vbl_end = 0;
1640 }
1641
1642 /* Test scanout position against vblank region. */
1643 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1644 in_vbl = false;
1645
1646 /* Check if inside vblank area and apply corrective offsets:
1647 * vpos will then be >=0 in video scanout area, but negative
1648 * within vblank area, counting down the number of lines until
1649 * start of scanout.
1650 */
1651
1652 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1653 if (in_vbl && (*vpos >= vbl_start)) {
1654 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1655 *vpos = *vpos - vtotal;
1656 }
1657
1658 /* Correct for shifted end of vbl at vbl_end. */
1659 *vpos = *vpos - vbl_end;
1660
1661 /* In vblank? */
1662 if (in_vbl)
1663 ret |= DRM_SCANOUTPOS_INVBL;
1664
1665 return ret;
1666 }
kernel source for telekom puls (alcatel/mediatek)