2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/console.h>
29 #include <linux/slab.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/vgaarb.h>
35 #include <linux/vga_switcheroo.h>
36 #include <linux/efi.h>
37 #include "radeon_reg.h"
41 static const char radeon_family_name
[][16] = {
107 #if defined(CONFIG_VGA_SWITCHEROO)
108 bool radeon_has_atpx_dgpu_power_cntl(void);
109 bool radeon_is_atpx_hybrid(void);
111 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
112 static inline bool radeon_is_atpx_hybrid(void) { return false; }
115 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
117 struct radeon_px_quirk
{
125 static struct radeon_px_quirk radeon_px_quirk_list
[] = {
126 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
127 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
129 { PCI_VENDOR_ID_ATI
, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX
},
130 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
131 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
133 { PCI_VENDOR_ID_ATI
, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX
},
134 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
135 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
137 { PCI_VENDOR_ID_ATI
, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX
},
138 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
139 * https://bugs.freedesktop.org/show_bug.cgi?id=101491
141 { PCI_VENDOR_ID_ATI
, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX
},
142 /* Asus K73TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
143 * https://bugzilla.kernel.org/show_bug.cgi?id=51381#c52
145 { PCI_VENDOR_ID_ATI
, 0x6840, 0x1043, 0x2123, RADEON_PX_QUIRK_DISABLE_PX
},
149 bool radeon_is_px(struct drm_device
*dev
)
151 struct radeon_device
*rdev
= dev
->dev_private
;
153 if (rdev
->flags
& RADEON_IS_PX
)
158 static void radeon_device_handle_px_quirks(struct radeon_device
*rdev
)
160 struct radeon_px_quirk
*p
= radeon_px_quirk_list
;
162 /* Apply PX quirks */
163 while (p
&& p
->chip_device
!= 0) {
164 if (rdev
->pdev
->vendor
== p
->chip_vendor
&&
165 rdev
->pdev
->device
== p
->chip_device
&&
166 rdev
->pdev
->subsystem_vendor
== p
->subsys_vendor
&&
167 rdev
->pdev
->subsystem_device
== p
->subsys_device
) {
168 rdev
->px_quirk_flags
= p
->px_quirk_flags
;
174 if (rdev
->px_quirk_flags
& RADEON_PX_QUIRK_DISABLE_PX
)
175 rdev
->flags
&= ~RADEON_IS_PX
;
177 /* disable PX is the system doesn't support dGPU power control or hybrid gfx */
178 if (!radeon_is_atpx_hybrid() &&
179 !radeon_has_atpx_dgpu_power_cntl())
180 rdev
->flags
&= ~RADEON_IS_PX
;
184 * radeon_program_register_sequence - program an array of registers.
186 * @rdev: radeon_device pointer
187 * @registers: pointer to the register array
188 * @array_size: size of the register array
190 * Programs an array or registers with and and or masks.
191 * This is a helper for setting golden registers.
193 void radeon_program_register_sequence(struct radeon_device
*rdev
,
194 const u32
*registers
,
195 const u32 array_size
)
197 u32 tmp
, reg
, and_mask
, or_mask
;
203 for (i
= 0; i
< array_size
; i
+=3) {
204 reg
= registers
[i
+ 0];
205 and_mask
= registers
[i
+ 1];
206 or_mask
= registers
[i
+ 2];
208 if (and_mask
== 0xffffffff) {
219 void radeon_pci_config_reset(struct radeon_device
*rdev
)
221 pci_write_config_dword(rdev
->pdev
, 0x7c, RADEON_ASIC_RESET_DATA
);
225 * radeon_surface_init - Clear GPU surface registers.
227 * @rdev: radeon_device pointer
229 * Clear GPU surface registers (r1xx-r5xx).
231 void radeon_surface_init(struct radeon_device
*rdev
)
233 /* FIXME: check this out */
234 if (rdev
->family
< CHIP_R600
) {
237 for (i
= 0; i
< RADEON_GEM_MAX_SURFACES
; i
++) {
238 if (rdev
->surface_regs
[i
].bo
)
239 radeon_bo_get_surface_reg(rdev
->surface_regs
[i
].bo
);
241 radeon_clear_surface_reg(rdev
, i
);
243 /* enable surfaces */
244 WREG32(RADEON_SURFACE_CNTL
, 0);
249 * GPU scratch registers helpers function.
252 * radeon_scratch_init - Init scratch register driver information.
254 * @rdev: radeon_device pointer
256 * Init CP scratch register driver information (r1xx-r5xx)
258 void radeon_scratch_init(struct radeon_device
*rdev
)
262 /* FIXME: check this out */
263 if (rdev
->family
< CHIP_R300
) {
264 rdev
->scratch
.num_reg
= 5;
266 rdev
->scratch
.num_reg
= 7;
268 rdev
->scratch
.reg_base
= RADEON_SCRATCH_REG0
;
269 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
270 rdev
->scratch
.free
[i
] = true;
271 rdev
->scratch
.reg
[i
] = rdev
->scratch
.reg_base
+ (i
* 4);
276 * radeon_scratch_get - Allocate a scratch register
278 * @rdev: radeon_device pointer
279 * @reg: scratch register mmio offset
281 * Allocate a CP scratch register for use by the driver (all asics).
282 * Returns 0 on success or -EINVAL on failure.
284 int radeon_scratch_get(struct radeon_device
*rdev
, uint32_t *reg
)
288 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
289 if (rdev
->scratch
.free
[i
]) {
290 rdev
->scratch
.free
[i
] = false;
291 *reg
= rdev
->scratch
.reg
[i
];
299 * radeon_scratch_free - Free a scratch register
301 * @rdev: radeon_device pointer
302 * @reg: scratch register mmio offset
304 * Free a CP scratch register allocated for use by the driver (all asics)
306 void radeon_scratch_free(struct radeon_device
*rdev
, uint32_t reg
)
310 for (i
= 0; i
< rdev
->scratch
.num_reg
; i
++) {
311 if (rdev
->scratch
.reg
[i
] == reg
) {
312 rdev
->scratch
.free
[i
] = true;
319 * GPU doorbell aperture helpers function.
322 * radeon_doorbell_init - Init doorbell driver information.
324 * @rdev: radeon_device pointer
326 * Init doorbell driver information (CIK)
327 * Returns 0 on success, error on failure.
329 static int radeon_doorbell_init(struct radeon_device
*rdev
)
331 /* doorbell bar mapping */
332 rdev
->doorbell
.base
= pci_resource_start(rdev
->pdev
, 2);
333 rdev
->doorbell
.size
= pci_resource_len(rdev
->pdev
, 2);
335 rdev
->doorbell
.num_doorbells
= min_t(u32
, rdev
->doorbell
.size
/ sizeof(u32
), RADEON_MAX_DOORBELLS
);
336 if (rdev
->doorbell
.num_doorbells
== 0)
339 rdev
->doorbell
.ptr
= ioremap(rdev
->doorbell
.base
, rdev
->doorbell
.num_doorbells
* sizeof(u32
));
340 if (rdev
->doorbell
.ptr
== NULL
) {
343 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev
->doorbell
.base
);
344 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev
->doorbell
.size
);
346 memset(&rdev
->doorbell
.used
, 0, sizeof(rdev
->doorbell
.used
));
352 * radeon_doorbell_fini - Tear down doorbell driver information.
354 * @rdev: radeon_device pointer
356 * Tear down doorbell driver information (CIK)
358 static void radeon_doorbell_fini(struct radeon_device
*rdev
)
360 iounmap(rdev
->doorbell
.ptr
);
361 rdev
->doorbell
.ptr
= NULL
;
365 * radeon_doorbell_get - Allocate a doorbell entry
367 * @rdev: radeon_device pointer
368 * @doorbell: doorbell index
370 * Allocate a doorbell for use by the driver (all asics).
371 * Returns 0 on success or -EINVAL on failure.
373 int radeon_doorbell_get(struct radeon_device
*rdev
, u32
*doorbell
)
375 unsigned long offset
= find_first_zero_bit(rdev
->doorbell
.used
, rdev
->doorbell
.num_doorbells
);
376 if (offset
< rdev
->doorbell
.num_doorbells
) {
377 __set_bit(offset
, rdev
->doorbell
.used
);
386 * radeon_doorbell_free - Free a doorbell entry
388 * @rdev: radeon_device pointer
389 * @doorbell: doorbell index
391 * Free a doorbell allocated for use by the driver (all asics)
393 void radeon_doorbell_free(struct radeon_device
*rdev
, u32 doorbell
)
395 if (doorbell
< rdev
->doorbell
.num_doorbells
)
396 __clear_bit(doorbell
, rdev
->doorbell
.used
);
400 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to
403 * @rdev: radeon_device pointer
404 * @aperture_base: output returning doorbell aperture base physical address
405 * @aperture_size: output returning doorbell aperture size in bytes
406 * @start_offset: output returning # of doorbell bytes reserved for radeon.
408 * Radeon and the KFD share the doorbell aperture. Radeon sets it up,
409 * takes doorbells required for its own rings and reports the setup to KFD.
410 * Radeon reserved doorbells are at the start of the doorbell aperture.
412 void radeon_doorbell_get_kfd_info(struct radeon_device
*rdev
,
413 phys_addr_t
*aperture_base
,
414 size_t *aperture_size
,
415 size_t *start_offset
)
417 /* The first num_doorbells are used by radeon.
418 * KFD takes whatever's left in the aperture. */
419 if (rdev
->doorbell
.size
> rdev
->doorbell
.num_doorbells
* sizeof(u32
)) {
420 *aperture_base
= rdev
->doorbell
.base
;
421 *aperture_size
= rdev
->doorbell
.size
;
422 *start_offset
= rdev
->doorbell
.num_doorbells
* sizeof(u32
);
432 * Writeback is the the method by which the the GPU updates special pages
433 * in memory with the status of certain GPU events (fences, ring pointers,
438 * radeon_wb_disable - Disable Writeback
440 * @rdev: radeon_device pointer
442 * Disables Writeback (all asics). Used for suspend.
444 void radeon_wb_disable(struct radeon_device
*rdev
)
446 rdev
->wb
.enabled
= false;
450 * radeon_wb_fini - Disable Writeback and free memory
452 * @rdev: radeon_device pointer
454 * Disables Writeback and frees the Writeback memory (all asics).
455 * Used at driver shutdown.
457 void radeon_wb_fini(struct radeon_device
*rdev
)
459 radeon_wb_disable(rdev
);
460 if (rdev
->wb
.wb_obj
) {
461 if (!radeon_bo_reserve(rdev
->wb
.wb_obj
, false)) {
462 radeon_bo_kunmap(rdev
->wb
.wb_obj
);
463 radeon_bo_unpin(rdev
->wb
.wb_obj
);
464 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
466 radeon_bo_unref(&rdev
->wb
.wb_obj
);
468 rdev
->wb
.wb_obj
= NULL
;
473 * radeon_wb_init- Init Writeback driver info and allocate memory
475 * @rdev: radeon_device pointer
477 * Disables Writeback and frees the Writeback memory (all asics).
478 * Used at driver startup.
479 * Returns 0 on success or an -error on failure.
481 int radeon_wb_init(struct radeon_device
*rdev
)
485 if (rdev
->wb
.wb_obj
== NULL
) {
486 r
= radeon_bo_create(rdev
, RADEON_GPU_PAGE_SIZE
, PAGE_SIZE
, true,
487 RADEON_GEM_DOMAIN_GTT
, 0, NULL
, NULL
,
490 dev_warn(rdev
->dev
, "(%d) create WB bo failed\n", r
);
493 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
494 if (unlikely(r
!= 0)) {
495 radeon_wb_fini(rdev
);
498 r
= radeon_bo_pin(rdev
->wb
.wb_obj
, RADEON_GEM_DOMAIN_GTT
,
501 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
502 dev_warn(rdev
->dev
, "(%d) pin WB bo failed\n", r
);
503 radeon_wb_fini(rdev
);
506 r
= radeon_bo_kmap(rdev
->wb
.wb_obj
, (void **)&rdev
->wb
.wb
);
507 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
509 dev_warn(rdev
->dev
, "(%d) map WB bo failed\n", r
);
510 radeon_wb_fini(rdev
);
515 /* clear wb memory */
516 memset((char *)rdev
->wb
.wb
, 0, RADEON_GPU_PAGE_SIZE
);
517 /* disable event_write fences */
518 rdev
->wb
.use_event
= false;
519 /* disabled via module param */
520 if (radeon_no_wb
== 1) {
521 rdev
->wb
.enabled
= false;
523 if (rdev
->flags
& RADEON_IS_AGP
) {
524 /* often unreliable on AGP */
525 rdev
->wb
.enabled
= false;
526 } else if (rdev
->family
< CHIP_R300
) {
527 /* often unreliable on pre-r300 */
528 rdev
->wb
.enabled
= false;
530 rdev
->wb
.enabled
= true;
531 /* event_write fences are only available on r600+ */
532 if (rdev
->family
>= CHIP_R600
) {
533 rdev
->wb
.use_event
= true;
537 /* always use writeback/events on NI, APUs */
538 if (rdev
->family
>= CHIP_PALM
) {
539 rdev
->wb
.enabled
= true;
540 rdev
->wb
.use_event
= true;
543 dev_info(rdev
->dev
, "WB %sabled\n", rdev
->wb
.enabled
? "en" : "dis");
549 * radeon_vram_location - try to find VRAM location
550 * @rdev: radeon device structure holding all necessary informations
551 * @mc: memory controller structure holding memory informations
552 * @base: base address at which to put VRAM
554 * Function will place try to place VRAM at base address provided
555 * as parameter (which is so far either PCI aperture address or
556 * for IGP TOM base address).
558 * If there is not enough space to fit the unvisible VRAM in the 32bits
559 * address space then we limit the VRAM size to the aperture.
561 * If we are using AGP and if the AGP aperture doesn't allow us to have
562 * room for all the VRAM than we restrict the VRAM to the PCI aperture
563 * size and print a warning.
565 * This function will never fails, worst case are limiting VRAM.
567 * Note: GTT start, end, size should be initialized before calling this
568 * function on AGP platform.
570 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
571 * this shouldn't be a problem as we are using the PCI aperture as a reference.
572 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
575 * Note: we use mc_vram_size as on some board we need to program the mc to
576 * cover the whole aperture even if VRAM size is inferior to aperture size
577 * Novell bug 204882 + along with lots of ubuntu ones
579 * Note: when limiting vram it's safe to overwritte real_vram_size because
580 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
581 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
584 * Note: IGP TOM addr should be the same as the aperture addr, we don't
585 * explicitly check for that thought.
587 * FIXME: when reducing VRAM size align new size on power of 2.
589 void radeon_vram_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
, u64 base
)
591 uint64_t limit
= (uint64_t)radeon_vram_limit
<< 20;
593 mc
->vram_start
= base
;
594 if (mc
->mc_vram_size
> (rdev
->mc
.mc_mask
- base
+ 1)) {
595 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
596 mc
->real_vram_size
= mc
->aper_size
;
597 mc
->mc_vram_size
= mc
->aper_size
;
599 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
600 if (rdev
->flags
& RADEON_IS_AGP
&& mc
->vram_end
> mc
->gtt_start
&& mc
->vram_start
<= mc
->gtt_end
) {
601 dev_warn(rdev
->dev
, "limiting VRAM to PCI aperture size\n");
602 mc
->real_vram_size
= mc
->aper_size
;
603 mc
->mc_vram_size
= mc
->aper_size
;
605 mc
->vram_end
= mc
->vram_start
+ mc
->mc_vram_size
- 1;
606 if (limit
&& limit
< mc
->real_vram_size
)
607 mc
->real_vram_size
= limit
;
608 dev_info(rdev
->dev
, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
609 mc
->mc_vram_size
>> 20, mc
->vram_start
,
610 mc
->vram_end
, mc
->real_vram_size
>> 20);
614 * radeon_gtt_location - try to find GTT location
615 * @rdev: radeon device structure holding all necessary informations
616 * @mc: memory controller structure holding memory informations
618 * Function will place try to place GTT before or after VRAM.
620 * If GTT size is bigger than space left then we ajust GTT size.
621 * Thus function will never fails.
623 * FIXME: when reducing GTT size align new size on power of 2.
625 void radeon_gtt_location(struct radeon_device
*rdev
, struct radeon_mc
*mc
)
627 u64 size_af
, size_bf
;
629 size_af
= ((rdev
->mc
.mc_mask
- mc
->vram_end
) + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
630 size_bf
= mc
->vram_start
& ~mc
->gtt_base_align
;
631 if (size_bf
> size_af
) {
632 if (mc
->gtt_size
> size_bf
) {
633 dev_warn(rdev
->dev
, "limiting GTT\n");
634 mc
->gtt_size
= size_bf
;
636 mc
->gtt_start
= (mc
->vram_start
& ~mc
->gtt_base_align
) - mc
->gtt_size
;
638 if (mc
->gtt_size
> size_af
) {
639 dev_warn(rdev
->dev
, "limiting GTT\n");
640 mc
->gtt_size
= size_af
;
642 mc
->gtt_start
= (mc
->vram_end
+ 1 + mc
->gtt_base_align
) & ~mc
->gtt_base_align
;
644 mc
->gtt_end
= mc
->gtt_start
+ mc
->gtt_size
- 1;
645 dev_info(rdev
->dev
, "GTT: %lluM 0x%016llX - 0x%016llX\n",
646 mc
->gtt_size
>> 20, mc
->gtt_start
, mc
->gtt_end
);
650 * GPU helpers function.
654 * radeon_device_is_virtual - check if we are running is a virtual environment
656 * Check if the asic has been passed through to a VM (all asics).
657 * Used at driver startup.
658 * Returns true if virtual or false if not.
660 bool radeon_device_is_virtual(void)
663 return boot_cpu_has(X86_FEATURE_HYPERVISOR
);
670 * radeon_card_posted - check if the hw has already been initialized
672 * @rdev: radeon_device pointer
674 * Check if the asic has been initialized (all asics).
675 * Used at driver startup.
676 * Returns true if initialized or false if not.
678 bool radeon_card_posted(struct radeon_device
*rdev
)
682 /* for pass through, always force asic_init for CI */
683 if (rdev
->family
>= CHIP_BONAIRE
&&
684 radeon_device_is_virtual())
687 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
688 if (efi_enabled(EFI_BOOT
) &&
689 (rdev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
) &&
690 (rdev
->family
< CHIP_R600
))
693 if (ASIC_IS_NODCE(rdev
))
696 /* first check CRTCs */
697 if (ASIC_IS_DCE4(rdev
)) {
698 reg
= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET
) |
699 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC1_REGISTER_OFFSET
);
700 if (rdev
->num_crtc
>= 4) {
701 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC2_REGISTER_OFFSET
) |
702 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC3_REGISTER_OFFSET
);
704 if (rdev
->num_crtc
>= 6) {
705 reg
|= RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC4_REGISTER_OFFSET
) |
706 RREG32(EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC5_REGISTER_OFFSET
);
708 if (reg
& EVERGREEN_CRTC_MASTER_EN
)
710 } else if (ASIC_IS_AVIVO(rdev
)) {
711 reg
= RREG32(AVIVO_D1CRTC_CONTROL
) |
712 RREG32(AVIVO_D2CRTC_CONTROL
);
713 if (reg
& AVIVO_CRTC_EN
) {
717 reg
= RREG32(RADEON_CRTC_GEN_CNTL
) |
718 RREG32(RADEON_CRTC2_GEN_CNTL
);
719 if (reg
& RADEON_CRTC_EN
) {
725 /* then check MEM_SIZE, in case the crtcs are off */
726 if (rdev
->family
>= CHIP_R600
)
727 reg
= RREG32(R600_CONFIG_MEMSIZE
);
729 reg
= RREG32(RADEON_CONFIG_MEMSIZE
);
739 * radeon_update_bandwidth_info - update display bandwidth params
741 * @rdev: radeon_device pointer
743 * Used when sclk/mclk are switched or display modes are set.
744 * params are used to calculate display watermarks (all asics)
746 void radeon_update_bandwidth_info(struct radeon_device
*rdev
)
749 u32 sclk
= rdev
->pm
.current_sclk
;
750 u32 mclk
= rdev
->pm
.current_mclk
;
752 /* sclk/mclk in Mhz */
753 a
.full
= dfixed_const(100);
754 rdev
->pm
.sclk
.full
= dfixed_const(sclk
);
755 rdev
->pm
.sclk
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
756 rdev
->pm
.mclk
.full
= dfixed_const(mclk
);
757 rdev
->pm
.mclk
.full
= dfixed_div(rdev
->pm
.mclk
, a
);
759 if (rdev
->flags
& RADEON_IS_IGP
) {
760 a
.full
= dfixed_const(16);
761 /* core_bandwidth = sclk(Mhz) * 16 */
762 rdev
->pm
.core_bandwidth
.full
= dfixed_div(rdev
->pm
.sclk
, a
);
767 * radeon_boot_test_post_card - check and possibly initialize the hw
769 * @rdev: radeon_device pointer
771 * Check if the asic is initialized and if not, attempt to initialize
773 * Returns true if initialized or false if not.
775 bool radeon_boot_test_post_card(struct radeon_device
*rdev
)
777 if (radeon_card_posted(rdev
))
781 DRM_INFO("GPU not posted. posting now...\n");
782 if (rdev
->is_atom_bios
)
783 atom_asic_init(rdev
->mode_info
.atom_context
);
785 radeon_combios_asic_init(rdev
->ddev
);
788 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
794 * radeon_dummy_page_init - init dummy page used by the driver
796 * @rdev: radeon_device pointer
798 * Allocate the dummy page used by the driver (all asics).
799 * This dummy page is used by the driver as a filler for gart entries
800 * when pages are taken out of the GART
801 * Returns 0 on sucess, -ENOMEM on failure.
803 int radeon_dummy_page_init(struct radeon_device
*rdev
)
805 if (rdev
->dummy_page
.page
)
807 rdev
->dummy_page
.page
= alloc_page(GFP_DMA32
| GFP_KERNEL
| __GFP_ZERO
);
808 if (rdev
->dummy_page
.page
== NULL
)
810 rdev
->dummy_page
.addr
= pci_map_page(rdev
->pdev
, rdev
->dummy_page
.page
,
811 0, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
812 if (pci_dma_mapping_error(rdev
->pdev
, rdev
->dummy_page
.addr
)) {
813 dev_err(&rdev
->pdev
->dev
, "Failed to DMA MAP the dummy page\n");
814 __free_page(rdev
->dummy_page
.page
);
815 rdev
->dummy_page
.page
= NULL
;
818 rdev
->dummy_page
.entry
= radeon_gart_get_page_entry(rdev
->dummy_page
.addr
,
819 RADEON_GART_PAGE_DUMMY
);
824 * radeon_dummy_page_fini - free dummy page used by the driver
826 * @rdev: radeon_device pointer
828 * Frees the dummy page used by the driver (all asics).
830 void radeon_dummy_page_fini(struct radeon_device
*rdev
)
832 if (rdev
->dummy_page
.page
== NULL
)
834 pci_unmap_page(rdev
->pdev
, rdev
->dummy_page
.addr
,
835 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
836 __free_page(rdev
->dummy_page
.page
);
837 rdev
->dummy_page
.page
= NULL
;
841 /* ATOM accessor methods */
843 * ATOM is an interpreted byte code stored in tables in the vbios. The
844 * driver registers callbacks to access registers and the interpreter
845 * in the driver parses the tables and executes then to program specific
846 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
847 * atombios.h, and atom.c
851 * cail_pll_read - read PLL register
853 * @info: atom card_info pointer
854 * @reg: PLL register offset
856 * Provides a PLL register accessor for the atom interpreter (r4xx+).
857 * Returns the value of the PLL register.
859 static uint32_t cail_pll_read(struct card_info
*info
, uint32_t reg
)
861 struct radeon_device
*rdev
= info
->dev
->dev_private
;
864 r
= rdev
->pll_rreg(rdev
, reg
);
869 * cail_pll_write - write PLL register
871 * @info: atom card_info pointer
872 * @reg: PLL register offset
873 * @val: value to write to the pll register
875 * Provides a PLL register accessor for the atom interpreter (r4xx+).
877 static void cail_pll_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
879 struct radeon_device
*rdev
= info
->dev
->dev_private
;
881 rdev
->pll_wreg(rdev
, reg
, val
);
885 * cail_mc_read - read MC (Memory Controller) register
887 * @info: atom card_info pointer
888 * @reg: MC register offset
890 * Provides an MC register accessor for the atom interpreter (r4xx+).
891 * Returns the value of the MC register.
893 static uint32_t cail_mc_read(struct card_info
*info
, uint32_t reg
)
895 struct radeon_device
*rdev
= info
->dev
->dev_private
;
898 r
= rdev
->mc_rreg(rdev
, reg
);
903 * cail_mc_write - write MC (Memory Controller) register
905 * @info: atom card_info pointer
906 * @reg: MC register offset
907 * @val: value to write to the pll register
909 * Provides a MC register accessor for the atom interpreter (r4xx+).
911 static void cail_mc_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
913 struct radeon_device
*rdev
= info
->dev
->dev_private
;
915 rdev
->mc_wreg(rdev
, reg
, val
);
919 * cail_reg_write - write MMIO register
921 * @info: atom card_info pointer
922 * @reg: MMIO register offset
923 * @val: value to write to the pll register
925 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
927 static void cail_reg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
929 struct radeon_device
*rdev
= info
->dev
->dev_private
;
935 * cail_reg_read - read MMIO register
937 * @info: atom card_info pointer
938 * @reg: MMIO register offset
940 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
941 * Returns the value of the MMIO register.
943 static uint32_t cail_reg_read(struct card_info
*info
, uint32_t reg
)
945 struct radeon_device
*rdev
= info
->dev
->dev_private
;
953 * cail_ioreg_write - write IO register
955 * @info: atom card_info pointer
956 * @reg: IO register offset
957 * @val: value to write to the pll register
959 * Provides a IO register accessor for the atom interpreter (r4xx+).
961 static void cail_ioreg_write(struct card_info
*info
, uint32_t reg
, uint32_t val
)
963 struct radeon_device
*rdev
= info
->dev
->dev_private
;
965 WREG32_IO(reg
*4, val
);
969 * cail_ioreg_read - read IO register
971 * @info: atom card_info pointer
972 * @reg: IO register offset
974 * Provides an IO register accessor for the atom interpreter (r4xx+).
975 * Returns the value of the IO register.
977 static uint32_t cail_ioreg_read(struct card_info
*info
, uint32_t reg
)
979 struct radeon_device
*rdev
= info
->dev
->dev_private
;
982 r
= RREG32_IO(reg
*4);
987 * radeon_atombios_init - init the driver info and callbacks for atombios
989 * @rdev: radeon_device pointer
991 * Initializes the driver info and register access callbacks for the
992 * ATOM interpreter (r4xx+).
993 * Returns 0 on sucess, -ENOMEM on failure.
994 * Called at driver startup.
996 int radeon_atombios_init(struct radeon_device
*rdev
)
998 struct card_info
*atom_card_info
=
999 kzalloc(sizeof(struct card_info
), GFP_KERNEL
);
1001 if (!atom_card_info
)
1004 rdev
->mode_info
.atom_card_info
= atom_card_info
;
1005 atom_card_info
->dev
= rdev
->ddev
;
1006 atom_card_info
->reg_read
= cail_reg_read
;
1007 atom_card_info
->reg_write
= cail_reg_write
;
1008 /* needed for iio ops */
1009 if (rdev
->rio_mem
) {
1010 atom_card_info
->ioreg_read
= cail_ioreg_read
;
1011 atom_card_info
->ioreg_write
= cail_ioreg_write
;
1013 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
1014 atom_card_info
->ioreg_read
= cail_reg_read
;
1015 atom_card_info
->ioreg_write
= cail_reg_write
;
1017 atom_card_info
->mc_read
= cail_mc_read
;
1018 atom_card_info
->mc_write
= cail_mc_write
;
1019 atom_card_info
->pll_read
= cail_pll_read
;
1020 atom_card_info
->pll_write
= cail_pll_write
;
1022 rdev
->mode_info
.atom_context
= atom_parse(atom_card_info
, rdev
->bios
);
1023 if (!rdev
->mode_info
.atom_context
) {
1024 radeon_atombios_fini(rdev
);
1028 mutex_init(&rdev
->mode_info
.atom_context
->mutex
);
1029 mutex_init(&rdev
->mode_info
.atom_context
->scratch_mutex
);
1030 radeon_atom_initialize_bios_scratch_regs(rdev
->ddev
);
1031 atom_allocate_fb_scratch(rdev
->mode_info
.atom_context
);
1036 * radeon_atombios_fini - free the driver info and callbacks for atombios
1038 * @rdev: radeon_device pointer
1040 * Frees the driver info and register access callbacks for the ATOM
1041 * interpreter (r4xx+).
1042 * Called at driver shutdown.
1044 void radeon_atombios_fini(struct radeon_device
*rdev
)
1046 if (rdev
->mode_info
.atom_context
) {
1047 kfree(rdev
->mode_info
.atom_context
->scratch
);
1049 kfree(rdev
->mode_info
.atom_context
);
1050 rdev
->mode_info
.atom_context
= NULL
;
1051 kfree(rdev
->mode_info
.atom_card_info
);
1052 rdev
->mode_info
.atom_card_info
= NULL
;
1057 * COMBIOS is the bios format prior to ATOM. It provides
1058 * command tables similar to ATOM, but doesn't have a unified
1059 * parser. See radeon_combios.c
1063 * radeon_combios_init - init the driver info for combios
1065 * @rdev: radeon_device pointer
1067 * Initializes the driver info for combios (r1xx-r3xx).
1068 * Returns 0 on sucess.
1069 * Called at driver startup.
1071 int radeon_combios_init(struct radeon_device
*rdev
)
1073 radeon_combios_initialize_bios_scratch_regs(rdev
->ddev
);
1078 * radeon_combios_fini - free the driver info for combios
1080 * @rdev: radeon_device pointer
1082 * Frees the driver info for combios (r1xx-r3xx).
1083 * Called at driver shutdown.
1085 void radeon_combios_fini(struct radeon_device
*rdev
)
1089 /* if we get transitioned to only one device, take VGA back */
1091 * radeon_vga_set_decode - enable/disable vga decode
1093 * @cookie: radeon_device pointer
1094 * @state: enable/disable vga decode
1096 * Enable/disable vga decode (all asics).
1097 * Returns VGA resource flags.
1099 static unsigned int radeon_vga_set_decode(void *cookie
, bool state
)
1101 struct radeon_device
*rdev
= cookie
;
1102 radeon_vga_set_state(rdev
, state
);
1104 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1105 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1107 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1111 * radeon_check_pot_argument - check that argument is a power of two
1113 * @arg: value to check
1115 * Validates that a certain argument is a power of two (all asics).
1116 * Returns true if argument is valid.
1118 static bool radeon_check_pot_argument(int arg
)
1120 return (arg
& (arg
- 1)) == 0;
1124 * Determine a sensible default GART size according to ASIC family.
1126 * @family ASIC family name
1128 static int radeon_gart_size_auto(enum radeon_family family
)
1130 /* default to a larger gart size on newer asics */
1131 if (family
>= CHIP_TAHITI
)
1133 else if (family
>= CHIP_RV770
)
1140 * radeon_check_arguments - validate module params
1142 * @rdev: radeon_device pointer
1144 * Validates certain module parameters and updates
1145 * the associated values used by the driver (all asics).
1147 static void radeon_check_arguments(struct radeon_device
*rdev
)
1149 /* vramlimit must be a power of two */
1150 if (!radeon_check_pot_argument(radeon_vram_limit
)) {
1151 dev_warn(rdev
->dev
, "vram limit (%d) must be a power of 2\n",
1153 radeon_vram_limit
= 0;
1156 if (radeon_gart_size
== -1) {
1157 radeon_gart_size
= radeon_gart_size_auto(rdev
->family
);
1159 /* gtt size must be power of two and greater or equal to 32M */
1160 if (radeon_gart_size
< 32) {
1161 dev_warn(rdev
->dev
, "gart size (%d) too small\n",
1163 radeon_gart_size
= radeon_gart_size_auto(rdev
->family
);
1164 } else if (!radeon_check_pot_argument(radeon_gart_size
)) {
1165 dev_warn(rdev
->dev
, "gart size (%d) must be a power of 2\n",
1167 radeon_gart_size
= radeon_gart_size_auto(rdev
->family
);
1169 rdev
->mc
.gtt_size
= (uint64_t)radeon_gart_size
<< 20;
1171 /* AGP mode can only be -1, 1, 2, 4, 8 */
1172 switch (radeon_agpmode
) {
1181 dev_warn(rdev
->dev
, "invalid AGP mode %d (valid mode: "
1182 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode
);
1187 if (!radeon_check_pot_argument(radeon_vm_size
)) {
1188 dev_warn(rdev
->dev
, "VM size (%d) must be a power of 2\n",
1193 if (radeon_vm_size
< 1) {
1194 dev_warn(rdev
->dev
, "VM size (%d) too small, min is 1GB\n",
1200 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1202 if (radeon_vm_size
> 1024) {
1203 dev_warn(rdev
->dev
, "VM size (%d) too large, max is 1TB\n",
1208 /* defines number of bits in page table versus page directory,
1209 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1210 * page table and the remaining bits are in the page directory */
1211 if (radeon_vm_block_size
== -1) {
1213 /* Total bits covered by PD + PTs */
1214 unsigned bits
= ilog2(radeon_vm_size
) + 18;
1216 /* Make sure the PD is 4K in size up to 8GB address space.
1217 Above that split equal between PD and PTs */
1218 if (radeon_vm_size
<= 8)
1219 radeon_vm_block_size
= bits
- 9;
1221 radeon_vm_block_size
= (bits
+ 3) / 2;
1223 } else if (radeon_vm_block_size
< 9) {
1224 dev_warn(rdev
->dev
, "VM page table size (%d) too small\n",
1225 radeon_vm_block_size
);
1226 radeon_vm_block_size
= 9;
1229 if (radeon_vm_block_size
> 24 ||
1230 (radeon_vm_size
* 1024) < (1ull << radeon_vm_block_size
)) {
1231 dev_warn(rdev
->dev
, "VM page table size (%d) too large\n",
1232 radeon_vm_block_size
);
1233 radeon_vm_block_size
= 9;
1238 * radeon_switcheroo_set_state - set switcheroo state
1240 * @pdev: pci dev pointer
1241 * @state: vga_switcheroo state
1243 * Callback for the switcheroo driver. Suspends or resumes the
1244 * the asics before or after it is powered up using ACPI methods.
1246 static void radeon_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1248 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1250 if (radeon_is_px(dev
) && state
== VGA_SWITCHEROO_OFF
)
1253 if (state
== VGA_SWITCHEROO_ON
) {
1254 pr_info("radeon: switched on\n");
1255 /* don't suspend or resume card normally */
1256 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1258 radeon_resume_kms(dev
, true, true);
1260 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1261 drm_kms_helper_poll_enable(dev
);
1263 pr_info("radeon: switched off\n");
1264 drm_kms_helper_poll_disable(dev
);
1265 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1266 radeon_suspend_kms(dev
, true, true, false);
1267 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1272 * radeon_switcheroo_can_switch - see if switcheroo state can change
1274 * @pdev: pci dev pointer
1276 * Callback for the switcheroo driver. Check of the switcheroo
1277 * state can be changed.
1278 * Returns true if the state can be changed, false if not.
1280 static bool radeon_switcheroo_can_switch(struct pci_dev
*pdev
)
1282 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1285 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1286 * locking inversion with the driver load path. And the access here is
1287 * completely racy anyway. So don't bother with locking for now.
1289 return dev
->open_count
== 0;
1292 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops
= {
1293 .set_gpu_state
= radeon_switcheroo_set_state
,
1295 .can_switch
= radeon_switcheroo_can_switch
,
1299 * radeon_device_init - initialize the driver
1301 * @rdev: radeon_device pointer
1302 * @pdev: drm dev pointer
1303 * @pdev: pci dev pointer
1304 * @flags: driver flags
1306 * Initializes the driver info and hw (all asics).
1307 * Returns 0 for success or an error on failure.
1308 * Called at driver startup.
1310 int radeon_device_init(struct radeon_device
*rdev
,
1311 struct drm_device
*ddev
,
1312 struct pci_dev
*pdev
,
1317 bool runtime
= false;
1319 rdev
->shutdown
= false;
1320 rdev
->dev
= &pdev
->dev
;
1323 rdev
->flags
= flags
;
1324 rdev
->family
= flags
& RADEON_FAMILY_MASK
;
1325 rdev
->is_atom_bios
= false;
1326 rdev
->usec_timeout
= RADEON_MAX_USEC_TIMEOUT
;
1327 rdev
->mc
.gtt_size
= 512 * 1024 * 1024;
1328 rdev
->accel_working
= false;
1329 /* set up ring ids */
1330 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1331 rdev
->ring
[i
].idx
= i
;
1333 rdev
->fence_context
= dma_fence_context_alloc(RADEON_NUM_RINGS
);
1335 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1336 radeon_family_name
[rdev
->family
], pdev
->vendor
, pdev
->device
,
1337 pdev
->subsystem_vendor
, pdev
->subsystem_device
, pdev
->revision
);
1339 /* mutex initialization are all done here so we
1340 * can recall function without having locking issues */
1341 mutex_init(&rdev
->ring_lock
);
1342 mutex_init(&rdev
->dc_hw_i2c_mutex
);
1343 atomic_set(&rdev
->ih
.lock
, 0);
1344 mutex_init(&rdev
->gem
.mutex
);
1345 mutex_init(&rdev
->pm
.mutex
);
1346 mutex_init(&rdev
->gpu_clock_mutex
);
1347 mutex_init(&rdev
->srbm_mutex
);
1348 mutex_init(&rdev
->grbm_idx_mutex
);
1349 init_rwsem(&rdev
->pm
.mclk_lock
);
1350 init_rwsem(&rdev
->exclusive_lock
);
1351 init_waitqueue_head(&rdev
->irq
.vblank_queue
);
1352 mutex_init(&rdev
->mn_lock
);
1353 hash_init(rdev
->mn_hash
);
1354 r
= radeon_gem_init(rdev
);
1358 radeon_check_arguments(rdev
);
1359 /* Adjust VM size here.
1360 * Max GPUVM size for cayman+ is 40 bits.
1362 rdev
->vm_manager
.max_pfn
= radeon_vm_size
<< 18;
1364 /* Set asic functions */
1365 r
= radeon_asic_init(rdev
);
1369 /* all of the newer IGP chips have an internal gart
1370 * However some rs4xx report as AGP, so remove that here.
1372 if ((rdev
->family
>= CHIP_RS400
) &&
1373 (rdev
->flags
& RADEON_IS_IGP
)) {
1374 rdev
->flags
&= ~RADEON_IS_AGP
;
1377 if (rdev
->flags
& RADEON_IS_AGP
&& radeon_agpmode
== -1) {
1378 radeon_agp_disable(rdev
);
1381 /* Set the internal MC address mask
1382 * This is the max address of the GPU's
1383 * internal address space.
1385 if (rdev
->family
>= CHIP_CAYMAN
)
1386 rdev
->mc
.mc_mask
= 0xffffffffffULL
; /* 40 bit MC */
1387 else if (rdev
->family
>= CHIP_CEDAR
)
1388 rdev
->mc
.mc_mask
= 0xfffffffffULL
; /* 36 bit MC */
1390 rdev
->mc
.mc_mask
= 0xffffffffULL
; /* 32 bit MC */
1392 /* set DMA mask + need_dma32 flags.
1393 * PCIE - can handle 40-bits.
1394 * IGP - can handle 40-bits
1395 * AGP - generally dma32 is safest
1396 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1398 rdev
->need_dma32
= false;
1399 if (rdev
->flags
& RADEON_IS_AGP
)
1400 rdev
->need_dma32
= true;
1401 if ((rdev
->flags
& RADEON_IS_PCI
) &&
1402 (rdev
->family
<= CHIP_RS740
))
1403 rdev
->need_dma32
= true;
1405 if (rdev
->family
== CHIP_CEDAR
)
1406 rdev
->need_dma32
= true;
1409 dma_bits
= rdev
->need_dma32
? 32 : 40;
1410 r
= pci_set_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1412 rdev
->need_dma32
= true;
1414 pr_warn("radeon: No suitable DMA available\n");
1416 r
= pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(dma_bits
));
1418 pci_set_consistent_dma_mask(rdev
->pdev
, DMA_BIT_MASK(32));
1419 pr_warn("radeon: No coherent DMA available\n");
1422 /* Registers mapping */
1423 /* TODO: block userspace mapping of io register */
1424 spin_lock_init(&rdev
->mmio_idx_lock
);
1425 spin_lock_init(&rdev
->smc_idx_lock
);
1426 spin_lock_init(&rdev
->pll_idx_lock
);
1427 spin_lock_init(&rdev
->mc_idx_lock
);
1428 spin_lock_init(&rdev
->pcie_idx_lock
);
1429 spin_lock_init(&rdev
->pciep_idx_lock
);
1430 spin_lock_init(&rdev
->pif_idx_lock
);
1431 spin_lock_init(&rdev
->cg_idx_lock
);
1432 spin_lock_init(&rdev
->uvd_idx_lock
);
1433 spin_lock_init(&rdev
->rcu_idx_lock
);
1434 spin_lock_init(&rdev
->didt_idx_lock
);
1435 spin_lock_init(&rdev
->end_idx_lock
);
1436 if (rdev
->family
>= CHIP_BONAIRE
) {
1437 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 5);
1438 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 5);
1440 rdev
->rmmio_base
= pci_resource_start(rdev
->pdev
, 2);
1441 rdev
->rmmio_size
= pci_resource_len(rdev
->pdev
, 2);
1443 rdev
->rmmio
= ioremap(rdev
->rmmio_base
, rdev
->rmmio_size
);
1444 if (rdev
->rmmio
== NULL
)
1447 /* doorbell bar mapping */
1448 if (rdev
->family
>= CHIP_BONAIRE
)
1449 radeon_doorbell_init(rdev
);
1451 /* io port mapping */
1452 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1453 if (pci_resource_flags(rdev
->pdev
, i
) & IORESOURCE_IO
) {
1454 rdev
->rio_mem_size
= pci_resource_len(rdev
->pdev
, i
);
1455 rdev
->rio_mem
= pci_iomap(rdev
->pdev
, i
, rdev
->rio_mem_size
);
1459 if (rdev
->rio_mem
== NULL
)
1460 DRM_ERROR("Unable to find PCI I/O BAR\n");
1462 if (rdev
->flags
& RADEON_IS_PX
)
1463 radeon_device_handle_px_quirks(rdev
);
1465 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1466 /* this will fail for cards that aren't VGA class devices, just
1468 vga_client_register(rdev
->pdev
, rdev
, NULL
, radeon_vga_set_decode
);
1470 if (rdev
->flags
& RADEON_IS_PX
)
1472 if (!pci_is_thunderbolt_attached(rdev
->pdev
))
1473 vga_switcheroo_register_client(rdev
->pdev
,
1474 &radeon_switcheroo_ops
, runtime
);
1476 vga_switcheroo_init_domain_pm_ops(rdev
->dev
, &rdev
->vga_pm_domain
);
1478 r
= radeon_init(rdev
);
1482 r
= radeon_gem_debugfs_init(rdev
);
1484 DRM_ERROR("registering gem debugfs failed (%d).\n", r
);
1487 r
= radeon_mst_debugfs_init(rdev
);
1489 DRM_ERROR("registering mst debugfs failed (%d).\n", r
);
1492 if (rdev
->flags
& RADEON_IS_AGP
&& !rdev
->accel_working
) {
1493 /* Acceleration not working on AGP card try again
1494 * with fallback to PCI or PCIE GART
1496 radeon_asic_reset(rdev
);
1498 radeon_agp_disable(rdev
);
1499 r
= radeon_init(rdev
);
1504 r
= radeon_ib_ring_tests(rdev
);
1506 DRM_ERROR("ib ring test failed (%d).\n", r
);
1509 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
1510 * after the CP ring have chew one packet at least. Hence here we stop
1511 * and restart DPM after the radeon_ib_ring_tests().
1513 if (rdev
->pm
.dpm_enabled
&&
1514 (rdev
->pm
.pm_method
== PM_METHOD_DPM
) &&
1515 (rdev
->family
== CHIP_TURKS
) &&
1516 (rdev
->flags
& RADEON_IS_MOBILITY
)) {
1517 mutex_lock(&rdev
->pm
.mutex
);
1518 radeon_dpm_disable(rdev
);
1519 radeon_dpm_enable(rdev
);
1520 mutex_unlock(&rdev
->pm
.mutex
);
1523 if ((radeon_testing
& 1)) {
1524 if (rdev
->accel_working
)
1525 radeon_test_moves(rdev
);
1527 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1529 if ((radeon_testing
& 2)) {
1530 if (rdev
->accel_working
)
1531 radeon_test_syncing(rdev
);
1533 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1535 if (radeon_benchmarking
) {
1536 if (rdev
->accel_working
)
1537 radeon_benchmark(rdev
, radeon_benchmarking
);
1539 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1544 /* balance pm_runtime_get_sync() in radeon_driver_unload_kms() */
1545 if (radeon_is_px(ddev
))
1546 pm_runtime_put_noidle(ddev
->dev
);
1548 vga_switcheroo_fini_domain_pm_ops(rdev
->dev
);
1553 * radeon_device_fini - tear down the driver
1555 * @rdev: radeon_device pointer
1557 * Tear down the driver info (all asics).
1558 * Called at driver shutdown.
1560 void radeon_device_fini(struct radeon_device
*rdev
)
1562 DRM_INFO("radeon: finishing device.\n");
1563 rdev
->shutdown
= true;
1564 /* evict vram memory */
1565 radeon_bo_evict_vram(rdev
);
1567 if (!pci_is_thunderbolt_attached(rdev
->pdev
))
1568 vga_switcheroo_unregister_client(rdev
->pdev
);
1569 if (rdev
->flags
& RADEON_IS_PX
)
1570 vga_switcheroo_fini_domain_pm_ops(rdev
->dev
);
1571 vga_client_register(rdev
->pdev
, NULL
, NULL
, NULL
);
1573 pci_iounmap(rdev
->pdev
, rdev
->rio_mem
);
1574 rdev
->rio_mem
= NULL
;
1575 iounmap(rdev
->rmmio
);
1577 if (rdev
->family
>= CHIP_BONAIRE
)
1578 radeon_doorbell_fini(rdev
);
1586 * radeon_suspend_kms - initiate device suspend
1588 * @pdev: drm dev pointer
1589 * @state: suspend state
1591 * Puts the hw in the suspend state (all asics).
1592 * Returns 0 for success or an error on failure.
1593 * Called at driver suspend.
1595 int radeon_suspend_kms(struct drm_device
*dev
, bool suspend
,
1596 bool fbcon
, bool freeze
)
1598 struct radeon_device
*rdev
;
1599 struct drm_crtc
*crtc
;
1600 struct drm_connector
*connector
;
1603 if (dev
== NULL
|| dev
->dev_private
== NULL
) {
1607 rdev
= dev
->dev_private
;
1609 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1612 drm_kms_helper_poll_disable(dev
);
1614 drm_modeset_lock_all(dev
);
1615 /* turn off display hw */
1616 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1617 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
1619 drm_modeset_unlock_all(dev
);
1621 /* unpin the front buffers and cursors */
1622 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1623 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1624 struct radeon_framebuffer
*rfb
= to_radeon_framebuffer(crtc
->primary
->fb
);
1625 struct radeon_bo
*robj
;
1627 if (radeon_crtc
->cursor_bo
) {
1628 struct radeon_bo
*robj
= gem_to_radeon_bo(radeon_crtc
->cursor_bo
);
1629 r
= radeon_bo_reserve(robj
, false);
1631 radeon_bo_unpin(robj
);
1632 radeon_bo_unreserve(robj
);
1636 if (rfb
== NULL
|| rfb
->obj
== NULL
) {
1639 robj
= gem_to_radeon_bo(rfb
->obj
);
1640 /* don't unpin kernel fb objects */
1641 if (!radeon_fbdev_robj_is_fb(rdev
, robj
)) {
1642 r
= radeon_bo_reserve(robj
, false);
1644 radeon_bo_unpin(robj
);
1645 radeon_bo_unreserve(robj
);
1649 /* evict vram memory */
1650 radeon_bo_evict_vram(rdev
);
1652 /* wait for gpu to finish processing current batch */
1653 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1654 r
= radeon_fence_wait_empty(rdev
, i
);
1656 /* delay GPU reset to resume */
1657 radeon_fence_driver_force_completion(rdev
, i
);
1661 radeon_save_bios_scratch_regs(rdev
);
1663 radeon_suspend(rdev
);
1664 radeon_hpd_fini(rdev
);
1665 /* evict remaining vram memory
1666 * This second call to evict vram is to evict the gart page table
1669 radeon_bo_evict_vram(rdev
);
1671 radeon_agp_suspend(rdev
);
1673 pci_save_state(dev
->pdev
);
1674 if (freeze
&& rdev
->family
>= CHIP_CEDAR
&& !(rdev
->flags
& RADEON_IS_IGP
)) {
1675 rdev
->asic
->asic_reset(rdev
, true);
1676 pci_restore_state(dev
->pdev
);
1677 } else if (suspend
) {
1678 /* Shut down the device */
1679 pci_disable_device(dev
->pdev
);
1680 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
1685 radeon_fbdev_set_suspend(rdev
, 1);
1692 * radeon_resume_kms - initiate device resume
1694 * @pdev: drm dev pointer
1696 * Bring the hw back to operating state (all asics).
1697 * Returns 0 for success or an error on failure.
1698 * Called at driver resume.
1700 int radeon_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
)
1702 struct drm_connector
*connector
;
1703 struct radeon_device
*rdev
= dev
->dev_private
;
1704 struct drm_crtc
*crtc
;
1707 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1714 pci_set_power_state(dev
->pdev
, PCI_D0
);
1715 pci_restore_state(dev
->pdev
);
1716 if (pci_enable_device(dev
->pdev
)) {
1722 /* resume AGP if in use */
1723 radeon_agp_resume(rdev
);
1724 radeon_resume(rdev
);
1726 r
= radeon_ib_ring_tests(rdev
);
1728 DRM_ERROR("ib ring test failed (%d).\n", r
);
1730 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
1731 /* do dpm late init */
1732 r
= radeon_pm_late_init(rdev
);
1734 rdev
->pm
.dpm_enabled
= false;
1735 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1738 /* resume old pm late */
1739 radeon_pm_resume(rdev
);
1742 radeon_restore_bios_scratch_regs(rdev
);
1745 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1746 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(crtc
);
1748 if (radeon_crtc
->cursor_bo
) {
1749 struct radeon_bo
*robj
= gem_to_radeon_bo(radeon_crtc
->cursor_bo
);
1750 r
= radeon_bo_reserve(robj
, false);
1752 /* Only 27 bit offset for legacy cursor */
1753 r
= radeon_bo_pin_restricted(robj
,
1754 RADEON_GEM_DOMAIN_VRAM
,
1755 ASIC_IS_AVIVO(rdev
) ?
1757 &radeon_crtc
->cursor_addr
);
1759 DRM_ERROR("Failed to pin cursor BO (%d)\n", r
);
1760 radeon_bo_unreserve(robj
);
1765 /* init dig PHYs, disp eng pll */
1766 if (rdev
->is_atom_bios
) {
1767 radeon_atom_encoder_init(rdev
);
1768 radeon_atom_disp_eng_pll_init(rdev
);
1769 /* turn on the BL */
1770 if (rdev
->mode_info
.bl_encoder
) {
1771 u8 bl_level
= radeon_get_backlight_level(rdev
,
1772 rdev
->mode_info
.bl_encoder
);
1773 radeon_set_backlight_level(rdev
, rdev
->mode_info
.bl_encoder
,
1777 /* reset hpd state */
1778 radeon_hpd_init(rdev
);
1779 /* blat the mode back in */
1781 drm_helper_resume_force_mode(dev
);
1782 /* turn on display hw */
1783 drm_modeset_lock_all(dev
);
1784 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1785 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
1787 drm_modeset_unlock_all(dev
);
1790 drm_kms_helper_poll_enable(dev
);
1792 /* set the power state here in case we are a PX system or headless */
1793 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
)
1794 radeon_pm_compute_clocks(rdev
);
1797 radeon_fbdev_set_suspend(rdev
, 0);
1805 * radeon_gpu_reset - reset the asic
1807 * @rdev: radeon device pointer
1809 * Attempt the reset the GPU if it has hung (all asics).
1810 * Returns 0 for success or an error on failure.
1812 int radeon_gpu_reset(struct radeon_device
*rdev
)
1814 unsigned ring_sizes
[RADEON_NUM_RINGS
];
1815 uint32_t *ring_data
[RADEON_NUM_RINGS
];
1822 down_write(&rdev
->exclusive_lock
);
1824 if (!rdev
->needs_reset
) {
1825 up_write(&rdev
->exclusive_lock
);
1829 atomic_inc(&rdev
->gpu_reset_counter
);
1831 radeon_save_bios_scratch_regs(rdev
);
1833 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
1834 radeon_suspend(rdev
);
1835 radeon_hpd_fini(rdev
);
1837 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1838 ring_sizes
[i
] = radeon_ring_backup(rdev
, &rdev
->ring
[i
],
1840 if (ring_sizes
[i
]) {
1842 dev_info(rdev
->dev
, "Saved %d dwords of commands "
1843 "on ring %d.\n", ring_sizes
[i
], i
);
1847 r
= radeon_asic_reset(rdev
);
1849 dev_info(rdev
->dev
, "GPU reset succeeded, trying to resume\n");
1850 radeon_resume(rdev
);
1853 radeon_restore_bios_scratch_regs(rdev
);
1855 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1856 if (!r
&& ring_data
[i
]) {
1857 radeon_ring_restore(rdev
, &rdev
->ring
[i
],
1858 ring_sizes
[i
], ring_data
[i
]);
1860 radeon_fence_driver_force_completion(rdev
, i
);
1861 kfree(ring_data
[i
]);
1865 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
1866 /* do dpm late init */
1867 r
= radeon_pm_late_init(rdev
);
1869 rdev
->pm
.dpm_enabled
= false;
1870 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1873 /* resume old pm late */
1874 radeon_pm_resume(rdev
);
1877 /* init dig PHYs, disp eng pll */
1878 if (rdev
->is_atom_bios
) {
1879 radeon_atom_encoder_init(rdev
);
1880 radeon_atom_disp_eng_pll_init(rdev
);
1881 /* turn on the BL */
1882 if (rdev
->mode_info
.bl_encoder
) {
1883 u8 bl_level
= radeon_get_backlight_level(rdev
,
1884 rdev
->mode_info
.bl_encoder
);
1885 radeon_set_backlight_level(rdev
, rdev
->mode_info
.bl_encoder
,
1889 /* reset hpd state */
1890 radeon_hpd_init(rdev
);
1892 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1894 rdev
->in_reset
= true;
1895 rdev
->needs_reset
= false;
1897 downgrade_write(&rdev
->exclusive_lock
);
1899 drm_helper_resume_force_mode(rdev
->ddev
);
1901 /* set the power state here in case we are a PX system or headless */
1902 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
)
1903 radeon_pm_compute_clocks(rdev
);
1906 r
= radeon_ib_ring_tests(rdev
);
1910 /* bad news, how to tell it to userspace ? */
1911 dev_info(rdev
->dev
, "GPU reset failed\n");
1914 rdev
->needs_reset
= r
== -EAGAIN
;
1915 rdev
->in_reset
= false;
1917 up_read(&rdev
->exclusive_lock
);
1925 int radeon_debugfs_add_files(struct radeon_device
*rdev
,
1926 struct drm_info_list
*files
,
1931 for (i
= 0; i
< rdev
->debugfs_count
; i
++) {
1932 if (rdev
->debugfs
[i
].files
== files
) {
1933 /* Already registered */
1938 i
= rdev
->debugfs_count
+ 1;
1939 if (i
> RADEON_DEBUGFS_MAX_COMPONENTS
) {
1940 DRM_ERROR("Reached maximum number of debugfs components.\n");
1941 DRM_ERROR("Report so we increase "
1942 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1945 rdev
->debugfs
[rdev
->debugfs_count
].files
= files
;
1946 rdev
->debugfs
[rdev
->debugfs_count
].num_files
= nfiles
;
1947 rdev
->debugfs_count
= i
;
1948 #if defined(CONFIG_DEBUG_FS)
1949 drm_debugfs_create_files(files
, nfiles
,
1950 rdev
->ddev
->primary
->debugfs_root
,
1951 rdev
->ddev
->primary
);