2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_encoder.c */
42 radeon_get_encoder_enum(struct drm_device
*dev
, uint32_t supported_device
,
44 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
46 /* from radeon_connector.c */
48 radeon_add_legacy_connector(struct drm_device
*dev
,
49 uint32_t connector_id
,
50 uint32_t supported_device
,
52 struct radeon_i2c_bus_rec
*i2c_bus
,
53 uint16_t connector_object_id
,
54 struct radeon_hpd
*hpd
);
56 /* from radeon_legacy_encoder.c */
58 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
59 uint32_t supported_device
);
61 /* old legacy ATI BIOS routines */
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset
{
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE
,
67 COMBIOS_BIOS_SUPPORT_TABLE
,
68 COMBIOS_DAC_PROGRAMMING_TABLE
,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE
,
70 COMBIOS_CRTC_INFO_TABLE
,
71 COMBIOS_PLL_INFO_TABLE
,
72 COMBIOS_TV_INFO_TABLE
,
73 COMBIOS_DFP_INFO_TABLE
,
74 COMBIOS_HW_CONFIG_INFO_TABLE
,
75 COMBIOS_MULTIMEDIA_INFO_TABLE
,
76 COMBIOS_TV_STD_PATCH_TABLE
,
77 COMBIOS_LCD_INFO_TABLE
,
78 COMBIOS_MOBILE_INFO_TABLE
,
79 COMBIOS_PLL_INIT_TABLE
,
80 COMBIOS_MEM_CONFIG_TABLE
,
81 COMBIOS_SAVE_MASK_TABLE
,
82 COMBIOS_HARDCODED_EDID_TABLE
,
83 COMBIOS_ASIC_INIT_2_TABLE
,
84 COMBIOS_CONNECTOR_INFO_TABLE
,
85 COMBIOS_DYN_CLK_1_TABLE
,
86 COMBIOS_RESERVED_MEM_TABLE
,
87 COMBIOS_EXT_TMDS_INFO_TABLE
,
88 COMBIOS_MEM_CLK_INFO_TABLE
,
89 COMBIOS_EXT_DAC_INFO_TABLE
,
90 COMBIOS_MISC_INFO_TABLE
,
91 COMBIOS_CRT_INFO_TABLE
,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE
,
94 COMBIOS_FAN_SPEED_INFO_TABLE
,
95 COMBIOS_OVERDRIVE_INFO_TABLE
,
96 COMBIOS_OEM_INFO_TABLE
,
97 COMBIOS_DYN_CLK_2_TABLE
,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE
,
99 COMBIOS_I2C_INFO_TABLE
,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE
, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE
, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE
, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE
, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE
, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE
, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE
, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE
, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE
, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE
, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE
, /* offset from tmds power */
114 enum radeon_combios_ddc
{
124 enum radeon_combios_connector
{
125 CONNECTOR_NONE_LEGACY
,
126 CONNECTOR_PROPRIETARY_LEGACY
,
127 CONNECTOR_CRT_LEGACY
,
128 CONNECTOR_DVI_I_LEGACY
,
129 CONNECTOR_DVI_D_LEGACY
,
130 CONNECTOR_CTV_LEGACY
,
131 CONNECTOR_STV_LEGACY
,
132 CONNECTOR_UNSUPPORTED_LEGACY
135 const int legacy_connector_convert
[] = {
136 DRM_MODE_CONNECTOR_Unknown
,
137 DRM_MODE_CONNECTOR_DVID
,
138 DRM_MODE_CONNECTOR_VGA
,
139 DRM_MODE_CONNECTOR_DVII
,
140 DRM_MODE_CONNECTOR_DVID
,
141 DRM_MODE_CONNECTOR_Composite
,
142 DRM_MODE_CONNECTOR_SVIDEO
,
143 DRM_MODE_CONNECTOR_Unknown
,
146 static uint16_t combios_get_table_offset(struct drm_device
*dev
,
147 enum radeon_combios_table_offset table
)
149 struct radeon_device
*rdev
= dev
->dev_private
;
151 uint16_t offset
= 0, check_offset
;
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE
:
159 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0xc);
161 offset
= check_offset
;
163 case COMBIOS_BIOS_SUPPORT_TABLE
:
164 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x14);
166 offset
= check_offset
;
168 case COMBIOS_DAC_PROGRAMMING_TABLE
:
169 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2a);
171 offset
= check_offset
;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE
:
174 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2c);
176 offset
= check_offset
;
178 case COMBIOS_CRTC_INFO_TABLE
:
179 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x2e);
181 offset
= check_offset
;
183 case COMBIOS_PLL_INFO_TABLE
:
184 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x30);
186 offset
= check_offset
;
188 case COMBIOS_TV_INFO_TABLE
:
189 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x32);
191 offset
= check_offset
;
193 case COMBIOS_DFP_INFO_TABLE
:
194 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x34);
196 offset
= check_offset
;
198 case COMBIOS_HW_CONFIG_INFO_TABLE
:
199 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x36);
201 offset
= check_offset
;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE
:
204 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x38);
206 offset
= check_offset
;
208 case COMBIOS_TV_STD_PATCH_TABLE
:
209 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x3e);
211 offset
= check_offset
;
213 case COMBIOS_LCD_INFO_TABLE
:
214 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x40);
216 offset
= check_offset
;
218 case COMBIOS_MOBILE_INFO_TABLE
:
219 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x42);
221 offset
= check_offset
;
223 case COMBIOS_PLL_INIT_TABLE
:
224 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x46);
226 offset
= check_offset
;
228 case COMBIOS_MEM_CONFIG_TABLE
:
229 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x48);
231 offset
= check_offset
;
233 case COMBIOS_SAVE_MASK_TABLE
:
234 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4a);
236 offset
= check_offset
;
238 case COMBIOS_HARDCODED_EDID_TABLE
:
239 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4c);
241 offset
= check_offset
;
243 case COMBIOS_ASIC_INIT_2_TABLE
:
244 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x4e);
246 offset
= check_offset
;
248 case COMBIOS_CONNECTOR_INFO_TABLE
:
249 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x50);
251 offset
= check_offset
;
253 case COMBIOS_DYN_CLK_1_TABLE
:
254 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x52);
256 offset
= check_offset
;
258 case COMBIOS_RESERVED_MEM_TABLE
:
259 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x54);
261 offset
= check_offset
;
263 case COMBIOS_EXT_TMDS_INFO_TABLE
:
264 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x58);
266 offset
= check_offset
;
268 case COMBIOS_MEM_CLK_INFO_TABLE
:
269 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5a);
271 offset
= check_offset
;
273 case COMBIOS_EXT_DAC_INFO_TABLE
:
274 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5c);
276 offset
= check_offset
;
278 case COMBIOS_MISC_INFO_TABLE
:
279 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x5e);
281 offset
= check_offset
;
283 case COMBIOS_CRT_INFO_TABLE
:
284 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x60);
286 offset
= check_offset
;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
:
289 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x62);
291 offset
= check_offset
;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE
:
294 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x64);
296 offset
= check_offset
;
298 case COMBIOS_FAN_SPEED_INFO_TABLE
:
299 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x66);
301 offset
= check_offset
;
303 case COMBIOS_OVERDRIVE_INFO_TABLE
:
304 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x68);
306 offset
= check_offset
;
308 case COMBIOS_OEM_INFO_TABLE
:
309 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6a);
311 offset
= check_offset
;
313 case COMBIOS_DYN_CLK_2_TABLE
:
314 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6c);
316 offset
= check_offset
;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE
:
319 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x6e);
321 offset
= check_offset
;
323 case COMBIOS_I2C_INFO_TABLE
:
324 check_offset
= RBIOS16(rdev
->bios_header_start
+ 0x70);
326 offset
= check_offset
;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE
: /* offset from misc info */
331 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
333 rev
= RBIOS8(check_offset
);
335 check_offset
= RBIOS16(check_offset
+ 0x3);
337 offset
= check_offset
;
341 case COMBIOS_ASIC_INIT_4_TABLE
: /* offset from misc info */
343 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
345 rev
= RBIOS8(check_offset
);
347 check_offset
= RBIOS16(check_offset
+ 0x5);
349 offset
= check_offset
;
353 case COMBIOS_DETECTED_MEM_TABLE
: /* offset from misc info */
355 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
357 rev
= RBIOS8(check_offset
);
359 check_offset
= RBIOS16(check_offset
+ 0x7);
361 offset
= check_offset
;
365 case COMBIOS_ASIC_INIT_5_TABLE
: /* offset from misc info */
367 combios_get_table_offset(dev
, COMBIOS_MISC_INFO_TABLE
);
369 rev
= RBIOS8(check_offset
);
371 check_offset
= RBIOS16(check_offset
+ 0x9);
373 offset
= check_offset
;
377 case COMBIOS_RAM_RESET_TABLE
: /* offset from mem config */
379 combios_get_table_offset(dev
, COMBIOS_MEM_CONFIG_TABLE
);
381 while (RBIOS8(check_offset
++));
384 offset
= check_offset
;
387 case COMBIOS_POWERPLAY_INFO_TABLE
: /* offset from mobile info */
389 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
391 check_offset
= RBIOS16(check_offset
+ 0x11);
393 offset
= check_offset
;
396 case COMBIOS_GPIO_INFO_TABLE
: /* offset from mobile info */
398 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
400 check_offset
= RBIOS16(check_offset
+ 0x13);
402 offset
= check_offset
;
405 case COMBIOS_LCD_DDC_INFO_TABLE
: /* offset from mobile info */
407 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
409 check_offset
= RBIOS16(check_offset
+ 0x15);
411 offset
= check_offset
;
414 case COMBIOS_TMDS_POWER_TABLE
: /* offset from mobile info */
416 combios_get_table_offset(dev
, COMBIOS_MOBILE_INFO_TABLE
);
418 check_offset
= RBIOS16(check_offset
+ 0x17);
420 offset
= check_offset
;
423 case COMBIOS_TMDS_POWER_ON_TABLE
: /* offset from tmds power */
425 combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_TABLE
);
427 check_offset
= RBIOS16(check_offset
+ 0x2);
429 offset
= check_offset
;
432 case COMBIOS_TMDS_POWER_OFF_TABLE
: /* offset from tmds power */
434 combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_TABLE
);
436 check_offset
= RBIOS16(check_offset
+ 0x4);
438 offset
= check_offset
;
449 bool radeon_combios_check_hardcoded_edid(struct radeon_device
*rdev
)
454 edid_info
= combios_get_table_offset(rdev
->ddev
, COMBIOS_HARDCODED_EDID_TABLE
);
458 raw
= rdev
->bios
+ edid_info
;
459 size
= EDID_LENGTH
* (raw
[0x7e] + 1);
460 edid
= kmalloc(size
, GFP_KERNEL
);
464 memcpy((unsigned char *)edid
, raw
, size
);
466 if (!drm_edid_is_valid(edid
)) {
471 rdev
->mode_info
.bios_hardcoded_edid
= edid
;
472 rdev
->mode_info
.bios_hardcoded_edid_size
= size
;
476 /* this is used for atom LCDs as well */
478 radeon_bios_get_hardcoded_edid(struct radeon_device
*rdev
)
482 if (rdev
->mode_info
.bios_hardcoded_edid
) {
483 edid
= kmalloc(rdev
->mode_info
.bios_hardcoded_edid_size
, GFP_KERNEL
);
485 memcpy((unsigned char *)edid
,
486 (unsigned char *)rdev
->mode_info
.bios_hardcoded_edid
,
487 rdev
->mode_info
.bios_hardcoded_edid_size
);
494 static struct radeon_i2c_bus_rec
combios_setup_i2c_bus(struct radeon_device
*rdev
,
495 enum radeon_combios_ddc ddc
,
499 struct radeon_i2c_bus_rec i2c
;
503 * DDC_NONE_DETECTED = none
504 * DDC_DVI = RADEON_GPIO_DVI_DDC
505 * DDC_VGA = RADEON_GPIO_VGA_DDC
506 * DDC_LCD = RADEON_GPIOPAD_MASK
507 * DDC_GPIO = RADEON_MDGPIO_MASK
509 * DDC_MONID = RADEON_GPIO_MONID
510 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
512 * DDC_MONID = RADEON_GPIO_MONID
513 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
515 * DDC_MONID = RADEON_GPIO_DVI_DDC
516 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
518 * DDC_MONID = RADEON_GPIO_MONID
519 * DDC_CRT2 = RADEON_GPIO_MONID
521 * DDC_MONID = RADEON_GPIOPAD_MASK
522 * DDC_CRT2 = RADEON_GPIO_MONID
525 case DDC_NONE_DETECTED
:
530 ddc_line
= RADEON_GPIO_DVI_DDC
;
533 ddc_line
= RADEON_GPIO_VGA_DDC
;
536 ddc_line
= RADEON_GPIOPAD_MASK
;
539 ddc_line
= RADEON_MDGPIO_MASK
;
542 if (rdev
->family
== CHIP_RS300
||
543 rdev
->family
== CHIP_RS400
||
544 rdev
->family
== CHIP_RS480
)
545 ddc_line
= RADEON_GPIOPAD_MASK
;
546 else if (rdev
->family
== CHIP_R300
||
547 rdev
->family
== CHIP_R350
) {
548 ddc_line
= RADEON_GPIO_DVI_DDC
;
551 ddc_line
= RADEON_GPIO_MONID
;
554 if (rdev
->family
== CHIP_R200
||
555 rdev
->family
== CHIP_R300
||
556 rdev
->family
== CHIP_R350
) {
557 ddc_line
= RADEON_GPIO_DVI_DDC
;
559 } else if (rdev
->family
== CHIP_RS300
||
560 rdev
->family
== CHIP_RS400
||
561 rdev
->family
== CHIP_RS480
)
562 ddc_line
= RADEON_GPIO_MONID
;
563 else if (rdev
->family
>= CHIP_RV350
) {
564 ddc_line
= RADEON_GPIO_MONID
;
567 ddc_line
= RADEON_GPIO_CRT2_DDC
;
571 if (ddc_line
== RADEON_GPIOPAD_MASK
) {
572 i2c
.mask_clk_reg
= RADEON_GPIOPAD_MASK
;
573 i2c
.mask_data_reg
= RADEON_GPIOPAD_MASK
;
574 i2c
.a_clk_reg
= RADEON_GPIOPAD_A
;
575 i2c
.a_data_reg
= RADEON_GPIOPAD_A
;
576 i2c
.en_clk_reg
= RADEON_GPIOPAD_EN
;
577 i2c
.en_data_reg
= RADEON_GPIOPAD_EN
;
578 i2c
.y_clk_reg
= RADEON_GPIOPAD_Y
;
579 i2c
.y_data_reg
= RADEON_GPIOPAD_Y
;
580 } else if (ddc_line
== RADEON_MDGPIO_MASK
) {
581 i2c
.mask_clk_reg
= RADEON_MDGPIO_MASK
;
582 i2c
.mask_data_reg
= RADEON_MDGPIO_MASK
;
583 i2c
.a_clk_reg
= RADEON_MDGPIO_A
;
584 i2c
.a_data_reg
= RADEON_MDGPIO_A
;
585 i2c
.en_clk_reg
= RADEON_MDGPIO_EN
;
586 i2c
.en_data_reg
= RADEON_MDGPIO_EN
;
587 i2c
.y_clk_reg
= RADEON_MDGPIO_Y
;
588 i2c
.y_data_reg
= RADEON_MDGPIO_Y
;
590 i2c
.mask_clk_reg
= ddc_line
;
591 i2c
.mask_data_reg
= ddc_line
;
592 i2c
.a_clk_reg
= ddc_line
;
593 i2c
.a_data_reg
= ddc_line
;
594 i2c
.en_clk_reg
= ddc_line
;
595 i2c
.en_data_reg
= ddc_line
;
596 i2c
.y_clk_reg
= ddc_line
;
597 i2c
.y_data_reg
= ddc_line
;
600 if (clk_mask
&& data_mask
) {
601 /* system specific masks */
602 i2c
.mask_clk_mask
= clk_mask
;
603 i2c
.mask_data_mask
= data_mask
;
604 i2c
.a_clk_mask
= clk_mask
;
605 i2c
.a_data_mask
= data_mask
;
606 i2c
.en_clk_mask
= clk_mask
;
607 i2c
.en_data_mask
= data_mask
;
608 i2c
.y_clk_mask
= clk_mask
;
609 i2c
.y_data_mask
= data_mask
;
610 } else if ((ddc_line
== RADEON_GPIOPAD_MASK
) ||
611 (ddc_line
== RADEON_MDGPIO_MASK
)) {
612 /* default gpiopad masks */
613 i2c
.mask_clk_mask
= (0x20 << 8);
614 i2c
.mask_data_mask
= 0x80;
615 i2c
.a_clk_mask
= (0x20 << 8);
616 i2c
.a_data_mask
= 0x80;
617 i2c
.en_clk_mask
= (0x20 << 8);
618 i2c
.en_data_mask
= 0x80;
619 i2c
.y_clk_mask
= (0x20 << 8);
620 i2c
.y_data_mask
= 0x80;
622 /* default masks for ddc pads */
623 i2c
.mask_clk_mask
= RADEON_GPIO_MASK_1
;
624 i2c
.mask_data_mask
= RADEON_GPIO_MASK_0
;
625 i2c
.a_clk_mask
= RADEON_GPIO_A_1
;
626 i2c
.a_data_mask
= RADEON_GPIO_A_0
;
627 i2c
.en_clk_mask
= RADEON_GPIO_EN_1
;
628 i2c
.en_data_mask
= RADEON_GPIO_EN_0
;
629 i2c
.y_clk_mask
= RADEON_GPIO_Y_1
;
630 i2c
.y_data_mask
= RADEON_GPIO_Y_0
;
633 switch (rdev
->family
) {
641 case RADEON_GPIO_DVI_DDC
:
642 i2c
.hw_capable
= true;
645 i2c
.hw_capable
= false;
651 case RADEON_GPIO_DVI_DDC
:
652 case RADEON_GPIO_MONID
:
653 i2c
.hw_capable
= true;
656 i2c
.hw_capable
= false;
663 case RADEON_GPIO_VGA_DDC
:
664 case RADEON_GPIO_DVI_DDC
:
665 case RADEON_GPIO_CRT2_DDC
:
666 i2c
.hw_capable
= true;
669 i2c
.hw_capable
= false;
676 case RADEON_GPIO_VGA_DDC
:
677 case RADEON_GPIO_DVI_DDC
:
678 i2c
.hw_capable
= true;
681 i2c
.hw_capable
= false;
690 case RADEON_GPIO_VGA_DDC
:
691 case RADEON_GPIO_DVI_DDC
:
692 i2c
.hw_capable
= true;
694 case RADEON_GPIO_MONID
:
695 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
696 * reliably on some pre-r4xx hardware; not sure why.
698 i2c
.hw_capable
= false;
701 i2c
.hw_capable
= false;
706 i2c
.hw_capable
= false;
712 i2c
.hpd
= RADEON_HPD_NONE
;
722 static struct radeon_i2c_bus_rec
radeon_combios_get_i2c_info_from_table(struct radeon_device
*rdev
)
724 struct drm_device
*dev
= rdev
->ddev
;
725 struct radeon_i2c_bus_rec i2c
;
727 u8 id
, blocks
, clk
, data
;
732 offset
= combios_get_table_offset(dev
, COMBIOS_I2C_INFO_TABLE
);
734 blocks
= RBIOS8(offset
+ 2);
735 for (i
= 0; i
< blocks
; i
++) {
736 id
= RBIOS8(offset
+ 3 + (i
* 5) + 0);
738 clk
= RBIOS8(offset
+ 3 + (i
* 5) + 3);
739 data
= RBIOS8(offset
+ 3 + (i
* 5) + 4);
741 i2c
= combios_setup_i2c_bus(rdev
, DDC_MONID
,
742 (1 << clk
), (1 << data
));
750 void radeon_combios_i2c_init(struct radeon_device
*rdev
)
752 struct drm_device
*dev
= rdev
->ddev
;
753 struct radeon_i2c_bus_rec i2c
;
757 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
759 * 0x60, 0x64, 0x68, mm
763 * 0x60, 0x64, 0x68, gpiopads, mm
767 i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
768 rdev
->i2c_bus
[0] = radeon_i2c_create(dev
, &i2c
, "DVI_DDC");
770 i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
771 rdev
->i2c_bus
[1] = radeon_i2c_create(dev
, &i2c
, "VGA_DDC");
775 i2c
.hw_capable
= true;
778 rdev
->i2c_bus
[2] = radeon_i2c_create(dev
, &i2c
, "MM_I2C");
780 if (rdev
->family
== CHIP_R300
||
781 rdev
->family
== CHIP_R350
) {
782 /* only 2 sw i2c pads */
783 } else if (rdev
->family
== CHIP_RS300
||
784 rdev
->family
== CHIP_RS400
||
785 rdev
->family
== CHIP_RS480
) {
787 i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
788 rdev
->i2c_bus
[3] = radeon_i2c_create(dev
, &i2c
, "MONID");
791 i2c
= radeon_combios_get_i2c_info_from_table(rdev
);
793 rdev
->i2c_bus
[4] = radeon_i2c_create(dev
, &i2c
, "GPIOPAD_MASK");
794 } else if ((rdev
->family
== CHIP_R200
) ||
795 (rdev
->family
>= CHIP_R300
)) {
797 i2c
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
798 rdev
->i2c_bus
[3] = radeon_i2c_create(dev
, &i2c
, "MONID");
801 i2c
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
802 rdev
->i2c_bus
[3] = radeon_i2c_create(dev
, &i2c
, "MONID");
804 i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
805 rdev
->i2c_bus
[4] = radeon_i2c_create(dev
, &i2c
, "CRT2_DDC");
809 bool radeon_combios_get_clock_info(struct drm_device
*dev
)
811 struct radeon_device
*rdev
= dev
->dev_private
;
813 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
814 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
815 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
816 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
820 pll_info
= combios_get_table_offset(dev
, COMBIOS_PLL_INFO_TABLE
);
822 rev
= RBIOS8(pll_info
);
825 p1pll
->reference_freq
= RBIOS16(pll_info
+ 0xe);
826 p1pll
->reference_div
= RBIOS16(pll_info
+ 0x10);
827 p1pll
->pll_out_min
= RBIOS32(pll_info
+ 0x12);
828 p1pll
->pll_out_max
= RBIOS32(pll_info
+ 0x16);
829 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
830 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
833 p1pll
->pll_in_min
= RBIOS32(pll_info
+ 0x36);
834 p1pll
->pll_in_max
= RBIOS32(pll_info
+ 0x3a);
836 p1pll
->pll_in_min
= 40;
837 p1pll
->pll_in_max
= 500;
842 spll
->reference_freq
= RBIOS16(pll_info
+ 0x1a);
843 spll
->reference_div
= RBIOS16(pll_info
+ 0x1c);
844 spll
->pll_out_min
= RBIOS32(pll_info
+ 0x1e);
845 spll
->pll_out_max
= RBIOS32(pll_info
+ 0x22);
848 spll
->pll_in_min
= RBIOS32(pll_info
+ 0x48);
849 spll
->pll_in_max
= RBIOS32(pll_info
+ 0x4c);
852 spll
->pll_in_min
= 40;
853 spll
->pll_in_max
= 500;
857 mpll
->reference_freq
= RBIOS16(pll_info
+ 0x26);
858 mpll
->reference_div
= RBIOS16(pll_info
+ 0x28);
859 mpll
->pll_out_min
= RBIOS32(pll_info
+ 0x2a);
860 mpll
->pll_out_max
= RBIOS32(pll_info
+ 0x2e);
863 mpll
->pll_in_min
= RBIOS32(pll_info
+ 0x5a);
864 mpll
->pll_in_max
= RBIOS32(pll_info
+ 0x5e);
867 mpll
->pll_in_min
= 40;
868 mpll
->pll_in_max
= 500;
871 /* default sclk/mclk */
872 sclk
= RBIOS16(pll_info
+ 0xa);
873 mclk
= RBIOS16(pll_info
+ 0x8);
879 rdev
->clock
.default_sclk
= sclk
;
880 rdev
->clock
.default_mclk
= mclk
;
882 if (RBIOS32(pll_info
+ 0x16))
883 rdev
->clock
.max_pixel_clock
= RBIOS32(pll_info
+ 0x16);
885 rdev
->clock
.max_pixel_clock
= 35000; /* might need something asic specific */
892 bool radeon_combios_sideport_present(struct radeon_device
*rdev
)
894 struct drm_device
*dev
= rdev
->ddev
;
897 /* sideport is AMD only */
898 if (rdev
->family
== CHIP_RS400
)
901 igp_info
= combios_get_table_offset(dev
, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE
);
904 if (RBIOS16(igp_info
+ 0x4))
910 static const uint32_t default_primarydac_adj
[CHIP_LAST
] = {
911 0x00000808, /* r100 */
912 0x00000808, /* rv100 */
913 0x00000808, /* rs100 */
914 0x00000808, /* rv200 */
915 0x00000808, /* rs200 */
916 0x00000808, /* r200 */
917 0x00000808, /* rv250 */
918 0x00000000, /* rs300 */
919 0x00000808, /* rv280 */
920 0x00000808, /* r300 */
921 0x00000808, /* r350 */
922 0x00000808, /* rv350 */
923 0x00000808, /* rv380 */
924 0x00000808, /* r420 */
925 0x00000808, /* r423 */
926 0x00000808, /* rv410 */
927 0x00000000, /* rs400 */
928 0x00000000, /* rs480 */
931 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device
*rdev
,
932 struct radeon_encoder_primary_dac
*p_dac
)
934 p_dac
->ps2_pdac_adj
= default_primarydac_adj
[rdev
->family
];
938 struct radeon_encoder_primary_dac
*radeon_combios_get_primary_dac_info(struct
942 struct drm_device
*dev
= encoder
->base
.dev
;
943 struct radeon_device
*rdev
= dev
->dev_private
;
945 uint8_t rev
, bg
, dac
;
946 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
949 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
),
955 /* check CRT table */
956 dac_info
= combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
958 rev
= RBIOS8(dac_info
) & 0x3;
960 bg
= RBIOS8(dac_info
+ 0x2) & 0xf;
961 dac
= (RBIOS8(dac_info
+ 0x2) >> 4) & 0xf;
962 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
964 bg
= RBIOS8(dac_info
+ 0x2) & 0xf;
965 dac
= RBIOS8(dac_info
+ 0x3) & 0xf;
966 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
968 /* if the values are all zeros, use the table */
969 if (p_dac
->ps2_pdac_adj
)
974 /* Radeon 9100 (R200) */
975 if ((dev
->pdev
->device
== 0x514D) &&
976 (dev
->pdev
->subsystem_vendor
== 0x174B) &&
977 (dev
->pdev
->subsystem_device
== 0x7149)) {
978 /* vbios value is bad, use the default */
982 if (!found
) /* fallback to defaults */
983 radeon_legacy_get_primary_dac_info_from_table(rdev
, p_dac
);
989 radeon_combios_get_tv_info(struct radeon_device
*rdev
)
991 struct drm_device
*dev
= rdev
->ddev
;
993 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
995 tv_info
= combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
997 if (RBIOS8(tv_info
+ 6) == 'T') {
998 switch (RBIOS8(tv_info
+ 7) & 0xf) {
1000 tv_std
= TV_STD_NTSC
;
1001 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1004 tv_std
= TV_STD_PAL
;
1005 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1008 tv_std
= TV_STD_PAL_M
;
1009 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1012 tv_std
= TV_STD_PAL_60
;
1013 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1016 tv_std
= TV_STD_NTSC_J
;
1017 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1020 tv_std
= TV_STD_SCART_PAL
;
1021 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1024 tv_std
= TV_STD_NTSC
;
1026 ("Unknown TV standard; defaulting to NTSC\n");
1030 switch ((RBIOS8(tv_info
+ 9) >> 2) & 0x3) {
1032 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1035 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1038 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1041 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1051 static const uint32_t default_tvdac_adj
[CHIP_LAST
] = {
1052 0x00000000, /* r100 */
1053 0x00280000, /* rv100 */
1054 0x00000000, /* rs100 */
1055 0x00880000, /* rv200 */
1056 0x00000000, /* rs200 */
1057 0x00000000, /* r200 */
1058 0x00770000, /* rv250 */
1059 0x00290000, /* rs300 */
1060 0x00560000, /* rv280 */
1061 0x00780000, /* r300 */
1062 0x00770000, /* r350 */
1063 0x00780000, /* rv350 */
1064 0x00780000, /* rv380 */
1065 0x01080000, /* r420 */
1066 0x01080000, /* r423 */
1067 0x01080000, /* rv410 */
1068 0x00780000, /* rs400 */
1069 0x00780000, /* rs480 */
1072 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device
*rdev
,
1073 struct radeon_encoder_tv_dac
*tv_dac
)
1075 tv_dac
->ps2_tvdac_adj
= default_tvdac_adj
[rdev
->family
];
1076 if ((rdev
->flags
& RADEON_IS_MOBILITY
) && (rdev
->family
== CHIP_RV250
))
1077 tv_dac
->ps2_tvdac_adj
= 0x00880000;
1078 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
1079 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
1083 struct radeon_encoder_tv_dac
*radeon_combios_get_tv_dac_info(struct
1087 struct drm_device
*dev
= encoder
->base
.dev
;
1088 struct radeon_device
*rdev
= dev
->dev_private
;
1090 uint8_t rev
, bg
, dac
;
1091 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1094 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1098 /* first check TV table */
1099 dac_info
= combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
1101 rev
= RBIOS8(dac_info
+ 0x3);
1103 bg
= RBIOS8(dac_info
+ 0xc) & 0xf;
1104 dac
= RBIOS8(dac_info
+ 0xd) & 0xf;
1105 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1107 bg
= RBIOS8(dac_info
+ 0xe) & 0xf;
1108 dac
= RBIOS8(dac_info
+ 0xf) & 0xf;
1109 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1111 bg
= RBIOS8(dac_info
+ 0x10) & 0xf;
1112 dac
= RBIOS8(dac_info
+ 0x11) & 0xf;
1113 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1114 /* if the values are all zeros, use the table */
1115 if (tv_dac
->ps2_tvdac_adj
)
1117 } else if (rev
> 1) {
1118 bg
= RBIOS8(dac_info
+ 0xc) & 0xf;
1119 dac
= (RBIOS8(dac_info
+ 0xc) >> 4) & 0xf;
1120 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1122 bg
= RBIOS8(dac_info
+ 0xd) & 0xf;
1123 dac
= (RBIOS8(dac_info
+ 0xd) >> 4) & 0xf;
1124 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1126 bg
= RBIOS8(dac_info
+ 0xe) & 0xf;
1127 dac
= (RBIOS8(dac_info
+ 0xe) >> 4) & 0xf;
1128 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1129 /* if the values are all zeros, use the table */
1130 if (tv_dac
->ps2_tvdac_adj
)
1133 tv_dac
->tv_std
= radeon_combios_get_tv_info(rdev
);
1136 /* then check CRT table */
1138 combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
1140 rev
= RBIOS8(dac_info
) & 0x3;
1142 bg
= RBIOS8(dac_info
+ 0x3) & 0xf;
1143 dac
= (RBIOS8(dac_info
+ 0x3) >> 4) & 0xf;
1144 tv_dac
->ps2_tvdac_adj
=
1145 (bg
<< 16) | (dac
<< 20);
1146 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
1147 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
1148 /* if the values are all zeros, use the table */
1149 if (tv_dac
->ps2_tvdac_adj
)
1152 bg
= RBIOS8(dac_info
+ 0x4) & 0xf;
1153 dac
= RBIOS8(dac_info
+ 0x5) & 0xf;
1154 tv_dac
->ps2_tvdac_adj
=
1155 (bg
<< 16) | (dac
<< 20);
1156 tv_dac
->pal_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
1157 tv_dac
->ntsc_tvdac_adj
= tv_dac
->ps2_tvdac_adj
;
1158 /* if the values are all zeros, use the table */
1159 if (tv_dac
->ps2_tvdac_adj
)
1163 DRM_INFO("No TV DAC info found in BIOS\n");
1167 if (!found
) /* fallback to defaults */
1168 radeon_legacy_get_tv_dac_info_from_table(rdev
, tv_dac
);
1173 static struct radeon_encoder_lvds
*radeon_legacy_get_lvds_info_from_regs(struct
1177 struct radeon_encoder_lvds
*lvds
= NULL
;
1178 uint32_t fp_vert_stretch
, fp_horz_stretch
;
1179 uint32_t ppll_div_sel
, ppll_val
;
1180 uint32_t lvds_ss_gen_cntl
= RREG32(RADEON_LVDS_SS_GEN_CNTL
);
1182 lvds
= kzalloc(sizeof(struct radeon_encoder_lvds
), GFP_KERNEL
);
1187 fp_vert_stretch
= RREG32(RADEON_FP_VERT_STRETCH
);
1188 fp_horz_stretch
= RREG32(RADEON_FP_HORZ_STRETCH
);
1190 /* These should be fail-safe defaults, fingers crossed */
1191 lvds
->panel_pwr_delay
= 200;
1192 lvds
->panel_vcc_delay
= 2000;
1194 lvds
->lvds_gen_cntl
= RREG32(RADEON_LVDS_GEN_CNTL
);
1195 lvds
->panel_digon_delay
= (lvds_ss_gen_cntl
>> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT
) & 0xf;
1196 lvds
->panel_blon_delay
= (lvds_ss_gen_cntl
>> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT
) & 0xf;
1198 if (fp_vert_stretch
& RADEON_VERT_STRETCH_ENABLE
)
1199 lvds
->native_mode
.vdisplay
=
1200 ((fp_vert_stretch
& RADEON_VERT_PANEL_SIZE
) >>
1201 RADEON_VERT_PANEL_SHIFT
) + 1;
1203 lvds
->native_mode
.vdisplay
=
1204 (RREG32(RADEON_CRTC_V_TOTAL_DISP
) >> 16) + 1;
1206 if (fp_horz_stretch
& RADEON_HORZ_STRETCH_ENABLE
)
1207 lvds
->native_mode
.hdisplay
=
1208 (((fp_horz_stretch
& RADEON_HORZ_PANEL_SIZE
) >>
1209 RADEON_HORZ_PANEL_SHIFT
) + 1) * 8;
1211 lvds
->native_mode
.hdisplay
=
1212 ((RREG32(RADEON_CRTC_H_TOTAL_DISP
) >> 16) + 1) * 8;
1214 if ((lvds
->native_mode
.hdisplay
< 640) ||
1215 (lvds
->native_mode
.vdisplay
< 480)) {
1216 lvds
->native_mode
.hdisplay
= 640;
1217 lvds
->native_mode
.vdisplay
= 480;
1220 ppll_div_sel
= RREG8(RADEON_CLOCK_CNTL_INDEX
+ 1) & 0x3;
1221 ppll_val
= RREG32_PLL(RADEON_PPLL_DIV_0
+ ppll_div_sel
);
1222 if ((ppll_val
& 0x000707ff) == 0x1bb)
1223 lvds
->use_bios_dividers
= false;
1225 lvds
->panel_ref_divider
=
1226 RREG32_PLL(RADEON_PPLL_REF_DIV
) & 0x3ff;
1227 lvds
->panel_post_divider
= (ppll_val
>> 16) & 0x7;
1228 lvds
->panel_fb_divider
= ppll_val
& 0x7ff;
1230 if ((lvds
->panel_ref_divider
!= 0) &&
1231 (lvds
->panel_fb_divider
> 3))
1232 lvds
->use_bios_dividers
= true;
1234 lvds
->panel_vcc_delay
= 200;
1236 DRM_INFO("Panel info derived from registers\n");
1237 DRM_INFO("Panel Size %dx%d\n", lvds
->native_mode
.hdisplay
,
1238 lvds
->native_mode
.vdisplay
);
1243 struct radeon_encoder_lvds
*radeon_combios_get_lvds_info(struct radeon_encoder
1246 struct drm_device
*dev
= encoder
->base
.dev
;
1247 struct radeon_device
*rdev
= dev
->dev_private
;
1249 uint32_t panel_setup
;
1252 struct radeon_encoder_lvds
*lvds
= NULL
;
1254 lcd_info
= combios_get_table_offset(dev
, COMBIOS_LCD_INFO_TABLE
);
1257 lvds
= kzalloc(sizeof(struct radeon_encoder_lvds
), GFP_KERNEL
);
1262 for (i
= 0; i
< 24; i
++)
1263 stmp
[i
] = RBIOS8(lcd_info
+ i
+ 1);
1266 DRM_INFO("Panel ID String: %s\n", stmp
);
1268 lvds
->native_mode
.hdisplay
= RBIOS16(lcd_info
+ 0x19);
1269 lvds
->native_mode
.vdisplay
= RBIOS16(lcd_info
+ 0x1b);
1271 DRM_INFO("Panel Size %dx%d\n", lvds
->native_mode
.hdisplay
,
1272 lvds
->native_mode
.vdisplay
);
1274 lvds
->panel_vcc_delay
= RBIOS16(lcd_info
+ 0x2c);
1275 lvds
->panel_vcc_delay
= min_t(u16
, lvds
->panel_vcc_delay
, 2000);
1277 lvds
->panel_pwr_delay
= RBIOS8(lcd_info
+ 0x24);
1278 lvds
->panel_digon_delay
= RBIOS16(lcd_info
+ 0x38) & 0xf;
1279 lvds
->panel_blon_delay
= (RBIOS16(lcd_info
+ 0x38) >> 4) & 0xf;
1281 lvds
->panel_ref_divider
= RBIOS16(lcd_info
+ 0x2e);
1282 lvds
->panel_post_divider
= RBIOS8(lcd_info
+ 0x30);
1283 lvds
->panel_fb_divider
= RBIOS16(lcd_info
+ 0x31);
1284 if ((lvds
->panel_ref_divider
!= 0) &&
1285 (lvds
->panel_fb_divider
> 3))
1286 lvds
->use_bios_dividers
= true;
1288 panel_setup
= RBIOS32(lcd_info
+ 0x39);
1289 lvds
->lvds_gen_cntl
= 0xff00;
1290 if (panel_setup
& 0x1)
1291 lvds
->lvds_gen_cntl
|= RADEON_LVDS_PANEL_FORMAT
;
1293 if ((panel_setup
>> 4) & 0x1)
1294 lvds
->lvds_gen_cntl
|= RADEON_LVDS_PANEL_TYPE
;
1296 switch ((panel_setup
>> 8) & 0x7) {
1298 lvds
->lvds_gen_cntl
|= RADEON_LVDS_NO_FM
;
1301 lvds
->lvds_gen_cntl
|= RADEON_LVDS_2_GREY
;
1304 lvds
->lvds_gen_cntl
|= RADEON_LVDS_4_GREY
;
1310 if ((panel_setup
>> 16) & 0x1)
1311 lvds
->lvds_gen_cntl
|= RADEON_LVDS_FP_POL_LOW
;
1313 if ((panel_setup
>> 17) & 0x1)
1314 lvds
->lvds_gen_cntl
|= RADEON_LVDS_LP_POL_LOW
;
1316 if ((panel_setup
>> 18) & 0x1)
1317 lvds
->lvds_gen_cntl
|= RADEON_LVDS_DTM_POL_LOW
;
1319 if ((panel_setup
>> 23) & 0x1)
1320 lvds
->lvds_gen_cntl
|= RADEON_LVDS_BL_CLK_SEL
;
1322 lvds
->lvds_gen_cntl
|= (panel_setup
& 0xf0000000);
1324 for (i
= 0; i
< 32; i
++) {
1325 tmp
= RBIOS16(lcd_info
+ 64 + i
* 2);
1329 if ((RBIOS16(tmp
) == lvds
->native_mode
.hdisplay
) &&
1330 (RBIOS16(tmp
+ 2) == lvds
->native_mode
.vdisplay
)) {
1331 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1332 (RBIOS16(tmp
+ 17) - RBIOS16(tmp
+ 19)) * 8;
1333 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1334 (RBIOS16(tmp
+ 21) - RBIOS16(tmp
+ 19) - 1) * 8;
1335 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1336 (RBIOS8(tmp
+ 23) * 8);
1338 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1339 (RBIOS16(tmp
+ 24) - RBIOS16(tmp
+ 26));
1340 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1341 ((RBIOS16(tmp
+ 28) & 0x7ff) - RBIOS16(tmp
+ 26));
1342 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1343 ((RBIOS16(tmp
+ 28) & 0xf800) >> 11);
1345 lvds
->native_mode
.clock
= RBIOS16(tmp
+ 9) * 10;
1346 lvds
->native_mode
.flags
= 0;
1347 /* set crtc values */
1348 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1353 DRM_INFO("No panel info found in BIOS\n");
1354 lvds
= radeon_legacy_get_lvds_info_from_regs(rdev
);
1358 encoder
->native_mode
= lvds
->native_mode
;
1362 static const struct radeon_tmds_pll default_tmds_pll
[CHIP_LAST
][4] = {
1363 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1364 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1365 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1366 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1367 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1368 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1369 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1370 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1371 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1372 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1373 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1374 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1375 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1376 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1377 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1378 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1379 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1380 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1383 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder
*encoder
,
1384 struct radeon_encoder_int_tmds
*tmds
)
1386 struct drm_device
*dev
= encoder
->base
.dev
;
1387 struct radeon_device
*rdev
= dev
->dev_private
;
1390 for (i
= 0; i
< 4; i
++) {
1391 tmds
->tmds_pll
[i
].value
=
1392 default_tmds_pll
[rdev
->family
][i
].value
;
1393 tmds
->tmds_pll
[i
].freq
= default_tmds_pll
[rdev
->family
][i
].freq
;
1399 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder
*encoder
,
1400 struct radeon_encoder_int_tmds
*tmds
)
1402 struct drm_device
*dev
= encoder
->base
.dev
;
1403 struct radeon_device
*rdev
= dev
->dev_private
;
1408 tmds_info
= combios_get_table_offset(dev
, COMBIOS_DFP_INFO_TABLE
);
1411 ver
= RBIOS8(tmds_info
);
1412 DRM_DEBUG_KMS("DFP table revision: %d\n", ver
);
1414 n
= RBIOS8(tmds_info
+ 5) + 1;
1417 for (i
= 0; i
< n
; i
++) {
1418 tmds
->tmds_pll
[i
].value
=
1419 RBIOS32(tmds_info
+ i
* 10 + 0x08);
1420 tmds
->tmds_pll
[i
].freq
=
1421 RBIOS16(tmds_info
+ i
* 10 + 0x10);
1422 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1423 tmds
->tmds_pll
[i
].freq
,
1424 tmds
->tmds_pll
[i
].value
);
1426 } else if (ver
== 4) {
1428 n
= RBIOS8(tmds_info
+ 5) + 1;
1431 for (i
= 0; i
< n
; i
++) {
1432 tmds
->tmds_pll
[i
].value
=
1433 RBIOS32(tmds_info
+ stride
+ 0x08);
1434 tmds
->tmds_pll
[i
].freq
=
1435 RBIOS16(tmds_info
+ stride
+ 0x10);
1440 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1441 tmds
->tmds_pll
[i
].freq
,
1442 tmds
->tmds_pll
[i
].value
);
1446 DRM_INFO("No TMDS info found in BIOS\n");
1452 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder
*encoder
,
1453 struct radeon_encoder_ext_tmds
*tmds
)
1455 struct drm_device
*dev
= encoder
->base
.dev
;
1456 struct radeon_device
*rdev
= dev
->dev_private
;
1457 struct radeon_i2c_bus_rec i2c_bus
;
1459 /* default for macs */
1460 i2c_bus
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
1461 tmds
->i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
1463 /* XXX some macs have duallink chips */
1464 switch (rdev
->mode_info
.connector_table
) {
1465 case CT_POWERBOOK_EXTERNAL
:
1466 case CT_MINI_EXTERNAL
:
1468 tmds
->dvo_chip
= DVO_SIL164
;
1469 tmds
->slave_addr
= 0x70 >> 1; /* 7 bit addressing */
1476 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder
*encoder
,
1477 struct radeon_encoder_ext_tmds
*tmds
)
1479 struct drm_device
*dev
= encoder
->base
.dev
;
1480 struct radeon_device
*rdev
= dev
->dev_private
;
1483 enum radeon_combios_ddc gpio
;
1484 struct radeon_i2c_bus_rec i2c_bus
;
1486 tmds
->i2c_bus
= NULL
;
1487 if (rdev
->flags
& RADEON_IS_IGP
) {
1488 i2c_bus
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
1489 tmds
->i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
1490 tmds
->dvo_chip
= DVO_SIL164
;
1491 tmds
->slave_addr
= 0x70 >> 1; /* 7 bit addressing */
1493 offset
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
1495 ver
= RBIOS8(offset
);
1496 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver
);
1497 tmds
->slave_addr
= RBIOS8(offset
+ 4 + 2);
1498 tmds
->slave_addr
>>= 1; /* 7 bit addressing */
1499 gpio
= RBIOS8(offset
+ 4 + 3);
1500 if (gpio
== DDC_LCD
) {
1502 i2c_bus
.valid
= true;
1503 i2c_bus
.hw_capable
= true;
1504 i2c_bus
.mm_i2c
= true;
1505 i2c_bus
.i2c_id
= 0xa0;
1507 i2c_bus
= combios_setup_i2c_bus(rdev
, gpio
, 0, 0);
1508 tmds
->i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
1512 if (!tmds
->i2c_bus
) {
1513 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1520 bool radeon_get_legacy_connector_info_from_table(struct drm_device
*dev
)
1522 struct radeon_device
*rdev
= dev
->dev_private
;
1523 struct radeon_i2c_bus_rec ddc_i2c
;
1524 struct radeon_hpd hpd
;
1526 rdev
->mode_info
.connector_table
= radeon_connector_table
;
1527 if (rdev
->mode_info
.connector_table
== CT_NONE
) {
1528 #ifdef CONFIG_PPC_PMAC
1529 if (of_machine_is_compatible("PowerBook3,3")) {
1530 /* powerbook with VGA */
1531 rdev
->mode_info
.connector_table
= CT_POWERBOOK_VGA
;
1532 } else if (of_machine_is_compatible("PowerBook3,4") ||
1533 of_machine_is_compatible("PowerBook3,5")) {
1534 /* powerbook with internal tmds */
1535 rdev
->mode_info
.connector_table
= CT_POWERBOOK_INTERNAL
;
1536 } else if (of_machine_is_compatible("PowerBook5,1") ||
1537 of_machine_is_compatible("PowerBook5,2") ||
1538 of_machine_is_compatible("PowerBook5,3") ||
1539 of_machine_is_compatible("PowerBook5,4") ||
1540 of_machine_is_compatible("PowerBook5,5")) {
1541 /* powerbook with external single link tmds (sil164) */
1542 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1543 } else if (of_machine_is_compatible("PowerBook5,6")) {
1544 /* powerbook with external dual or single link tmds */
1545 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1546 } else if (of_machine_is_compatible("PowerBook5,7") ||
1547 of_machine_is_compatible("PowerBook5,8") ||
1548 of_machine_is_compatible("PowerBook5,9")) {
1549 /* PowerBook6,2 ? */
1550 /* powerbook with external dual link tmds (sil1178?) */
1551 rdev
->mode_info
.connector_table
= CT_POWERBOOK_EXTERNAL
;
1552 } else if (of_machine_is_compatible("PowerBook4,1") ||
1553 of_machine_is_compatible("PowerBook4,2") ||
1554 of_machine_is_compatible("PowerBook4,3") ||
1555 of_machine_is_compatible("PowerBook6,3") ||
1556 of_machine_is_compatible("PowerBook6,5") ||
1557 of_machine_is_compatible("PowerBook6,7")) {
1559 rdev
->mode_info
.connector_table
= CT_IBOOK
;
1560 } else if (of_machine_is_compatible("PowerMac3,5")) {
1561 /* PowerMac G4 Silver radeon 7500 */
1562 rdev
->mode_info
.connector_table
= CT_MAC_G4_SILVER
;
1563 } else if (of_machine_is_compatible("PowerMac4,4")) {
1565 rdev
->mode_info
.connector_table
= CT_EMAC
;
1566 } else if (of_machine_is_compatible("PowerMac10,1")) {
1567 /* mini with internal tmds */
1568 rdev
->mode_info
.connector_table
= CT_MINI_INTERNAL
;
1569 } else if (of_machine_is_compatible("PowerMac10,2")) {
1570 /* mini with external tmds */
1571 rdev
->mode_info
.connector_table
= CT_MINI_EXTERNAL
;
1572 } else if (of_machine_is_compatible("PowerMac12,1")) {
1574 /* imac g5 isight */
1575 rdev
->mode_info
.connector_table
= CT_IMAC_G5_ISIGHT
;
1576 } else if ((rdev
->pdev
->device
== 0x4a48) &&
1577 (rdev
->pdev
->subsystem_vendor
== 0x1002) &&
1578 (rdev
->pdev
->subsystem_device
== 0x4a48)) {
1580 rdev
->mode_info
.connector_table
= CT_MAC_X800
;
1581 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1582 of_machine_is_compatible("PowerMac7,3")) &&
1583 (rdev
->pdev
->device
== 0x4150) &&
1584 (rdev
->pdev
->subsystem_vendor
== 0x1002) &&
1585 (rdev
->pdev
->subsystem_device
== 0x4150)) {
1586 /* Mac G5 tower 9600 */
1587 rdev
->mode_info
.connector_table
= CT_MAC_G5_9600
;
1588 } else if ((rdev
->pdev
->device
== 0x4c66) &&
1589 (rdev
->pdev
->subsystem_vendor
== 0x1002) &&
1590 (rdev
->pdev
->subsystem_device
== 0x4c66)) {
1591 /* SAM440ep RV250 embedded board */
1592 rdev
->mode_info
.connector_table
= CT_SAM440EP
;
1594 #endif /* CONFIG_PPC_PMAC */
1596 if (ASIC_IS_RN50(rdev
))
1597 rdev
->mode_info
.connector_table
= CT_RN50_POWER
;
1600 rdev
->mode_info
.connector_table
= CT_GENERIC
;
1603 switch (rdev
->mode_info
.connector_table
) {
1605 DRM_INFO("Connector Table: %d (generic)\n",
1606 rdev
->mode_info
.connector_table
);
1607 /* these are the most common settings */
1608 if (rdev
->flags
& RADEON_SINGLE_CRTC
) {
1609 /* VGA - primary dac */
1610 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1611 hpd
.hpd
= RADEON_HPD_NONE
;
1612 radeon_add_legacy_encoder(dev
,
1613 radeon_get_encoder_enum(dev
,
1614 ATOM_DEVICE_CRT1_SUPPORT
,
1616 ATOM_DEVICE_CRT1_SUPPORT
);
1617 radeon_add_legacy_connector(dev
, 0,
1618 ATOM_DEVICE_CRT1_SUPPORT
,
1619 DRM_MODE_CONNECTOR_VGA
,
1621 CONNECTOR_OBJECT_ID_VGA
,
1623 } else if (rdev
->flags
& RADEON_IS_MOBILITY
) {
1625 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_NONE_DETECTED
, 0, 0);
1626 hpd
.hpd
= RADEON_HPD_NONE
;
1627 radeon_add_legacy_encoder(dev
,
1628 radeon_get_encoder_enum(dev
,
1629 ATOM_DEVICE_LCD1_SUPPORT
,
1631 ATOM_DEVICE_LCD1_SUPPORT
);
1632 radeon_add_legacy_connector(dev
, 0,
1633 ATOM_DEVICE_LCD1_SUPPORT
,
1634 DRM_MODE_CONNECTOR_LVDS
,
1636 CONNECTOR_OBJECT_ID_LVDS
,
1639 /* VGA - primary dac */
1640 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1641 hpd
.hpd
= RADEON_HPD_NONE
;
1642 radeon_add_legacy_encoder(dev
,
1643 radeon_get_encoder_enum(dev
,
1644 ATOM_DEVICE_CRT1_SUPPORT
,
1646 ATOM_DEVICE_CRT1_SUPPORT
);
1647 radeon_add_legacy_connector(dev
, 1,
1648 ATOM_DEVICE_CRT1_SUPPORT
,
1649 DRM_MODE_CONNECTOR_VGA
,
1651 CONNECTOR_OBJECT_ID_VGA
,
1654 /* DVI-I - tv dac, int tmds */
1655 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1656 hpd
.hpd
= RADEON_HPD_1
;
1657 radeon_add_legacy_encoder(dev
,
1658 radeon_get_encoder_enum(dev
,
1659 ATOM_DEVICE_DFP1_SUPPORT
,
1661 ATOM_DEVICE_DFP1_SUPPORT
);
1662 radeon_add_legacy_encoder(dev
,
1663 radeon_get_encoder_enum(dev
,
1664 ATOM_DEVICE_CRT2_SUPPORT
,
1666 ATOM_DEVICE_CRT2_SUPPORT
);
1667 radeon_add_legacy_connector(dev
, 0,
1668 ATOM_DEVICE_DFP1_SUPPORT
|
1669 ATOM_DEVICE_CRT2_SUPPORT
,
1670 DRM_MODE_CONNECTOR_DVII
,
1672 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1675 /* VGA - primary dac */
1676 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1677 hpd
.hpd
= RADEON_HPD_NONE
;
1678 radeon_add_legacy_encoder(dev
,
1679 radeon_get_encoder_enum(dev
,
1680 ATOM_DEVICE_CRT1_SUPPORT
,
1682 ATOM_DEVICE_CRT1_SUPPORT
);
1683 radeon_add_legacy_connector(dev
, 1,
1684 ATOM_DEVICE_CRT1_SUPPORT
,
1685 DRM_MODE_CONNECTOR_VGA
,
1687 CONNECTOR_OBJECT_ID_VGA
,
1691 if (rdev
->family
!= CHIP_R100
&& rdev
->family
!= CHIP_R200
) {
1693 ddc_i2c
.valid
= false;
1694 hpd
.hpd
= RADEON_HPD_NONE
;
1695 radeon_add_legacy_encoder(dev
,
1696 radeon_get_encoder_enum(dev
,
1697 ATOM_DEVICE_TV1_SUPPORT
,
1699 ATOM_DEVICE_TV1_SUPPORT
);
1700 radeon_add_legacy_connector(dev
, 2,
1701 ATOM_DEVICE_TV1_SUPPORT
,
1702 DRM_MODE_CONNECTOR_SVIDEO
,
1704 CONNECTOR_OBJECT_ID_SVIDEO
,
1709 DRM_INFO("Connector Table: %d (ibook)\n",
1710 rdev
->mode_info
.connector_table
);
1712 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1713 hpd
.hpd
= RADEON_HPD_NONE
;
1714 radeon_add_legacy_encoder(dev
,
1715 radeon_get_encoder_enum(dev
,
1716 ATOM_DEVICE_LCD1_SUPPORT
,
1718 ATOM_DEVICE_LCD1_SUPPORT
);
1719 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1720 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1721 CONNECTOR_OBJECT_ID_LVDS
,
1724 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1725 hpd
.hpd
= RADEON_HPD_NONE
;
1726 radeon_add_legacy_encoder(dev
,
1727 radeon_get_encoder_enum(dev
,
1728 ATOM_DEVICE_CRT2_SUPPORT
,
1730 ATOM_DEVICE_CRT2_SUPPORT
);
1731 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1732 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1733 CONNECTOR_OBJECT_ID_VGA
,
1736 ddc_i2c
.valid
= false;
1737 hpd
.hpd
= RADEON_HPD_NONE
;
1738 radeon_add_legacy_encoder(dev
,
1739 radeon_get_encoder_enum(dev
,
1740 ATOM_DEVICE_TV1_SUPPORT
,
1742 ATOM_DEVICE_TV1_SUPPORT
);
1743 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1744 DRM_MODE_CONNECTOR_SVIDEO
,
1746 CONNECTOR_OBJECT_ID_SVIDEO
,
1749 case CT_POWERBOOK_EXTERNAL
:
1750 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1751 rdev
->mode_info
.connector_table
);
1753 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1754 hpd
.hpd
= RADEON_HPD_NONE
;
1755 radeon_add_legacy_encoder(dev
,
1756 radeon_get_encoder_enum(dev
,
1757 ATOM_DEVICE_LCD1_SUPPORT
,
1759 ATOM_DEVICE_LCD1_SUPPORT
);
1760 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1761 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1762 CONNECTOR_OBJECT_ID_LVDS
,
1764 /* DVI-I - primary dac, ext tmds */
1765 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1766 hpd
.hpd
= RADEON_HPD_2
; /* ??? */
1767 radeon_add_legacy_encoder(dev
,
1768 radeon_get_encoder_enum(dev
,
1769 ATOM_DEVICE_DFP2_SUPPORT
,
1771 ATOM_DEVICE_DFP2_SUPPORT
);
1772 radeon_add_legacy_encoder(dev
,
1773 radeon_get_encoder_enum(dev
,
1774 ATOM_DEVICE_CRT1_SUPPORT
,
1776 ATOM_DEVICE_CRT1_SUPPORT
);
1777 /* XXX some are SL */
1778 radeon_add_legacy_connector(dev
, 1,
1779 ATOM_DEVICE_DFP2_SUPPORT
|
1780 ATOM_DEVICE_CRT1_SUPPORT
,
1781 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1782 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
,
1785 ddc_i2c
.valid
= false;
1786 hpd
.hpd
= RADEON_HPD_NONE
;
1787 radeon_add_legacy_encoder(dev
,
1788 radeon_get_encoder_enum(dev
,
1789 ATOM_DEVICE_TV1_SUPPORT
,
1791 ATOM_DEVICE_TV1_SUPPORT
);
1792 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1793 DRM_MODE_CONNECTOR_SVIDEO
,
1795 CONNECTOR_OBJECT_ID_SVIDEO
,
1798 case CT_POWERBOOK_INTERNAL
:
1799 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1800 rdev
->mode_info
.connector_table
);
1802 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1803 hpd
.hpd
= RADEON_HPD_NONE
;
1804 radeon_add_legacy_encoder(dev
,
1805 radeon_get_encoder_enum(dev
,
1806 ATOM_DEVICE_LCD1_SUPPORT
,
1808 ATOM_DEVICE_LCD1_SUPPORT
);
1809 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1810 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1811 CONNECTOR_OBJECT_ID_LVDS
,
1813 /* DVI-I - primary dac, int tmds */
1814 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1815 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1816 radeon_add_legacy_encoder(dev
,
1817 radeon_get_encoder_enum(dev
,
1818 ATOM_DEVICE_DFP1_SUPPORT
,
1820 ATOM_DEVICE_DFP1_SUPPORT
);
1821 radeon_add_legacy_encoder(dev
,
1822 radeon_get_encoder_enum(dev
,
1823 ATOM_DEVICE_CRT1_SUPPORT
,
1825 ATOM_DEVICE_CRT1_SUPPORT
);
1826 radeon_add_legacy_connector(dev
, 1,
1827 ATOM_DEVICE_DFP1_SUPPORT
|
1828 ATOM_DEVICE_CRT1_SUPPORT
,
1829 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1830 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1833 ddc_i2c
.valid
= false;
1834 hpd
.hpd
= RADEON_HPD_NONE
;
1835 radeon_add_legacy_encoder(dev
,
1836 radeon_get_encoder_enum(dev
,
1837 ATOM_DEVICE_TV1_SUPPORT
,
1839 ATOM_DEVICE_TV1_SUPPORT
);
1840 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1841 DRM_MODE_CONNECTOR_SVIDEO
,
1843 CONNECTOR_OBJECT_ID_SVIDEO
,
1846 case CT_POWERBOOK_VGA
:
1847 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1848 rdev
->mode_info
.connector_table
);
1850 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1851 hpd
.hpd
= RADEON_HPD_NONE
;
1852 radeon_add_legacy_encoder(dev
,
1853 radeon_get_encoder_enum(dev
,
1854 ATOM_DEVICE_LCD1_SUPPORT
,
1856 ATOM_DEVICE_LCD1_SUPPORT
);
1857 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
1858 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
1859 CONNECTOR_OBJECT_ID_LVDS
,
1861 /* VGA - primary dac */
1862 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
1863 hpd
.hpd
= RADEON_HPD_NONE
;
1864 radeon_add_legacy_encoder(dev
,
1865 radeon_get_encoder_enum(dev
,
1866 ATOM_DEVICE_CRT1_SUPPORT
,
1868 ATOM_DEVICE_CRT1_SUPPORT
);
1869 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT1_SUPPORT
,
1870 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1871 CONNECTOR_OBJECT_ID_VGA
,
1874 ddc_i2c
.valid
= false;
1875 hpd
.hpd
= RADEON_HPD_NONE
;
1876 radeon_add_legacy_encoder(dev
,
1877 radeon_get_encoder_enum(dev
,
1878 ATOM_DEVICE_TV1_SUPPORT
,
1880 ATOM_DEVICE_TV1_SUPPORT
);
1881 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1882 DRM_MODE_CONNECTOR_SVIDEO
,
1884 CONNECTOR_OBJECT_ID_SVIDEO
,
1887 case CT_MINI_EXTERNAL
:
1888 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1889 rdev
->mode_info
.connector_table
);
1890 /* DVI-I - tv dac, ext tmds */
1891 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
1892 hpd
.hpd
= RADEON_HPD_2
; /* ??? */
1893 radeon_add_legacy_encoder(dev
,
1894 radeon_get_encoder_enum(dev
,
1895 ATOM_DEVICE_DFP2_SUPPORT
,
1897 ATOM_DEVICE_DFP2_SUPPORT
);
1898 radeon_add_legacy_encoder(dev
,
1899 radeon_get_encoder_enum(dev
,
1900 ATOM_DEVICE_CRT2_SUPPORT
,
1902 ATOM_DEVICE_CRT2_SUPPORT
);
1903 /* XXX are any DL? */
1904 radeon_add_legacy_connector(dev
, 0,
1905 ATOM_DEVICE_DFP2_SUPPORT
|
1906 ATOM_DEVICE_CRT2_SUPPORT
,
1907 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1908 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1911 ddc_i2c
.valid
= false;
1912 hpd
.hpd
= RADEON_HPD_NONE
;
1913 radeon_add_legacy_encoder(dev
,
1914 radeon_get_encoder_enum(dev
,
1915 ATOM_DEVICE_TV1_SUPPORT
,
1917 ATOM_DEVICE_TV1_SUPPORT
);
1918 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_TV1_SUPPORT
,
1919 DRM_MODE_CONNECTOR_SVIDEO
,
1921 CONNECTOR_OBJECT_ID_SVIDEO
,
1924 case CT_MINI_INTERNAL
:
1925 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1926 rdev
->mode_info
.connector_table
);
1927 /* DVI-I - tv dac, int tmds */
1928 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
1929 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1930 radeon_add_legacy_encoder(dev
,
1931 radeon_get_encoder_enum(dev
,
1932 ATOM_DEVICE_DFP1_SUPPORT
,
1934 ATOM_DEVICE_DFP1_SUPPORT
);
1935 radeon_add_legacy_encoder(dev
,
1936 radeon_get_encoder_enum(dev
,
1937 ATOM_DEVICE_CRT2_SUPPORT
,
1939 ATOM_DEVICE_CRT2_SUPPORT
);
1940 radeon_add_legacy_connector(dev
, 0,
1941 ATOM_DEVICE_DFP1_SUPPORT
|
1942 ATOM_DEVICE_CRT2_SUPPORT
,
1943 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
1944 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
1947 ddc_i2c
.valid
= false;
1948 hpd
.hpd
= RADEON_HPD_NONE
;
1949 radeon_add_legacy_encoder(dev
,
1950 radeon_get_encoder_enum(dev
,
1951 ATOM_DEVICE_TV1_SUPPORT
,
1953 ATOM_DEVICE_TV1_SUPPORT
);
1954 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_TV1_SUPPORT
,
1955 DRM_MODE_CONNECTOR_SVIDEO
,
1957 CONNECTOR_OBJECT_ID_SVIDEO
,
1960 case CT_IMAC_G5_ISIGHT
:
1961 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1962 rdev
->mode_info
.connector_table
);
1963 /* DVI-D - int tmds */
1964 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
1965 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
1966 radeon_add_legacy_encoder(dev
,
1967 radeon_get_encoder_enum(dev
,
1968 ATOM_DEVICE_DFP1_SUPPORT
,
1970 ATOM_DEVICE_DFP1_SUPPORT
);
1971 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_DFP1_SUPPORT
,
1972 DRM_MODE_CONNECTOR_DVID
, &ddc_i2c
,
1973 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
,
1976 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
1977 hpd
.hpd
= RADEON_HPD_NONE
;
1978 radeon_add_legacy_encoder(dev
,
1979 radeon_get_encoder_enum(dev
,
1980 ATOM_DEVICE_CRT2_SUPPORT
,
1982 ATOM_DEVICE_CRT2_SUPPORT
);
1983 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
1984 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
1985 CONNECTOR_OBJECT_ID_VGA
,
1988 ddc_i2c
.valid
= false;
1989 hpd
.hpd
= RADEON_HPD_NONE
;
1990 radeon_add_legacy_encoder(dev
,
1991 radeon_get_encoder_enum(dev
,
1992 ATOM_DEVICE_TV1_SUPPORT
,
1994 ATOM_DEVICE_TV1_SUPPORT
);
1995 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
1996 DRM_MODE_CONNECTOR_SVIDEO
,
1998 CONNECTOR_OBJECT_ID_SVIDEO
,
2002 DRM_INFO("Connector Table: %d (emac)\n",
2003 rdev
->mode_info
.connector_table
);
2004 /* VGA - primary dac */
2005 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
2006 hpd
.hpd
= RADEON_HPD_NONE
;
2007 radeon_add_legacy_encoder(dev
,
2008 radeon_get_encoder_enum(dev
,
2009 ATOM_DEVICE_CRT1_SUPPORT
,
2011 ATOM_DEVICE_CRT1_SUPPORT
);
2012 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_CRT1_SUPPORT
,
2013 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
2014 CONNECTOR_OBJECT_ID_VGA
,
2017 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
2018 hpd
.hpd
= RADEON_HPD_NONE
;
2019 radeon_add_legacy_encoder(dev
,
2020 radeon_get_encoder_enum(dev
,
2021 ATOM_DEVICE_CRT2_SUPPORT
,
2023 ATOM_DEVICE_CRT2_SUPPORT
);
2024 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
2025 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
2026 CONNECTOR_OBJECT_ID_VGA
,
2029 ddc_i2c
.valid
= false;
2030 hpd
.hpd
= RADEON_HPD_NONE
;
2031 radeon_add_legacy_encoder(dev
,
2032 radeon_get_encoder_enum(dev
,
2033 ATOM_DEVICE_TV1_SUPPORT
,
2035 ATOM_DEVICE_TV1_SUPPORT
);
2036 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
2037 DRM_MODE_CONNECTOR_SVIDEO
,
2039 CONNECTOR_OBJECT_ID_SVIDEO
,
2043 DRM_INFO("Connector Table: %d (rn50-power)\n",
2044 rdev
->mode_info
.connector_table
);
2045 /* VGA - primary dac */
2046 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
2047 hpd
.hpd
= RADEON_HPD_NONE
;
2048 radeon_add_legacy_encoder(dev
,
2049 radeon_get_encoder_enum(dev
,
2050 ATOM_DEVICE_CRT1_SUPPORT
,
2052 ATOM_DEVICE_CRT1_SUPPORT
);
2053 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_CRT1_SUPPORT
,
2054 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
2055 CONNECTOR_OBJECT_ID_VGA
,
2057 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_CRT2
, 0, 0);
2058 hpd
.hpd
= RADEON_HPD_NONE
;
2059 radeon_add_legacy_encoder(dev
,
2060 radeon_get_encoder_enum(dev
,
2061 ATOM_DEVICE_CRT2_SUPPORT
,
2063 ATOM_DEVICE_CRT2_SUPPORT
);
2064 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT2_SUPPORT
,
2065 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
2066 CONNECTOR_OBJECT_ID_VGA
,
2070 DRM_INFO("Connector Table: %d (mac x800)\n",
2071 rdev
->mode_info
.connector_table
);
2072 /* DVI - primary dac, internal tmds */
2073 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
2074 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
2075 radeon_add_legacy_encoder(dev
,
2076 radeon_get_encoder_enum(dev
,
2077 ATOM_DEVICE_DFP1_SUPPORT
,
2079 ATOM_DEVICE_DFP1_SUPPORT
);
2080 radeon_add_legacy_encoder(dev
,
2081 radeon_get_encoder_enum(dev
,
2082 ATOM_DEVICE_CRT1_SUPPORT
,
2084 ATOM_DEVICE_CRT1_SUPPORT
);
2085 radeon_add_legacy_connector(dev
, 0,
2086 ATOM_DEVICE_DFP1_SUPPORT
|
2087 ATOM_DEVICE_CRT1_SUPPORT
,
2088 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
2089 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
2091 /* DVI - tv dac, dvo */
2092 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
2093 hpd
.hpd
= RADEON_HPD_2
; /* ??? */
2094 radeon_add_legacy_encoder(dev
,
2095 radeon_get_encoder_enum(dev
,
2096 ATOM_DEVICE_DFP2_SUPPORT
,
2098 ATOM_DEVICE_DFP2_SUPPORT
);
2099 radeon_add_legacy_encoder(dev
,
2100 radeon_get_encoder_enum(dev
,
2101 ATOM_DEVICE_CRT2_SUPPORT
,
2103 ATOM_DEVICE_CRT2_SUPPORT
);
2104 radeon_add_legacy_connector(dev
, 1,
2105 ATOM_DEVICE_DFP2_SUPPORT
|
2106 ATOM_DEVICE_CRT2_SUPPORT
,
2107 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
2108 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
,
2111 case CT_MAC_G5_9600
:
2112 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2113 rdev
->mode_info
.connector_table
);
2114 /* DVI - tv dac, dvo */
2115 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
2116 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
2117 radeon_add_legacy_encoder(dev
,
2118 radeon_get_encoder_enum(dev
,
2119 ATOM_DEVICE_DFP2_SUPPORT
,
2121 ATOM_DEVICE_DFP2_SUPPORT
);
2122 radeon_add_legacy_encoder(dev
,
2123 radeon_get_encoder_enum(dev
,
2124 ATOM_DEVICE_CRT2_SUPPORT
,
2126 ATOM_DEVICE_CRT2_SUPPORT
);
2127 radeon_add_legacy_connector(dev
, 0,
2128 ATOM_DEVICE_DFP2_SUPPORT
|
2129 ATOM_DEVICE_CRT2_SUPPORT
,
2130 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
2131 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
2133 /* ADC - primary dac, internal tmds */
2134 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
2135 hpd
.hpd
= RADEON_HPD_2
; /* ??? */
2136 radeon_add_legacy_encoder(dev
,
2137 radeon_get_encoder_enum(dev
,
2138 ATOM_DEVICE_DFP1_SUPPORT
,
2140 ATOM_DEVICE_DFP1_SUPPORT
);
2141 radeon_add_legacy_encoder(dev
,
2142 radeon_get_encoder_enum(dev
,
2143 ATOM_DEVICE_CRT1_SUPPORT
,
2145 ATOM_DEVICE_CRT1_SUPPORT
);
2146 radeon_add_legacy_connector(dev
, 1,
2147 ATOM_DEVICE_DFP1_SUPPORT
|
2148 ATOM_DEVICE_CRT1_SUPPORT
,
2149 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
2150 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
2153 ddc_i2c
.valid
= false;
2154 hpd
.hpd
= RADEON_HPD_NONE
;
2155 radeon_add_legacy_encoder(dev
,
2156 radeon_get_encoder_enum(dev
,
2157 ATOM_DEVICE_TV1_SUPPORT
,
2159 ATOM_DEVICE_TV1_SUPPORT
);
2160 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
2161 DRM_MODE_CONNECTOR_SVIDEO
,
2163 CONNECTOR_OBJECT_ID_SVIDEO
,
2167 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2168 rdev
->mode_info
.connector_table
);
2170 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_NONE_DETECTED
, 0, 0);
2171 hpd
.hpd
= RADEON_HPD_NONE
;
2172 radeon_add_legacy_encoder(dev
,
2173 radeon_get_encoder_enum(dev
,
2174 ATOM_DEVICE_LCD1_SUPPORT
,
2176 ATOM_DEVICE_LCD1_SUPPORT
);
2177 radeon_add_legacy_connector(dev
, 0, ATOM_DEVICE_LCD1_SUPPORT
,
2178 DRM_MODE_CONNECTOR_LVDS
, &ddc_i2c
,
2179 CONNECTOR_OBJECT_ID_LVDS
,
2181 /* DVI-I - secondary dac, int tmds */
2182 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
2183 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
2184 radeon_add_legacy_encoder(dev
,
2185 radeon_get_encoder_enum(dev
,
2186 ATOM_DEVICE_DFP1_SUPPORT
,
2188 ATOM_DEVICE_DFP1_SUPPORT
);
2189 radeon_add_legacy_encoder(dev
,
2190 radeon_get_encoder_enum(dev
,
2191 ATOM_DEVICE_CRT2_SUPPORT
,
2193 ATOM_DEVICE_CRT2_SUPPORT
);
2194 radeon_add_legacy_connector(dev
, 1,
2195 ATOM_DEVICE_DFP1_SUPPORT
|
2196 ATOM_DEVICE_CRT2_SUPPORT
,
2197 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
2198 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
2200 /* VGA - primary dac */
2201 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
2202 hpd
.hpd
= RADEON_HPD_NONE
;
2203 radeon_add_legacy_encoder(dev
,
2204 radeon_get_encoder_enum(dev
,
2205 ATOM_DEVICE_CRT1_SUPPORT
,
2207 ATOM_DEVICE_CRT1_SUPPORT
);
2208 radeon_add_legacy_connector(dev
, 2,
2209 ATOM_DEVICE_CRT1_SUPPORT
,
2210 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
2211 CONNECTOR_OBJECT_ID_VGA
,
2214 ddc_i2c
.valid
= false;
2215 hpd
.hpd
= RADEON_HPD_NONE
;
2216 radeon_add_legacy_encoder(dev
,
2217 radeon_get_encoder_enum(dev
,
2218 ATOM_DEVICE_TV1_SUPPORT
,
2220 ATOM_DEVICE_TV1_SUPPORT
);
2221 radeon_add_legacy_connector(dev
, 3, ATOM_DEVICE_TV1_SUPPORT
,
2222 DRM_MODE_CONNECTOR_SVIDEO
,
2224 CONNECTOR_OBJECT_ID_SVIDEO
,
2227 case CT_MAC_G4_SILVER
:
2228 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2229 rdev
->mode_info
.connector_table
);
2230 /* DVI-I - tv dac, int tmds */
2231 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
2232 hpd
.hpd
= RADEON_HPD_1
; /* ??? */
2233 radeon_add_legacy_encoder(dev
,
2234 radeon_get_encoder_enum(dev
,
2235 ATOM_DEVICE_DFP1_SUPPORT
,
2237 ATOM_DEVICE_DFP1_SUPPORT
);
2238 radeon_add_legacy_encoder(dev
,
2239 radeon_get_encoder_enum(dev
,
2240 ATOM_DEVICE_CRT2_SUPPORT
,
2242 ATOM_DEVICE_CRT2_SUPPORT
);
2243 radeon_add_legacy_connector(dev
, 0,
2244 ATOM_DEVICE_DFP1_SUPPORT
|
2245 ATOM_DEVICE_CRT2_SUPPORT
,
2246 DRM_MODE_CONNECTOR_DVII
, &ddc_i2c
,
2247 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
2249 /* VGA - primary dac */
2250 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
2251 hpd
.hpd
= RADEON_HPD_NONE
;
2252 radeon_add_legacy_encoder(dev
,
2253 radeon_get_encoder_enum(dev
,
2254 ATOM_DEVICE_CRT1_SUPPORT
,
2256 ATOM_DEVICE_CRT1_SUPPORT
);
2257 radeon_add_legacy_connector(dev
, 1, ATOM_DEVICE_CRT1_SUPPORT
,
2258 DRM_MODE_CONNECTOR_VGA
, &ddc_i2c
,
2259 CONNECTOR_OBJECT_ID_VGA
,
2262 ddc_i2c
.valid
= false;
2263 hpd
.hpd
= RADEON_HPD_NONE
;
2264 radeon_add_legacy_encoder(dev
,
2265 radeon_get_encoder_enum(dev
,
2266 ATOM_DEVICE_TV1_SUPPORT
,
2268 ATOM_DEVICE_TV1_SUPPORT
);
2269 radeon_add_legacy_connector(dev
, 2, ATOM_DEVICE_TV1_SUPPORT
,
2270 DRM_MODE_CONNECTOR_SVIDEO
,
2272 CONNECTOR_OBJECT_ID_SVIDEO
,
2276 DRM_INFO("Connector table: %d (invalid)\n",
2277 rdev
->mode_info
.connector_table
);
2281 radeon_link_encoder_connector(dev
);
2286 static bool radeon_apply_legacy_quirks(struct drm_device
*dev
,
2288 enum radeon_combios_connector
2290 struct radeon_i2c_bus_rec
*ddc_i2c
,
2291 struct radeon_hpd
*hpd
)
2294 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2295 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2296 if (dev
->pdev
->device
== 0x515e &&
2297 dev
->pdev
->subsystem_vendor
== 0x1014) {
2298 if (*legacy_connector
== CONNECTOR_CRT_LEGACY
&&
2299 ddc_i2c
->mask_clk_reg
== RADEON_GPIO_CRT2_DDC
)
2303 /* X300 card with extra non-existent DVI port */
2304 if (dev
->pdev
->device
== 0x5B60 &&
2305 dev
->pdev
->subsystem_vendor
== 0x17af &&
2306 dev
->pdev
->subsystem_device
== 0x201e && bios_index
== 2) {
2307 if (*legacy_connector
== CONNECTOR_DVI_I_LEGACY
)
2314 static bool radeon_apply_legacy_tv_quirks(struct drm_device
*dev
)
2316 /* Acer 5102 has non-existent TV port */
2317 if (dev
->pdev
->device
== 0x5975 &&
2318 dev
->pdev
->subsystem_vendor
== 0x1025 &&
2319 dev
->pdev
->subsystem_device
== 0x009f)
2322 /* HP dc5750 has non-existent TV port */
2323 if (dev
->pdev
->device
== 0x5974 &&
2324 dev
->pdev
->subsystem_vendor
== 0x103c &&
2325 dev
->pdev
->subsystem_device
== 0x280a)
2328 /* MSI S270 has non-existent TV port */
2329 if (dev
->pdev
->device
== 0x5955 &&
2330 dev
->pdev
->subsystem_vendor
== 0x1462 &&
2331 dev
->pdev
->subsystem_device
== 0x0131)
2337 static uint16_t combios_check_dl_dvi(struct drm_device
*dev
, int is_dvi_d
)
2339 struct radeon_device
*rdev
= dev
->dev_private
;
2340 uint32_t ext_tmds_info
;
2342 if (rdev
->flags
& RADEON_IS_IGP
) {
2344 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
2346 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2348 ext_tmds_info
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
2349 if (ext_tmds_info
) {
2350 uint8_t rev
= RBIOS8(ext_tmds_info
);
2351 uint8_t flags
= RBIOS8(ext_tmds_info
+ 4 + 5);
2354 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
2356 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
2360 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
2362 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
2367 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
2369 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2372 bool radeon_get_legacy_connector_info_from_bios(struct drm_device
*dev
)
2374 struct radeon_device
*rdev
= dev
->dev_private
;
2375 uint32_t conn_info
, entry
, devices
;
2376 uint16_t tmp
, connector_object_id
;
2377 enum radeon_combios_ddc ddc_type
;
2378 enum radeon_combios_connector connector
;
2380 struct radeon_i2c_bus_rec ddc_i2c
;
2381 struct radeon_hpd hpd
;
2383 conn_info
= combios_get_table_offset(dev
, COMBIOS_CONNECTOR_INFO_TABLE
);
2385 for (i
= 0; i
< 4; i
++) {
2386 entry
= conn_info
+ 2 + i
* 2;
2388 if (!RBIOS16(entry
))
2391 tmp
= RBIOS16(entry
);
2393 connector
= (tmp
>> 12) & 0xf;
2395 ddc_type
= (tmp
>> 8) & 0xf;
2397 ddc_i2c
= radeon_combios_get_i2c_info_from_table(rdev
);
2399 ddc_i2c
= combios_setup_i2c_bus(rdev
, ddc_type
, 0, 0);
2401 switch (connector
) {
2402 case CONNECTOR_PROPRIETARY_LEGACY
:
2403 case CONNECTOR_DVI_I_LEGACY
:
2404 case CONNECTOR_DVI_D_LEGACY
:
2405 if ((tmp
>> 4) & 0x1)
2406 hpd
.hpd
= RADEON_HPD_2
;
2408 hpd
.hpd
= RADEON_HPD_1
;
2411 hpd
.hpd
= RADEON_HPD_NONE
;
2415 if (!radeon_apply_legacy_quirks(dev
, i
, &connector
,
2419 switch (connector
) {
2420 case CONNECTOR_PROPRIETARY_LEGACY
:
2421 if ((tmp
>> 4) & 0x1)
2422 devices
= ATOM_DEVICE_DFP2_SUPPORT
;
2424 devices
= ATOM_DEVICE_DFP1_SUPPORT
;
2425 radeon_add_legacy_encoder(dev
,
2426 radeon_get_encoder_enum
2429 radeon_add_legacy_connector(dev
, i
, devices
,
2430 legacy_connector_convert
2433 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
,
2436 case CONNECTOR_CRT_LEGACY
:
2438 devices
= ATOM_DEVICE_CRT2_SUPPORT
;
2439 radeon_add_legacy_encoder(dev
,
2440 radeon_get_encoder_enum
2442 ATOM_DEVICE_CRT2_SUPPORT
,
2444 ATOM_DEVICE_CRT2_SUPPORT
);
2446 devices
= ATOM_DEVICE_CRT1_SUPPORT
;
2447 radeon_add_legacy_encoder(dev
,
2448 radeon_get_encoder_enum
2450 ATOM_DEVICE_CRT1_SUPPORT
,
2452 ATOM_DEVICE_CRT1_SUPPORT
);
2454 radeon_add_legacy_connector(dev
,
2457 legacy_connector_convert
2460 CONNECTOR_OBJECT_ID_VGA
,
2463 case CONNECTOR_DVI_I_LEGACY
:
2466 devices
|= ATOM_DEVICE_CRT2_SUPPORT
;
2467 radeon_add_legacy_encoder(dev
,
2468 radeon_get_encoder_enum
2470 ATOM_DEVICE_CRT2_SUPPORT
,
2472 ATOM_DEVICE_CRT2_SUPPORT
);
2474 devices
|= ATOM_DEVICE_CRT1_SUPPORT
;
2475 radeon_add_legacy_encoder(dev
,
2476 radeon_get_encoder_enum
2478 ATOM_DEVICE_CRT1_SUPPORT
,
2480 ATOM_DEVICE_CRT1_SUPPORT
);
2482 /* RV100 board with external TDMS bit mis-set.
2483 * Actually uses internal TMDS, clear the bit.
2485 if (dev
->pdev
->device
== 0x5159 &&
2486 dev
->pdev
->subsystem_vendor
== 0x1014 &&
2487 dev
->pdev
->subsystem_device
== 0x029A) {
2490 if ((tmp
>> 4) & 0x1) {
2491 devices
|= ATOM_DEVICE_DFP2_SUPPORT
;
2492 radeon_add_legacy_encoder(dev
,
2493 radeon_get_encoder_enum
2495 ATOM_DEVICE_DFP2_SUPPORT
,
2497 ATOM_DEVICE_DFP2_SUPPORT
);
2498 connector_object_id
= combios_check_dl_dvi(dev
, 0);
2500 devices
|= ATOM_DEVICE_DFP1_SUPPORT
;
2501 radeon_add_legacy_encoder(dev
,
2502 radeon_get_encoder_enum
2504 ATOM_DEVICE_DFP1_SUPPORT
,
2506 ATOM_DEVICE_DFP1_SUPPORT
);
2507 connector_object_id
= CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2509 radeon_add_legacy_connector(dev
,
2512 legacy_connector_convert
2515 connector_object_id
,
2518 case CONNECTOR_DVI_D_LEGACY
:
2519 if ((tmp
>> 4) & 0x1) {
2520 devices
= ATOM_DEVICE_DFP2_SUPPORT
;
2521 connector_object_id
= combios_check_dl_dvi(dev
, 1);
2523 devices
= ATOM_DEVICE_DFP1_SUPPORT
;
2524 connector_object_id
= CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
2526 radeon_add_legacy_encoder(dev
,
2527 radeon_get_encoder_enum
2530 radeon_add_legacy_connector(dev
, i
, devices
,
2531 legacy_connector_convert
2534 connector_object_id
,
2537 case CONNECTOR_CTV_LEGACY
:
2538 case CONNECTOR_STV_LEGACY
:
2539 radeon_add_legacy_encoder(dev
,
2540 radeon_get_encoder_enum
2542 ATOM_DEVICE_TV1_SUPPORT
,
2544 ATOM_DEVICE_TV1_SUPPORT
);
2545 radeon_add_legacy_connector(dev
, i
,
2546 ATOM_DEVICE_TV1_SUPPORT
,
2547 legacy_connector_convert
2550 CONNECTOR_OBJECT_ID_SVIDEO
,
2554 DRM_ERROR("Unknown connector type: %d\n",
2561 uint16_t tmds_info
=
2562 combios_get_table_offset(dev
, COMBIOS_DFP_INFO_TABLE
);
2564 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2566 radeon_add_legacy_encoder(dev
,
2567 radeon_get_encoder_enum(dev
,
2568 ATOM_DEVICE_CRT1_SUPPORT
,
2570 ATOM_DEVICE_CRT1_SUPPORT
);
2571 radeon_add_legacy_encoder(dev
,
2572 radeon_get_encoder_enum(dev
,
2573 ATOM_DEVICE_DFP1_SUPPORT
,
2575 ATOM_DEVICE_DFP1_SUPPORT
);
2577 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_DVI
, 0, 0);
2578 hpd
.hpd
= RADEON_HPD_1
;
2579 radeon_add_legacy_connector(dev
,
2581 ATOM_DEVICE_CRT1_SUPPORT
|
2582 ATOM_DEVICE_DFP1_SUPPORT
,
2583 DRM_MODE_CONNECTOR_DVII
,
2585 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
,
2589 combios_get_table_offset(dev
, COMBIOS_CRT_INFO_TABLE
);
2590 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2592 radeon_add_legacy_encoder(dev
,
2593 radeon_get_encoder_enum(dev
,
2594 ATOM_DEVICE_CRT1_SUPPORT
,
2596 ATOM_DEVICE_CRT1_SUPPORT
);
2597 ddc_i2c
= combios_setup_i2c_bus(rdev
, DDC_VGA
, 0, 0);
2598 hpd
.hpd
= RADEON_HPD_NONE
;
2599 radeon_add_legacy_connector(dev
,
2601 ATOM_DEVICE_CRT1_SUPPORT
,
2602 DRM_MODE_CONNECTOR_VGA
,
2604 CONNECTOR_OBJECT_ID_VGA
,
2607 DRM_DEBUG_KMS("No connector info found\n");
2613 if (rdev
->flags
& RADEON_IS_MOBILITY
|| rdev
->flags
& RADEON_IS_IGP
) {
2615 combios_get_table_offset(dev
, COMBIOS_LCD_INFO_TABLE
);
2617 uint16_t lcd_ddc_info
=
2618 combios_get_table_offset(dev
,
2619 COMBIOS_LCD_DDC_INFO_TABLE
);
2621 radeon_add_legacy_encoder(dev
,
2622 radeon_get_encoder_enum(dev
,
2623 ATOM_DEVICE_LCD1_SUPPORT
,
2625 ATOM_DEVICE_LCD1_SUPPORT
);
2628 ddc_type
= RBIOS8(lcd_ddc_info
+ 2);
2632 combios_setup_i2c_bus(rdev
,
2634 RBIOS32(lcd_ddc_info
+ 3),
2635 RBIOS32(lcd_ddc_info
+ 7));
2636 radeon_i2c_add(rdev
, &ddc_i2c
, "LCD");
2640 combios_setup_i2c_bus(rdev
,
2642 RBIOS32(lcd_ddc_info
+ 3),
2643 RBIOS32(lcd_ddc_info
+ 7));
2644 radeon_i2c_add(rdev
, &ddc_i2c
, "LCD");
2648 combios_setup_i2c_bus(rdev
, ddc_type
, 0, 0);
2651 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2653 ddc_i2c
.valid
= false;
2655 hpd
.hpd
= RADEON_HPD_NONE
;
2656 radeon_add_legacy_connector(dev
,
2658 ATOM_DEVICE_LCD1_SUPPORT
,
2659 DRM_MODE_CONNECTOR_LVDS
,
2661 CONNECTOR_OBJECT_ID_LVDS
,
2666 /* check TV table */
2667 if (rdev
->family
!= CHIP_R100
&& rdev
->family
!= CHIP_R200
) {
2669 combios_get_table_offset(dev
, COMBIOS_TV_INFO_TABLE
);
2671 if (RBIOS8(tv_info
+ 6) == 'T') {
2672 if (radeon_apply_legacy_tv_quirks(dev
)) {
2673 hpd
.hpd
= RADEON_HPD_NONE
;
2674 ddc_i2c
.valid
= false;
2675 radeon_add_legacy_encoder(dev
,
2676 radeon_get_encoder_enum
2678 ATOM_DEVICE_TV1_SUPPORT
,
2680 ATOM_DEVICE_TV1_SUPPORT
);
2681 radeon_add_legacy_connector(dev
, 6,
2682 ATOM_DEVICE_TV1_SUPPORT
,
2683 DRM_MODE_CONNECTOR_SVIDEO
,
2685 CONNECTOR_OBJECT_ID_SVIDEO
,
2692 radeon_link_encoder_connector(dev
);
2697 static const char *thermal_controller_names
[] = {
2703 void radeon_combios_get_power_modes(struct radeon_device
*rdev
)
2705 struct drm_device
*dev
= rdev
->ddev
;
2706 u16 offset
, misc
, misc2
= 0;
2707 u8 rev
, blocks
, tmp
;
2708 int state_index
= 0;
2709 struct radeon_i2c_bus_rec i2c_bus
;
2711 rdev
->pm
.default_power_state_index
= -1;
2713 /* allocate 2 power states */
2714 rdev
->pm
.power_state
= kzalloc(sizeof(struct radeon_power_state
) * 2, GFP_KERNEL
);
2715 if (rdev
->pm
.power_state
) {
2716 /* allocate 1 clock mode per state */
2717 rdev
->pm
.power_state
[0].clock_info
=
2718 kzalloc(sizeof(struct radeon_pm_clock_info
) * 1, GFP_KERNEL
);
2719 rdev
->pm
.power_state
[1].clock_info
=
2720 kzalloc(sizeof(struct radeon_pm_clock_info
) * 1, GFP_KERNEL
);
2721 if (!rdev
->pm
.power_state
[0].clock_info
||
2722 !rdev
->pm
.power_state
[1].clock_info
)
2727 /* check for a thermal chip */
2728 offset
= combios_get_table_offset(dev
, COMBIOS_OVERDRIVE_INFO_TABLE
);
2730 u8 thermal_controller
= 0, gpio
= 0, i2c_addr
= 0, clk_bit
= 0, data_bit
= 0;
2732 rev
= RBIOS8(offset
);
2735 thermal_controller
= RBIOS8(offset
+ 3);
2736 gpio
= RBIOS8(offset
+ 4) & 0x3f;
2737 i2c_addr
= RBIOS8(offset
+ 5);
2738 } else if (rev
== 1) {
2739 thermal_controller
= RBIOS8(offset
+ 4);
2740 gpio
= RBIOS8(offset
+ 5) & 0x3f;
2741 i2c_addr
= RBIOS8(offset
+ 6);
2742 } else if (rev
== 2) {
2743 thermal_controller
= RBIOS8(offset
+ 4);
2744 gpio
= RBIOS8(offset
+ 5) & 0x3f;
2745 i2c_addr
= RBIOS8(offset
+ 6);
2746 clk_bit
= RBIOS8(offset
+ 0xa);
2747 data_bit
= RBIOS8(offset
+ 0xb);
2749 if ((thermal_controller
> 0) && (thermal_controller
< 3)) {
2750 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2751 thermal_controller_names
[thermal_controller
],
2753 if (gpio
== DDC_LCD
) {
2755 i2c_bus
.valid
= true;
2756 i2c_bus
.hw_capable
= true;
2757 i2c_bus
.mm_i2c
= true;
2758 i2c_bus
.i2c_id
= 0xa0;
2759 } else if (gpio
== DDC_GPIO
)
2760 i2c_bus
= combios_setup_i2c_bus(rdev
, gpio
, 1 << clk_bit
, 1 << data_bit
);
2762 i2c_bus
= combios_setup_i2c_bus(rdev
, gpio
, 0, 0);
2763 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
2764 if (rdev
->pm
.i2c_bus
) {
2765 struct i2c_board_info info
= { };
2766 const char *name
= thermal_controller_names
[thermal_controller
];
2767 info
.addr
= i2c_addr
>> 1;
2768 strlcpy(info
.type
, name
, sizeof(info
.type
));
2769 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
2773 /* boards with a thermal chip, but no overdrive table */
2775 /* Asus 9600xt has an f75375 on the monid bus */
2776 if ((dev
->pdev
->device
== 0x4152) &&
2777 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
2778 (dev
->pdev
->subsystem_device
== 0xc002)) {
2779 i2c_bus
= combios_setup_i2c_bus(rdev
, DDC_MONID
, 0, 0);
2780 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
2781 if (rdev
->pm
.i2c_bus
) {
2782 struct i2c_board_info info
= { };
2783 const char *name
= "f75375";
2785 strlcpy(info
.type
, name
, sizeof(info
.type
));
2786 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
2787 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2793 if (rdev
->flags
& RADEON_IS_MOBILITY
) {
2794 offset
= combios_get_table_offset(dev
, COMBIOS_POWERPLAY_INFO_TABLE
);
2796 rev
= RBIOS8(offset
);
2797 blocks
= RBIOS8(offset
+ 0x2);
2798 /* power mode 0 tends to be the only valid one */
2799 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2800 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= RBIOS32(offset
+ 0x5 + 0x2);
2801 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= RBIOS32(offset
+ 0x5 + 0x6);
2802 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
2803 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
2805 rdev
->pm
.power_state
[state_index
].type
=
2806 POWER_STATE_TYPE_BATTERY
;
2807 misc
= RBIOS16(offset
+ 0x5 + 0x0);
2809 misc2
= RBIOS16(offset
+ 0x5 + 0xe);
2810 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2811 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2813 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_GPIO
;
2815 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2818 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
2820 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.valid
= true;
2822 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.reg
=
2823 RBIOS16(offset
+ 0x5 + 0xb) * 4;
2824 tmp
= RBIOS8(offset
+ 0x5 + 0xd);
2825 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.mask
= (1 << tmp
);
2827 u8 entries
= RBIOS8(offset
+ 0x5 + 0xb);
2828 u16 voltage_table_offset
= RBIOS16(offset
+ 0x5 + 0xc);
2829 if (entries
&& voltage_table_offset
) {
2830 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.reg
=
2831 RBIOS16(voltage_table_offset
) * 4;
2832 tmp
= RBIOS8(voltage_table_offset
+ 0x2);
2833 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.mask
= (1 << tmp
);
2835 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
.valid
= false;
2837 switch ((misc2
& 0x700) >> 8) {
2840 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 0;
2843 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 33;
2846 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 66;
2849 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 99;
2852 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.delay
= 132;
2856 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2858 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2859 RBIOS8(offset
+ 0x5 + 0x10);
2860 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2863 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2866 /* XXX figure out some good default low power mode for desktop cards */
2870 /* add the default mode */
2871 rdev
->pm
.power_state
[state_index
].type
=
2872 POWER_STATE_TYPE_DEFAULT
;
2873 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2874 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
2875 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
2876 rdev
->pm
.power_state
[state_index
].default_clock_mode
= &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2877 if ((state_index
> 0) &&
2878 (rdev
->pm
.power_state
[0].clock_info
[0].voltage
.type
== VOLTAGE_GPIO
))
2879 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
=
2880 rdev
->pm
.power_state
[0].clock_info
[0].voltage
;
2882 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2883 rdev
->pm
.power_state
[state_index
].pcie_lanes
= 16;
2884 rdev
->pm
.power_state
[state_index
].flags
= 0;
2885 rdev
->pm
.default_power_state_index
= state_index
;
2886 rdev
->pm
.num_power_states
= state_index
+ 1;
2888 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
2889 rdev
->pm
.current_clock_mode_index
= 0;
2893 rdev
->pm
.default_power_state_index
= state_index
;
2894 rdev
->pm
.num_power_states
= 0;
2896 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
2897 rdev
->pm
.current_clock_mode_index
= 0;
2900 void radeon_external_tmds_setup(struct drm_encoder
*encoder
)
2902 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2903 struct radeon_encoder_ext_tmds
*tmds
= radeon_encoder
->enc_priv
;
2908 switch (tmds
->dvo_chip
) {
2911 radeon_i2c_put_byte(tmds
->i2c_bus
,
2914 radeon_i2c_put_byte(tmds
->i2c_bus
,
2917 radeon_i2c_put_byte(tmds
->i2c_bus
,
2920 radeon_i2c_put_byte(tmds
->i2c_bus
,
2923 radeon_i2c_put_byte(tmds
->i2c_bus
,
2928 /* sil 1178 - untested */
2947 bool radeon_combios_external_tmds_setup(struct drm_encoder
*encoder
)
2949 struct drm_device
*dev
= encoder
->dev
;
2950 struct radeon_device
*rdev
= dev
->dev_private
;
2951 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2953 uint8_t blocks
, slave_addr
, rev
;
2955 uint32_t reg
, val
, and_mask
, or_mask
;
2956 struct radeon_encoder_ext_tmds
*tmds
= radeon_encoder
->enc_priv
;
2961 if (rdev
->flags
& RADEON_IS_IGP
) {
2962 offset
= combios_get_table_offset(dev
, COMBIOS_TMDS_POWER_ON_TABLE
);
2963 rev
= RBIOS8(offset
);
2965 rev
= RBIOS8(offset
);
2967 blocks
= RBIOS8(offset
+ 3);
2969 while (blocks
> 0) {
2970 id
= RBIOS16(index
);
2974 reg
= (id
& 0x1fff) * 4;
2975 val
= RBIOS32(index
);
2980 reg
= (id
& 0x1fff) * 4;
2981 and_mask
= RBIOS32(index
);
2983 or_mask
= RBIOS32(index
);
2986 val
= (val
& and_mask
) | or_mask
;
2990 val
= RBIOS16(index
);
2995 val
= RBIOS16(index
);
3000 slave_addr
= id
& 0xff;
3001 slave_addr
>>= 1; /* 7 bit addressing */
3003 reg
= RBIOS8(index
);
3005 val
= RBIOS8(index
);
3007 radeon_i2c_put_byte(tmds
->i2c_bus
,
3012 DRM_ERROR("Unknown id %d\n", id
>> 13);
3021 offset
= combios_get_table_offset(dev
, COMBIOS_EXT_TMDS_INFO_TABLE
);
3023 index
= offset
+ 10;
3024 id
= RBIOS16(index
);
3025 while (id
!= 0xffff) {
3029 reg
= (id
& 0x1fff) * 4;
3030 val
= RBIOS32(index
);
3034 reg
= (id
& 0x1fff) * 4;
3035 and_mask
= RBIOS32(index
);
3037 or_mask
= RBIOS32(index
);
3040 val
= (val
& and_mask
) | or_mask
;
3044 val
= RBIOS16(index
);
3050 and_mask
= RBIOS32(index
);
3052 or_mask
= RBIOS32(index
);
3054 val
= RREG32_PLL(reg
);
3055 val
= (val
& and_mask
) | or_mask
;
3056 WREG32_PLL(reg
, val
);
3060 val
= RBIOS8(index
);
3062 radeon_i2c_put_byte(tmds
->i2c_bus
,
3067 DRM_ERROR("Unknown id %d\n", id
>> 13);
3070 id
= RBIOS16(index
);
3078 static void combios_parse_mmio_table(struct drm_device
*dev
, uint16_t offset
)
3080 struct radeon_device
*rdev
= dev
->dev_private
;
3083 while (RBIOS16(offset
)) {
3084 uint16_t cmd
= ((RBIOS16(offset
) & 0xe000) >> 13);
3085 uint32_t addr
= (RBIOS16(offset
) & 0x1fff);
3086 uint32_t val
, and_mask
, or_mask
;
3092 val
= RBIOS32(offset
);
3097 val
= RBIOS32(offset
);
3102 and_mask
= RBIOS32(offset
);
3104 or_mask
= RBIOS32(offset
);
3112 and_mask
= RBIOS32(offset
);
3114 or_mask
= RBIOS32(offset
);
3122 val
= RBIOS16(offset
);
3127 val
= RBIOS16(offset
);
3134 (RADEON_CLK_PWRMGT_CNTL
) &
3141 if ((RREG32(RADEON_MC_STATUS
) &
3157 static void combios_parse_pll_table(struct drm_device
*dev
, uint16_t offset
)
3159 struct radeon_device
*rdev
= dev
->dev_private
;
3162 while (RBIOS8(offset
)) {
3163 uint8_t cmd
= ((RBIOS8(offset
) & 0xc0) >> 6);
3164 uint8_t addr
= (RBIOS8(offset
) & 0x3f);
3165 uint32_t val
, shift
, tmp
;
3166 uint32_t and_mask
, or_mask
;
3171 val
= RBIOS32(offset
);
3173 WREG32_PLL(addr
, val
);
3176 shift
= RBIOS8(offset
) * 8;
3178 and_mask
= RBIOS8(offset
) << shift
;
3179 and_mask
|= ~(0xff << shift
);
3181 or_mask
= RBIOS8(offset
) << shift
;
3183 tmp
= RREG32_PLL(addr
);
3186 WREG32_PLL(addr
, tmp
);
3202 (RADEON_CLK_PWRMGT_CNTL
) &
3210 (RADEON_CLK_PWRMGT_CNTL
) &
3217 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL
);
3218 if (tmp
& RADEON_CG_NO1_DEBUG_0
) {
3220 uint32_t mclk_cntl
=
3223 mclk_cntl
&= 0xffff0000;
3224 /*mclk_cntl |= 0x00001111;*//* ??? */
3225 WREG32_PLL(RADEON_MCLK_CNTL
,
3230 (RADEON_CLK_PWRMGT_CNTL
,
3232 ~RADEON_CG_NO1_DEBUG_0
);
3247 static void combios_parse_ram_reset_table(struct drm_device
*dev
,
3250 struct radeon_device
*rdev
= dev
->dev_private
;
3254 uint8_t val
= RBIOS8(offset
);
3255 while (val
!= 0xff) {
3259 uint32_t channel_complete_mask
;
3261 if (ASIC_IS_R300(rdev
))
3262 channel_complete_mask
=
3263 R300_MEM_PWRUP_COMPLETE
;
3265 channel_complete_mask
=
3266 RADEON_MEM_PWRUP_COMPLETE
;
3269 if ((RREG32(RADEON_MEM_STR_CNTL
) &
3270 channel_complete_mask
) ==
3271 channel_complete_mask
)
3275 uint32_t or_mask
= RBIOS16(offset
);
3278 tmp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
3279 tmp
&= RADEON_SDRAM_MODE_MASK
;
3281 WREG32(RADEON_MEM_SDRAM_MODE_REG
, tmp
);
3283 or_mask
= val
<< 24;
3284 tmp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
3285 tmp
&= RADEON_B3MEM_RESET_MASK
;
3287 WREG32(RADEON_MEM_SDRAM_MODE_REG
, tmp
);
3289 val
= RBIOS8(offset
);
3294 static uint32_t combios_detect_ram(struct drm_device
*dev
, int ram
,
3295 int mem_addr_mapping
)
3297 struct radeon_device
*rdev
= dev
->dev_private
;
3302 mem_cntl
= RREG32(RADEON_MEM_CNTL
);
3303 if (mem_cntl
& RV100_HALF_MODE
)
3306 mem_cntl
&= ~(0xff << 8);
3307 mem_cntl
|= (mem_addr_mapping
& 0xff) << 8;
3308 WREG32(RADEON_MEM_CNTL
, mem_cntl
);
3309 RREG32(RADEON_MEM_CNTL
);
3313 /* something like this???? */
3315 addr
= ram
* 1024 * 1024;
3316 /* write to each page */
3317 WREG32_IDX((addr
) | RADEON_MM_APER
, 0xdeadbeef);
3318 /* read back and verify */
3319 if (RREG32_IDX((addr
) | RADEON_MM_APER
) != 0xdeadbeef)
3326 static void combios_write_ram_size(struct drm_device
*dev
)
3328 struct radeon_device
*rdev
= dev
->dev_private
;
3331 uint32_t mem_size
= 0;
3332 uint32_t mem_cntl
= 0;
3334 /* should do something smarter here I guess... */
3335 if (rdev
->flags
& RADEON_IS_IGP
)
3338 /* first check detected mem table */
3339 offset
= combios_get_table_offset(dev
, COMBIOS_DETECTED_MEM_TABLE
);
3341 rev
= RBIOS8(offset
);
3343 mem_cntl
= RBIOS32(offset
+ 1);
3344 mem_size
= RBIOS16(offset
+ 5);
3345 if ((rdev
->family
< CHIP_R200
) &&
3346 !ASIC_IS_RN50(rdev
))
3347 WREG32(RADEON_MEM_CNTL
, mem_cntl
);
3353 combios_get_table_offset(dev
, COMBIOS_MEM_CONFIG_TABLE
);
3355 rev
= RBIOS8(offset
- 1);
3357 if ((rdev
->family
< CHIP_R200
)
3358 && !ASIC_IS_RN50(rdev
)) {
3360 int mem_addr_mapping
= 0;
3362 while (RBIOS8(offset
)) {
3363 ram
= RBIOS8(offset
);
3366 if (mem_addr_mapping
!= 0x25)
3369 combios_detect_ram(dev
, ram
,
3376 mem_size
= RBIOS8(offset
);
3378 mem_size
= RBIOS8(offset
);
3379 mem_size
*= 2; /* convert to MB */
3384 mem_size
*= (1024 * 1024); /* convert to bytes */
3385 WREG32(RADEON_CONFIG_MEMSIZE
, mem_size
);
3388 void radeon_combios_asic_init(struct drm_device
*dev
)
3390 struct radeon_device
*rdev
= dev
->dev_private
;
3393 /* port hardcoded mac stuff from radeonfb */
3394 if (rdev
->bios
== NULL
)
3398 table
= combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_1_TABLE
);
3400 combios_parse_mmio_table(dev
, table
);
3403 table
= combios_get_table_offset(dev
, COMBIOS_PLL_INIT_TABLE
);
3405 combios_parse_pll_table(dev
, table
);
3408 table
= combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_2_TABLE
);
3410 combios_parse_mmio_table(dev
, table
);
3412 if (!(rdev
->flags
& RADEON_IS_IGP
)) {
3415 combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_4_TABLE
);
3417 combios_parse_mmio_table(dev
, table
);
3420 table
= combios_get_table_offset(dev
, COMBIOS_RAM_RESET_TABLE
);
3422 combios_parse_ram_reset_table(dev
, table
);
3426 combios_get_table_offset(dev
, COMBIOS_ASIC_INIT_3_TABLE
);
3428 combios_parse_mmio_table(dev
, table
);
3430 /* write CONFIG_MEMSIZE */
3431 combios_write_ram_size(dev
);
3434 /* quirk for rs4xx HP nx6125 laptop to make it resume
3435 * - it hangs on resume inside the dynclk 1 table.
3437 if (rdev
->family
== CHIP_RS480
&&
3438 rdev
->pdev
->subsystem_vendor
== 0x103c &&
3439 rdev
->pdev
->subsystem_device
== 0x308b)
3442 /* quirk for rs4xx HP dv5000 laptop to make it resume
3443 * - it hangs on resume inside the dynclk 1 table.
3445 if (rdev
->family
== CHIP_RS480
&&
3446 rdev
->pdev
->subsystem_vendor
== 0x103c &&
3447 rdev
->pdev
->subsystem_device
== 0x30a4)
3450 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3451 * - it hangs on resume inside the dynclk 1 table.
3453 if (rdev
->family
== CHIP_RS480
&&
3454 rdev
->pdev
->subsystem_vendor
== 0x103c &&
3455 rdev
->pdev
->subsystem_device
== 0x30ae)
3459 table
= combios_get_table_offset(dev
, COMBIOS_DYN_CLK_1_TABLE
);
3461 combios_parse_pll_table(dev
, table
);
3465 void radeon_combios_initialize_bios_scratch_regs(struct drm_device
*dev
)
3467 struct radeon_device
*rdev
= dev
->dev_private
;
3468 uint32_t bios_0_scratch
, bios_6_scratch
, bios_7_scratch
;
3470 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
3471 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3472 bios_7_scratch
= RREG32(RADEON_BIOS_7_SCRATCH
);
3474 /* let the bios control the backlight */
3475 bios_0_scratch
&= ~RADEON_DRIVER_BRIGHTNESS_EN
;
3477 /* tell the bios not to handle mode switching */
3478 bios_6_scratch
|= (RADEON_DISPLAY_SWITCHING_DIS
|
3479 RADEON_ACC_MODE_CHANGE
);
3481 /* tell the bios a driver is loaded */
3482 bios_7_scratch
|= RADEON_DRV_LOADED
;
3484 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
3485 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
3486 WREG32(RADEON_BIOS_7_SCRATCH
, bios_7_scratch
);
3489 void radeon_combios_output_lock(struct drm_encoder
*encoder
, bool lock
)
3491 struct drm_device
*dev
= encoder
->dev
;
3492 struct radeon_device
*rdev
= dev
->dev_private
;
3493 uint32_t bios_6_scratch
;
3495 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3498 bios_6_scratch
|= RADEON_DRIVER_CRITICAL
;
3500 bios_6_scratch
&= ~RADEON_DRIVER_CRITICAL
;
3502 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
3506 radeon_combios_connected_scratch_regs(struct drm_connector
*connector
,
3507 struct drm_encoder
*encoder
,
3510 struct drm_device
*dev
= connector
->dev
;
3511 struct radeon_device
*rdev
= dev
->dev_private
;
3512 struct radeon_connector
*radeon_connector
=
3513 to_radeon_connector(connector
);
3514 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3515 uint32_t bios_4_scratch
= RREG32(RADEON_BIOS_4_SCRATCH
);
3516 uint32_t bios_5_scratch
= RREG32(RADEON_BIOS_5_SCRATCH
);
3518 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
3519 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
3521 DRM_DEBUG_KMS("TV1 connected\n");
3523 bios_4_scratch
|= RADEON_TV1_ATTACHED_SVIDEO
;
3524 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3525 bios_5_scratch
|= RADEON_TV1_ON
;
3526 bios_5_scratch
|= RADEON_ACC_REQ_TV1
;
3528 DRM_DEBUG_KMS("TV1 disconnected\n");
3529 bios_4_scratch
&= ~RADEON_TV1_ATTACHED_MASK
;
3530 bios_5_scratch
&= ~RADEON_TV1_ON
;
3531 bios_5_scratch
&= ~RADEON_ACC_REQ_TV1
;
3534 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
3535 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
3537 DRM_DEBUG_KMS("LCD1 connected\n");
3538 bios_4_scratch
|= RADEON_LCD1_ATTACHED
;
3539 bios_5_scratch
|= RADEON_LCD1_ON
;
3540 bios_5_scratch
|= RADEON_ACC_REQ_LCD1
;
3542 DRM_DEBUG_KMS("LCD1 disconnected\n");
3543 bios_4_scratch
&= ~RADEON_LCD1_ATTACHED
;
3544 bios_5_scratch
&= ~RADEON_LCD1_ON
;
3545 bios_5_scratch
&= ~RADEON_ACC_REQ_LCD1
;
3548 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
3549 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
3551 DRM_DEBUG_KMS("CRT1 connected\n");
3552 bios_4_scratch
|= RADEON_CRT1_ATTACHED_COLOR
;
3553 bios_5_scratch
|= RADEON_CRT1_ON
;
3554 bios_5_scratch
|= RADEON_ACC_REQ_CRT1
;
3556 DRM_DEBUG_KMS("CRT1 disconnected\n");
3557 bios_4_scratch
&= ~RADEON_CRT1_ATTACHED_MASK
;
3558 bios_5_scratch
&= ~RADEON_CRT1_ON
;
3559 bios_5_scratch
&= ~RADEON_ACC_REQ_CRT1
;
3562 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
3563 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
3565 DRM_DEBUG_KMS("CRT2 connected\n");
3566 bios_4_scratch
|= RADEON_CRT2_ATTACHED_COLOR
;
3567 bios_5_scratch
|= RADEON_CRT2_ON
;
3568 bios_5_scratch
|= RADEON_ACC_REQ_CRT2
;
3570 DRM_DEBUG_KMS("CRT2 disconnected\n");
3571 bios_4_scratch
&= ~RADEON_CRT2_ATTACHED_MASK
;
3572 bios_5_scratch
&= ~RADEON_CRT2_ON
;
3573 bios_5_scratch
&= ~RADEON_ACC_REQ_CRT2
;
3576 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
3577 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
3579 DRM_DEBUG_KMS("DFP1 connected\n");
3580 bios_4_scratch
|= RADEON_DFP1_ATTACHED
;
3581 bios_5_scratch
|= RADEON_DFP1_ON
;
3582 bios_5_scratch
|= RADEON_ACC_REQ_DFP1
;
3584 DRM_DEBUG_KMS("DFP1 disconnected\n");
3585 bios_4_scratch
&= ~RADEON_DFP1_ATTACHED
;
3586 bios_5_scratch
&= ~RADEON_DFP1_ON
;
3587 bios_5_scratch
&= ~RADEON_ACC_REQ_DFP1
;
3590 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
3591 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
3593 DRM_DEBUG_KMS("DFP2 connected\n");
3594 bios_4_scratch
|= RADEON_DFP2_ATTACHED
;
3595 bios_5_scratch
|= RADEON_DFP2_ON
;
3596 bios_5_scratch
|= RADEON_ACC_REQ_DFP2
;
3598 DRM_DEBUG_KMS("DFP2 disconnected\n");
3599 bios_4_scratch
&= ~RADEON_DFP2_ATTACHED
;
3600 bios_5_scratch
&= ~RADEON_DFP2_ON
;
3601 bios_5_scratch
&= ~RADEON_ACC_REQ_DFP2
;
3604 WREG32(RADEON_BIOS_4_SCRATCH
, bios_4_scratch
);
3605 WREG32(RADEON_BIOS_5_SCRATCH
, bios_5_scratch
);
3609 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
3611 struct drm_device
*dev
= encoder
->dev
;
3612 struct radeon_device
*rdev
= dev
->dev_private
;
3613 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3614 uint32_t bios_5_scratch
= RREG32(RADEON_BIOS_5_SCRATCH
);
3616 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
3617 bios_5_scratch
&= ~RADEON_TV1_CRTC_MASK
;
3618 bios_5_scratch
|= (crtc
<< RADEON_TV1_CRTC_SHIFT
);
3620 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
3621 bios_5_scratch
&= ~RADEON_CRT1_CRTC_MASK
;
3622 bios_5_scratch
|= (crtc
<< RADEON_CRT1_CRTC_SHIFT
);
3624 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
3625 bios_5_scratch
&= ~RADEON_CRT2_CRTC_MASK
;
3626 bios_5_scratch
|= (crtc
<< RADEON_CRT2_CRTC_SHIFT
);
3628 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
3629 bios_5_scratch
&= ~RADEON_LCD1_CRTC_MASK
;
3630 bios_5_scratch
|= (crtc
<< RADEON_LCD1_CRTC_SHIFT
);
3632 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
3633 bios_5_scratch
&= ~RADEON_DFP1_CRTC_MASK
;
3634 bios_5_scratch
|= (crtc
<< RADEON_DFP1_CRTC_SHIFT
);
3636 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
3637 bios_5_scratch
&= ~RADEON_DFP2_CRTC_MASK
;
3638 bios_5_scratch
|= (crtc
<< RADEON_DFP2_CRTC_SHIFT
);
3640 WREG32(RADEON_BIOS_5_SCRATCH
, bios_5_scratch
);
3644 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
3646 struct drm_device
*dev
= encoder
->dev
;
3647 struct radeon_device
*rdev
= dev
->dev_private
;
3648 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
3649 uint32_t bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
3651 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
)) {
3653 bios_6_scratch
|= RADEON_TV_DPMS_ON
;
3655 bios_6_scratch
&= ~RADEON_TV_DPMS_ON
;
3657 if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3659 bios_6_scratch
|= RADEON_CRT_DPMS_ON
;
3661 bios_6_scratch
&= ~RADEON_CRT_DPMS_ON
;
3663 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3665 bios_6_scratch
|= RADEON_LCD_DPMS_ON
;
3667 bios_6_scratch
&= ~RADEON_LCD_DPMS_ON
;
3669 if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
3671 bios_6_scratch
|= RADEON_DFP_DPMS_ON
;
3673 bios_6_scratch
&= ~RADEON_DFP_DPMS_ON
;
3675 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);