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ALSA: hda - Use LPIB for ATI/AMD chipsets as default
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_atombios.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54 /* from radeon_legacy_encoder.c */
55 extern void
56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
58
59 union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63 };
64
65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
67 {
68 struct atom_context *ctx = rdev->mode_info.atom_context;
69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
73 uint16_t data_offset, size;
74 int i, num_indices;
75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i];
87
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev)) {
103 if ((i == 4) &&
104 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
105 (gpio->sucI2cId.ucAccess == 0x94))
106 gpio->sucI2cId.ucAccess = 0x14;
107 }
108
109 if (gpio->sucI2cId.ucAccess == id) {
110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
112 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
113 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
114 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
115 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
116 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
117 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
118 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
119 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
120 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
121 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
122 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
123 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
124 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
125 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
126
127 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
128 i2c.hw_capable = true;
129 else
130 i2c.hw_capable = false;
131
132 if (gpio->sucI2cId.ucAccess == 0xa0)
133 i2c.mm_i2c = true;
134 else
135 i2c.mm_i2c = false;
136
137 i2c.i2c_id = gpio->sucI2cId.ucAccess;
138
139 if (i2c.mask_clk_reg)
140 i2c.valid = true;
141 break;
142 }
143 }
144 }
145
146 return i2c;
147 }
148
149 void radeon_atombios_i2c_init(struct radeon_device *rdev)
150 {
151 struct atom_context *ctx = rdev->mode_info.atom_context;
152 ATOM_GPIO_I2C_ASSIGMENT *gpio;
153 struct radeon_i2c_bus_rec i2c;
154 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
155 struct _ATOM_GPIO_I2C_INFO *i2c_info;
156 uint16_t data_offset, size;
157 int i, num_indices;
158 char stmp[32];
159
160 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
161
162 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
163 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
164
165 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
167
168 for (i = 0; i < num_indices; i++) {
169 gpio = &i2c_info->asGPIO_Info[i];
170 i2c.valid = false;
171
172 /* some evergreen boards have bad data for this entry */
173 if (ASIC_IS_DCE4(rdev)) {
174 if ((i == 7) &&
175 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
176 (gpio->sucI2cId.ucAccess == 0)) {
177 gpio->sucI2cId.ucAccess = 0x97;
178 gpio->ucDataMaskShift = 8;
179 gpio->ucDataEnShift = 8;
180 gpio->ucDataY_Shift = 8;
181 gpio->ucDataA_Shift = 8;
182 }
183 }
184
185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev)) {
187 if ((i == 4) &&
188 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
189 (gpio->sucI2cId.ucAccess == 0x94))
190 gpio->sucI2cId.ucAccess = 0x14;
191 }
192
193 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
194 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
195 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
196 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
197 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
198 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
199 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
200 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
201 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
202 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
203 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
204 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
205 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
206 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
207 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
208 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
209
210 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
211 i2c.hw_capable = true;
212 else
213 i2c.hw_capable = false;
214
215 if (gpio->sucI2cId.ucAccess == 0xa0)
216 i2c.mm_i2c = true;
217 else
218 i2c.mm_i2c = false;
219
220 i2c.i2c_id = gpio->sucI2cId.ucAccess;
221
222 if (i2c.mask_clk_reg) {
223 i2c.valid = true;
224 sprintf(stmp, "0x%x", i2c.i2c_id);
225 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
226 }
227 }
228 }
229 }
230
231 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
232 u8 id)
233 {
234 struct atom_context *ctx = rdev->mode_info.atom_context;
235 struct radeon_gpio_rec gpio;
236 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
237 struct _ATOM_GPIO_PIN_LUT *gpio_info;
238 ATOM_GPIO_PIN_ASSIGNMENT *pin;
239 u16 data_offset, size;
240 int i, num_indices;
241
242 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
243 gpio.valid = false;
244
245 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
246 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
247
248 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
250
251 for (i = 0; i < num_indices; i++) {
252 pin = &gpio_info->asGPIO_Pin[i];
253 if (id == pin->ucGPIO_ID) {
254 gpio.id = pin->ucGPIO_ID;
255 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
256 gpio.mask = (1 << pin->ucGpioPinBitShift);
257 gpio.valid = true;
258 break;
259 }
260 }
261 }
262
263 return gpio;
264 }
265
266 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
267 struct radeon_gpio_rec *gpio)
268 {
269 struct radeon_hpd hpd;
270 u32 reg;
271
272 memset(&hpd, 0, sizeof(struct radeon_hpd));
273
274 if (ASIC_IS_DCE4(rdev))
275 reg = EVERGREEN_DC_GPIO_HPD_A;
276 else
277 reg = AVIVO_DC_GPIO_HPD_A;
278
279 hpd.gpio = *gpio;
280 if (gpio->reg == reg) {
281 switch(gpio->mask) {
282 case (1 << 0):
283 hpd.hpd = RADEON_HPD_1;
284 break;
285 case (1 << 8):
286 hpd.hpd = RADEON_HPD_2;
287 break;
288 case (1 << 16):
289 hpd.hpd = RADEON_HPD_3;
290 break;
291 case (1 << 24):
292 hpd.hpd = RADEON_HPD_4;
293 break;
294 case (1 << 26):
295 hpd.hpd = RADEON_HPD_5;
296 break;
297 case (1 << 28):
298 hpd.hpd = RADEON_HPD_6;
299 break;
300 default:
301 hpd.hpd = RADEON_HPD_NONE;
302 break;
303 }
304 } else
305 hpd.hpd = RADEON_HPD_NONE;
306 return hpd;
307 }
308
309 static bool radeon_atom_apply_quirks(struct drm_device *dev,
310 uint32_t supported_device,
311 int *connector_type,
312 struct radeon_i2c_bus_rec *i2c_bus,
313 uint16_t *line_mux,
314 struct radeon_hpd *hpd)
315 {
316
317 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
318 if ((dev->pdev->device == 0x791e) &&
319 (dev->pdev->subsystem_vendor == 0x1043) &&
320 (dev->pdev->subsystem_device == 0x826d)) {
321 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
322 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
323 *connector_type = DRM_MODE_CONNECTOR_DVID;
324 }
325
326 /* Asrock RS600 board lists the DVI port as HDMI */
327 if ((dev->pdev->device == 0x7941) &&
328 (dev->pdev->subsystem_vendor == 0x1849) &&
329 (dev->pdev->subsystem_device == 0x7941)) {
330 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
331 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
332 *connector_type = DRM_MODE_CONNECTOR_DVID;
333 }
334
335 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
336 if ((dev->pdev->device == 0x796e) &&
337 (dev->pdev->subsystem_vendor == 0x1462) &&
338 (dev->pdev->subsystem_device == 0x7302)) {
339 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
340 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
341 return false;
342 }
343
344 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
345 if ((dev->pdev->device == 0x7941) &&
346 (dev->pdev->subsystem_vendor == 0x147b) &&
347 (dev->pdev->subsystem_device == 0x2412)) {
348 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
349 return false;
350 }
351
352 /* Falcon NW laptop lists vga ddc line for LVDS */
353 if ((dev->pdev->device == 0x5653) &&
354 (dev->pdev->subsystem_vendor == 0x1462) &&
355 (dev->pdev->subsystem_device == 0x0291)) {
356 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
357 i2c_bus->valid = false;
358 *line_mux = 53;
359 }
360 }
361
362 /* HIS X1300 is DVI+VGA, not DVI+DVI */
363 if ((dev->pdev->device == 0x7146) &&
364 (dev->pdev->subsystem_vendor == 0x17af) &&
365 (dev->pdev->subsystem_device == 0x2058)) {
366 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
367 return false;
368 }
369
370 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
371 if ((dev->pdev->device == 0x7142) &&
372 (dev->pdev->subsystem_vendor == 0x1458) &&
373 (dev->pdev->subsystem_device == 0x2134)) {
374 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
375 return false;
376 }
377
378
379 /* Funky macbooks */
380 if ((dev->pdev->device == 0x71C5) &&
381 (dev->pdev->subsystem_vendor == 0x106b) &&
382 (dev->pdev->subsystem_device == 0x0080)) {
383 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
384 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
385 return false;
386 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
387 *line_mux = 0x90;
388 }
389
390 /* mac rv630, rv730, others */
391 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
392 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
393 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
394 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
395 }
396
397 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
398 if ((dev->pdev->device == 0x9598) &&
399 (dev->pdev->subsystem_vendor == 0x1043) &&
400 (dev->pdev->subsystem_device == 0x01da)) {
401 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
402 *connector_type = DRM_MODE_CONNECTOR_DVII;
403 }
404 }
405
406 /* ASUS HD 3600 board lists the DVI port as HDMI */
407 if ((dev->pdev->device == 0x9598) &&
408 (dev->pdev->subsystem_vendor == 0x1043) &&
409 (dev->pdev->subsystem_device == 0x01e4)) {
410 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
411 *connector_type = DRM_MODE_CONNECTOR_DVII;
412 }
413 }
414
415 /* ASUS HD 3450 board lists the DVI port as HDMI */
416 if ((dev->pdev->device == 0x95C5) &&
417 (dev->pdev->subsystem_vendor == 0x1043) &&
418 (dev->pdev->subsystem_device == 0x01e2)) {
419 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
420 *connector_type = DRM_MODE_CONNECTOR_DVII;
421 }
422 }
423
424 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
425 * HDMI + VGA reporting as HDMI
426 */
427 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
428 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
429 *connector_type = DRM_MODE_CONNECTOR_VGA;
430 *line_mux = 0;
431 }
432 }
433
434 /* Acer laptop (Acer TravelMate 5730G) has an HDMI port
435 * on the laptop and a DVI port on the docking station and
436 * both share the same encoder, hpd pin, and ddc line.
437 * So while the bios table is technically correct,
438 * we drop the DVI port here since xrandr has no concept of
439 * encoders and will try and drive both connectors
440 * with different crtcs which isn't possible on the hardware
441 * side and leaves no crtcs for LVDS or VGA.
442 */
443 if ((dev->pdev->device == 0x95c4) &&
444 (dev->pdev->subsystem_vendor == 0x1025) &&
445 (dev->pdev->subsystem_device == 0x013c)) {
446 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
447 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
448 /* actually it's a DVI-D port not DVI-I */
449 *connector_type = DRM_MODE_CONNECTOR_DVID;
450 return false;
451 }
452 }
453
454 /* XFX Pine Group device rv730 reports no VGA DDC lines
455 * even though they are wired up to record 0x93
456 */
457 if ((dev->pdev->device == 0x9498) &&
458 (dev->pdev->subsystem_vendor == 0x1682) &&
459 (dev->pdev->subsystem_device == 0x2452)) {
460 struct radeon_device *rdev = dev->dev_private;
461 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
462 }
463 return true;
464 }
465
466 const int supported_devices_connector_convert[] = {
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_VGA,
469 DRM_MODE_CONNECTOR_DVII,
470 DRM_MODE_CONNECTOR_DVID,
471 DRM_MODE_CONNECTOR_DVIA,
472 DRM_MODE_CONNECTOR_SVIDEO,
473 DRM_MODE_CONNECTOR_Composite,
474 DRM_MODE_CONNECTOR_LVDS,
475 DRM_MODE_CONNECTOR_Unknown,
476 DRM_MODE_CONNECTOR_Unknown,
477 DRM_MODE_CONNECTOR_HDMIA,
478 DRM_MODE_CONNECTOR_HDMIB,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_9PinDIN,
482 DRM_MODE_CONNECTOR_DisplayPort
483 };
484
485 const uint16_t supported_devices_connector_object_id_convert[] = {
486 CONNECTOR_OBJECT_ID_NONE,
487 CONNECTOR_OBJECT_ID_VGA,
488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
490 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
491 CONNECTOR_OBJECT_ID_COMPOSITE,
492 CONNECTOR_OBJECT_ID_SVIDEO,
493 CONNECTOR_OBJECT_ID_LVDS,
494 CONNECTOR_OBJECT_ID_9PIN_DIN,
495 CONNECTOR_OBJECT_ID_9PIN_DIN,
496 CONNECTOR_OBJECT_ID_DISPLAYPORT,
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
499 CONNECTOR_OBJECT_ID_SVIDEO
500 };
501
502 const int object_connector_convert[] = {
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_DVII,
505 DRM_MODE_CONNECTOR_DVII,
506 DRM_MODE_CONNECTOR_DVID,
507 DRM_MODE_CONNECTOR_DVID,
508 DRM_MODE_CONNECTOR_VGA,
509 DRM_MODE_CONNECTOR_Composite,
510 DRM_MODE_CONNECTOR_SVIDEO,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_Unknown,
513 DRM_MODE_CONNECTOR_9PinDIN,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_HDMIA,
516 DRM_MODE_CONNECTOR_HDMIB,
517 DRM_MODE_CONNECTOR_LVDS,
518 DRM_MODE_CONNECTOR_9PinDIN,
519 DRM_MODE_CONNECTOR_Unknown,
520 DRM_MODE_CONNECTOR_Unknown,
521 DRM_MODE_CONNECTOR_Unknown,
522 DRM_MODE_CONNECTOR_DisplayPort,
523 DRM_MODE_CONNECTOR_eDP,
524 DRM_MODE_CONNECTOR_Unknown
525 };
526
527 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
528 {
529 struct radeon_device *rdev = dev->dev_private;
530 struct radeon_mode_info *mode_info = &rdev->mode_info;
531 struct atom_context *ctx = mode_info->atom_context;
532 int index = GetIndexIntoMasterTable(DATA, Object_Header);
533 u16 size, data_offset;
534 u8 frev, crev;
535 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
536 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
537 ATOM_OBJECT_TABLE *router_obj;
538 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
539 ATOM_OBJECT_HEADER *obj_header;
540 int i, j, k, path_size, device_support;
541 int connector_type;
542 u16 igp_lane_info, conn_id, connector_object_id;
543 struct radeon_i2c_bus_rec ddc_bus;
544 struct radeon_router router;
545 struct radeon_gpio_rec gpio;
546 struct radeon_hpd hpd;
547
548 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
549 return false;
550
551 if (crev < 2)
552 return false;
553
554 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
555 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usDisplayPathTableOffset));
558 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
559 (ctx->bios + data_offset +
560 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
561 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
562 (ctx->bios + data_offset +
563 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
564 router_obj = (ATOM_OBJECT_TABLE *)
565 (ctx->bios + data_offset +
566 le16_to_cpu(obj_header->usRouterObjectTableOffset));
567 device_support = le16_to_cpu(obj_header->usDeviceSupport);
568
569 path_size = 0;
570 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
571 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
572 ATOM_DISPLAY_OBJECT_PATH *path;
573 addr += path_size;
574 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
575 path_size += le16_to_cpu(path->usSize);
576
577 if (device_support & le16_to_cpu(path->usDeviceTag)) {
578 uint8_t con_obj_id, con_obj_num, con_obj_type;
579
580 con_obj_id =
581 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
582 >> OBJECT_ID_SHIFT;
583 con_obj_num =
584 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
585 >> ENUM_ID_SHIFT;
586 con_obj_type =
587 (le16_to_cpu(path->usConnObjectId) &
588 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
589
590 /* TODO CV support */
591 if (le16_to_cpu(path->usDeviceTag) ==
592 ATOM_DEVICE_CV_SUPPORT)
593 continue;
594
595 /* IGP chips */
596 if ((rdev->flags & RADEON_IS_IGP) &&
597 (con_obj_id ==
598 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
599 uint16_t igp_offset = 0;
600 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
601
602 index =
603 GetIndexIntoMasterTable(DATA,
604 IntegratedSystemInfo);
605
606 if (atom_parse_data_header(ctx, index, &size, &frev,
607 &crev, &igp_offset)) {
608
609 if (crev >= 2) {
610 igp_obj =
611 (ATOM_INTEGRATED_SYSTEM_INFO_V2
612 *) (ctx->bios + igp_offset);
613
614 if (igp_obj) {
615 uint32_t slot_config, ct;
616
617 if (con_obj_num == 1)
618 slot_config =
619 igp_obj->
620 ulDDISlot1Config;
621 else
622 slot_config =
623 igp_obj->
624 ulDDISlot2Config;
625
626 ct = (slot_config >> 16) & 0xff;
627 connector_type =
628 object_connector_convert
629 [ct];
630 connector_object_id = ct;
631 igp_lane_info =
632 slot_config & 0xffff;
633 } else
634 continue;
635 } else
636 continue;
637 } else {
638 igp_lane_info = 0;
639 connector_type =
640 object_connector_convert[con_obj_id];
641 connector_object_id = con_obj_id;
642 }
643 } else {
644 igp_lane_info = 0;
645 connector_type =
646 object_connector_convert[con_obj_id];
647 connector_object_id = con_obj_id;
648 }
649
650 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
651 continue;
652
653 router.ddc_valid = false;
654 router.cd_valid = false;
655 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
656 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
657
658 grph_obj_id =
659 (le16_to_cpu(path->usGraphicObjIds[j]) &
660 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
661 grph_obj_num =
662 (le16_to_cpu(path->usGraphicObjIds[j]) &
663 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
664 grph_obj_type =
665 (le16_to_cpu(path->usGraphicObjIds[j]) &
666 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
667
668 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
669 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
670 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
671 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
672 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
673 (ctx->bios + data_offset +
674 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
675 ATOM_ENCODER_CAP_RECORD *cap_record;
676 u16 caps = 0;
677
678 while (record->ucRecordSize > 0 &&
679 record->ucRecordType > 0 &&
680 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
681 switch (record->ucRecordType) {
682 case ATOM_ENCODER_CAP_RECORD_TYPE:
683 cap_record =(ATOM_ENCODER_CAP_RECORD *)
684 record;
685 caps = le16_to_cpu(cap_record->usEncoderCap);
686 break;
687 }
688 record = (ATOM_COMMON_RECORD_HEADER *)
689 ((char *)record + record->ucRecordSize);
690 }
691 radeon_add_atom_encoder(dev,
692 encoder_obj,
693 le16_to_cpu
694 (path->
695 usDeviceTag),
696 caps);
697 }
698 }
699 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
700 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
701 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
702 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
703 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
704 (ctx->bios + data_offset +
705 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
706 ATOM_I2C_RECORD *i2c_record;
707 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
708 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
709 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
710 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
711 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
712 (ctx->bios + data_offset +
713 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
714 int enum_id;
715
716 router.router_id = router_obj_id;
717 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
718 enum_id++) {
719 if (le16_to_cpu(path->usConnObjectId) ==
720 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
721 break;
722 }
723
724 while (record->ucRecordSize > 0 &&
725 record->ucRecordType > 0 &&
726 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
727 switch (record->ucRecordType) {
728 case ATOM_I2C_RECORD_TYPE:
729 i2c_record =
730 (ATOM_I2C_RECORD *)
731 record;
732 i2c_config =
733 (ATOM_I2C_ID_CONFIG_ACCESS *)
734 &i2c_record->sucI2cId;
735 router.i2c_info =
736 radeon_lookup_i2c_gpio(rdev,
737 i2c_config->
738 ucAccess);
739 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
740 break;
741 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
742 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
743 record;
744 router.ddc_valid = true;
745 router.ddc_mux_type = ddc_path->ucMuxType;
746 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
747 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
748 break;
749 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
750 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
751 record;
752 router.cd_valid = true;
753 router.cd_mux_type = cd_path->ucMuxType;
754 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
755 router.cd_mux_state = cd_path->ucMuxState[enum_id];
756 break;
757 }
758 record = (ATOM_COMMON_RECORD_HEADER *)
759 ((char *)record + record->ucRecordSize);
760 }
761 }
762 }
763 }
764 }
765
766 /* look up gpio for ddc, hpd */
767 ddc_bus.valid = false;
768 hpd.hpd = RADEON_HPD_NONE;
769 if ((le16_to_cpu(path->usDeviceTag) &
770 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
772 if (le16_to_cpu(path->usConnObjectId) ==
773 le16_to_cpu(con_obj->asObjects[j].
774 usObjectID)) {
775 ATOM_COMMON_RECORD_HEADER
776 *record =
777 (ATOM_COMMON_RECORD_HEADER
778 *)
779 (ctx->bios + data_offset +
780 le16_to_cpu(con_obj->
781 asObjects[j].
782 usRecordOffset));
783 ATOM_I2C_RECORD *i2c_record;
784 ATOM_HPD_INT_RECORD *hpd_record;
785 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
786
787 while (record->ucRecordSize > 0 &&
788 record->ucRecordType > 0 &&
789 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
790 switch (record->ucRecordType) {
791 case ATOM_I2C_RECORD_TYPE:
792 i2c_record =
793 (ATOM_I2C_RECORD *)
794 record;
795 i2c_config =
796 (ATOM_I2C_ID_CONFIG_ACCESS *)
797 &i2c_record->sucI2cId;
798 ddc_bus = radeon_lookup_i2c_gpio(rdev,
799 i2c_config->
800 ucAccess);
801 break;
802 case ATOM_HPD_INT_RECORD_TYPE:
803 hpd_record =
804 (ATOM_HPD_INT_RECORD *)
805 record;
806 gpio = radeon_lookup_gpio(rdev,
807 hpd_record->ucHPDIntGPIOID);
808 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
809 hpd.plugged_state = hpd_record->ucPlugged_PinState;
810 break;
811 }
812 record =
813 (ATOM_COMMON_RECORD_HEADER
814 *) ((char *)record
815 +
816 record->
817 ucRecordSize);
818 }
819 break;
820 }
821 }
822 }
823
824 /* needed for aux chan transactions */
825 ddc_bus.hpd = hpd.hpd;
826
827 conn_id = le16_to_cpu(path->usConnObjectId);
828
829 if (!radeon_atom_apply_quirks
830 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
831 &ddc_bus, &conn_id, &hpd))
832 continue;
833
834 radeon_add_atom_connector(dev,
835 conn_id,
836 le16_to_cpu(path->
837 usDeviceTag),
838 connector_type, &ddc_bus,
839 igp_lane_info,
840 connector_object_id,
841 &hpd,
842 &router);
843
844 }
845 }
846
847 radeon_link_encoder_connector(dev);
848
849 return true;
850 }
851
852 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
853 int connector_type,
854 uint16_t devices)
855 {
856 struct radeon_device *rdev = dev->dev_private;
857
858 if (rdev->flags & RADEON_IS_IGP) {
859 return supported_devices_connector_object_id_convert
860 [connector_type];
861 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
862 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
863 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
864 struct radeon_mode_info *mode_info = &rdev->mode_info;
865 struct atom_context *ctx = mode_info->atom_context;
866 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
867 uint16_t size, data_offset;
868 uint8_t frev, crev;
869 ATOM_XTMDS_INFO *xtmds;
870
871 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
872 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
873
874 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
875 if (connector_type == DRM_MODE_CONNECTOR_DVII)
876 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
877 else
878 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
879 } else {
880 if (connector_type == DRM_MODE_CONNECTOR_DVII)
881 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
882 else
883 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
884 }
885 } else
886 return supported_devices_connector_object_id_convert
887 [connector_type];
888 } else {
889 return supported_devices_connector_object_id_convert
890 [connector_type];
891 }
892 }
893
894 struct bios_connector {
895 bool valid;
896 uint16_t line_mux;
897 uint16_t devices;
898 int connector_type;
899 struct radeon_i2c_bus_rec ddc_bus;
900 struct radeon_hpd hpd;
901 };
902
903 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
904 drm_device
905 *dev)
906 {
907 struct radeon_device *rdev = dev->dev_private;
908 struct radeon_mode_info *mode_info = &rdev->mode_info;
909 struct atom_context *ctx = mode_info->atom_context;
910 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
911 uint16_t size, data_offset;
912 uint8_t frev, crev;
913 uint16_t device_support;
914 uint8_t dac;
915 union atom_supported_devices *supported_devices;
916 int i, j, max_device;
917 struct bios_connector *bios_connectors;
918 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
919 struct radeon_router router;
920
921 router.ddc_valid = false;
922 router.cd_valid = false;
923
924 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
925 if (!bios_connectors)
926 return false;
927
928 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
929 &data_offset)) {
930 kfree(bios_connectors);
931 return false;
932 }
933
934 supported_devices =
935 (union atom_supported_devices *)(ctx->bios + data_offset);
936
937 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
938
939 if (frev > 1)
940 max_device = ATOM_MAX_SUPPORTED_DEVICE;
941 else
942 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
943
944 for (i = 0; i < max_device; i++) {
945 ATOM_CONNECTOR_INFO_I2C ci =
946 supported_devices->info.asConnInfo[i];
947
948 bios_connectors[i].valid = false;
949
950 if (!(device_support & (1 << i))) {
951 continue;
952 }
953
954 if (i == ATOM_DEVICE_CV_INDEX) {
955 DRM_DEBUG_KMS("Skipping Component Video\n");
956 continue;
957 }
958
959 bios_connectors[i].connector_type =
960 supported_devices_connector_convert[ci.sucConnectorInfo.
961 sbfAccess.
962 bfConnectorType];
963
964 if (bios_connectors[i].connector_type ==
965 DRM_MODE_CONNECTOR_Unknown)
966 continue;
967
968 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
969
970 bios_connectors[i].line_mux =
971 ci.sucI2cId.ucAccess;
972
973 /* give tv unique connector ids */
974 if (i == ATOM_DEVICE_TV1_INDEX) {
975 bios_connectors[i].ddc_bus.valid = false;
976 bios_connectors[i].line_mux = 50;
977 } else if (i == ATOM_DEVICE_TV2_INDEX) {
978 bios_connectors[i].ddc_bus.valid = false;
979 bios_connectors[i].line_mux = 51;
980 } else if (i == ATOM_DEVICE_CV_INDEX) {
981 bios_connectors[i].ddc_bus.valid = false;
982 bios_connectors[i].line_mux = 52;
983 } else
984 bios_connectors[i].ddc_bus =
985 radeon_lookup_i2c_gpio(rdev,
986 bios_connectors[i].line_mux);
987
988 if ((crev > 1) && (frev > 1)) {
989 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
990 switch (isb) {
991 case 0x4:
992 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
993 break;
994 case 0xa:
995 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
996 break;
997 default:
998 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
999 break;
1000 }
1001 } else {
1002 if (i == ATOM_DEVICE_DFP1_INDEX)
1003 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1004 else if (i == ATOM_DEVICE_DFP2_INDEX)
1005 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1006 else
1007 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1008 }
1009
1010 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1011 * shared with a DVI port, we'll pick up the DVI connector when we
1012 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1013 */
1014 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1015 bios_connectors[i].connector_type =
1016 DRM_MODE_CONNECTOR_VGA;
1017
1018 if (!radeon_atom_apply_quirks
1019 (dev, (1 << i), &bios_connectors[i].connector_type,
1020 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1021 &bios_connectors[i].hpd))
1022 continue;
1023
1024 bios_connectors[i].valid = true;
1025 bios_connectors[i].devices = (1 << i);
1026
1027 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1028 radeon_add_atom_encoder(dev,
1029 radeon_get_encoder_enum(dev,
1030 (1 << i),
1031 dac),
1032 (1 << i),
1033 0);
1034 else
1035 radeon_add_legacy_encoder(dev,
1036 radeon_get_encoder_enum(dev,
1037 (1 << i),
1038 dac),
1039 (1 << i));
1040 }
1041
1042 /* combine shared connectors */
1043 for (i = 0; i < max_device; i++) {
1044 if (bios_connectors[i].valid) {
1045 for (j = 0; j < max_device; j++) {
1046 if (bios_connectors[j].valid && (i != j)) {
1047 if (bios_connectors[i].line_mux ==
1048 bios_connectors[j].line_mux) {
1049 /* make sure not to combine LVDS */
1050 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051 bios_connectors[i].line_mux = 53;
1052 bios_connectors[i].ddc_bus.valid = false;
1053 continue;
1054 }
1055 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1056 bios_connectors[j].line_mux = 53;
1057 bios_connectors[j].ddc_bus.valid = false;
1058 continue;
1059 }
1060 /* combine analog and digital for DVI-I */
1061 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1062 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1063 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1064 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1065 bios_connectors[i].devices |=
1066 bios_connectors[j].devices;
1067 bios_connectors[i].connector_type =
1068 DRM_MODE_CONNECTOR_DVII;
1069 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1070 bios_connectors[i].hpd =
1071 bios_connectors[j].hpd;
1072 bios_connectors[j].valid = false;
1073 }
1074 }
1075 }
1076 }
1077 }
1078 }
1079
1080 /* add the connectors */
1081 for (i = 0; i < max_device; i++) {
1082 if (bios_connectors[i].valid) {
1083 uint16_t connector_object_id =
1084 atombios_get_connector_object_id(dev,
1085 bios_connectors[i].connector_type,
1086 bios_connectors[i].devices);
1087 radeon_add_atom_connector(dev,
1088 bios_connectors[i].line_mux,
1089 bios_connectors[i].devices,
1090 bios_connectors[i].
1091 connector_type,
1092 &bios_connectors[i].ddc_bus,
1093 0,
1094 connector_object_id,
1095 &bios_connectors[i].hpd,
1096 &router);
1097 }
1098 }
1099
1100 radeon_link_encoder_connector(dev);
1101
1102 kfree(bios_connectors);
1103 return true;
1104 }
1105
1106 union firmware_info {
1107 ATOM_FIRMWARE_INFO info;
1108 ATOM_FIRMWARE_INFO_V1_2 info_12;
1109 ATOM_FIRMWARE_INFO_V1_3 info_13;
1110 ATOM_FIRMWARE_INFO_V1_4 info_14;
1111 ATOM_FIRMWARE_INFO_V2_1 info_21;
1112 ATOM_FIRMWARE_INFO_V2_2 info_22;
1113 };
1114
1115 bool radeon_atom_get_clock_info(struct drm_device *dev)
1116 {
1117 struct radeon_device *rdev = dev->dev_private;
1118 struct radeon_mode_info *mode_info = &rdev->mode_info;
1119 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1120 union firmware_info *firmware_info;
1121 uint8_t frev, crev;
1122 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1123 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1124 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1125 struct radeon_pll *spll = &rdev->clock.spll;
1126 struct radeon_pll *mpll = &rdev->clock.mpll;
1127 uint16_t data_offset;
1128
1129 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1130 &frev, &crev, &data_offset)) {
1131 firmware_info =
1132 (union firmware_info *)(mode_info->atom_context->bios +
1133 data_offset);
1134 /* pixel clocks */
1135 p1pll->reference_freq =
1136 le16_to_cpu(firmware_info->info.usReferenceClock);
1137 p1pll->reference_div = 0;
1138
1139 if (crev < 2)
1140 p1pll->pll_out_min =
1141 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1142 else
1143 p1pll->pll_out_min =
1144 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1145 p1pll->pll_out_max =
1146 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1147
1148 if (crev >= 4) {
1149 p1pll->lcd_pll_out_min =
1150 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1151 if (p1pll->lcd_pll_out_min == 0)
1152 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1153 p1pll->lcd_pll_out_max =
1154 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1155 if (p1pll->lcd_pll_out_max == 0)
1156 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1157 } else {
1158 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1159 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1160 }
1161
1162 if (p1pll->pll_out_min == 0) {
1163 if (ASIC_IS_AVIVO(rdev))
1164 p1pll->pll_out_min = 64800;
1165 else
1166 p1pll->pll_out_min = 20000;
1167 }
1168
1169 p1pll->pll_in_min =
1170 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1171 p1pll->pll_in_max =
1172 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1173
1174 *p2pll = *p1pll;
1175
1176 /* system clock */
1177 if (ASIC_IS_DCE4(rdev))
1178 spll->reference_freq =
1179 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1180 else
1181 spll->reference_freq =
1182 le16_to_cpu(firmware_info->info.usReferenceClock);
1183 spll->reference_div = 0;
1184
1185 spll->pll_out_min =
1186 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1187 spll->pll_out_max =
1188 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1189
1190 /* ??? */
1191 if (spll->pll_out_min == 0) {
1192 if (ASIC_IS_AVIVO(rdev))
1193 spll->pll_out_min = 64800;
1194 else
1195 spll->pll_out_min = 20000;
1196 }
1197
1198 spll->pll_in_min =
1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1200 spll->pll_in_max =
1201 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1202
1203 /* memory clock */
1204 if (ASIC_IS_DCE4(rdev))
1205 mpll->reference_freq =
1206 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1207 else
1208 mpll->reference_freq =
1209 le16_to_cpu(firmware_info->info.usReferenceClock);
1210 mpll->reference_div = 0;
1211
1212 mpll->pll_out_min =
1213 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1214 mpll->pll_out_max =
1215 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1216
1217 /* ??? */
1218 if (mpll->pll_out_min == 0) {
1219 if (ASIC_IS_AVIVO(rdev))
1220 mpll->pll_out_min = 64800;
1221 else
1222 mpll->pll_out_min = 20000;
1223 }
1224
1225 mpll->pll_in_min =
1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1227 mpll->pll_in_max =
1228 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1229
1230 rdev->clock.default_sclk =
1231 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1232 rdev->clock.default_mclk =
1233 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1234
1235 if (ASIC_IS_DCE4(rdev)) {
1236 rdev->clock.default_dispclk =
1237 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1238 if (rdev->clock.default_dispclk == 0) {
1239 if (ASIC_IS_DCE5(rdev))
1240 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1241 else
1242 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1243 }
1244 rdev->clock.dp_extclk =
1245 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1246 }
1247 *dcpll = *p1pll;
1248
1249 return true;
1250 }
1251
1252 return false;
1253 }
1254
1255 union igp_info {
1256 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1257 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1258 };
1259
1260 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1261 {
1262 struct radeon_mode_info *mode_info = &rdev->mode_info;
1263 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1264 union igp_info *igp_info;
1265 u8 frev, crev;
1266 u16 data_offset;
1267
1268 /* sideport is AMD only */
1269 if (rdev->family == CHIP_RS600)
1270 return false;
1271
1272 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1273 &frev, &crev, &data_offset)) {
1274 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1275 data_offset);
1276 switch (crev) {
1277 case 1:
1278 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1279 return true;
1280 break;
1281 case 2:
1282 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1283 return true;
1284 break;
1285 default:
1286 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1287 break;
1288 }
1289 }
1290 return false;
1291 }
1292
1293 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1294 struct radeon_encoder_int_tmds *tmds)
1295 {
1296 struct drm_device *dev = encoder->base.dev;
1297 struct radeon_device *rdev = dev->dev_private;
1298 struct radeon_mode_info *mode_info = &rdev->mode_info;
1299 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1300 uint16_t data_offset;
1301 struct _ATOM_TMDS_INFO *tmds_info;
1302 uint8_t frev, crev;
1303 uint16_t maxfreq;
1304 int i;
1305
1306 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1307 &frev, &crev, &data_offset)) {
1308 tmds_info =
1309 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1310 data_offset);
1311
1312 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1313 for (i = 0; i < 4; i++) {
1314 tmds->tmds_pll[i].freq =
1315 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1316 tmds->tmds_pll[i].value =
1317 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1318 tmds->tmds_pll[i].value |=
1319 (tmds_info->asMiscInfo[i].
1320 ucPLL_VCO_Gain & 0x3f) << 6;
1321 tmds->tmds_pll[i].value |=
1322 (tmds_info->asMiscInfo[i].
1323 ucPLL_DutyCycle & 0xf) << 12;
1324 tmds->tmds_pll[i].value |=
1325 (tmds_info->asMiscInfo[i].
1326 ucPLL_VoltageSwing & 0xf) << 16;
1327
1328 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1329 tmds->tmds_pll[i].freq,
1330 tmds->tmds_pll[i].value);
1331
1332 if (maxfreq == tmds->tmds_pll[i].freq) {
1333 tmds->tmds_pll[i].freq = 0xffffffff;
1334 break;
1335 }
1336 }
1337 return true;
1338 }
1339 return false;
1340 }
1341
1342 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1343 struct radeon_atom_ss *ss,
1344 int id)
1345 {
1346 struct radeon_mode_info *mode_info = &rdev->mode_info;
1347 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1348 uint16_t data_offset, size;
1349 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1350 uint8_t frev, crev;
1351 int i, num_indices;
1352
1353 memset(ss, 0, sizeof(struct radeon_atom_ss));
1354 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1355 &frev, &crev, &data_offset)) {
1356 ss_info =
1357 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1358
1359 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1360 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1361
1362 for (i = 0; i < num_indices; i++) {
1363 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1364 ss->percentage =
1365 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1366 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1367 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1368 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1369 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1370 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1371 return true;
1372 }
1373 }
1374 }
1375 return false;
1376 }
1377
1378 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1379 struct radeon_atom_ss *ss,
1380 int id)
1381 {
1382 struct radeon_mode_info *mode_info = &rdev->mode_info;
1383 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1384 u16 data_offset, size;
1385 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1386 u8 frev, crev;
1387 u16 percentage = 0, rate = 0;
1388
1389 /* get any igp specific overrides */
1390 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1391 &frev, &crev, &data_offset)) {
1392 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1393 (mode_info->atom_context->bios + data_offset);
1394 switch (id) {
1395 case ASIC_INTERNAL_SS_ON_TMDS:
1396 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1397 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1398 break;
1399 case ASIC_INTERNAL_SS_ON_HDMI:
1400 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1401 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1402 break;
1403 case ASIC_INTERNAL_SS_ON_LVDS:
1404 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1405 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1406 break;
1407 }
1408 if (percentage)
1409 ss->percentage = percentage;
1410 if (rate)
1411 ss->rate = rate;
1412 }
1413 }
1414
1415 union asic_ss_info {
1416 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1417 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1418 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1419 };
1420
1421 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1422 struct radeon_atom_ss *ss,
1423 int id, u32 clock)
1424 {
1425 struct radeon_mode_info *mode_info = &rdev->mode_info;
1426 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1427 uint16_t data_offset, size;
1428 union asic_ss_info *ss_info;
1429 uint8_t frev, crev;
1430 int i, num_indices;
1431
1432 memset(ss, 0, sizeof(struct radeon_atom_ss));
1433 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1434 &frev, &crev, &data_offset)) {
1435
1436 ss_info =
1437 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1438
1439 switch (frev) {
1440 case 1:
1441 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1442 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1443
1444 for (i = 0; i < num_indices; i++) {
1445 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1446 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1447 ss->percentage =
1448 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1449 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1450 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1451 return true;
1452 }
1453 }
1454 break;
1455 case 2:
1456 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1457 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1458 for (i = 0; i < num_indices; i++) {
1459 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1460 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1461 ss->percentage =
1462 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1463 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1464 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1465 return true;
1466 }
1467 }
1468 break;
1469 case 3:
1470 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1471 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1472 for (i = 0; i < num_indices; i++) {
1473 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1474 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1475 ss->percentage =
1476 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1477 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1478 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1479 if (rdev->flags & RADEON_IS_IGP)
1480 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1481 return true;
1482 }
1483 }
1484 break;
1485 default:
1486 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1487 break;
1488 }
1489
1490 }
1491 return false;
1492 }
1493
1494 union lvds_info {
1495 struct _ATOM_LVDS_INFO info;
1496 struct _ATOM_LVDS_INFO_V12 info_12;
1497 };
1498
1499 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1500 radeon_encoder
1501 *encoder)
1502 {
1503 struct drm_device *dev = encoder->base.dev;
1504 struct radeon_device *rdev = dev->dev_private;
1505 struct radeon_mode_info *mode_info = &rdev->mode_info;
1506 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1507 uint16_t data_offset, misc;
1508 union lvds_info *lvds_info;
1509 uint8_t frev, crev;
1510 struct radeon_encoder_atom_dig *lvds = NULL;
1511 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1512
1513 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1514 &frev, &crev, &data_offset)) {
1515 lvds_info =
1516 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1517 lvds =
1518 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1519
1520 if (!lvds)
1521 return NULL;
1522
1523 lvds->native_mode.clock =
1524 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1525 lvds->native_mode.hdisplay =
1526 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1527 lvds->native_mode.vdisplay =
1528 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1529 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1530 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1531 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1532 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1533 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1534 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1535 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1536 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1537 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1538 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1539 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1540 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1541 lvds->panel_pwr_delay =
1542 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1543 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1544
1545 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1546 if (misc & ATOM_VSYNC_POLARITY)
1547 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1548 if (misc & ATOM_HSYNC_POLARITY)
1549 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1550 if (misc & ATOM_COMPOSITESYNC)
1551 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1552 if (misc & ATOM_INTERLACE)
1553 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1554 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1555 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1556
1557 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1558 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1559
1560 /* set crtc values */
1561 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1562
1563 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1564
1565 encoder->native_mode = lvds->native_mode;
1566
1567 if (encoder_enum == 2)
1568 lvds->linkb = true;
1569 else
1570 lvds->linkb = false;
1571
1572 /* parse the lcd record table */
1573 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1574 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1575 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1576 bool bad_record = false;
1577 u8 *record = (u8 *)(mode_info->atom_context->bios +
1578 data_offset +
1579 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1580 while (*record != ATOM_RECORD_END_TYPE) {
1581 switch (*record) {
1582 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1583 record += sizeof(ATOM_PATCH_RECORD_MODE);
1584 break;
1585 case LCD_RTS_RECORD_TYPE:
1586 record += sizeof(ATOM_LCD_RTS_RECORD);
1587 break;
1588 case LCD_CAP_RECORD_TYPE:
1589 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1590 break;
1591 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1592 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1593 if (fake_edid_record->ucFakeEDIDLength) {
1594 struct edid *edid;
1595 int edid_size =
1596 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1597 edid = kmalloc(edid_size, GFP_KERNEL);
1598 if (edid) {
1599 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1600 fake_edid_record->ucFakeEDIDLength);
1601
1602 if (drm_edid_is_valid(edid))
1603 rdev->mode_info.bios_hardcoded_edid = edid;
1604 else
1605 kfree(edid);
1606 }
1607 }
1608 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1609 break;
1610 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1611 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1612 lvds->native_mode.width_mm = panel_res_record->usHSize;
1613 lvds->native_mode.height_mm = panel_res_record->usVSize;
1614 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1615 break;
1616 default:
1617 DRM_ERROR("Bad LCD record %d\n", *record);
1618 bad_record = true;
1619 break;
1620 }
1621 if (bad_record)
1622 break;
1623 }
1624 }
1625 }
1626 return lvds;
1627 }
1628
1629 struct radeon_encoder_primary_dac *
1630 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1631 {
1632 struct drm_device *dev = encoder->base.dev;
1633 struct radeon_device *rdev = dev->dev_private;
1634 struct radeon_mode_info *mode_info = &rdev->mode_info;
1635 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1636 uint16_t data_offset;
1637 struct _COMPASSIONATE_DATA *dac_info;
1638 uint8_t frev, crev;
1639 uint8_t bg, dac;
1640 struct radeon_encoder_primary_dac *p_dac = NULL;
1641
1642 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1643 &frev, &crev, &data_offset)) {
1644 dac_info = (struct _COMPASSIONATE_DATA *)
1645 (mode_info->atom_context->bios + data_offset);
1646
1647 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1648
1649 if (!p_dac)
1650 return NULL;
1651
1652 bg = dac_info->ucDAC1_BG_Adjustment;
1653 dac = dac_info->ucDAC1_DAC_Adjustment;
1654 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1655
1656 }
1657 return p_dac;
1658 }
1659
1660 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1661 struct drm_display_mode *mode)
1662 {
1663 struct radeon_mode_info *mode_info = &rdev->mode_info;
1664 ATOM_ANALOG_TV_INFO *tv_info;
1665 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1666 ATOM_DTD_FORMAT *dtd_timings;
1667 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1668 u8 frev, crev;
1669 u16 data_offset, misc;
1670
1671 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1672 &frev, &crev, &data_offset))
1673 return false;
1674
1675 switch (crev) {
1676 case 1:
1677 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1678 if (index >= MAX_SUPPORTED_TV_TIMING)
1679 return false;
1680
1681 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1682 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1683 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1684 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1685 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1686
1687 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1688 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1689 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1690 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1691 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1692
1693 mode->flags = 0;
1694 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1695 if (misc & ATOM_VSYNC_POLARITY)
1696 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1697 if (misc & ATOM_HSYNC_POLARITY)
1698 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1699 if (misc & ATOM_COMPOSITESYNC)
1700 mode->flags |= DRM_MODE_FLAG_CSYNC;
1701 if (misc & ATOM_INTERLACE)
1702 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1703 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1704 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1705
1706 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1707
1708 if (index == 1) {
1709 /* PAL timings appear to have wrong values for totals */
1710 mode->crtc_htotal -= 1;
1711 mode->crtc_vtotal -= 1;
1712 }
1713 break;
1714 case 2:
1715 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1716 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1717 return false;
1718
1719 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1720 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1721 le16_to_cpu(dtd_timings->usHBlanking_Time);
1722 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1723 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1724 le16_to_cpu(dtd_timings->usHSyncOffset);
1725 mode->crtc_hsync_end = mode->crtc_hsync_start +
1726 le16_to_cpu(dtd_timings->usHSyncWidth);
1727
1728 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1729 le16_to_cpu(dtd_timings->usVBlanking_Time);
1730 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1731 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1732 le16_to_cpu(dtd_timings->usVSyncOffset);
1733 mode->crtc_vsync_end = mode->crtc_vsync_start +
1734 le16_to_cpu(dtd_timings->usVSyncWidth);
1735
1736 mode->flags = 0;
1737 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1738 if (misc & ATOM_VSYNC_POLARITY)
1739 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1740 if (misc & ATOM_HSYNC_POLARITY)
1741 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1742 if (misc & ATOM_COMPOSITESYNC)
1743 mode->flags |= DRM_MODE_FLAG_CSYNC;
1744 if (misc & ATOM_INTERLACE)
1745 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1746 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1747 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1748
1749 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1750 break;
1751 }
1752 return true;
1753 }
1754
1755 enum radeon_tv_std
1756 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1757 {
1758 struct radeon_mode_info *mode_info = &rdev->mode_info;
1759 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1760 uint16_t data_offset;
1761 uint8_t frev, crev;
1762 struct _ATOM_ANALOG_TV_INFO *tv_info;
1763 enum radeon_tv_std tv_std = TV_STD_NTSC;
1764
1765 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1766 &frev, &crev, &data_offset)) {
1767
1768 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1769 (mode_info->atom_context->bios + data_offset);
1770
1771 switch (tv_info->ucTV_BootUpDefaultStandard) {
1772 case ATOM_TV_NTSC:
1773 tv_std = TV_STD_NTSC;
1774 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1775 break;
1776 case ATOM_TV_NTSCJ:
1777 tv_std = TV_STD_NTSC_J;
1778 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1779 break;
1780 case ATOM_TV_PAL:
1781 tv_std = TV_STD_PAL;
1782 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1783 break;
1784 case ATOM_TV_PALM:
1785 tv_std = TV_STD_PAL_M;
1786 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1787 break;
1788 case ATOM_TV_PALN:
1789 tv_std = TV_STD_PAL_N;
1790 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1791 break;
1792 case ATOM_TV_PALCN:
1793 tv_std = TV_STD_PAL_CN;
1794 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1795 break;
1796 case ATOM_TV_PAL60:
1797 tv_std = TV_STD_PAL_60;
1798 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1799 break;
1800 case ATOM_TV_SECAM:
1801 tv_std = TV_STD_SECAM;
1802 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1803 break;
1804 default:
1805 tv_std = TV_STD_NTSC;
1806 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1807 break;
1808 }
1809 }
1810 return tv_std;
1811 }
1812
1813 struct radeon_encoder_tv_dac *
1814 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1815 {
1816 struct drm_device *dev = encoder->base.dev;
1817 struct radeon_device *rdev = dev->dev_private;
1818 struct radeon_mode_info *mode_info = &rdev->mode_info;
1819 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1820 uint16_t data_offset;
1821 struct _COMPASSIONATE_DATA *dac_info;
1822 uint8_t frev, crev;
1823 uint8_t bg, dac;
1824 struct radeon_encoder_tv_dac *tv_dac = NULL;
1825
1826 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1827 &frev, &crev, &data_offset)) {
1828
1829 dac_info = (struct _COMPASSIONATE_DATA *)
1830 (mode_info->atom_context->bios + data_offset);
1831
1832 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1833
1834 if (!tv_dac)
1835 return NULL;
1836
1837 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1838 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1839 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1840
1841 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1842 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1843 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1844
1845 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1846 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1847 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1848
1849 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1850 }
1851 return tv_dac;
1852 }
1853
1854 static const char *thermal_controller_names[] = {
1855 "NONE",
1856 "lm63",
1857 "adm1032",
1858 "adm1030",
1859 "max6649",
1860 "lm64",
1861 "f75375",
1862 "asc7xxx",
1863 };
1864
1865 static const char *pp_lib_thermal_controller_names[] = {
1866 "NONE",
1867 "lm63",
1868 "adm1032",
1869 "adm1030",
1870 "max6649",
1871 "lm64",
1872 "f75375",
1873 "RV6xx",
1874 "RV770",
1875 "adt7473",
1876 "NONE",
1877 "External GPIO",
1878 "Evergreen",
1879 "emc2103",
1880 "Sumo",
1881 "Northern Islands",
1882 };
1883
1884 union power_info {
1885 struct _ATOM_POWERPLAY_INFO info;
1886 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1887 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1888 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1889 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1890 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1891 };
1892
1893 union pplib_clock_info {
1894 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1895 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1896 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1897 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1898 };
1899
1900 union pplib_power_state {
1901 struct _ATOM_PPLIB_STATE v1;
1902 struct _ATOM_PPLIB_STATE_V2 v2;
1903 };
1904
1905 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1906 int state_index,
1907 u32 misc, u32 misc2)
1908 {
1909 rdev->pm.power_state[state_index].misc = misc;
1910 rdev->pm.power_state[state_index].misc2 = misc2;
1911 /* order matters! */
1912 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1913 rdev->pm.power_state[state_index].type =
1914 POWER_STATE_TYPE_POWERSAVE;
1915 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1916 rdev->pm.power_state[state_index].type =
1917 POWER_STATE_TYPE_BATTERY;
1918 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1919 rdev->pm.power_state[state_index].type =
1920 POWER_STATE_TYPE_BATTERY;
1921 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1922 rdev->pm.power_state[state_index].type =
1923 POWER_STATE_TYPE_BALANCED;
1924 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1925 rdev->pm.power_state[state_index].type =
1926 POWER_STATE_TYPE_PERFORMANCE;
1927 rdev->pm.power_state[state_index].flags &=
1928 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1929 }
1930 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1931 rdev->pm.power_state[state_index].type =
1932 POWER_STATE_TYPE_BALANCED;
1933 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1934 rdev->pm.power_state[state_index].type =
1935 POWER_STATE_TYPE_DEFAULT;
1936 rdev->pm.default_power_state_index = state_index;
1937 rdev->pm.power_state[state_index].default_clock_mode =
1938 &rdev->pm.power_state[state_index].clock_info[0];
1939 } else if (state_index == 0) {
1940 rdev->pm.power_state[state_index].clock_info[0].flags |=
1941 RADEON_PM_MODE_NO_DISPLAY;
1942 }
1943 }
1944
1945 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1946 {
1947 struct radeon_mode_info *mode_info = &rdev->mode_info;
1948 u32 misc, misc2 = 0;
1949 int num_modes = 0, i;
1950 int state_index = 0;
1951 struct radeon_i2c_bus_rec i2c_bus;
1952 union power_info *power_info;
1953 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1954 u16 data_offset;
1955 u8 frev, crev;
1956
1957 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1958 &frev, &crev, &data_offset))
1959 return state_index;
1960 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1961
1962 /* add the i2c bus for thermal/fan chip */
1963 if (power_info->info.ucOverdriveThermalController > 0) {
1964 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1965 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1966 power_info->info.ucOverdriveControllerAddress >> 1);
1967 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1968 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1969 if (rdev->pm.i2c_bus) {
1970 struct i2c_board_info info = { };
1971 const char *name = thermal_controller_names[power_info->info.
1972 ucOverdriveThermalController];
1973 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1974 strlcpy(info.type, name, sizeof(info.type));
1975 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1976 }
1977 }
1978 num_modes = power_info->info.ucNumOfPowerModeEntries;
1979 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1980 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1981 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
1982 if (!rdev->pm.power_state)
1983 return state_index;
1984 /* last mode is usually default, array is low to high */
1985 for (i = 0; i < num_modes; i++) {
1986 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1987 switch (frev) {
1988 case 1:
1989 rdev->pm.power_state[state_index].num_clock_modes = 1;
1990 rdev->pm.power_state[state_index].clock_info[0].mclk =
1991 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1992 rdev->pm.power_state[state_index].clock_info[0].sclk =
1993 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1994 /* skip invalid modes */
1995 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1996 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1997 continue;
1998 rdev->pm.power_state[state_index].pcie_lanes =
1999 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2000 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2001 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2002 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2003 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2004 VOLTAGE_GPIO;
2005 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2006 radeon_lookup_gpio(rdev,
2007 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2008 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2009 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2010 true;
2011 else
2012 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2013 false;
2014 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2015 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2016 VOLTAGE_VDDC;
2017 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2018 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2019 }
2020 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2021 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2022 state_index++;
2023 break;
2024 case 2:
2025 rdev->pm.power_state[state_index].num_clock_modes = 1;
2026 rdev->pm.power_state[state_index].clock_info[0].mclk =
2027 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2028 rdev->pm.power_state[state_index].clock_info[0].sclk =
2029 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2030 /* skip invalid modes */
2031 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2032 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2033 continue;
2034 rdev->pm.power_state[state_index].pcie_lanes =
2035 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2036 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2037 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2038 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2039 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2040 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2041 VOLTAGE_GPIO;
2042 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2043 radeon_lookup_gpio(rdev,
2044 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2045 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2046 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2047 true;
2048 else
2049 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2050 false;
2051 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2052 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2053 VOLTAGE_VDDC;
2054 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2055 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2056 }
2057 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2058 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2059 state_index++;
2060 break;
2061 case 3:
2062 rdev->pm.power_state[state_index].num_clock_modes = 1;
2063 rdev->pm.power_state[state_index].clock_info[0].mclk =
2064 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2065 rdev->pm.power_state[state_index].clock_info[0].sclk =
2066 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2067 /* skip invalid modes */
2068 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2069 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2070 continue;
2071 rdev->pm.power_state[state_index].pcie_lanes =
2072 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2073 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2074 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2075 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2076 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2077 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2078 VOLTAGE_GPIO;
2079 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2080 radeon_lookup_gpio(rdev,
2081 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2082 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2083 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2084 true;
2085 else
2086 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2087 false;
2088 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2089 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2090 VOLTAGE_VDDC;
2091 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2092 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2093 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2094 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2095 true;
2096 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2097 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2098 }
2099 }
2100 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2101 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2102 state_index++;
2103 break;
2104 }
2105 }
2106 /* last mode is usually default */
2107 if (rdev->pm.default_power_state_index == -1) {
2108 rdev->pm.power_state[state_index - 1].type =
2109 POWER_STATE_TYPE_DEFAULT;
2110 rdev->pm.default_power_state_index = state_index - 1;
2111 rdev->pm.power_state[state_index - 1].default_clock_mode =
2112 &rdev->pm.power_state[state_index - 1].clock_info[0];
2113 rdev->pm.power_state[state_index].flags &=
2114 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2115 rdev->pm.power_state[state_index].misc = 0;
2116 rdev->pm.power_state[state_index].misc2 = 0;
2117 }
2118 return state_index;
2119 }
2120
2121 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2122 ATOM_PPLIB_THERMALCONTROLLER *controller)
2123 {
2124 struct radeon_i2c_bus_rec i2c_bus;
2125
2126 /* add the i2c bus for thermal/fan chip */
2127 if (controller->ucType > 0) {
2128 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2129 DRM_INFO("Internal thermal controller %s fan control\n",
2130 (controller->ucFanParameters &
2131 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2132 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2133 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2134 DRM_INFO("Internal thermal controller %s fan control\n",
2135 (controller->ucFanParameters &
2136 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2137 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2138 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2139 DRM_INFO("Internal thermal controller %s fan control\n",
2140 (controller->ucFanParameters &
2141 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2142 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2143 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2144 DRM_INFO("Internal thermal controller %s fan control\n",
2145 (controller->ucFanParameters &
2146 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2147 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2148 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2149 DRM_INFO("Internal thermal controller %s fan control\n",
2150 (controller->ucFanParameters &
2151 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2152 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2153 } else if ((controller->ucType ==
2154 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2155 (controller->ucType ==
2156 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2157 (controller->ucType ==
2158 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2159 DRM_INFO("Special thermal controller config\n");
2160 } else {
2161 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2162 pp_lib_thermal_controller_names[controller->ucType],
2163 controller->ucI2cAddress >> 1,
2164 (controller->ucFanParameters &
2165 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2166 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2167 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2168 if (rdev->pm.i2c_bus) {
2169 struct i2c_board_info info = { };
2170 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2171 info.addr = controller->ucI2cAddress >> 1;
2172 strlcpy(info.type, name, sizeof(info.type));
2173 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2174 }
2175 }
2176 }
2177 }
2178
2179 static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev)
2180 {
2181 struct radeon_mode_info *mode_info = &rdev->mode_info;
2182 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2183 u8 frev, crev;
2184 u16 data_offset;
2185 union firmware_info *firmware_info;
2186 u16 vddc = 0;
2187
2188 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2189 &frev, &crev, &data_offset)) {
2190 firmware_info =
2191 (union firmware_info *)(mode_info->atom_context->bios +
2192 data_offset);
2193 vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2194 }
2195
2196 return vddc;
2197 }
2198
2199 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2200 int state_index, int mode_index,
2201 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2202 {
2203 int j;
2204 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2205 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2206 u16 vddc = radeon_atombios_get_default_vddc(rdev);
2207
2208 rdev->pm.power_state[state_index].misc = misc;
2209 rdev->pm.power_state[state_index].misc2 = misc2;
2210 rdev->pm.power_state[state_index].pcie_lanes =
2211 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2212 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2213 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2214 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2215 rdev->pm.power_state[state_index].type =
2216 POWER_STATE_TYPE_BATTERY;
2217 break;
2218 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2219 rdev->pm.power_state[state_index].type =
2220 POWER_STATE_TYPE_BALANCED;
2221 break;
2222 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2223 rdev->pm.power_state[state_index].type =
2224 POWER_STATE_TYPE_PERFORMANCE;
2225 break;
2226 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2227 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2228 rdev->pm.power_state[state_index].type =
2229 POWER_STATE_TYPE_PERFORMANCE;
2230 break;
2231 }
2232 rdev->pm.power_state[state_index].flags = 0;
2233 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2234 rdev->pm.power_state[state_index].flags |=
2235 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2236 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2237 rdev->pm.power_state[state_index].type =
2238 POWER_STATE_TYPE_DEFAULT;
2239 rdev->pm.default_power_state_index = state_index;
2240 rdev->pm.power_state[state_index].default_clock_mode =
2241 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2242 if (ASIC_IS_DCE5(rdev)) {
2243 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2244 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2245 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2246 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2247 } else {
2248 /* patch the table values with the default slck/mclk from firmware info */
2249 for (j = 0; j < mode_index; j++) {
2250 rdev->pm.power_state[state_index].clock_info[j].mclk =
2251 rdev->clock.default_mclk;
2252 rdev->pm.power_state[state_index].clock_info[j].sclk =
2253 rdev->clock.default_sclk;
2254 if (vddc)
2255 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2256 vddc;
2257 }
2258 }
2259 }
2260 }
2261
2262 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2263 int state_index, int mode_index,
2264 union pplib_clock_info *clock_info)
2265 {
2266 u32 sclk, mclk;
2267
2268 if (rdev->flags & RADEON_IS_IGP) {
2269 if (rdev->family >= CHIP_PALM) {
2270 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2271 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2272 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2273 } else {
2274 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2275 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2276 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2277 }
2278 } else if (ASIC_IS_DCE4(rdev)) {
2279 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2280 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2281 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2282 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2283 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2284 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2285 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2286 VOLTAGE_SW;
2287 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2288 le16_to_cpu(clock_info->evergreen.usVDDC);
2289 } else {
2290 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2291 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2292 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2293 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2294 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2295 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2296 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2297 VOLTAGE_SW;
2298 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2299 le16_to_cpu(clock_info->r600.usVDDC);
2300 }
2301
2302 if (rdev->flags & RADEON_IS_IGP) {
2303 /* skip invalid modes */
2304 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2305 return false;
2306 } else {
2307 /* skip invalid modes */
2308 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2309 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2310 return false;
2311 }
2312 return true;
2313 }
2314
2315 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2316 {
2317 struct radeon_mode_info *mode_info = &rdev->mode_info;
2318 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2319 union pplib_power_state *power_state;
2320 int i, j;
2321 int state_index = 0, mode_index = 0;
2322 union pplib_clock_info *clock_info;
2323 bool valid;
2324 union power_info *power_info;
2325 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2326 u16 data_offset;
2327 u8 frev, crev;
2328
2329 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2330 &frev, &crev, &data_offset))
2331 return state_index;
2332 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2333
2334 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2335 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2336 power_info->pplib.ucNumStates, GFP_KERNEL);
2337 if (!rdev->pm.power_state)
2338 return state_index;
2339 /* first mode is usually default, followed by low to high */
2340 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2341 mode_index = 0;
2342 power_state = (union pplib_power_state *)
2343 (mode_info->atom_context->bios + data_offset +
2344 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2345 i * power_info->pplib.ucStateEntrySize);
2346 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2347 (mode_info->atom_context->bios + data_offset +
2348 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2349 (power_state->v1.ucNonClockStateIndex *
2350 power_info->pplib.ucNonClockSize));
2351 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2352 clock_info = (union pplib_clock_info *)
2353 (mode_info->atom_context->bios + data_offset +
2354 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2355 (power_state->v1.ucClockStateIndices[j] *
2356 power_info->pplib.ucClockInfoSize));
2357 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2358 state_index, mode_index,
2359 clock_info);
2360 if (valid)
2361 mode_index++;
2362 }
2363 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2364 if (mode_index) {
2365 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2366 non_clock_info);
2367 state_index++;
2368 }
2369 }
2370 /* if multiple clock modes, mark the lowest as no display */
2371 for (i = 0; i < state_index; i++) {
2372 if (rdev->pm.power_state[i].num_clock_modes > 1)
2373 rdev->pm.power_state[i].clock_info[0].flags |=
2374 RADEON_PM_MODE_NO_DISPLAY;
2375 }
2376 /* first mode is usually default */
2377 if (rdev->pm.default_power_state_index == -1) {
2378 rdev->pm.power_state[0].type =
2379 POWER_STATE_TYPE_DEFAULT;
2380 rdev->pm.default_power_state_index = 0;
2381 rdev->pm.power_state[0].default_clock_mode =
2382 &rdev->pm.power_state[0].clock_info[0];
2383 }
2384 return state_index;
2385 }
2386
2387 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2388 {
2389 struct radeon_mode_info *mode_info = &rdev->mode_info;
2390 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2391 union pplib_power_state *power_state;
2392 int i, j, non_clock_array_index, clock_array_index;
2393 int state_index = 0, mode_index = 0;
2394 union pplib_clock_info *clock_info;
2395 struct StateArray *state_array;
2396 struct ClockInfoArray *clock_info_array;
2397 struct NonClockInfoArray *non_clock_info_array;
2398 bool valid;
2399 union power_info *power_info;
2400 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2401 u16 data_offset;
2402 u8 frev, crev;
2403
2404 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2405 &frev, &crev, &data_offset))
2406 return state_index;
2407 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2408
2409 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2410 state_array = (struct StateArray *)
2411 (mode_info->atom_context->bios + data_offset +
2412 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2413 clock_info_array = (struct ClockInfoArray *)
2414 (mode_info->atom_context->bios + data_offset +
2415 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2416 non_clock_info_array = (struct NonClockInfoArray *)
2417 (mode_info->atom_context->bios + data_offset +
2418 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2419 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2420 state_array->ucNumEntries, GFP_KERNEL);
2421 if (!rdev->pm.power_state)
2422 return state_index;
2423 for (i = 0; i < state_array->ucNumEntries; i++) {
2424 mode_index = 0;
2425 power_state = (union pplib_power_state *)&state_array->states[i];
2426 /* XXX this might be an inagua bug... */
2427 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2428 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2429 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2430 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2431 clock_array_index = power_state->v2.clockInfoIndex[j];
2432 /* XXX this might be an inagua bug... */
2433 if (clock_array_index >= clock_info_array->ucNumEntries)
2434 continue;
2435 clock_info = (union pplib_clock_info *)
2436 &clock_info_array->clockInfo[clock_array_index];
2437 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2438 state_index, mode_index,
2439 clock_info);
2440 if (valid)
2441 mode_index++;
2442 }
2443 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2444 if (mode_index) {
2445 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2446 non_clock_info);
2447 state_index++;
2448 }
2449 }
2450 /* if multiple clock modes, mark the lowest as no display */
2451 for (i = 0; i < state_index; i++) {
2452 if (rdev->pm.power_state[i].num_clock_modes > 1)
2453 rdev->pm.power_state[i].clock_info[0].flags |=
2454 RADEON_PM_MODE_NO_DISPLAY;
2455 }
2456 /* first mode is usually default */
2457 if (rdev->pm.default_power_state_index == -1) {
2458 rdev->pm.power_state[0].type =
2459 POWER_STATE_TYPE_DEFAULT;
2460 rdev->pm.default_power_state_index = 0;
2461 rdev->pm.power_state[0].default_clock_mode =
2462 &rdev->pm.power_state[0].clock_info[0];
2463 }
2464 return state_index;
2465 }
2466
2467 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2468 {
2469 struct radeon_mode_info *mode_info = &rdev->mode_info;
2470 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2471 u16 data_offset;
2472 u8 frev, crev;
2473 int state_index = 0;
2474
2475 rdev->pm.default_power_state_index = -1;
2476
2477 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2478 &frev, &crev, &data_offset)) {
2479 switch (frev) {
2480 case 1:
2481 case 2:
2482 case 3:
2483 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2484 break;
2485 case 4:
2486 case 5:
2487 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2488 break;
2489 case 6:
2490 state_index = radeon_atombios_parse_power_table_6(rdev);
2491 break;
2492 default:
2493 break;
2494 }
2495 } else {
2496 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2497 if (rdev->pm.power_state) {
2498 /* add the default mode */
2499 rdev->pm.power_state[state_index].type =
2500 POWER_STATE_TYPE_DEFAULT;
2501 rdev->pm.power_state[state_index].num_clock_modes = 1;
2502 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2503 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2504 rdev->pm.power_state[state_index].default_clock_mode =
2505 &rdev->pm.power_state[state_index].clock_info[0];
2506 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2507 rdev->pm.power_state[state_index].pcie_lanes = 16;
2508 rdev->pm.default_power_state_index = state_index;
2509 rdev->pm.power_state[state_index].flags = 0;
2510 state_index++;
2511 }
2512 }
2513
2514 rdev->pm.num_power_states = state_index;
2515
2516 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2517 rdev->pm.current_clock_mode_index = 0;
2518 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2519 }
2520
2521 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2522 {
2523 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2524 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2525
2526 args.ucEnable = enable;
2527
2528 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2529 }
2530
2531 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2532 {
2533 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2534 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2535
2536 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2537 return le32_to_cpu(args.ulReturnEngineClock);
2538 }
2539
2540 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2541 {
2542 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2543 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2544
2545 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2546 return le32_to_cpu(args.ulReturnMemoryClock);
2547 }
2548
2549 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2550 uint32_t eng_clock)
2551 {
2552 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2553 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2554
2555 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2556
2557 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2558 }
2559
2560 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2561 uint32_t mem_clock)
2562 {
2563 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2564 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2565
2566 if (rdev->flags & RADEON_IS_IGP)
2567 return;
2568
2569 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2570
2571 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2572 }
2573
2574 union set_voltage {
2575 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2576 struct _SET_VOLTAGE_PARAMETERS v1;
2577 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2578 };
2579
2580 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2581 {
2582 union set_voltage args;
2583 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2584 u8 frev, crev, volt_index = level;
2585
2586 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2587 return;
2588
2589 switch (crev) {
2590 case 1:
2591 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2592 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2593 args.v1.ucVoltageIndex = volt_index;
2594 break;
2595 case 2:
2596 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2597 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2598 args.v2.usVoltageLevel = cpu_to_le16(level);
2599 break;
2600 default:
2601 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2602 return;
2603 }
2604
2605 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2606 }
2607
2608
2609
2610 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2611 {
2612 struct radeon_device *rdev = dev->dev_private;
2613 uint32_t bios_2_scratch, bios_6_scratch;
2614
2615 if (rdev->family >= CHIP_R600) {
2616 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2617 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2618 } else {
2619 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2620 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2621 }
2622
2623 /* let the bios control the backlight */
2624 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2625
2626 /* tell the bios not to handle mode switching */
2627 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2628
2629 if (rdev->family >= CHIP_R600) {
2630 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2631 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2632 } else {
2633 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2634 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2635 }
2636
2637 }
2638
2639 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2640 {
2641 uint32_t scratch_reg;
2642 int i;
2643
2644 if (rdev->family >= CHIP_R600)
2645 scratch_reg = R600_BIOS_0_SCRATCH;
2646 else
2647 scratch_reg = RADEON_BIOS_0_SCRATCH;
2648
2649 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2650 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2651 }
2652
2653 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2654 {
2655 uint32_t scratch_reg;
2656 int i;
2657
2658 if (rdev->family >= CHIP_R600)
2659 scratch_reg = R600_BIOS_0_SCRATCH;
2660 else
2661 scratch_reg = RADEON_BIOS_0_SCRATCH;
2662
2663 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2664 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2665 }
2666
2667 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2668 {
2669 struct drm_device *dev = encoder->dev;
2670 struct radeon_device *rdev = dev->dev_private;
2671 uint32_t bios_6_scratch;
2672
2673 if (rdev->family >= CHIP_R600)
2674 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2675 else
2676 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2677
2678 if (lock) {
2679 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2680 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2681 } else {
2682 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2683 bios_6_scratch |= ATOM_S6_ACC_MODE;
2684 }
2685
2686 if (rdev->family >= CHIP_R600)
2687 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2688 else
2689 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2690 }
2691
2692 /* at some point we may want to break this out into individual functions */
2693 void
2694 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2695 struct drm_encoder *encoder,
2696 bool connected)
2697 {
2698 struct drm_device *dev = connector->dev;
2699 struct radeon_device *rdev = dev->dev_private;
2700 struct radeon_connector *radeon_connector =
2701 to_radeon_connector(connector);
2702 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2703 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2704
2705 if (rdev->family >= CHIP_R600) {
2706 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2707 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2708 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2709 } else {
2710 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2711 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2712 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2713 }
2714
2715 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2716 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2717 if (connected) {
2718 DRM_DEBUG_KMS("TV1 connected\n");
2719 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2720 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2721 } else {
2722 DRM_DEBUG_KMS("TV1 disconnected\n");
2723 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2724 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2725 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2726 }
2727 }
2728 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2729 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2730 if (connected) {
2731 DRM_DEBUG_KMS("CV connected\n");
2732 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2733 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2734 } else {
2735 DRM_DEBUG_KMS("CV disconnected\n");
2736 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2737 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2738 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2739 }
2740 }
2741 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2742 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2743 if (connected) {
2744 DRM_DEBUG_KMS("LCD1 connected\n");
2745 bios_0_scratch |= ATOM_S0_LCD1;
2746 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2747 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2748 } else {
2749 DRM_DEBUG_KMS("LCD1 disconnected\n");
2750 bios_0_scratch &= ~ATOM_S0_LCD1;
2751 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2752 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2753 }
2754 }
2755 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2756 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2757 if (connected) {
2758 DRM_DEBUG_KMS("CRT1 connected\n");
2759 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2760 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2761 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2762 } else {
2763 DRM_DEBUG_KMS("CRT1 disconnected\n");
2764 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2765 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2766 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2767 }
2768 }
2769 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2770 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2771 if (connected) {
2772 DRM_DEBUG_KMS("CRT2 connected\n");
2773 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2774 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2775 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2776 } else {
2777 DRM_DEBUG_KMS("CRT2 disconnected\n");
2778 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2779 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2780 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2781 }
2782 }
2783 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2784 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2785 if (connected) {
2786 DRM_DEBUG_KMS("DFP1 connected\n");
2787 bios_0_scratch |= ATOM_S0_DFP1;
2788 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2789 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2790 } else {
2791 DRM_DEBUG_KMS("DFP1 disconnected\n");
2792 bios_0_scratch &= ~ATOM_S0_DFP1;
2793 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2794 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2795 }
2796 }
2797 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2798 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2799 if (connected) {
2800 DRM_DEBUG_KMS("DFP2 connected\n");
2801 bios_0_scratch |= ATOM_S0_DFP2;
2802 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2803 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2804 } else {
2805 DRM_DEBUG_KMS("DFP2 disconnected\n");
2806 bios_0_scratch &= ~ATOM_S0_DFP2;
2807 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2808 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2809 }
2810 }
2811 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2812 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2813 if (connected) {
2814 DRM_DEBUG_KMS("DFP3 connected\n");
2815 bios_0_scratch |= ATOM_S0_DFP3;
2816 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2817 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2818 } else {
2819 DRM_DEBUG_KMS("DFP3 disconnected\n");
2820 bios_0_scratch &= ~ATOM_S0_DFP3;
2821 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2822 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2823 }
2824 }
2825 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2826 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2827 if (connected) {
2828 DRM_DEBUG_KMS("DFP4 connected\n");
2829 bios_0_scratch |= ATOM_S0_DFP4;
2830 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2831 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2832 } else {
2833 DRM_DEBUG_KMS("DFP4 disconnected\n");
2834 bios_0_scratch &= ~ATOM_S0_DFP4;
2835 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2836 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2837 }
2838 }
2839 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2840 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2841 if (connected) {
2842 DRM_DEBUG_KMS("DFP5 connected\n");
2843 bios_0_scratch |= ATOM_S0_DFP5;
2844 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2845 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2846 } else {
2847 DRM_DEBUG_KMS("DFP5 disconnected\n");
2848 bios_0_scratch &= ~ATOM_S0_DFP5;
2849 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2850 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2851 }
2852 }
2853
2854 if (rdev->family >= CHIP_R600) {
2855 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2856 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2857 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2858 } else {
2859 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2860 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2861 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2862 }
2863 }
2864
2865 void
2866 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2867 {
2868 struct drm_device *dev = encoder->dev;
2869 struct radeon_device *rdev = dev->dev_private;
2870 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2871 uint32_t bios_3_scratch;
2872
2873 if (rdev->family >= CHIP_R600)
2874 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2875 else
2876 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2877
2878 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2879 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2880 bios_3_scratch |= (crtc << 18);
2881 }
2882 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2883 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2884 bios_3_scratch |= (crtc << 24);
2885 }
2886 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2887 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2888 bios_3_scratch |= (crtc << 16);
2889 }
2890 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2891 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2892 bios_3_scratch |= (crtc << 20);
2893 }
2894 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2895 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2896 bios_3_scratch |= (crtc << 17);
2897 }
2898 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2899 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2900 bios_3_scratch |= (crtc << 19);
2901 }
2902 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2903 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2904 bios_3_scratch |= (crtc << 23);
2905 }
2906 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2907 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2908 bios_3_scratch |= (crtc << 25);
2909 }
2910
2911 if (rdev->family >= CHIP_R600)
2912 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2913 else
2914 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2915 }
2916
2917 void
2918 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2919 {
2920 struct drm_device *dev = encoder->dev;
2921 struct radeon_device *rdev = dev->dev_private;
2922 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2923 uint32_t bios_2_scratch;
2924
2925 if (rdev->family >= CHIP_R600)
2926 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2927 else
2928 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2929
2930 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2931 if (on)
2932 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2933 else
2934 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2935 }
2936 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2937 if (on)
2938 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2939 else
2940 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2941 }
2942 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2943 if (on)
2944 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2945 else
2946 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2947 }
2948 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2949 if (on)
2950 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2951 else
2952 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2953 }
2954 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2955 if (on)
2956 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2957 else
2958 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2959 }
2960 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2961 if (on)
2962 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2963 else
2964 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2965 }
2966 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2967 if (on)
2968 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2969 else
2970 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2971 }
2972 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2973 if (on)
2974 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2975 else
2976 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2977 }
2978 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2979 if (on)
2980 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2981 else
2982 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2983 }
2984 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2985 if (on)
2986 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2987 else
2988 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2989 }
2990
2991 if (rdev->family >= CHIP_R600)
2992 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2993 else
2994 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2995 }
kernel source for telekom puls (alcatel/mediatek)