drivers/gpu/drm/radeon/radeon_asic.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_ASIC_H__
  29 #define __RADEON_ASIC_H__
  30
  31 /*
  32  * common functions
  33  */
  34 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  35 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  36
  37 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  38 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  39 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  40
  41 /*
  42  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  43  */
  44 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
  45 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  46 void r100_errata(struct radeon_device *rdev);
  47 void r100_vram_info(struct radeon_device *rdev);
  48 int r100_gpu_reset(struct radeon_device *rdev);
  49 int r100_mc_init(struct radeon_device *rdev);
  50 void r100_mc_fini(struct radeon_device *rdev);
  51 int r100_wb_init(struct radeon_device *rdev);
  52 void r100_wb_fini(struct radeon_device *rdev);
  53 int r100_gart_enable(struct radeon_device *rdev);
  54 void r100_pci_gart_disable(struct radeon_device *rdev);
  55 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  56 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  57 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  58 void r100_cp_fini(struct radeon_device *rdev);
  59 void r100_cp_disable(struct radeon_device *rdev);
  60 void r100_ring_start(struct radeon_device *rdev);
  61 int r100_irq_set(struct radeon_device *rdev);
  62 int r100_irq_process(struct radeon_device *rdev);
  63 void r100_fence_ring_emit(struct radeon_device *rdev,
  64                           struct radeon_fence *fence);
  65 int r100_cs_parse(struct radeon_cs_parser *p);
  66 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  67 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  68 int r100_copy_blit(struct radeon_device *rdev,
  69                    uint64_t src_offset,
  70                    uint64_t dst_offset,
  71                    unsigned num_pages,
  72                    struct radeon_fence *fence);
  73
  74 static struct radeon_asic r100_asic = {
  75         .errata = &r100_errata,
  76         .vram_info = &r100_vram_info,
  77         .gpu_reset = &r100_gpu_reset,
  78         .mc_init = &r100_mc_init,
  79         .mc_fini = &r100_mc_fini,
  80         .wb_init = &r100_wb_init,
  81         .wb_fini = &r100_wb_fini,
  82         .gart_enable = &r100_gart_enable,
  83         .gart_disable = &r100_pci_gart_disable,
  84         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
  85         .gart_set_page = &r100_pci_gart_set_page,
  86         .cp_init = &r100_cp_init,
  87         .cp_fini = &r100_cp_fini,
  88         .cp_disable = &r100_cp_disable,
  89         .ring_start = &r100_ring_start,
  90         .irq_set = &r100_irq_set,
  91         .irq_process = &r100_irq_process,
  92         .fence_ring_emit = &r100_fence_ring_emit,
  93         .cs_parse = &r100_cs_parse,
  94         .copy_blit = &r100_copy_blit,
  95         .copy_dma = NULL,
  96         .copy = &r100_copy_blit,
  97         .set_engine_clock = &radeon_legacy_set_engine_clock,
  98         .set_memory_clock = NULL,
  99         .set_pcie_lanes = NULL,
 100         .set_clock_gating = &radeon_legacy_set_clock_gating,
 101 };
 102
 103
 104 /*
 105  * r300,r350,rv350,rv380
 106  */
 107 void r300_errata(struct radeon_device *rdev);
 108 void r300_vram_info(struct radeon_device *rdev);
 109 int r300_gpu_reset(struct radeon_device *rdev);
 110 int r300_mc_init(struct radeon_device *rdev);
 111 void r300_mc_fini(struct radeon_device *rdev);
 112 void r300_ring_start(struct radeon_device *rdev);
 113 void r300_fence_ring_emit(struct radeon_device *rdev,
 114                           struct radeon_fence *fence);
 115 int r300_cs_parse(struct radeon_cs_parser *p);
 116 int r300_gart_enable(struct radeon_device *rdev);
 117 void rv370_pcie_gart_disable(struct radeon_device *rdev);
 118 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
 119 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 120 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
 121 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 122 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 123 int r300_copy_dma(struct radeon_device *rdev,
 124                   uint64_t src_offset,
 125                   uint64_t dst_offset,
 126                   unsigned num_pages,
 127                   struct radeon_fence *fence);
 128 static struct radeon_asic r300_asic = {
 129         .errata = &r300_errata,
 130         .vram_info = &r300_vram_info,
 131         .gpu_reset = &r300_gpu_reset,
 132         .mc_init = &r300_mc_init,
 133         .mc_fini = &r300_mc_fini,
 134         .wb_init = &r100_wb_init,
 135         .wb_fini = &r100_wb_fini,
 136         .gart_enable = &r300_gart_enable,
 137         .gart_disable = &r100_pci_gart_disable,
 138         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
 139         .gart_set_page = &r100_pci_gart_set_page,
 140         .cp_init = &r100_cp_init,
 141         .cp_fini = &r100_cp_fini,
 142         .cp_disable = &r100_cp_disable,
 143         .ring_start = &r300_ring_start,
 144         .irq_set = &r100_irq_set,
 145         .irq_process = &r100_irq_process,
 146         .fence_ring_emit = &r300_fence_ring_emit,
 147         .cs_parse = &r300_cs_parse,
 148         .copy_blit = &r100_copy_blit,
 149         .copy_dma = &r300_copy_dma,
 150         .copy = &r100_copy_blit,
 151         .set_engine_clock = &radeon_legacy_set_engine_clock,
 152         .set_memory_clock = NULL,
 153         .set_pcie_lanes = &rv370_set_pcie_lanes,
 154         .set_clock_gating = &radeon_legacy_set_clock_gating,
 155 };
 156
 157 /*
 158  * r420,r423,rv410
 159  */
 160 void r420_errata(struct radeon_device *rdev);
 161 void r420_vram_info(struct radeon_device *rdev);
 162 int r420_mc_init(struct radeon_device *rdev);
 163 void r420_mc_fini(struct radeon_device *rdev);
 164 static struct radeon_asic r420_asic = {
 165         .errata = &r420_errata,
 166         .vram_info = &r420_vram_info,
 167         .gpu_reset = &r300_gpu_reset,
 168         .mc_init = &r420_mc_init,
 169         .mc_fini = &r420_mc_fini,
 170         .wb_init = &r100_wb_init,
 171         .wb_fini = &r100_wb_fini,
 172         .gart_enable = &r300_gart_enable,
 173         .gart_disable = &rv370_pcie_gart_disable,
 174         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 175         .gart_set_page = &rv370_pcie_gart_set_page,
 176         .cp_init = &r100_cp_init,
 177         .cp_fini = &r100_cp_fini,
 178         .cp_disable = &r100_cp_disable,
 179         .ring_start = &r300_ring_start,
 180         .irq_set = &r100_irq_set,
 181         .irq_process = &r100_irq_process,
 182         .fence_ring_emit = &r300_fence_ring_emit,
 183         .cs_parse = &r300_cs_parse,
 184         .copy_blit = &r100_copy_blit,
 185         .copy_dma = &r300_copy_dma,
 186         .copy = &r100_copy_blit,
 187         .set_engine_clock = &radeon_atom_set_engine_clock,
 188         .set_memory_clock = &radeon_atom_set_memory_clock,
 189         .set_pcie_lanes = &rv370_set_pcie_lanes,
 190         .set_clock_gating = &radeon_atom_set_clock_gating,
 191 };
 192
 193
 194 /*
 195  * rs400,rs480
 196  */
 197 void rs400_errata(struct radeon_device *rdev);
 198 void rs400_vram_info(struct radeon_device *rdev);
 199 int rs400_mc_init(struct radeon_device *rdev);
 200 void rs400_mc_fini(struct radeon_device *rdev);
 201 int rs400_gart_enable(struct radeon_device *rdev);
 202 void rs400_gart_disable(struct radeon_device *rdev);
 203 void rs400_gart_tlb_flush(struct radeon_device *rdev);
 204 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 205 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 206 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 207 static struct radeon_asic rs400_asic = {
 208         .errata = &rs400_errata,
 209         .vram_info = &rs400_vram_info,
 210         .gpu_reset = &r300_gpu_reset,
 211         .mc_init = &rs400_mc_init,
 212         .mc_fini = &rs400_mc_fini,
 213         .wb_init = &r100_wb_init,
 214         .wb_fini = &r100_wb_fini,
 215         .gart_enable = &rs400_gart_enable,
 216         .gart_disable = &rs400_gart_disable,
 217         .gart_tlb_flush = &rs400_gart_tlb_flush,
 218         .gart_set_page = &rs400_gart_set_page,
 219         .cp_init = &r100_cp_init,
 220         .cp_fini = &r100_cp_fini,
 221         .cp_disable = &r100_cp_disable,
 222         .ring_start = &r300_ring_start,
 223         .irq_set = &r100_irq_set,
 224         .irq_process = &r100_irq_process,
 225         .fence_ring_emit = &r300_fence_ring_emit,
 226         .cs_parse = &r300_cs_parse,
 227         .copy_blit = &r100_copy_blit,
 228         .copy_dma = &r300_copy_dma,
 229         .copy = &r100_copy_blit,
 230         .set_engine_clock = &radeon_legacy_set_engine_clock,
 231         .set_memory_clock = NULL,
 232         .set_pcie_lanes = NULL,
 233         .set_clock_gating = &radeon_legacy_set_clock_gating,
 234 };
 235
 236
 237 /*
 238  * rs600.
 239  */
 240 void rs600_errata(struct radeon_device *rdev);
 241 void rs600_vram_info(struct radeon_device *rdev);
 242 int rs600_mc_init(struct radeon_device *rdev);
 243 void rs600_mc_fini(struct radeon_device *rdev);
 244 int rs600_irq_set(struct radeon_device *rdev);
 245 int rs600_gart_enable(struct radeon_device *rdev);
 246 void rs600_gart_disable(struct radeon_device *rdev);
 247 void rs600_gart_tlb_flush(struct radeon_device *rdev);
 248 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 249 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 250 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 251 static struct radeon_asic rs600_asic = {
 252         .errata = &rs600_errata,
 253         .vram_info = &rs600_vram_info,
 254         .gpu_reset = &r300_gpu_reset,
 255         .mc_init = &rs600_mc_init,
 256         .mc_fini = &rs600_mc_fini,
 257         .wb_init = &r100_wb_init,
 258         .wb_fini = &r100_wb_fini,
 259         .gart_enable = &rs600_gart_enable,
 260         .gart_disable = &rs600_gart_disable,
 261         .gart_tlb_flush = &rs600_gart_tlb_flush,
 262         .gart_set_page = &rs600_gart_set_page,
 263         .cp_init = &r100_cp_init,
 264         .cp_fini = &r100_cp_fini,
 265         .cp_disable = &r100_cp_disable,
 266         .ring_start = &r300_ring_start,
 267         .irq_set = &rs600_irq_set,
 268         .irq_process = &r100_irq_process,
 269         .fence_ring_emit = &r300_fence_ring_emit,
 270         .cs_parse = &r300_cs_parse,
 271         .copy_blit = &r100_copy_blit,
 272         .copy_dma = &r300_copy_dma,
 273         .copy = &r100_copy_blit,
 274         .set_engine_clock = &radeon_atom_set_engine_clock,
 275         .set_memory_clock = &radeon_atom_set_memory_clock,
 276         .set_pcie_lanes = NULL,
 277         .set_clock_gating = &radeon_atom_set_clock_gating,
 278 };
 279
 280
 281 /*
 282  * rs690,rs740
 283  */
 284 void rs690_errata(struct radeon_device *rdev);
 285 void rs690_vram_info(struct radeon_device *rdev);
 286 int rs690_mc_init(struct radeon_device *rdev);
 287 void rs690_mc_fini(struct radeon_device *rdev);
 288 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 289 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 290 static struct radeon_asic rs690_asic = {
 291         .errata = &rs690_errata,
 292         .vram_info = &rs690_vram_info,
 293         .gpu_reset = &r300_gpu_reset,
 294         .mc_init = &rs690_mc_init,
 295         .mc_fini = &rs690_mc_fini,
 296         .wb_init = &r100_wb_init,
 297         .wb_fini = &r100_wb_fini,
 298         .gart_enable = &rs400_gart_enable,
 299         .gart_disable = &rs400_gart_disable,
 300         .gart_tlb_flush = &rs400_gart_tlb_flush,
 301         .gart_set_page = &rs400_gart_set_page,
 302         .cp_init = &r100_cp_init,
 303         .cp_fini = &r100_cp_fini,
 304         .cp_disable = &r100_cp_disable,
 305         .ring_start = &r300_ring_start,
 306         .irq_set = &rs600_irq_set,
 307         .irq_process = &r100_irq_process,
 308         .fence_ring_emit = &r300_fence_ring_emit,
 309         .cs_parse = &r300_cs_parse,
 310         .copy_blit = &r100_copy_blit,
 311         .copy_dma = &r300_copy_dma,
 312         .copy = &r300_copy_dma,
 313         .set_engine_clock = &radeon_atom_set_engine_clock,
 314         .set_memory_clock = &radeon_atom_set_memory_clock,
 315         .set_pcie_lanes = NULL,
 316         .set_clock_gating = &radeon_atom_set_clock_gating,
 317 };
 318
 319
 320 /*
 321  * rv515
 322  */
 323 void rv515_errata(struct radeon_device *rdev);
 324 void rv515_vram_info(struct radeon_device *rdev);
 325 int rv515_gpu_reset(struct radeon_device *rdev);
 326 int rv515_mc_init(struct radeon_device *rdev);
 327 void rv515_mc_fini(struct radeon_device *rdev);
 328 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 329 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 330 void rv515_ring_start(struct radeon_device *rdev);
 331 uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
 332 void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 333 static struct radeon_asic rv515_asic = {
 334         .errata = &rv515_errata,
 335         .vram_info = &rv515_vram_info,
 336         .gpu_reset = &rv515_gpu_reset,
 337         .mc_init = &rv515_mc_init,
 338         .mc_fini = &rv515_mc_fini,
 339         .wb_init = &r100_wb_init,
 340         .wb_fini = &r100_wb_fini,
 341         .gart_enable = &r300_gart_enable,
 342         .gart_disable = &rv370_pcie_gart_disable,
 343         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 344         .gart_set_page = &rv370_pcie_gart_set_page,
 345         .cp_init = &r100_cp_init,
 346         .cp_fini = &r100_cp_fini,
 347         .cp_disable = &r100_cp_disable,
 348         .ring_start = &rv515_ring_start,
 349         .irq_set = &r100_irq_set,
 350         .irq_process = &r100_irq_process,
 351         .fence_ring_emit = &r300_fence_ring_emit,
 352         .cs_parse = &r100_cs_parse,
 353         .copy_blit = &r100_copy_blit,
 354         .copy_dma = &r300_copy_dma,
 355         .copy = &r100_copy_blit,
 356         .set_engine_clock = &radeon_atom_set_engine_clock,
 357         .set_memory_clock = &radeon_atom_set_memory_clock,
 358         .set_pcie_lanes = &rv370_set_pcie_lanes,
 359         .set_clock_gating = &radeon_atom_set_clock_gating,
 360 };
 361
 362
 363 /*
 364  * r520,rv530,rv560,rv570,r580
 365  */
 366 void r520_errata(struct radeon_device *rdev);
 367 void r520_vram_info(struct radeon_device *rdev);
 368 int r520_mc_init(struct radeon_device *rdev);
 369 void r520_mc_fini(struct radeon_device *rdev);
 370 static struct radeon_asic r520_asic = {
 371         .errata = &r520_errata,
 372         .vram_info = &r520_vram_info,
 373         .gpu_reset = &rv515_gpu_reset,
 374         .mc_init = &r520_mc_init,
 375         .mc_fini = &r520_mc_fini,
 376         .wb_init = &r100_wb_init,
 377         .wb_fini = &r100_wb_fini,
 378         .gart_enable = &r300_gart_enable,
 379         .gart_disable = &rv370_pcie_gart_disable,
 380         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
 381         .gart_set_page = &rv370_pcie_gart_set_page,
 382         .cp_init = &r100_cp_init,
 383         .cp_fini = &r100_cp_fini,
 384         .cp_disable = &r100_cp_disable,
 385         .ring_start = &rv515_ring_start,
 386         .irq_set = &r100_irq_set,
 387         .irq_process = &r100_irq_process,
 388         .fence_ring_emit = &r300_fence_ring_emit,
 389         .cs_parse = &r100_cs_parse,
 390         .copy_blit = &r100_copy_blit,
 391         .copy_dma = &r300_copy_dma,
 392         .copy = &r100_copy_blit,
 393         .set_engine_clock = &radeon_atom_set_engine_clock,
 394         .set_memory_clock = &radeon_atom_set_memory_clock,
 395         .set_pcie_lanes = &rv370_set_pcie_lanes,
 396         .set_clock_gating = &radeon_atom_set_clock_gating,
 397 };
 398
 399 /*
 400  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710
 401  */
 402 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 403 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 404
 405 #endif