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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
67
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
73
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
77
78 /*
79 * Modules parameters.
80 */
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
91 extern int radeon_tv;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98
99 /*
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting
101 * symbol;
102 */
103 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
106 #define RADEON_IB_POOL_SIZE 16
107 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
108 #define RADEONFB_CONN_LIMIT 4
109 #define RADEON_BIOS_NUM_SCRATCH 8
110
111 /* max number of rings */
112 #define RADEON_NUM_RINGS 5
113
114 /* fence seq are set to this number when signaled */
115 #define RADEON_FENCE_SIGNALED_SEQ 0LL
116
117 /* internal ring indices */
118 /* r1xx+ has gfx CP ring */
119 #define RADEON_RING_TYPE_GFX_INDEX 0
120
121 /* cayman has 2 compute CP rings */
122 #define CAYMAN_RING_TYPE_CP1_INDEX 1
123 #define CAYMAN_RING_TYPE_CP2_INDEX 2
124
125 /* R600+ has an async dma ring */
126 #define R600_RING_TYPE_DMA_INDEX 3
127 /* cayman add a second async dma ring */
128 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
129
130 /* hardcode those limit for now */
131 #define RADEON_VA_IB_OFFSET (1 << 20)
132 #define RADEON_VA_RESERVED_SIZE (8 << 20)
133 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
134
135 /*
136 * Errata workarounds.
137 */
138 enum radeon_pll_errata {
139 CHIP_ERRATA_R300_CG = 0x00000001,
140 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
141 CHIP_ERRATA_PLL_DELAY = 0x00000004
142 };
143
144
145 struct radeon_device;
146
147
148 /*
149 * BIOS.
150 */
151 bool radeon_get_bios(struct radeon_device *rdev);
152
153 /*
154 * Dummy page
155 */
156 struct radeon_dummy_page {
157 struct page *page;
158 dma_addr_t addr;
159 };
160 int radeon_dummy_page_init(struct radeon_device *rdev);
161 void radeon_dummy_page_fini(struct radeon_device *rdev);
162
163
164 /*
165 * Clocks
166 */
167 struct radeon_clock {
168 struct radeon_pll p1pll;
169 struct radeon_pll p2pll;
170 struct radeon_pll dcpll;
171 struct radeon_pll spll;
172 struct radeon_pll mpll;
173 /* 10 Khz units */
174 uint32_t default_mclk;
175 uint32_t default_sclk;
176 uint32_t default_dispclk;
177 uint32_t dp_extclk;
178 uint32_t max_pixel_clock;
179 };
180
181 /*
182 * Power management
183 */
184 int radeon_pm_init(struct radeon_device *rdev);
185 void radeon_pm_fini(struct radeon_device *rdev);
186 void radeon_pm_compute_clocks(struct radeon_device *rdev);
187 void radeon_pm_suspend(struct radeon_device *rdev);
188 void radeon_pm_resume(struct radeon_device *rdev);
189 void radeon_combios_get_power_modes(struct radeon_device *rdev);
190 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
191 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
192 void rs690_pm_info(struct radeon_device *rdev);
193 extern int rv6xx_get_temp(struct radeon_device *rdev);
194 extern int rv770_get_temp(struct radeon_device *rdev);
195 extern int evergreen_get_temp(struct radeon_device *rdev);
196 extern int sumo_get_temp(struct radeon_device *rdev);
197 extern int si_get_temp(struct radeon_device *rdev);
198 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
199 unsigned *bankh, unsigned *mtaspect,
200 unsigned *tile_split);
201
202 /*
203 * Fences.
204 */
205 struct radeon_fence_driver {
206 uint32_t scratch_reg;
207 uint64_t gpu_addr;
208 volatile uint32_t *cpu_addr;
209 /* sync_seq is protected by ring emission lock */
210 uint64_t sync_seq[RADEON_NUM_RINGS];
211 atomic64_t last_seq;
212 unsigned long last_activity;
213 bool initialized;
214 };
215
216 struct radeon_fence {
217 struct radeon_device *rdev;
218 struct kref kref;
219 /* protected by radeon_fence.lock */
220 uint64_t seq;
221 /* RB, DMA, etc. */
222 unsigned ring;
223 };
224
225 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
226 int radeon_fence_driver_init(struct radeon_device *rdev);
227 void radeon_fence_driver_fini(struct radeon_device *rdev);
228 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
229 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
230 void radeon_fence_process(struct radeon_device *rdev, int ring);
231 bool radeon_fence_signaled(struct radeon_fence *fence);
232 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
233 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
234 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
235 int radeon_fence_wait_any(struct radeon_device *rdev,
236 struct radeon_fence **fences,
237 bool intr);
238 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
239 void radeon_fence_unref(struct radeon_fence **fence);
240 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
241 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
242 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
243 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
244 struct radeon_fence *b)
245 {
246 if (!a) {
247 return b;
248 }
249
250 if (!b) {
251 return a;
252 }
253
254 BUG_ON(a->ring != b->ring);
255
256 if (a->seq > b->seq) {
257 return a;
258 } else {
259 return b;
260 }
261 }
262
263 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
264 struct radeon_fence *b)
265 {
266 if (!a) {
267 return false;
268 }
269
270 if (!b) {
271 return true;
272 }
273
274 BUG_ON(a->ring != b->ring);
275
276 return a->seq < b->seq;
277 }
278
279 /*
280 * Tiling registers
281 */
282 struct radeon_surface_reg {
283 struct radeon_bo *bo;
284 };
285
286 #define RADEON_GEM_MAX_SURFACES 8
287
288 /*
289 * TTM.
290 */
291 struct radeon_mman {
292 struct ttm_bo_global_ref bo_global_ref;
293 struct drm_global_reference mem_global_ref;
294 struct ttm_bo_device bdev;
295 bool mem_global_referenced;
296 bool initialized;
297 };
298
299 /* bo virtual address in a specific vm */
300 struct radeon_bo_va {
301 /* protected by bo being reserved */
302 struct list_head bo_list;
303 uint64_t soffset;
304 uint64_t eoffset;
305 uint32_t flags;
306 bool valid;
307 unsigned ref_count;
308
309 /* protected by vm mutex */
310 struct list_head vm_list;
311
312 /* constant after initialization */
313 struct radeon_vm *vm;
314 struct radeon_bo *bo;
315 };
316
317 struct radeon_bo {
318 /* Protected by gem.mutex */
319 struct list_head list;
320 /* Protected by tbo.reserved */
321 u32 placements[3];
322 u32 busy_placements[3];
323 struct ttm_placement placement;
324 struct ttm_buffer_object tbo;
325 struct ttm_bo_kmap_obj kmap;
326 unsigned pin_count;
327 void *kptr;
328 u32 tiling_flags;
329 u32 pitch;
330 int surface_reg;
331 /* list of all virtual address to which this bo
332 * is associated to
333 */
334 struct list_head va;
335 /* Constant after initialization */
336 struct radeon_device *rdev;
337 struct drm_gem_object gem_base;
338
339 struct ttm_bo_kmap_obj dma_buf_vmap;
340 int vmapping_count;
341 };
342 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
343
344 struct radeon_bo_list {
345 struct ttm_validate_buffer tv;
346 struct radeon_bo *bo;
347 uint64_t gpu_offset;
348 unsigned rdomain;
349 unsigned wdomain;
350 u32 tiling_flags;
351 };
352
353 /* sub-allocation manager, it has to be protected by another lock.
354 * By conception this is an helper for other part of the driver
355 * like the indirect buffer or semaphore, which both have their
356 * locking.
357 *
358 * Principe is simple, we keep a list of sub allocation in offset
359 * order (first entry has offset == 0, last entry has the highest
360 * offset).
361 *
362 * When allocating new object we first check if there is room at
363 * the end total_size - (last_object_offset + last_object_size) >=
364 * alloc_size. If so we allocate new object there.
365 *
366 * When there is not enough room at the end, we start waiting for
367 * each sub object until we reach object_offset+object_size >=
368 * alloc_size, this object then become the sub object we return.
369 *
370 * Alignment can't be bigger than page size.
371 *
372 * Hole are not considered for allocation to keep things simple.
373 * Assumption is that there won't be hole (all object on same
374 * alignment).
375 */
376 struct radeon_sa_manager {
377 wait_queue_head_t wq;
378 struct radeon_bo *bo;
379 struct list_head *hole;
380 struct list_head flist[RADEON_NUM_RINGS];
381 struct list_head olist;
382 unsigned size;
383 uint64_t gpu_addr;
384 void *cpu_ptr;
385 uint32_t domain;
386 };
387
388 struct radeon_sa_bo;
389
390 /* sub-allocation buffer */
391 struct radeon_sa_bo {
392 struct list_head olist;
393 struct list_head flist;
394 struct radeon_sa_manager *manager;
395 unsigned soffset;
396 unsigned eoffset;
397 struct radeon_fence *fence;
398 };
399
400 /*
401 * GEM objects.
402 */
403 struct radeon_gem {
404 struct mutex mutex;
405 struct list_head objects;
406 };
407
408 int radeon_gem_init(struct radeon_device *rdev);
409 void radeon_gem_fini(struct radeon_device *rdev);
410 int radeon_gem_object_create(struct radeon_device *rdev, int size,
411 int alignment, int initial_domain,
412 bool discardable, bool kernel,
413 struct drm_gem_object **obj);
414
415 int radeon_mode_dumb_create(struct drm_file *file_priv,
416 struct drm_device *dev,
417 struct drm_mode_create_dumb *args);
418 int radeon_mode_dumb_mmap(struct drm_file *filp,
419 struct drm_device *dev,
420 uint32_t handle, uint64_t *offset_p);
421 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
422 struct drm_device *dev,
423 uint32_t handle);
424
425 /*
426 * Semaphores.
427 */
428 /* everything here is constant */
429 struct radeon_semaphore {
430 struct radeon_sa_bo *sa_bo;
431 signed waiters;
432 uint64_t gpu_addr;
433 };
434
435 int radeon_semaphore_create(struct radeon_device *rdev,
436 struct radeon_semaphore **semaphore);
437 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
438 struct radeon_semaphore *semaphore);
439 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
440 struct radeon_semaphore *semaphore);
441 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
442 struct radeon_semaphore *semaphore,
443 int signaler, int waiter);
444 void radeon_semaphore_free(struct radeon_device *rdev,
445 struct radeon_semaphore **semaphore,
446 struct radeon_fence *fence);
447
448 /*
449 * GART structures, functions & helpers
450 */
451 struct radeon_mc;
452
453 #define RADEON_GPU_PAGE_SIZE 4096
454 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
455 #define RADEON_GPU_PAGE_SHIFT 12
456 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
457
458 struct radeon_gart {
459 dma_addr_t table_addr;
460 struct radeon_bo *robj;
461 void *ptr;
462 unsigned num_gpu_pages;
463 unsigned num_cpu_pages;
464 unsigned table_size;
465 struct page **pages;
466 dma_addr_t *pages_addr;
467 bool ready;
468 };
469
470 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
471 void radeon_gart_table_ram_free(struct radeon_device *rdev);
472 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
473 void radeon_gart_table_vram_free(struct radeon_device *rdev);
474 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
475 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
476 int radeon_gart_init(struct radeon_device *rdev);
477 void radeon_gart_fini(struct radeon_device *rdev);
478 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
479 int pages);
480 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
481 int pages, struct page **pagelist,
482 dma_addr_t *dma_addr);
483 void radeon_gart_restore(struct radeon_device *rdev);
484
485
486 /*
487 * GPU MC structures, functions & helpers
488 */
489 struct radeon_mc {
490 resource_size_t aper_size;
491 resource_size_t aper_base;
492 resource_size_t agp_base;
493 /* for some chips with <= 32MB we need to lie
494 * about vram size near mc fb location */
495 u64 mc_vram_size;
496 u64 visible_vram_size;
497 u64 gtt_size;
498 u64 gtt_start;
499 u64 gtt_end;
500 u64 vram_start;
501 u64 vram_end;
502 unsigned vram_width;
503 u64 real_vram_size;
504 int vram_mtrr;
505 bool vram_is_ddr;
506 bool igp_sideport_enabled;
507 u64 gtt_base_align;
508 };
509
510 bool radeon_combios_sideport_present(struct radeon_device *rdev);
511 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
512
513 /*
514 * GPU scratch registers structures, functions & helpers
515 */
516 struct radeon_scratch {
517 unsigned num_reg;
518 uint32_t reg_base;
519 bool free[32];
520 uint32_t reg[32];
521 };
522
523 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
524 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
525
526
527 /*
528 * IRQS.
529 */
530
531 struct radeon_unpin_work {
532 struct work_struct work;
533 struct radeon_device *rdev;
534 int crtc_id;
535 struct radeon_fence *fence;
536 struct drm_pending_vblank_event *event;
537 struct radeon_bo *old_rbo;
538 u64 new_crtc_base;
539 };
540
541 struct r500_irq_stat_regs {
542 u32 disp_int;
543 u32 hdmi0_status;
544 };
545
546 struct r600_irq_stat_regs {
547 u32 disp_int;
548 u32 disp_int_cont;
549 u32 disp_int_cont2;
550 u32 d1grph_int;
551 u32 d2grph_int;
552 u32 hdmi0_status;
553 u32 hdmi1_status;
554 };
555
556 struct evergreen_irq_stat_regs {
557 u32 disp_int;
558 u32 disp_int_cont;
559 u32 disp_int_cont2;
560 u32 disp_int_cont3;
561 u32 disp_int_cont4;
562 u32 disp_int_cont5;
563 u32 d1grph_int;
564 u32 d2grph_int;
565 u32 d3grph_int;
566 u32 d4grph_int;
567 u32 d5grph_int;
568 u32 d6grph_int;
569 u32 afmt_status1;
570 u32 afmt_status2;
571 u32 afmt_status3;
572 u32 afmt_status4;
573 u32 afmt_status5;
574 u32 afmt_status6;
575 };
576
577 union radeon_irq_stat_regs {
578 struct r500_irq_stat_regs r500;
579 struct r600_irq_stat_regs r600;
580 struct evergreen_irq_stat_regs evergreen;
581 };
582
583 #define RADEON_MAX_HPD_PINS 6
584 #define RADEON_MAX_CRTCS 6
585 #define RADEON_MAX_AFMT_BLOCKS 6
586
587 struct radeon_irq {
588 bool installed;
589 spinlock_t lock;
590 atomic_t ring_int[RADEON_NUM_RINGS];
591 bool crtc_vblank_int[RADEON_MAX_CRTCS];
592 atomic_t pflip[RADEON_MAX_CRTCS];
593 wait_queue_head_t vblank_queue;
594 bool hpd[RADEON_MAX_HPD_PINS];
595 bool afmt[RADEON_MAX_AFMT_BLOCKS];
596 union radeon_irq_stat_regs stat_regs;
597 };
598
599 int radeon_irq_kms_init(struct radeon_device *rdev);
600 void radeon_irq_kms_fini(struct radeon_device *rdev);
601 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
602 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
603 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
604 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
605 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
606 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
607 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
608 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
609
610 /*
611 * CP & rings.
612 */
613
614 struct radeon_ib {
615 struct radeon_sa_bo *sa_bo;
616 uint32_t length_dw;
617 uint64_t gpu_addr;
618 uint32_t *ptr;
619 int ring;
620 struct radeon_fence *fence;
621 struct radeon_vm *vm;
622 bool is_const_ib;
623 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
624 struct radeon_semaphore *semaphore;
625 };
626
627 struct radeon_ring {
628 struct radeon_bo *ring_obj;
629 volatile uint32_t *ring;
630 unsigned rptr;
631 unsigned rptr_offs;
632 unsigned rptr_reg;
633 unsigned rptr_save_reg;
634 u64 next_rptr_gpu_addr;
635 volatile u32 *next_rptr_cpu_addr;
636 unsigned wptr;
637 unsigned wptr_old;
638 unsigned wptr_reg;
639 unsigned ring_size;
640 unsigned ring_free_dw;
641 int count_dw;
642 unsigned long last_activity;
643 unsigned last_rptr;
644 uint64_t gpu_addr;
645 uint32_t align_mask;
646 uint32_t ptr_mask;
647 bool ready;
648 u32 ptr_reg_shift;
649 u32 ptr_reg_mask;
650 u32 nop;
651 u32 idx;
652 };
653
654 /*
655 * VM
656 */
657
658 /* maximum number of VMIDs */
659 #define RADEON_NUM_VM 16
660
661 /* defines number of bits in page table versus page directory,
662 * a page is 4KB so we have 12 bits offset, 9 bits in the page
663 * table and the remaining 19 bits are in the page directory */
664 #define RADEON_VM_BLOCK_SIZE 9
665
666 /* number of entries in page table */
667 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
668
669 struct radeon_vm {
670 struct list_head list;
671 struct list_head va;
672 unsigned id;
673
674 /* contains the page directory */
675 struct radeon_sa_bo *page_directory;
676 uint64_t pd_gpu_addr;
677
678 /* array of page tables, one for each page directory entry */
679 struct radeon_sa_bo **page_tables;
680
681 struct mutex mutex;
682 /* last fence for cs using this vm */
683 struct radeon_fence *fence;
684 /* last flush or NULL if we still need to flush */
685 struct radeon_fence *last_flush;
686 };
687
688 struct radeon_vm_manager {
689 struct mutex lock;
690 struct list_head lru_vm;
691 struct radeon_fence *active[RADEON_NUM_VM];
692 struct radeon_sa_manager sa_manager;
693 uint32_t max_pfn;
694 /* number of VMIDs */
695 unsigned nvm;
696 /* vram base address for page table entry */
697 u64 vram_base_offset;
698 /* is vm enabled? */
699 bool enabled;
700 };
701
702 /*
703 * file private structure
704 */
705 struct radeon_fpriv {
706 struct radeon_vm vm;
707 };
708
709 /*
710 * R6xx+ IH ring
711 */
712 struct r600_ih {
713 struct radeon_bo *ring_obj;
714 volatile uint32_t *ring;
715 unsigned rptr;
716 unsigned ring_size;
717 uint64_t gpu_addr;
718 uint32_t ptr_mask;
719 atomic_t lock;
720 bool enabled;
721 };
722
723 struct r600_blit_cp_primitives {
724 void (*set_render_target)(struct radeon_device *rdev, int format,
725 int w, int h, u64 gpu_addr);
726 void (*cp_set_surface_sync)(struct radeon_device *rdev,
727 u32 sync_type, u32 size,
728 u64 mc_addr);
729 void (*set_shaders)(struct radeon_device *rdev);
730 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
731 void (*set_tex_resource)(struct radeon_device *rdev,
732 int format, int w, int h, int pitch,
733 u64 gpu_addr, u32 size);
734 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
735 int x2, int y2);
736 void (*draw_auto)(struct radeon_device *rdev);
737 void (*set_default_state)(struct radeon_device *rdev);
738 };
739
740 struct r600_blit {
741 struct radeon_bo *shader_obj;
742 struct r600_blit_cp_primitives primitives;
743 int max_dim;
744 int ring_size_common;
745 int ring_size_per_loop;
746 u64 shader_gpu_addr;
747 u32 vs_offset, ps_offset;
748 u32 state_offset;
749 u32 state_len;
750 };
751
752 /*
753 * SI RLC stuff
754 */
755 struct si_rlc {
756 /* for power gating */
757 struct radeon_bo *save_restore_obj;
758 uint64_t save_restore_gpu_addr;
759 /* for clear state */
760 struct radeon_bo *clear_state_obj;
761 uint64_t clear_state_gpu_addr;
762 };
763
764 int radeon_ib_get(struct radeon_device *rdev, int ring,
765 struct radeon_ib *ib, struct radeon_vm *vm,
766 unsigned size);
767 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
768 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
769 struct radeon_ib *const_ib);
770 int radeon_ib_pool_init(struct radeon_device *rdev);
771 void radeon_ib_pool_fini(struct radeon_device *rdev);
772 int radeon_ib_ring_tests(struct radeon_device *rdev);
773 /* Ring access between begin & end cannot sleep */
774 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
775 struct radeon_ring *ring);
776 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
777 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
778 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
779 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
780 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
781 void radeon_ring_undo(struct radeon_ring *ring);
782 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
783 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
784 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
785 void radeon_ring_lockup_update(struct radeon_ring *ring);
786 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
787 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
788 uint32_t **data);
789 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
790 unsigned size, uint32_t *data);
791 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
792 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
793 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
794 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
795
796
797 /* r600 async dma */
798 void r600_dma_stop(struct radeon_device *rdev);
799 int r600_dma_resume(struct radeon_device *rdev);
800 void r600_dma_fini(struct radeon_device *rdev);
801
802 void cayman_dma_stop(struct radeon_device *rdev);
803 int cayman_dma_resume(struct radeon_device *rdev);
804 void cayman_dma_fini(struct radeon_device *rdev);
805
806 /*
807 * CS.
808 */
809 struct radeon_cs_reloc {
810 struct drm_gem_object *gobj;
811 struct radeon_bo *robj;
812 struct radeon_bo_list lobj;
813 uint32_t handle;
814 uint32_t flags;
815 };
816
817 struct radeon_cs_chunk {
818 uint32_t chunk_id;
819 uint32_t length_dw;
820 int kpage_idx[2];
821 uint32_t *kpage[2];
822 uint32_t *kdata;
823 void __user *user_ptr;
824 int last_copied_page;
825 int last_page_index;
826 };
827
828 struct radeon_cs_parser {
829 struct device *dev;
830 struct radeon_device *rdev;
831 struct drm_file *filp;
832 /* chunks */
833 unsigned nchunks;
834 struct radeon_cs_chunk *chunks;
835 uint64_t *chunks_array;
836 /* IB */
837 unsigned idx;
838 /* relocations */
839 unsigned nrelocs;
840 struct radeon_cs_reloc *relocs;
841 struct radeon_cs_reloc **relocs_ptr;
842 struct list_head validated;
843 unsigned dma_reloc_idx;
844 /* indices of various chunks */
845 int chunk_ib_idx;
846 int chunk_relocs_idx;
847 int chunk_flags_idx;
848 int chunk_const_ib_idx;
849 struct radeon_ib ib;
850 struct radeon_ib const_ib;
851 void *track;
852 unsigned family;
853 int parser_error;
854 u32 cs_flags;
855 u32 ring;
856 s32 priority;
857 };
858
859 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
860 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
861
862 struct radeon_cs_packet {
863 unsigned idx;
864 unsigned type;
865 unsigned reg;
866 unsigned opcode;
867 int count;
868 unsigned one_reg_wr;
869 };
870
871 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
872 struct radeon_cs_packet *pkt,
873 unsigned idx, unsigned reg);
874 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
875 struct radeon_cs_packet *pkt);
876
877
878 /*
879 * AGP
880 */
881 int radeon_agp_init(struct radeon_device *rdev);
882 void radeon_agp_resume(struct radeon_device *rdev);
883 void radeon_agp_suspend(struct radeon_device *rdev);
884 void radeon_agp_fini(struct radeon_device *rdev);
885
886
887 /*
888 * Writeback
889 */
890 struct radeon_wb {
891 struct radeon_bo *wb_obj;
892 volatile uint32_t *wb;
893 uint64_t gpu_addr;
894 bool enabled;
895 bool use_event;
896 };
897
898 #define RADEON_WB_SCRATCH_OFFSET 0
899 #define RADEON_WB_RING0_NEXT_RPTR 256
900 #define RADEON_WB_CP_RPTR_OFFSET 1024
901 #define RADEON_WB_CP1_RPTR_OFFSET 1280
902 #define RADEON_WB_CP2_RPTR_OFFSET 1536
903 #define R600_WB_DMA_RPTR_OFFSET 1792
904 #define R600_WB_IH_WPTR_OFFSET 2048
905 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
906 #define R600_WB_EVENT_OFFSET 3072
907
908 /**
909 * struct radeon_pm - power management datas
910 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
911 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
912 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
913 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
914 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
915 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
916 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
917 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
918 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
919 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
920 * @needed_bandwidth: current bandwidth needs
921 *
922 * It keeps track of various data needed to take powermanagement decision.
923 * Bandwidth need is used to determine minimun clock of the GPU and memory.
924 * Equation between gpu/memory clock and available bandwidth is hw dependent
925 * (type of memory, bus size, efficiency, ...)
926 */
927
928 enum radeon_pm_method {
929 PM_METHOD_PROFILE,
930 PM_METHOD_DYNPM,
931 };
932
933 enum radeon_dynpm_state {
934 DYNPM_STATE_DISABLED,
935 DYNPM_STATE_MINIMUM,
936 DYNPM_STATE_PAUSED,
937 DYNPM_STATE_ACTIVE,
938 DYNPM_STATE_SUSPENDED,
939 };
940 enum radeon_dynpm_action {
941 DYNPM_ACTION_NONE,
942 DYNPM_ACTION_MINIMUM,
943 DYNPM_ACTION_DOWNCLOCK,
944 DYNPM_ACTION_UPCLOCK,
945 DYNPM_ACTION_DEFAULT
946 };
947
948 enum radeon_voltage_type {
949 VOLTAGE_NONE = 0,
950 VOLTAGE_GPIO,
951 VOLTAGE_VDDC,
952 VOLTAGE_SW
953 };
954
955 enum radeon_pm_state_type {
956 POWER_STATE_TYPE_DEFAULT,
957 POWER_STATE_TYPE_POWERSAVE,
958 POWER_STATE_TYPE_BATTERY,
959 POWER_STATE_TYPE_BALANCED,
960 POWER_STATE_TYPE_PERFORMANCE,
961 };
962
963 enum radeon_pm_profile_type {
964 PM_PROFILE_DEFAULT,
965 PM_PROFILE_AUTO,
966 PM_PROFILE_LOW,
967 PM_PROFILE_MID,
968 PM_PROFILE_HIGH,
969 };
970
971 #define PM_PROFILE_DEFAULT_IDX 0
972 #define PM_PROFILE_LOW_SH_IDX 1
973 #define PM_PROFILE_MID_SH_IDX 2
974 #define PM_PROFILE_HIGH_SH_IDX 3
975 #define PM_PROFILE_LOW_MH_IDX 4
976 #define PM_PROFILE_MID_MH_IDX 5
977 #define PM_PROFILE_HIGH_MH_IDX 6
978 #define PM_PROFILE_MAX 7
979
980 struct radeon_pm_profile {
981 int dpms_off_ps_idx;
982 int dpms_on_ps_idx;
983 int dpms_off_cm_idx;
984 int dpms_on_cm_idx;
985 };
986
987 enum radeon_int_thermal_type {
988 THERMAL_TYPE_NONE,
989 THERMAL_TYPE_RV6XX,
990 THERMAL_TYPE_RV770,
991 THERMAL_TYPE_EVERGREEN,
992 THERMAL_TYPE_SUMO,
993 THERMAL_TYPE_NI,
994 THERMAL_TYPE_SI,
995 };
996
997 struct radeon_voltage {
998 enum radeon_voltage_type type;
999 /* gpio voltage */
1000 struct radeon_gpio_rec gpio;
1001 u32 delay; /* delay in usec from voltage drop to sclk change */
1002 bool active_high; /* voltage drop is active when bit is high */
1003 /* VDDC voltage */
1004 u8 vddc_id; /* index into vddc voltage table */
1005 u8 vddci_id; /* index into vddci voltage table */
1006 bool vddci_enabled;
1007 /* r6xx+ sw */
1008 u16 voltage;
1009 /* evergreen+ vddci */
1010 u16 vddci;
1011 };
1012
1013 /* clock mode flags */
1014 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1015
1016 struct radeon_pm_clock_info {
1017 /* memory clock */
1018 u32 mclk;
1019 /* engine clock */
1020 u32 sclk;
1021 /* voltage info */
1022 struct radeon_voltage voltage;
1023 /* standardized clock flags */
1024 u32 flags;
1025 };
1026
1027 /* state flags */
1028 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1029
1030 struct radeon_power_state {
1031 enum radeon_pm_state_type type;
1032 struct radeon_pm_clock_info *clock_info;
1033 /* number of valid clock modes in this power state */
1034 int num_clock_modes;
1035 struct radeon_pm_clock_info *default_clock_mode;
1036 /* standardized state flags */
1037 u32 flags;
1038 u32 misc; /* vbios specific flags */
1039 u32 misc2; /* vbios specific flags */
1040 int pcie_lanes; /* pcie lanes */
1041 };
1042
1043 /*
1044 * Some modes are overclocked by very low value, accept them
1045 */
1046 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1047
1048 struct radeon_pm {
1049 struct mutex mutex;
1050 /* write locked while reprogramming mclk */
1051 struct rw_semaphore mclk_lock;
1052 u32 active_crtcs;
1053 int active_crtc_count;
1054 int req_vblank;
1055 bool vblank_sync;
1056 fixed20_12 max_bandwidth;
1057 fixed20_12 igp_sideport_mclk;
1058 fixed20_12 igp_system_mclk;
1059 fixed20_12 igp_ht_link_clk;
1060 fixed20_12 igp_ht_link_width;
1061 fixed20_12 k8_bandwidth;
1062 fixed20_12 sideport_bandwidth;
1063 fixed20_12 ht_bandwidth;
1064 fixed20_12 core_bandwidth;
1065 fixed20_12 sclk;
1066 fixed20_12 mclk;
1067 fixed20_12 needed_bandwidth;
1068 struct radeon_power_state *power_state;
1069 /* number of valid power states */
1070 int num_power_states;
1071 int current_power_state_index;
1072 int current_clock_mode_index;
1073 int requested_power_state_index;
1074 int requested_clock_mode_index;
1075 int default_power_state_index;
1076 u32 current_sclk;
1077 u32 current_mclk;
1078 u16 current_vddc;
1079 u16 current_vddci;
1080 u32 default_sclk;
1081 u32 default_mclk;
1082 u16 default_vddc;
1083 u16 default_vddci;
1084 struct radeon_i2c_chan *i2c_bus;
1085 /* selected pm method */
1086 enum radeon_pm_method pm_method;
1087 /* dynpm power management */
1088 struct delayed_work dynpm_idle_work;
1089 enum radeon_dynpm_state dynpm_state;
1090 enum radeon_dynpm_action dynpm_planned_action;
1091 unsigned long dynpm_action_timeout;
1092 bool dynpm_can_upclock;
1093 bool dynpm_can_downclock;
1094 /* profile-based power management */
1095 enum radeon_pm_profile_type profile;
1096 int profile_index;
1097 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1098 /* internal thermal controller on rv6xx+ */
1099 enum radeon_int_thermal_type int_thermal_type;
1100 struct device *int_hwmon_dev;
1101 };
1102
1103 int radeon_pm_get_type_index(struct radeon_device *rdev,
1104 enum radeon_pm_state_type ps_type,
1105 int instance);
1106
1107 struct r600_audio {
1108 int channels;
1109 int rate;
1110 int bits_per_sample;
1111 u8 status_bits;
1112 u8 category_code;
1113 };
1114
1115 /*
1116 * Benchmarking
1117 */
1118 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1119
1120
1121 /*
1122 * Testing
1123 */
1124 void radeon_test_moves(struct radeon_device *rdev);
1125 void radeon_test_ring_sync(struct radeon_device *rdev,
1126 struct radeon_ring *cpA,
1127 struct radeon_ring *cpB);
1128 void radeon_test_syncing(struct radeon_device *rdev);
1129
1130
1131 /*
1132 * Debugfs
1133 */
1134 struct radeon_debugfs {
1135 struct drm_info_list *files;
1136 unsigned num_files;
1137 };
1138
1139 int radeon_debugfs_add_files(struct radeon_device *rdev,
1140 struct drm_info_list *files,
1141 unsigned nfiles);
1142 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1143
1144
1145 /*
1146 * ASIC specific functions.
1147 */
1148 struct radeon_asic {
1149 int (*init)(struct radeon_device *rdev);
1150 void (*fini)(struct radeon_device *rdev);
1151 int (*resume)(struct radeon_device *rdev);
1152 int (*suspend)(struct radeon_device *rdev);
1153 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1154 int (*asic_reset)(struct radeon_device *rdev);
1155 /* ioctl hw specific callback. Some hw might want to perform special
1156 * operation on specific ioctl. For instance on wait idle some hw
1157 * might want to perform and HDP flush through MMIO as it seems that
1158 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1159 * through ring.
1160 */
1161 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1162 /* check if 3D engine is idle */
1163 bool (*gui_idle)(struct radeon_device *rdev);
1164 /* wait for mc_idle */
1165 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1166 /* gart */
1167 struct {
1168 void (*tlb_flush)(struct radeon_device *rdev);
1169 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1170 } gart;
1171 struct {
1172 int (*init)(struct radeon_device *rdev);
1173 void (*fini)(struct radeon_device *rdev);
1174
1175 u32 pt_ring_index;
1176 void (*set_page)(struct radeon_device *rdev, uint64_t pe,
1177 uint64_t addr, unsigned count,
1178 uint32_t incr, uint32_t flags);
1179 } vm;
1180 /* ring specific callbacks */
1181 struct {
1182 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1183 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1184 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1185 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1186 struct radeon_semaphore *semaphore, bool emit_wait);
1187 int (*cs_parse)(struct radeon_cs_parser *p);
1188 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1189 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1190 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1191 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1192 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1193 } ring[RADEON_NUM_RINGS];
1194 /* irqs */
1195 struct {
1196 int (*set)(struct radeon_device *rdev);
1197 int (*process)(struct radeon_device *rdev);
1198 } irq;
1199 /* displays */
1200 struct {
1201 /* display watermarks */
1202 void (*bandwidth_update)(struct radeon_device *rdev);
1203 /* get frame count */
1204 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1205 /* wait for vblank */
1206 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1207 /* set backlight level */
1208 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1209 /* get backlight level */
1210 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1211 } display;
1212 /* copy functions for bo handling */
1213 struct {
1214 int (*blit)(struct radeon_device *rdev,
1215 uint64_t src_offset,
1216 uint64_t dst_offset,
1217 unsigned num_gpu_pages,
1218 struct radeon_fence **fence);
1219 u32 blit_ring_index;
1220 int (*dma)(struct radeon_device *rdev,
1221 uint64_t src_offset,
1222 uint64_t dst_offset,
1223 unsigned num_gpu_pages,
1224 struct radeon_fence **fence);
1225 u32 dma_ring_index;
1226 /* method used for bo copy */
1227 int (*copy)(struct radeon_device *rdev,
1228 uint64_t src_offset,
1229 uint64_t dst_offset,
1230 unsigned num_gpu_pages,
1231 struct radeon_fence **fence);
1232 /* ring used for bo copies */
1233 u32 copy_ring_index;
1234 } copy;
1235 /* surfaces */
1236 struct {
1237 int (*set_reg)(struct radeon_device *rdev, int reg,
1238 uint32_t tiling_flags, uint32_t pitch,
1239 uint32_t offset, uint32_t obj_size);
1240 void (*clear_reg)(struct radeon_device *rdev, int reg);
1241 } surface;
1242 /* hotplug detect */
1243 struct {
1244 void (*init)(struct radeon_device *rdev);
1245 void (*fini)(struct radeon_device *rdev);
1246 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1247 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1248 } hpd;
1249 /* power management */
1250 struct {
1251 void (*misc)(struct radeon_device *rdev);
1252 void (*prepare)(struct radeon_device *rdev);
1253 void (*finish)(struct radeon_device *rdev);
1254 void (*init_profile)(struct radeon_device *rdev);
1255 void (*get_dynpm_state)(struct radeon_device *rdev);
1256 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1257 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1258 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1259 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1260 int (*get_pcie_lanes)(struct radeon_device *rdev);
1261 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1262 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1263 } pm;
1264 /* pageflipping */
1265 struct {
1266 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1267 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1268 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1269 } pflip;
1270 };
1271
1272 /*
1273 * Asic structures
1274 */
1275 struct r100_asic {
1276 const unsigned *reg_safe_bm;
1277 unsigned reg_safe_bm_size;
1278 u32 hdp_cntl;
1279 };
1280
1281 struct r300_asic {
1282 const unsigned *reg_safe_bm;
1283 unsigned reg_safe_bm_size;
1284 u32 resync_scratch;
1285 u32 hdp_cntl;
1286 };
1287
1288 struct r600_asic {
1289 unsigned max_pipes;
1290 unsigned max_tile_pipes;
1291 unsigned max_simds;
1292 unsigned max_backends;
1293 unsigned max_gprs;
1294 unsigned max_threads;
1295 unsigned max_stack_entries;
1296 unsigned max_hw_contexts;
1297 unsigned max_gs_threads;
1298 unsigned sx_max_export_size;
1299 unsigned sx_max_export_pos_size;
1300 unsigned sx_max_export_smx_size;
1301 unsigned sq_num_cf_insts;
1302 unsigned tiling_nbanks;
1303 unsigned tiling_npipes;
1304 unsigned tiling_group_size;
1305 unsigned tile_config;
1306 unsigned backend_map;
1307 };
1308
1309 struct rv770_asic {
1310 unsigned max_pipes;
1311 unsigned max_tile_pipes;
1312 unsigned max_simds;
1313 unsigned max_backends;
1314 unsigned max_gprs;
1315 unsigned max_threads;
1316 unsigned max_stack_entries;
1317 unsigned max_hw_contexts;
1318 unsigned max_gs_threads;
1319 unsigned sx_max_export_size;
1320 unsigned sx_max_export_pos_size;
1321 unsigned sx_max_export_smx_size;
1322 unsigned sq_num_cf_insts;
1323 unsigned sx_num_of_sets;
1324 unsigned sc_prim_fifo_size;
1325 unsigned sc_hiz_tile_fifo_size;
1326 unsigned sc_earlyz_tile_fifo_fize;
1327 unsigned tiling_nbanks;
1328 unsigned tiling_npipes;
1329 unsigned tiling_group_size;
1330 unsigned tile_config;
1331 unsigned backend_map;
1332 };
1333
1334 struct evergreen_asic {
1335 unsigned num_ses;
1336 unsigned max_pipes;
1337 unsigned max_tile_pipes;
1338 unsigned max_simds;
1339 unsigned max_backends;
1340 unsigned max_gprs;
1341 unsigned max_threads;
1342 unsigned max_stack_entries;
1343 unsigned max_hw_contexts;
1344 unsigned max_gs_threads;
1345 unsigned sx_max_export_size;
1346 unsigned sx_max_export_pos_size;
1347 unsigned sx_max_export_smx_size;
1348 unsigned sq_num_cf_insts;
1349 unsigned sx_num_of_sets;
1350 unsigned sc_prim_fifo_size;
1351 unsigned sc_hiz_tile_fifo_size;
1352 unsigned sc_earlyz_tile_fifo_size;
1353 unsigned tiling_nbanks;
1354 unsigned tiling_npipes;
1355 unsigned tiling_group_size;
1356 unsigned tile_config;
1357 unsigned backend_map;
1358 };
1359
1360 struct cayman_asic {
1361 unsigned max_shader_engines;
1362 unsigned max_pipes_per_simd;
1363 unsigned max_tile_pipes;
1364 unsigned max_simds_per_se;
1365 unsigned max_backends_per_se;
1366 unsigned max_texture_channel_caches;
1367 unsigned max_gprs;
1368 unsigned max_threads;
1369 unsigned max_gs_threads;
1370 unsigned max_stack_entries;
1371 unsigned sx_num_of_sets;
1372 unsigned sx_max_export_size;
1373 unsigned sx_max_export_pos_size;
1374 unsigned sx_max_export_smx_size;
1375 unsigned max_hw_contexts;
1376 unsigned sq_num_cf_insts;
1377 unsigned sc_prim_fifo_size;
1378 unsigned sc_hiz_tile_fifo_size;
1379 unsigned sc_earlyz_tile_fifo_size;
1380
1381 unsigned num_shader_engines;
1382 unsigned num_shader_pipes_per_simd;
1383 unsigned num_tile_pipes;
1384 unsigned num_simds_per_se;
1385 unsigned num_backends_per_se;
1386 unsigned backend_disable_mask_per_asic;
1387 unsigned backend_map;
1388 unsigned num_texture_channel_caches;
1389 unsigned mem_max_burst_length_bytes;
1390 unsigned mem_row_size_in_kb;
1391 unsigned shader_engine_tile_size;
1392 unsigned num_gpus;
1393 unsigned multi_gpu_tile_size;
1394
1395 unsigned tile_config;
1396 };
1397
1398 struct si_asic {
1399 unsigned max_shader_engines;
1400 unsigned max_tile_pipes;
1401 unsigned max_cu_per_sh;
1402 unsigned max_sh_per_se;
1403 unsigned max_backends_per_se;
1404 unsigned max_texture_channel_caches;
1405 unsigned max_gprs;
1406 unsigned max_gs_threads;
1407 unsigned max_hw_contexts;
1408 unsigned sc_prim_fifo_size_frontend;
1409 unsigned sc_prim_fifo_size_backend;
1410 unsigned sc_hiz_tile_fifo_size;
1411 unsigned sc_earlyz_tile_fifo_size;
1412
1413 unsigned num_tile_pipes;
1414 unsigned num_backends_per_se;
1415 unsigned backend_disable_mask_per_asic;
1416 unsigned backend_map;
1417 unsigned num_texture_channel_caches;
1418 unsigned mem_max_burst_length_bytes;
1419 unsigned mem_row_size_in_kb;
1420 unsigned shader_engine_tile_size;
1421 unsigned num_gpus;
1422 unsigned multi_gpu_tile_size;
1423
1424 unsigned tile_config;
1425 };
1426
1427 union radeon_asic_config {
1428 struct r300_asic r300;
1429 struct r100_asic r100;
1430 struct r600_asic r600;
1431 struct rv770_asic rv770;
1432 struct evergreen_asic evergreen;
1433 struct cayman_asic cayman;
1434 struct si_asic si;
1435 };
1436
1437 /*
1438 * asic initizalization from radeon_asic.c
1439 */
1440 void radeon_agp_disable(struct radeon_device *rdev);
1441 int radeon_asic_init(struct radeon_device *rdev);
1442
1443
1444 /*
1445 * IOCTL.
1446 */
1447 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1448 struct drm_file *filp);
1449 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1450 struct drm_file *filp);
1451 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1452 struct drm_file *file_priv);
1453 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1454 struct drm_file *file_priv);
1455 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1456 struct drm_file *file_priv);
1457 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1458 struct drm_file *file_priv);
1459 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1460 struct drm_file *filp);
1461 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1462 struct drm_file *filp);
1463 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1464 struct drm_file *filp);
1465 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1466 struct drm_file *filp);
1467 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1468 struct drm_file *filp);
1469 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1470 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1471 struct drm_file *filp);
1472 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1473 struct drm_file *filp);
1474
1475 /* VRAM scratch page for HDP bug, default vram page */
1476 struct r600_vram_scratch {
1477 struct radeon_bo *robj;
1478 volatile uint32_t *ptr;
1479 u64 gpu_addr;
1480 };
1481
1482 /*
1483 * ACPI
1484 */
1485 struct radeon_atif_notification_cfg {
1486 bool enabled;
1487 int command_code;
1488 };
1489
1490 struct radeon_atif_notifications {
1491 bool display_switch;
1492 bool expansion_mode_change;
1493 bool thermal_state;
1494 bool forced_power_state;
1495 bool system_power_state;
1496 bool display_conf_change;
1497 bool px_gfx_switch;
1498 bool brightness_change;
1499 bool dgpu_display_event;
1500 };
1501
1502 struct radeon_atif_functions {
1503 bool system_params;
1504 bool sbios_requests;
1505 bool select_active_disp;
1506 bool lid_state;
1507 bool get_tv_standard;
1508 bool set_tv_standard;
1509 bool get_panel_expansion_mode;
1510 bool set_panel_expansion_mode;
1511 bool temperature_change;
1512 bool graphics_device_types;
1513 };
1514
1515 struct radeon_atif {
1516 struct radeon_atif_notifications notifications;
1517 struct radeon_atif_functions functions;
1518 struct radeon_atif_notification_cfg notification_cfg;
1519 struct radeon_encoder *encoder_for_bl;
1520 };
1521
1522 struct radeon_atcs_functions {
1523 bool get_ext_state;
1524 bool pcie_perf_req;
1525 bool pcie_dev_rdy;
1526 bool pcie_bus_width;
1527 };
1528
1529 struct radeon_atcs {
1530 struct radeon_atcs_functions functions;
1531 };
1532
1533 /*
1534 * Core structure, functions and helpers.
1535 */
1536 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1537 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1538
1539 struct radeon_device {
1540 struct device *dev;
1541 struct drm_device *ddev;
1542 struct pci_dev *pdev;
1543 struct rw_semaphore exclusive_lock;
1544 /* ASIC */
1545 union radeon_asic_config config;
1546 enum radeon_family family;
1547 unsigned long flags;
1548 int usec_timeout;
1549 enum radeon_pll_errata pll_errata;
1550 int num_gb_pipes;
1551 int num_z_pipes;
1552 int disp_priority;
1553 /* BIOS */
1554 uint8_t *bios;
1555 bool is_atom_bios;
1556 uint16_t bios_header_start;
1557 struct radeon_bo *stollen_vga_memory;
1558 /* Register mmio */
1559 resource_size_t rmmio_base;
1560 resource_size_t rmmio_size;
1561 /* protects concurrent MM_INDEX/DATA based register access */
1562 spinlock_t mmio_idx_lock;
1563 void __iomem *rmmio;
1564 radeon_rreg_t mc_rreg;
1565 radeon_wreg_t mc_wreg;
1566 radeon_rreg_t pll_rreg;
1567 radeon_wreg_t pll_wreg;
1568 uint32_t pcie_reg_mask;
1569 radeon_rreg_t pciep_rreg;
1570 radeon_wreg_t pciep_wreg;
1571 /* io port */
1572 void __iomem *rio_mem;
1573 resource_size_t rio_mem_size;
1574 struct radeon_clock clock;
1575 struct radeon_mc mc;
1576 struct radeon_gart gart;
1577 struct radeon_mode_info mode_info;
1578 struct radeon_scratch scratch;
1579 struct radeon_mman mman;
1580 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1581 wait_queue_head_t fence_queue;
1582 struct mutex ring_lock;
1583 struct radeon_ring ring[RADEON_NUM_RINGS];
1584 bool ib_pool_ready;
1585 struct radeon_sa_manager ring_tmp_bo;
1586 struct radeon_irq irq;
1587 struct radeon_asic *asic;
1588 struct radeon_gem gem;
1589 struct radeon_pm pm;
1590 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1591 struct radeon_wb wb;
1592 struct radeon_dummy_page dummy_page;
1593 bool shutdown;
1594 bool suspend;
1595 bool need_dma32;
1596 bool accel_working;
1597 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1598 const struct firmware *me_fw; /* all family ME firmware */
1599 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1600 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1601 const struct firmware *mc_fw; /* NI MC firmware */
1602 const struct firmware *ce_fw; /* SI CE firmware */
1603 struct r600_blit r600_blit;
1604 struct r600_vram_scratch vram_scratch;
1605 int msi_enabled; /* msi enabled */
1606 struct r600_ih ih; /* r6/700 interrupt ring */
1607 struct si_rlc rlc;
1608 struct work_struct hotplug_work;
1609 struct work_struct audio_work;
1610 int num_crtc; /* number of crtcs */
1611 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1612 bool audio_enabled;
1613 struct r600_audio audio_status; /* audio stuff */
1614 struct notifier_block acpi_nb;
1615 /* only one userspace can use Hyperz features or CMASK at a time */
1616 struct drm_file *hyperz_filp;
1617 struct drm_file *cmask_filp;
1618 /* i2c buses */
1619 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1620 /* debugfs */
1621 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1622 unsigned debugfs_count;
1623 /* virtual memory */
1624 struct radeon_vm_manager vm_manager;
1625 struct mutex gpu_clock_mutex;
1626 /* ACPI interface */
1627 struct radeon_atif atif;
1628 struct radeon_atcs atcs;
1629 };
1630
1631 int radeon_device_init(struct radeon_device *rdev,
1632 struct drm_device *ddev,
1633 struct pci_dev *pdev,
1634 uint32_t flags);
1635 void radeon_device_fini(struct radeon_device *rdev);
1636 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1637
1638 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
1639 bool always_indirect);
1640 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
1641 bool always_indirect);
1642 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1643 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1644
1645 /*
1646 * Cast helper
1647 */
1648 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1649
1650 /*
1651 * Registers read & write functions.
1652 */
1653 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1654 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1655 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1656 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1657 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
1658 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
1659 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
1660 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
1661 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1662 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1663 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1664 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1665 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1666 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1667 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1668 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1669 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1670 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1671 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1672 #define WREG32_P(reg, val, mask) \
1673 do { \
1674 uint32_t tmp_ = RREG32(reg); \
1675 tmp_ &= (mask); \
1676 tmp_ |= ((val) & ~(mask)); \
1677 WREG32(reg, tmp_); \
1678 } while (0)
1679 #define WREG32_PLL_P(reg, val, mask) \
1680 do { \
1681 uint32_t tmp_ = RREG32_PLL(reg); \
1682 tmp_ &= (mask); \
1683 tmp_ |= ((val) & ~(mask)); \
1684 WREG32_PLL(reg, tmp_); \
1685 } while (0)
1686 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1687 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1688 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1689
1690 /*
1691 * Indirect registers accessor
1692 */
1693 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1694 {
1695 uint32_t r;
1696
1697 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1698 r = RREG32(RADEON_PCIE_DATA);
1699 return r;
1700 }
1701
1702 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1703 {
1704 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1705 WREG32(RADEON_PCIE_DATA, (v));
1706 }
1707
1708 void r100_pll_errata_after_index(struct radeon_device *rdev);
1709
1710
1711 /*
1712 * ASICs helpers.
1713 */
1714 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1715 (rdev->pdev->device == 0x5969))
1716 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1717 (rdev->family == CHIP_RV200) || \
1718 (rdev->family == CHIP_RS100) || \
1719 (rdev->family == CHIP_RS200) || \
1720 (rdev->family == CHIP_RV250) || \
1721 (rdev->family == CHIP_RV280) || \
1722 (rdev->family == CHIP_RS300))
1723 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1724 (rdev->family == CHIP_RV350) || \
1725 (rdev->family == CHIP_R350) || \
1726 (rdev->family == CHIP_RV380) || \
1727 (rdev->family == CHIP_R420) || \
1728 (rdev->family == CHIP_R423) || \
1729 (rdev->family == CHIP_RV410) || \
1730 (rdev->family == CHIP_RS400) || \
1731 (rdev->family == CHIP_RS480))
1732 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1733 (rdev->ddev->pdev->device == 0x9443) || \
1734 (rdev->ddev->pdev->device == 0x944B) || \
1735 (rdev->ddev->pdev->device == 0x9506) || \
1736 (rdev->ddev->pdev->device == 0x9509) || \
1737 (rdev->ddev->pdev->device == 0x950F) || \
1738 (rdev->ddev->pdev->device == 0x689C) || \
1739 (rdev->ddev->pdev->device == 0x689D))
1740 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1741 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1742 (rdev->family == CHIP_RS690) || \
1743 (rdev->family == CHIP_RS740) || \
1744 (rdev->family >= CHIP_R600))
1745 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1746 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1747 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1748 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1749 (rdev->flags & RADEON_IS_IGP))
1750 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1751 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1752 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1753 (rdev->flags & RADEON_IS_IGP))
1754
1755 /*
1756 * BIOS helpers.
1757 */
1758 #define RBIOS8(i) (rdev->bios[i])
1759 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1760 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1761
1762 int radeon_combios_init(struct radeon_device *rdev);
1763 void radeon_combios_fini(struct radeon_device *rdev);
1764 int radeon_atombios_init(struct radeon_device *rdev);
1765 void radeon_atombios_fini(struct radeon_device *rdev);
1766
1767
1768 /*
1769 * RING helpers.
1770 */
1771 #if DRM_DEBUG_CODE == 0
1772 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1773 {
1774 ring->ring[ring->wptr++] = v;
1775 ring->wptr &= ring->ptr_mask;
1776 ring->count_dw--;
1777 ring->ring_free_dw--;
1778 }
1779 #else
1780 /* With debugging this is just too big to inline */
1781 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1782 #endif
1783
1784 /*
1785 * ASICs macro.
1786 */
1787 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1788 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1789 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1790 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1791 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1792 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1793 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1794 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1795 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1796 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
1797 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
1798 #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags)))
1799 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1800 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1801 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1802 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1803 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1804 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1805 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
1806 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1807 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1808 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1809 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1810 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
1811 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1812 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1813 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1814 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1815 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1816 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1817 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1818 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1819 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1820 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1821 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1822 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1823 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1824 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1825 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1826 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1827 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1828 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1829 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1830 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1831 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1832 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1833 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1834 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1835 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1836 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1837 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1838 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1839 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1840 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1841 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1842 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1843 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1844
1845 /* Common functions */
1846 /* AGP */
1847 extern int radeon_gpu_reset(struct radeon_device *rdev);
1848 extern void radeon_agp_disable(struct radeon_device *rdev);
1849 extern int radeon_modeset_init(struct radeon_device *rdev);
1850 extern void radeon_modeset_fini(struct radeon_device *rdev);
1851 extern bool radeon_card_posted(struct radeon_device *rdev);
1852 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1853 extern void radeon_update_display_priority(struct radeon_device *rdev);
1854 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1855 extern void radeon_scratch_init(struct radeon_device *rdev);
1856 extern void radeon_wb_fini(struct radeon_device *rdev);
1857 extern int radeon_wb_init(struct radeon_device *rdev);
1858 extern void radeon_wb_disable(struct radeon_device *rdev);
1859 extern void radeon_surface_init(struct radeon_device *rdev);
1860 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1861 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1862 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1863 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1864 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1865 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1866 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1867 extern int radeon_resume_kms(struct drm_device *dev);
1868 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1869 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1870
1871 /*
1872 * vm
1873 */
1874 int radeon_vm_manager_init(struct radeon_device *rdev);
1875 void radeon_vm_manager_fini(struct radeon_device *rdev);
1876 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1877 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1878 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
1879 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
1880 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
1881 struct radeon_vm *vm, int ring);
1882 void radeon_vm_fence(struct radeon_device *rdev,
1883 struct radeon_vm *vm,
1884 struct radeon_fence *fence);
1885 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
1886 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1887 struct radeon_vm *vm,
1888 struct radeon_bo *bo,
1889 struct ttm_mem_reg *mem);
1890 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1891 struct radeon_bo *bo);
1892 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
1893 struct radeon_bo *bo);
1894 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
1895 struct radeon_vm *vm,
1896 struct radeon_bo *bo);
1897 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
1898 struct radeon_bo_va *bo_va,
1899 uint64_t offset,
1900 uint32_t flags);
1901 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1902 struct radeon_bo_va *bo_va);
1903
1904 /* audio */
1905 void r600_audio_update_hdmi(struct work_struct *work);
1906
1907 /*
1908 * R600 vram scratch functions
1909 */
1910 int r600_vram_scratch_init(struct radeon_device *rdev);
1911 void r600_vram_scratch_fini(struct radeon_device *rdev);
1912
1913 /*
1914 * r600 cs checking helper
1915 */
1916 unsigned r600_mip_minify(unsigned size, unsigned level);
1917 bool r600_fmt_is_valid_color(u32 format);
1918 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1919 int r600_fmt_get_blocksize(u32 format);
1920 int r600_fmt_get_nblocksx(u32 format, u32 w);
1921 int r600_fmt_get_nblocksy(u32 format, u32 h);
1922
1923 /*
1924 * r600 functions used by radeon_encoder.c
1925 */
1926 struct radeon_hdmi_acr {
1927 u32 clock;
1928
1929 int n_32khz;
1930 int cts_32khz;
1931
1932 int n_44_1khz;
1933 int cts_44_1khz;
1934
1935 int n_48khz;
1936 int cts_48khz;
1937
1938 };
1939
1940 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1941
1942 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1943 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1944 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1945 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1946 u32 tiling_pipe_num,
1947 u32 max_rb_num,
1948 u32 total_max_rb_num,
1949 u32 enabled_rb_mask);
1950
1951 /*
1952 * evergreen functions used by radeon_encoder.c
1953 */
1954
1955 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1956
1957 extern int ni_init_microcode(struct radeon_device *rdev);
1958 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1959
1960 /* radeon_acpi.c */
1961 #if defined(CONFIG_ACPI)
1962 extern int radeon_acpi_init(struct radeon_device *rdev);
1963 extern void radeon_acpi_fini(struct radeon_device *rdev);
1964 #else
1965 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1966 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1967 #endif
1968
1969 #include "radeon_object.h"
1970
1971 #endif
kernel source for telekom puls (alcatel/mediatek)