drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <linux/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72 #include <ttm/ttm_execbuf_util.h>
  73
  74 #include "radeon_family.h"
  75 #include "radeon_mode.h"
  76 #include "radeon_reg.h"
  77
  78 /*
  79  * Modules parameters.
  80  */
  81 extern int radeon_no_wb;
  82 extern int radeon_modeset;
  83 extern int radeon_dynclks;
  84 extern int radeon_r4xx_atom;
  85 extern int radeon_agpmode;
  86 extern int radeon_vram_limit;
  87 extern int radeon_gart_size;
  88 extern int radeon_benchmarking;
  89 extern int radeon_testing;
  90 extern int radeon_connector_table;
  91 extern int radeon_tv;
  92 extern int radeon_audio;
  93 extern int radeon_disp_priority;
  94 extern int radeon_hw_i2c;
  95 extern int radeon_pcie_gen2;
  96 extern int radeon_msi;
  97 extern int radeon_lockup_timeout;
  98
  99 /*
 100  * Copy from radeon_drv.h so we don't have to include both and have conflicting
 101  * symbol;
 102  */
 103 #define RADEON_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
 104 #define RADEON_FENCE_JIFFIES_TIMEOUT            (HZ / 2)
 105 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 106 #define RADEON_IB_POOL_SIZE                     16
 107 #define RADEON_DEBUGFS_MAX_COMPONENTS           32
 108 #define RADEONFB_CONN_LIMIT                     4
 109 #define RADEON_BIOS_NUM_SCRATCH                 8
 110
 111 /* max number of rings */
 112 #define RADEON_NUM_RINGS                        3
 113
 114 /* fence seq are set to this number when signaled */
 115 #define RADEON_FENCE_SIGNALED_SEQ               0LL
 116 #define RADEON_FENCE_NOTEMITED_SEQ              (~0LL)
 117
 118 /* internal ring indices */
 119 /* r1xx+ has gfx CP ring */
 120 #define RADEON_RING_TYPE_GFX_INDEX              0
 121
 122 /* cayman has 2 compute CP rings */
 123 #define CAYMAN_RING_TYPE_CP1_INDEX              1
 124 #define CAYMAN_RING_TYPE_CP2_INDEX              2
 125
 126 /* hardcode those limit for now */
 127 #define RADEON_VA_RESERVED_SIZE                 (8 << 20)
 128 #define RADEON_IB_VM_MAX_SIZE                   (64 << 10)
 129
 130 /*
 131  * Errata workarounds.
 132  */
 133 enum radeon_pll_errata {
 134         CHIP_ERRATA_R300_CG             = 0x00000001,
 135         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 136         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 137 };
 138
 139
 140 struct radeon_device;
 141
 142
 143 /*
 144  * BIOS.
 145  */
 146 #define ATRM_BIOS_PAGE 4096
 147
 148 #if defined(CONFIG_VGA_SWITCHEROO)
 149 bool radeon_atrm_supported(struct pci_dev *pdev);
 150 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
 151 #else
 152 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
 153 {
 154         return false;
 155 }
 156
 157 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
 158         return -EINVAL;
 159 }
 160 #endif
 161 bool radeon_get_bios(struct radeon_device *rdev);
 162
 163
 164 /*
 165  * Mutex which allows recursive locking from the same process.
 166  */
 167 struct radeon_mutex {
 168         struct mutex            mutex;
 169         struct task_struct      *owner;
 170         int                     level;
 171 };
 172
 173 static inline void radeon_mutex_init(struct radeon_mutex *mutex)
 174 {
 175         mutex_init(&mutex->mutex);
 176         mutex->owner = NULL;
 177         mutex->level = 0;
 178 }
 179
 180 static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
 181 {
 182         if (mutex_trylock(&mutex->mutex)) {
 183                 /* The mutex was unlocked before, so it's ours now */
 184                 mutex->owner = current;
 185         } else if (mutex->owner != current) {
 186                 /* Another process locked the mutex, take it */
 187                 mutex_lock(&mutex->mutex);
 188                 mutex->owner = current;
 189         }
 190         /* Otherwise the mutex was already locked by this process */
 191
 192         mutex->level++;
 193 }
 194
 195 static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
 196 {
 197         if (--mutex->level > 0)
 198                 return;
 199
 200         mutex->owner = NULL;
 201         mutex_unlock(&mutex->mutex);
 202 }
 203
 204
 205 /*
 206  * Dummy page
 207  */
 208 struct radeon_dummy_page {
 209         struct page     *page;
 210         dma_addr_t      addr;
 211 };
 212 int radeon_dummy_page_init(struct radeon_device *rdev);
 213 void radeon_dummy_page_fini(struct radeon_device *rdev);
 214
 215
 216 /*
 217  * Clocks
 218  */
 219 struct radeon_clock {
 220         struct radeon_pll p1pll;
 221         struct radeon_pll p2pll;
 222         struct radeon_pll dcpll;
 223         struct radeon_pll spll;
 224         struct radeon_pll mpll;
 225         /* 10 Khz units */
 226         uint32_t default_mclk;
 227         uint32_t default_sclk;
 228         uint32_t default_dispclk;
 229         uint32_t dp_extclk;
 230         uint32_t max_pixel_clock;
 231 };
 232
 233 /*
 234  * Power management
 235  */
 236 int radeon_pm_init(struct radeon_device *rdev);
 237 void radeon_pm_fini(struct radeon_device *rdev);
 238 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 239 void radeon_pm_suspend(struct radeon_device *rdev);
 240 void radeon_pm_resume(struct radeon_device *rdev);
 241 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 242 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 243 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 244 void rs690_pm_info(struct radeon_device *rdev);
 245 extern int rv6xx_get_temp(struct radeon_device *rdev);
 246 extern int rv770_get_temp(struct radeon_device *rdev);
 247 extern int evergreen_get_temp(struct radeon_device *rdev);
 248 extern int sumo_get_temp(struct radeon_device *rdev);
 249 extern int si_get_temp(struct radeon_device *rdev);
 250 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
 251                                     unsigned *bankh, unsigned *mtaspect,
 252                                     unsigned *tile_split);
 253
 254 /*
 255  * Fences.
 256  */
 257 struct radeon_fence_driver {
 258         uint32_t                        scratch_reg;
 259         uint64_t                        gpu_addr;
 260         volatile uint32_t               *cpu_addr;
 261         /* seq is protected by ring emission lock */
 262         uint64_t                        seq;
 263         atomic64_t                      last_seq;
 264         unsigned long                   last_activity;
 265         bool                            initialized;
 266 };
 267
 268 struct radeon_fence {
 269         struct radeon_device            *rdev;
 270         struct kref                     kref;
 271         /* protected by radeon_fence.lock */
 272         uint64_t                        seq;
 273         /* RB, DMA, etc. */
 274         unsigned                        ring;
 275 };
 276
 277 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
 278 int radeon_fence_driver_init(struct radeon_device *rdev);
 279 void radeon_fence_driver_fini(struct radeon_device *rdev);
 280 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
 281 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 282 void radeon_fence_process(struct radeon_device *rdev, int ring);
 283 bool radeon_fence_signaled(struct radeon_fence *fence);
 284 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 285 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
 286 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
 287 int radeon_fence_wait_any(struct radeon_device *rdev,
 288                           struct radeon_fence **fences,
 289                           bool intr);
 290 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 291 void radeon_fence_unref(struct radeon_fence **fence);
 292 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
 293
 294 /*
 295  * Tiling registers
 296  */
 297 struct radeon_surface_reg {
 298         struct radeon_bo *bo;
 299 };
 300
 301 #define RADEON_GEM_MAX_SURFACES 8
 302
 303 /*
 304  * TTM.
 305  */
 306 struct radeon_mman {
 307         struct ttm_bo_global_ref        bo_global_ref;
 308         struct drm_global_reference     mem_global_ref;
 309         struct ttm_bo_device            bdev;
 310         bool                            mem_global_referenced;
 311         bool                            initialized;
 312 };
 313
 314 /* bo virtual address in a specific vm */
 315 struct radeon_bo_va {
 316         /* bo list is protected by bo being reserved */
 317         struct list_head                bo_list;
 318         /* vm list is protected by vm mutex */
 319         struct list_head                vm_list;
 320         /* constant after initialization */
 321         struct radeon_vm                *vm;
 322         struct radeon_bo                *bo;
 323         uint64_t                        soffset;
 324         uint64_t                        eoffset;
 325         uint32_t                        flags;
 326         bool                            valid;
 327 };
 328
 329 struct radeon_bo {
 330         /* Protected by gem.mutex */
 331         struct list_head                list;
 332         /* Protected by tbo.reserved */
 333         u32                             placements[3];
 334         struct ttm_placement            placement;
 335         struct ttm_buffer_object        tbo;
 336         struct ttm_bo_kmap_obj          kmap;
 337         unsigned                        pin_count;
 338         void                            *kptr;
 339         u32                             tiling_flags;
 340         u32                             pitch;
 341         int                             surface_reg;
 342         /* list of all virtual address to which this bo
 343          * is associated to
 344          */
 345         struct list_head                va;
 346         /* Constant after initialization */
 347         struct radeon_device            *rdev;
 348         struct drm_gem_object           gem_base;
 349 };
 350 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 351
 352 struct radeon_bo_list {
 353         struct ttm_validate_buffer tv;
 354         struct radeon_bo        *bo;
 355         uint64_t                gpu_offset;
 356         unsigned                rdomain;
 357         unsigned                wdomain;
 358         u32                     tiling_flags;
 359 };
 360
 361 /* sub-allocation manager, it has to be protected by another lock.
 362  * By conception this is an helper for other part of the driver
 363  * like the indirect buffer or semaphore, which both have their
 364  * locking.
 365  *
 366  * Principe is simple, we keep a list of sub allocation in offset
 367  * order (first entry has offset == 0, last entry has the highest
 368  * offset).
 369  *
 370  * When allocating new object we first check if there is room at
 371  * the end total_size - (last_object_offset + last_object_size) >=
 372  * alloc_size. If so we allocate new object there.
 373  *
 374  * When there is not enough room at the end, we start waiting for
 375  * each sub object until we reach object_offset+object_size >=
 376  * alloc_size, this object then become the sub object we return.
 377  *
 378  * Alignment can't be bigger than page size.
 379  *
 380  * Hole are not considered for allocation to keep things simple.
 381  * Assumption is that there won't be hole (all object on same
 382  * alignment).
 383  */
 384 struct radeon_sa_manager {
 385         spinlock_t              lock;
 386         struct radeon_bo        *bo;
 387         struct list_head        *hole;
 388         struct list_head        flist[RADEON_NUM_RINGS];
 389         struct list_head        olist;
 390         unsigned                size;
 391         uint64_t                gpu_addr;
 392         void                    *cpu_ptr;
 393         uint32_t                domain;
 394 };
 395
 396 struct radeon_sa_bo;
 397
 398 /* sub-allocation buffer */
 399 struct radeon_sa_bo {
 400         struct list_head                olist;
 401         struct list_head                flist;
 402         struct radeon_sa_manager        *manager;
 403         unsigned                        soffset;
 404         unsigned                        eoffset;
 405         struct radeon_fence             *fence;
 406 };
 407
 408 /*
 409  * GEM objects.
 410  */
 411 struct radeon_gem {
 412         struct mutex            mutex;
 413         struct list_head        objects;
 414 };
 415
 416 int radeon_gem_init(struct radeon_device *rdev);
 417 void radeon_gem_fini(struct radeon_device *rdev);
 418 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 419                                 int alignment, int initial_domain,
 420                                 bool discardable, bool kernel,
 421                                 struct drm_gem_object **obj);
 422
 423 int radeon_mode_dumb_create(struct drm_file *file_priv,
 424                             struct drm_device *dev,
 425                             struct drm_mode_create_dumb *args);
 426 int radeon_mode_dumb_mmap(struct drm_file *filp,
 427                           struct drm_device *dev,
 428                           uint32_t handle, uint64_t *offset_p);
 429 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
 430                              struct drm_device *dev,
 431                              uint32_t handle);
 432
 433 /*
 434  * Semaphores.
 435  */
 436 /* everything here is constant */
 437 struct radeon_semaphore {
 438         struct radeon_sa_bo             *sa_bo;
 439         signed                          waiters;
 440         uint64_t                        gpu_addr;
 441 };
 442
 443 int radeon_semaphore_create(struct radeon_device *rdev,
 444                             struct radeon_semaphore **semaphore);
 445 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
 446                                   struct radeon_semaphore *semaphore);
 447 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
 448                                 struct radeon_semaphore *semaphore);
 449 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
 450                                 struct radeon_semaphore *semaphore,
 451                                 bool sync_to[RADEON_NUM_RINGS],
 452                                 int dst_ring);
 453 void radeon_semaphore_free(struct radeon_device *rdev,
 454                            struct radeon_semaphore *semaphore,
 455                            struct radeon_fence *fence);
 456
 457 /*
 458  * GART structures, functions & helpers
 459  */
 460 struct radeon_mc;
 461
 462 #define RADEON_GPU_PAGE_SIZE 4096
 463 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 464 #define RADEON_GPU_PAGE_SHIFT 12
 465 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
 466
 467 struct radeon_gart {
 468         dma_addr_t                      table_addr;
 469         struct radeon_bo                *robj;
 470         void                            *ptr;
 471         unsigned                        num_gpu_pages;
 472         unsigned                        num_cpu_pages;
 473         unsigned                        table_size;
 474         struct page                     **pages;
 475         dma_addr_t                      *pages_addr;
 476         bool                            ready;
 477 };
 478
 479 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 480 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 481 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 482 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 483 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 484 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
 485 int radeon_gart_init(struct radeon_device *rdev);
 486 void radeon_gart_fini(struct radeon_device *rdev);
 487 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 488                         int pages);
 489 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 490                      int pages, struct page **pagelist,
 491                      dma_addr_t *dma_addr);
 492 void radeon_gart_restore(struct radeon_device *rdev);
 493
 494
 495 /*
 496  * GPU MC structures, functions & helpers
 497  */
 498 struct radeon_mc {
 499         resource_size_t         aper_size;
 500         resource_size_t         aper_base;
 501         resource_size_t         agp_base;
 502         /* for some chips with <= 32MB we need to lie
 503          * about vram size near mc fb location */
 504         u64                     mc_vram_size;
 505         u64                     visible_vram_size;
 506         u64                     gtt_size;
 507         u64                     gtt_start;
 508         u64                     gtt_end;
 509         u64                     vram_start;
 510         u64                     vram_end;
 511         unsigned                vram_width;
 512         u64                     real_vram_size;
 513         int                     vram_mtrr;
 514         bool                    vram_is_ddr;
 515         bool                    igp_sideport_enabled;
 516         u64                     gtt_base_align;
 517 };
 518
 519 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 520 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 521
 522 /*
 523  * GPU scratch registers structures, functions & helpers
 524  */
 525 struct radeon_scratch {
 526         unsigned                num_reg;
 527         uint32_t                reg_base;
 528         bool                    free[32];
 529         uint32_t                reg[32];
 530 };
 531
 532 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 533 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 534
 535
 536 /*
 537  * IRQS.
 538  */
 539
 540 struct radeon_unpin_work {
 541         struct work_struct work;
 542         struct radeon_device *rdev;
 543         int crtc_id;
 544         struct radeon_fence *fence;
 545         struct drm_pending_vblank_event *event;
 546         struct radeon_bo *old_rbo;
 547         u64 new_crtc_base;
 548 };
 549
 550 struct r500_irq_stat_regs {
 551         u32 disp_int;
 552         u32 hdmi0_status;
 553 };
 554
 555 struct r600_irq_stat_regs {
 556         u32 disp_int;
 557         u32 disp_int_cont;
 558         u32 disp_int_cont2;
 559         u32 d1grph_int;
 560         u32 d2grph_int;
 561         u32 hdmi0_status;
 562         u32 hdmi1_status;
 563 };
 564
 565 struct evergreen_irq_stat_regs {
 566         u32 disp_int;
 567         u32 disp_int_cont;
 568         u32 disp_int_cont2;
 569         u32 disp_int_cont3;
 570         u32 disp_int_cont4;
 571         u32 disp_int_cont5;
 572         u32 d1grph_int;
 573         u32 d2grph_int;
 574         u32 d3grph_int;
 575         u32 d4grph_int;
 576         u32 d5grph_int;
 577         u32 d6grph_int;
 578         u32 afmt_status1;
 579         u32 afmt_status2;
 580         u32 afmt_status3;
 581         u32 afmt_status4;
 582         u32 afmt_status5;
 583         u32 afmt_status6;
 584 };
 585
 586 union radeon_irq_stat_regs {
 587         struct r500_irq_stat_regs r500;
 588         struct r600_irq_stat_regs r600;
 589         struct evergreen_irq_stat_regs evergreen;
 590 };
 591
 592 #define RADEON_MAX_HPD_PINS 6
 593 #define RADEON_MAX_CRTCS 6
 594 #define RADEON_MAX_AFMT_BLOCKS 6
 595
 596 struct radeon_irq {
 597         bool            installed;
 598         bool            sw_int[RADEON_NUM_RINGS];
 599         bool            crtc_vblank_int[RADEON_MAX_CRTCS];
 600         bool            pflip[RADEON_MAX_CRTCS];
 601         wait_queue_head_t       vblank_queue;
 602         bool            hpd[RADEON_MAX_HPD_PINS];
 603         bool            gui_idle;
 604         bool            gui_idle_acked;
 605         wait_queue_head_t       idle_queue;
 606         bool            afmt[RADEON_MAX_AFMT_BLOCKS];
 607         spinlock_t sw_lock;
 608         int sw_refcount[RADEON_NUM_RINGS];
 609         union radeon_irq_stat_regs stat_regs;
 610         spinlock_t pflip_lock[RADEON_MAX_CRTCS];
 611         int pflip_refcount[RADEON_MAX_CRTCS];
 612 };
 613
 614 int radeon_irq_kms_init(struct radeon_device *rdev);
 615 void radeon_irq_kms_fini(struct radeon_device *rdev);
 616 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
 617 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
 618 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 619 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 620
 621 /*
 622  * CP & rings.
 623  */
 624
 625 struct radeon_ib {
 626         struct radeon_sa_bo             *sa_bo;
 627         uint32_t                        length_dw;
 628         uint64_t                        gpu_addr;
 629         uint32_t                        *ptr;
 630         struct radeon_fence             *fence;
 631         unsigned                        vm_id;
 632         bool                            is_const_ib;
 633         struct radeon_semaphore         *semaphore;
 634 };
 635
 636 struct radeon_ring {
 637         struct radeon_bo        *ring_obj;
 638         volatile uint32_t       *ring;
 639         unsigned                rptr;
 640         unsigned                rptr_offs;
 641         unsigned                rptr_reg;
 642         unsigned                wptr;
 643         unsigned                wptr_old;
 644         unsigned                wptr_reg;
 645         unsigned                ring_size;
 646         unsigned                ring_free_dw;
 647         int                     count_dw;
 648         unsigned long           last_activity;
 649         unsigned                last_rptr;
 650         uint64_t                gpu_addr;
 651         uint32_t                align_mask;
 652         uint32_t                ptr_mask;
 653         bool                    ready;
 654         u32                     ptr_reg_shift;
 655         u32                     ptr_reg_mask;
 656         u32                     nop;
 657 };
 658
 659 /*
 660  * VM
 661  */
 662 struct radeon_vm {
 663         struct list_head                list;
 664         struct list_head                va;
 665         int                             id;
 666         unsigned                        last_pfn;
 667         u64                             pt_gpu_addr;
 668         u64                             *pt;
 669         struct radeon_sa_bo             *sa_bo;
 670         struct mutex                    mutex;
 671         /* last fence for cs using this vm */
 672         struct radeon_fence             *fence;
 673 };
 674
 675 struct radeon_vm_funcs {
 676         int (*init)(struct radeon_device *rdev);
 677         void (*fini)(struct radeon_device *rdev);
 678         /* cs mutex must be lock for schedule_ib */
 679         int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
 680         void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
 681         void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
 682         uint32_t (*page_flags)(struct radeon_device *rdev,
 683                                struct radeon_vm *vm,
 684                                uint32_t flags);
 685         void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
 686                         unsigned pfn, uint64_t addr, uint32_t flags);
 687 };
 688
 689 struct radeon_vm_manager {
 690         struct list_head                lru_vm;
 691         uint32_t                        use_bitmap;
 692         struct radeon_sa_manager        sa_manager;
 693         uint32_t                        max_pfn;
 694         /* fields constant after init */
 695         const struct radeon_vm_funcs    *funcs;
 696         /* number of VMIDs */
 697         unsigned                        nvm;
 698         /* vram base address for page table entry  */
 699         u64                             vram_base_offset;
 700         /* is vm enabled? */
 701         bool                            enabled;
 702 };
 703
 704 /*
 705  * file private structure
 706  */
 707 struct radeon_fpriv {
 708         struct radeon_vm                vm;
 709 };
 710
 711 /*
 712  * R6xx+ IH ring
 713  */
 714 struct r600_ih {
 715         struct radeon_bo        *ring_obj;
 716         volatile uint32_t       *ring;
 717         unsigned                rptr;
 718         unsigned                rptr_offs;
 719         unsigned                wptr;
 720         unsigned                wptr_old;
 721         unsigned                ring_size;
 722         uint64_t                gpu_addr;
 723         uint32_t                ptr_mask;
 724         spinlock_t              lock;
 725         bool                    enabled;
 726 };
 727
 728 struct r600_blit_cp_primitives {
 729         void (*set_render_target)(struct radeon_device *rdev, int format,
 730                                   int w, int h, u64 gpu_addr);
 731         void (*cp_set_surface_sync)(struct radeon_device *rdev,
 732                                     u32 sync_type, u32 size,
 733                                     u64 mc_addr);
 734         void (*set_shaders)(struct radeon_device *rdev);
 735         void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
 736         void (*set_tex_resource)(struct radeon_device *rdev,
 737                                  int format, int w, int h, int pitch,
 738                                  u64 gpu_addr, u32 size);
 739         void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
 740                              int x2, int y2);
 741         void (*draw_auto)(struct radeon_device *rdev);
 742         void (*set_default_state)(struct radeon_device *rdev);
 743 };
 744
 745 struct r600_blit {
 746         struct radeon_bo        *shader_obj;
 747         struct r600_blit_cp_primitives primitives;
 748         int max_dim;
 749         int ring_size_common;
 750         int ring_size_per_loop;
 751         u64 shader_gpu_addr;
 752         u32 vs_offset, ps_offset;
 753         u32 state_offset;
 754         u32 state_len;
 755 };
 756
 757 void r600_blit_suspend(struct radeon_device *rdev);
 758
 759 /*
 760  * SI RLC stuff
 761  */
 762 struct si_rlc {
 763         /* for power gating */
 764         struct radeon_bo        *save_restore_obj;
 765         uint64_t                save_restore_gpu_addr;
 766         /* for clear state */
 767         struct radeon_bo        *clear_state_obj;
 768         uint64_t                clear_state_gpu_addr;
 769 };
 770
 771 int radeon_ib_get(struct radeon_device *rdev, int ring,
 772                   struct radeon_ib **ib, unsigned size);
 773 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 774 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 775 int radeon_ib_pool_init(struct radeon_device *rdev);
 776 void radeon_ib_pool_fini(struct radeon_device *rdev);
 777 int radeon_ib_pool_start(struct radeon_device *rdev);
 778 int radeon_ib_pool_suspend(struct radeon_device *rdev);
 779 int radeon_ib_ring_tests(struct radeon_device *rdev);
 780 /* Ring access between begin & end cannot sleep */
 781 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
 782 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
 783 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 784 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
 785 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 786 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
 787 void radeon_ring_undo(struct radeon_ring *ring);
 788 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
 789 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 790 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
 791 void radeon_ring_lockup_update(struct radeon_ring *ring);
 792 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 793 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
 794                      unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
 795                      u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
 796 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
 797
 798
 799 /*
 800  * CS.
 801  */
 802 struct radeon_cs_reloc {
 803         struct drm_gem_object           *gobj;
 804         struct radeon_bo                *robj;
 805         struct radeon_bo_list           lobj;
 806         uint32_t                        handle;
 807         uint32_t                        flags;
 808 };
 809
 810 struct radeon_cs_chunk {
 811         uint32_t                chunk_id;
 812         uint32_t                length_dw;
 813         int                     kpage_idx[2];
 814         uint32_t                *kpage[2];
 815         uint32_t                *kdata;
 816         void __user             *user_ptr;
 817         int                     last_copied_page;
 818         int                     last_page_index;
 819 };
 820
 821 struct radeon_cs_parser {
 822         struct device           *dev;
 823         struct radeon_device    *rdev;
 824         struct drm_file         *filp;
 825         /* chunks */
 826         unsigned                nchunks;
 827         struct radeon_cs_chunk  *chunks;
 828         uint64_t                *chunks_array;
 829         /* IB */
 830         unsigned                idx;
 831         /* relocations */
 832         unsigned                nrelocs;
 833         struct radeon_cs_reloc  *relocs;
 834         struct radeon_cs_reloc  **relocs_ptr;
 835         struct list_head        validated;
 836         /* indices of various chunks */
 837         int                     chunk_ib_idx;
 838         int                     chunk_relocs_idx;
 839         int                     chunk_flags_idx;
 840         int                     chunk_const_ib_idx;
 841         struct radeon_ib        *ib;
 842         struct radeon_ib        *const_ib;
 843         void                    *track;
 844         unsigned                family;
 845         int                     parser_error;
 846         u32                     cs_flags;
 847         u32                     ring;
 848         s32                     priority;
 849 };
 850
 851 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
 852 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 853 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
 854
 855 struct radeon_cs_packet {
 856         unsigned        idx;
 857         unsigned        type;
 858         unsigned        reg;
 859         unsigned        opcode;
 860         int             count;
 861         unsigned        one_reg_wr;
 862 };
 863
 864 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 865                                       struct radeon_cs_packet *pkt,
 866                                       unsigned idx, unsigned reg);
 867 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 868                                       struct radeon_cs_packet *pkt);
 869
 870
 871 /*
 872  * AGP
 873  */
 874 int radeon_agp_init(struct radeon_device *rdev);
 875 void radeon_agp_resume(struct radeon_device *rdev);
 876 void radeon_agp_suspend(struct radeon_device *rdev);
 877 void radeon_agp_fini(struct radeon_device *rdev);
 878
 879
 880 /*
 881  * Writeback
 882  */
 883 struct radeon_wb {
 884         struct radeon_bo        *wb_obj;
 885         volatile uint32_t       *wb;
 886         uint64_t                gpu_addr;
 887         bool                    enabled;
 888         bool                    use_event;
 889 };
 890
 891 #define RADEON_WB_SCRATCH_OFFSET 0
 892 #define RADEON_WB_CP_RPTR_OFFSET 1024
 893 #define RADEON_WB_CP1_RPTR_OFFSET 1280
 894 #define RADEON_WB_CP2_RPTR_OFFSET 1536
 895 #define R600_WB_IH_WPTR_OFFSET   2048
 896 #define R600_WB_EVENT_OFFSET     3072
 897
 898 /**
 899  * struct radeon_pm - power management datas
 900  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 901  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 902  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 903  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 904  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 905  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 906  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 907  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 908  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 909  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
 910  * @needed_bandwidth:   current bandwidth needs
 911  *
 912  * It keeps track of various data needed to take powermanagement decision.
 913  * Bandwidth need is used to determine minimun clock of the GPU and memory.
 914  * Equation between gpu/memory clock and available bandwidth is hw dependent
 915  * (type of memory, bus size, efficiency, ...)
 916  */
 917
 918 enum radeon_pm_method {
 919         PM_METHOD_PROFILE,
 920         PM_METHOD_DYNPM,
 921 };
 922
 923 enum radeon_dynpm_state {
 924         DYNPM_STATE_DISABLED,
 925         DYNPM_STATE_MINIMUM,
 926         DYNPM_STATE_PAUSED,
 927         DYNPM_STATE_ACTIVE,
 928         DYNPM_STATE_SUSPENDED,
 929 };
 930 enum radeon_dynpm_action {
 931         DYNPM_ACTION_NONE,
 932         DYNPM_ACTION_MINIMUM,
 933         DYNPM_ACTION_DOWNCLOCK,
 934         DYNPM_ACTION_UPCLOCK,
 935         DYNPM_ACTION_DEFAULT
 936 };
 937
 938 enum radeon_voltage_type {
 939         VOLTAGE_NONE = 0,
 940         VOLTAGE_GPIO,
 941         VOLTAGE_VDDC,
 942         VOLTAGE_SW
 943 };
 944
 945 enum radeon_pm_state_type {
 946         POWER_STATE_TYPE_DEFAULT,
 947         POWER_STATE_TYPE_POWERSAVE,
 948         POWER_STATE_TYPE_BATTERY,
 949         POWER_STATE_TYPE_BALANCED,
 950         POWER_STATE_TYPE_PERFORMANCE,
 951 };
 952
 953 enum radeon_pm_profile_type {
 954         PM_PROFILE_DEFAULT,
 955         PM_PROFILE_AUTO,
 956         PM_PROFILE_LOW,
 957         PM_PROFILE_MID,
 958         PM_PROFILE_HIGH,
 959 };
 960
 961 #define PM_PROFILE_DEFAULT_IDX 0
 962 #define PM_PROFILE_LOW_SH_IDX  1
 963 #define PM_PROFILE_MID_SH_IDX  2
 964 #define PM_PROFILE_HIGH_SH_IDX 3
 965 #define PM_PROFILE_LOW_MH_IDX  4
 966 #define PM_PROFILE_MID_MH_IDX  5
 967 #define PM_PROFILE_HIGH_MH_IDX 6
 968 #define PM_PROFILE_MAX         7
 969
 970 struct radeon_pm_profile {
 971         int dpms_off_ps_idx;
 972         int dpms_on_ps_idx;
 973         int dpms_off_cm_idx;
 974         int dpms_on_cm_idx;
 975 };
 976
 977 enum radeon_int_thermal_type {
 978         THERMAL_TYPE_NONE,
 979         THERMAL_TYPE_RV6XX,
 980         THERMAL_TYPE_RV770,
 981         THERMAL_TYPE_EVERGREEN,
 982         THERMAL_TYPE_SUMO,
 983         THERMAL_TYPE_NI,
 984         THERMAL_TYPE_SI,
 985 };
 986
 987 struct radeon_voltage {
 988         enum radeon_voltage_type type;
 989         /* gpio voltage */
 990         struct radeon_gpio_rec gpio;
 991         u32 delay; /* delay in usec from voltage drop to sclk change */
 992         bool active_high; /* voltage drop is active when bit is high */
 993         /* VDDC voltage */
 994         u8 vddc_id; /* index into vddc voltage table */
 995         u8 vddci_id; /* index into vddci voltage table */
 996         bool vddci_enabled;
 997         /* r6xx+ sw */
 998         u16 voltage;
 999         /* evergreen+ vddci */
1000         u16 vddci;
1001 };
1002
1003 /* clock mode flags */
1004 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
1005
1006 struct radeon_pm_clock_info {
1007         /* memory clock */
1008         u32 mclk;
1009         /* engine clock */
1010         u32 sclk;
1011         /* voltage info */
1012         struct radeon_voltage voltage;
1013         /* standardized clock flags */
1014         u32 flags;
1015 };
1016
1017 /* state flags */
1018 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1019
1020 struct radeon_power_state {
1021         enum radeon_pm_state_type type;
1022         struct radeon_pm_clock_info *clock_info;
1023         /* number of valid clock modes in this power state */
1024         int num_clock_modes;
1025         struct radeon_pm_clock_info *default_clock_mode;
1026         /* standardized state flags */
1027         u32 flags;
1028         u32 misc; /* vbios specific flags */
1029         u32 misc2; /* vbios specific flags */
1030         int pcie_lanes; /* pcie lanes */
1031 };
1032
1033 /*
1034  * Some modes are overclocked by very low value, accept them
1035  */
1036 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1037
1038 struct radeon_pm {
1039         struct mutex            mutex;
1040         u32                     active_crtcs;
1041         int                     active_crtc_count;
1042         int                     req_vblank;
1043         bool                    vblank_sync;
1044         bool                    gui_idle;
1045         fixed20_12              max_bandwidth;
1046         fixed20_12              igp_sideport_mclk;
1047         fixed20_12              igp_system_mclk;
1048         fixed20_12              igp_ht_link_clk;
1049         fixed20_12              igp_ht_link_width;
1050         fixed20_12              k8_bandwidth;
1051         fixed20_12              sideport_bandwidth;
1052         fixed20_12              ht_bandwidth;
1053         fixed20_12              core_bandwidth;
1054         fixed20_12              sclk;
1055         fixed20_12              mclk;
1056         fixed20_12              needed_bandwidth;
1057         struct radeon_power_state *power_state;
1058         /* number of valid power states */
1059         int                     num_power_states;
1060         int                     current_power_state_index;
1061         int                     current_clock_mode_index;
1062         int                     requested_power_state_index;
1063         int                     requested_clock_mode_index;
1064         int                     default_power_state_index;
1065         u32                     current_sclk;
1066         u32                     current_mclk;
1067         u16                     current_vddc;
1068         u16                     current_vddci;
1069         u32                     default_sclk;
1070         u32                     default_mclk;
1071         u16                     default_vddc;
1072         u16                     default_vddci;
1073         struct radeon_i2c_chan *i2c_bus;
1074         /* selected pm method */
1075         enum radeon_pm_method     pm_method;
1076         /* dynpm power management */
1077         struct delayed_work     dynpm_idle_work;
1078         enum radeon_dynpm_state dynpm_state;
1079         enum radeon_dynpm_action        dynpm_planned_action;
1080         unsigned long           dynpm_action_timeout;
1081         bool                    dynpm_can_upclock;
1082         bool                    dynpm_can_downclock;
1083         /* profile-based power management */
1084         enum radeon_pm_profile_type profile;
1085         int                     profile_index;
1086         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1087         /* internal thermal controller on rv6xx+ */
1088         enum radeon_int_thermal_type int_thermal_type;
1089         struct device           *int_hwmon_dev;
1090 };
1091
1092 int radeon_pm_get_type_index(struct radeon_device *rdev,
1093                              enum radeon_pm_state_type ps_type,
1094                              int instance);
1095
1096 struct r600_audio {
1097         bool                    enabled;
1098         int                     channels;
1099         int                     rate;
1100         int                     bits_per_sample;
1101         u8                      status_bits;
1102         u8                      category_code;
1103 };
1104
1105 /*
1106  * Benchmarking
1107  */
1108 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1109
1110
1111 /*
1112  * Testing
1113  */
1114 void radeon_test_moves(struct radeon_device *rdev);
1115 void radeon_test_ring_sync(struct radeon_device *rdev,
1116                            struct radeon_ring *cpA,
1117                            struct radeon_ring *cpB);
1118 void radeon_test_syncing(struct radeon_device *rdev);
1119
1120
1121 /*
1122  * Debugfs
1123  */
1124 struct radeon_debugfs {
1125         struct drm_info_list    *files;
1126         unsigned                num_files;
1127 };
1128
1129 int radeon_debugfs_add_files(struct radeon_device *rdev,
1130                              struct drm_info_list *files,
1131                              unsigned nfiles);
1132 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1133
1134
1135 /*
1136  * ASIC specific functions.
1137  */
1138 struct radeon_asic {
1139         int (*init)(struct radeon_device *rdev);
1140         void (*fini)(struct radeon_device *rdev);
1141         int (*resume)(struct radeon_device *rdev);
1142         int (*suspend)(struct radeon_device *rdev);
1143         void (*vga_set_state)(struct radeon_device *rdev, bool state);
1144         int (*asic_reset)(struct radeon_device *rdev);
1145         /* ioctl hw specific callback. Some hw might want to perform special
1146          * operation on specific ioctl. For instance on wait idle some hw
1147          * might want to perform and HDP flush through MMIO as it seems that
1148          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1149          * through ring.
1150          */
1151         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1152         /* check if 3D engine is idle */
1153         bool (*gui_idle)(struct radeon_device *rdev);
1154         /* wait for mc_idle */
1155         int (*mc_wait_for_idle)(struct radeon_device *rdev);
1156         /* gart */
1157         struct {
1158                 void (*tlb_flush)(struct radeon_device *rdev);
1159                 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1160         } gart;
1161         /* ring specific callbacks */
1162         struct {
1163                 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1164                 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1165                 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1166                 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1167                                        struct radeon_semaphore *semaphore, bool emit_wait);
1168                 int (*cs_parse)(struct radeon_cs_parser *p);
1169                 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1170                 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1171                 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1172                 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1173         } ring[RADEON_NUM_RINGS];
1174         /* irqs */
1175         struct {
1176                 int (*set)(struct radeon_device *rdev);
1177                 int (*process)(struct radeon_device *rdev);
1178         } irq;
1179         /* displays */
1180         struct {
1181                 /* display watermarks */
1182                 void (*bandwidth_update)(struct radeon_device *rdev);
1183                 /* get frame count */
1184                 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1185                 /* wait for vblank */
1186                 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1187         } display;
1188         /* copy functions for bo handling */
1189         struct {
1190                 int (*blit)(struct radeon_device *rdev,
1191                             uint64_t src_offset,
1192                             uint64_t dst_offset,
1193                             unsigned num_gpu_pages,
1194                             struct radeon_fence *fence);
1195                 u32 blit_ring_index;
1196                 int (*dma)(struct radeon_device *rdev,
1197                            uint64_t src_offset,
1198                            uint64_t dst_offset,
1199                            unsigned num_gpu_pages,
1200                            struct radeon_fence *fence);
1201                 u32 dma_ring_index;
1202                 /* method used for bo copy */
1203                 int (*copy)(struct radeon_device *rdev,
1204                             uint64_t src_offset,
1205                             uint64_t dst_offset,
1206                             unsigned num_gpu_pages,
1207                             struct radeon_fence *fence);
1208                 /* ring used for bo copies */
1209                 u32 copy_ring_index;
1210         } copy;
1211         /* surfaces */
1212         struct {
1213                 int (*set_reg)(struct radeon_device *rdev, int reg,
1214                                        uint32_t tiling_flags, uint32_t pitch,
1215                                        uint32_t offset, uint32_t obj_size);
1216                 void (*clear_reg)(struct radeon_device *rdev, int reg);
1217         } surface;
1218         /* hotplug detect */
1219         struct {
1220                 void (*init)(struct radeon_device *rdev);
1221                 void (*fini)(struct radeon_device *rdev);
1222                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1223                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1224         } hpd;
1225         /* power management */
1226         struct {
1227                 void (*misc)(struct radeon_device *rdev);
1228                 void (*prepare)(struct radeon_device *rdev);
1229                 void (*finish)(struct radeon_device *rdev);
1230                 void (*init_profile)(struct radeon_device *rdev);
1231                 void (*get_dynpm_state)(struct radeon_device *rdev);
1232                 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1233                 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1234                 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1235                 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1236                 int (*get_pcie_lanes)(struct radeon_device *rdev);
1237                 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1238                 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1239         } pm;
1240         /* pageflipping */
1241         struct {
1242                 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1243                 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1244                 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1245         } pflip;
1246 };
1247
1248 /*
1249  * Asic structures
1250  */
1251 struct r100_asic {
1252         const unsigned          *reg_safe_bm;
1253         unsigned                reg_safe_bm_size;
1254         u32                     hdp_cntl;
1255 };
1256
1257 struct r300_asic {
1258         const unsigned          *reg_safe_bm;
1259         unsigned                reg_safe_bm_size;
1260         u32                     resync_scratch;
1261         u32                     hdp_cntl;
1262 };
1263
1264 struct r600_asic {
1265         unsigned                max_pipes;
1266         unsigned                max_tile_pipes;
1267         unsigned                max_simds;
1268         unsigned                max_backends;
1269         unsigned                max_gprs;
1270         unsigned                max_threads;
1271         unsigned                max_stack_entries;
1272         unsigned                max_hw_contexts;
1273         unsigned                max_gs_threads;
1274         unsigned                sx_max_export_size;
1275         unsigned                sx_max_export_pos_size;
1276         unsigned                sx_max_export_smx_size;
1277         unsigned                sq_num_cf_insts;
1278         unsigned                tiling_nbanks;
1279         unsigned                tiling_npipes;
1280         unsigned                tiling_group_size;
1281         unsigned                tile_config;
1282         unsigned                backend_map;
1283 };
1284
1285 struct rv770_asic {
1286         unsigned                max_pipes;
1287         unsigned                max_tile_pipes;
1288         unsigned                max_simds;
1289         unsigned                max_backends;
1290         unsigned                max_gprs;
1291         unsigned                max_threads;
1292         unsigned                max_stack_entries;
1293         unsigned                max_hw_contexts;
1294         unsigned                max_gs_threads;
1295         unsigned                sx_max_export_size;
1296         unsigned                sx_max_export_pos_size;
1297         unsigned                sx_max_export_smx_size;
1298         unsigned                sq_num_cf_insts;
1299         unsigned                sx_num_of_sets;
1300         unsigned                sc_prim_fifo_size;
1301         unsigned                sc_hiz_tile_fifo_size;
1302         unsigned                sc_earlyz_tile_fifo_fize;
1303         unsigned                tiling_nbanks;
1304         unsigned                tiling_npipes;
1305         unsigned                tiling_group_size;
1306         unsigned                tile_config;
1307         unsigned                backend_map;
1308 };
1309
1310 struct evergreen_asic {
1311         unsigned num_ses;
1312         unsigned max_pipes;
1313         unsigned max_tile_pipes;
1314         unsigned max_simds;
1315         unsigned max_backends;
1316         unsigned max_gprs;
1317         unsigned max_threads;
1318         unsigned max_stack_entries;
1319         unsigned max_hw_contexts;
1320         unsigned max_gs_threads;
1321         unsigned sx_max_export_size;
1322         unsigned sx_max_export_pos_size;
1323         unsigned sx_max_export_smx_size;
1324         unsigned sq_num_cf_insts;
1325         unsigned sx_num_of_sets;
1326         unsigned sc_prim_fifo_size;
1327         unsigned sc_hiz_tile_fifo_size;
1328         unsigned sc_earlyz_tile_fifo_size;
1329         unsigned tiling_nbanks;
1330         unsigned tiling_npipes;
1331         unsigned tiling_group_size;
1332         unsigned tile_config;
1333         unsigned backend_map;
1334 };
1335
1336 struct cayman_asic {
1337         unsigned max_shader_engines;
1338         unsigned max_pipes_per_simd;
1339         unsigned max_tile_pipes;
1340         unsigned max_simds_per_se;
1341         unsigned max_backends_per_se;
1342         unsigned max_texture_channel_caches;
1343         unsigned max_gprs;
1344         unsigned max_threads;
1345         unsigned max_gs_threads;
1346         unsigned max_stack_entries;
1347         unsigned sx_num_of_sets;
1348         unsigned sx_max_export_size;
1349         unsigned sx_max_export_pos_size;
1350         unsigned sx_max_export_smx_size;
1351         unsigned max_hw_contexts;
1352         unsigned sq_num_cf_insts;
1353         unsigned sc_prim_fifo_size;
1354         unsigned sc_hiz_tile_fifo_size;
1355         unsigned sc_earlyz_tile_fifo_size;
1356
1357         unsigned num_shader_engines;
1358         unsigned num_shader_pipes_per_simd;
1359         unsigned num_tile_pipes;
1360         unsigned num_simds_per_se;
1361         unsigned num_backends_per_se;
1362         unsigned backend_disable_mask_per_asic;
1363         unsigned backend_map;
1364         unsigned num_texture_channel_caches;
1365         unsigned mem_max_burst_length_bytes;
1366         unsigned mem_row_size_in_kb;
1367         unsigned shader_engine_tile_size;
1368         unsigned num_gpus;
1369         unsigned multi_gpu_tile_size;
1370
1371         unsigned tile_config;
1372 };
1373
1374 struct si_asic {
1375         unsigned max_shader_engines;
1376         unsigned max_pipes_per_simd;
1377         unsigned max_tile_pipes;
1378         unsigned max_simds_per_se;
1379         unsigned max_backends_per_se;
1380         unsigned max_texture_channel_caches;
1381         unsigned max_gprs;
1382         unsigned max_gs_threads;
1383         unsigned max_hw_contexts;
1384         unsigned sc_prim_fifo_size_frontend;
1385         unsigned sc_prim_fifo_size_backend;
1386         unsigned sc_hiz_tile_fifo_size;
1387         unsigned sc_earlyz_tile_fifo_size;
1388
1389         unsigned num_shader_engines;
1390         unsigned num_tile_pipes;
1391         unsigned num_backends_per_se;
1392         unsigned backend_disable_mask_per_asic;
1393         unsigned backend_map;
1394         unsigned num_texture_channel_caches;
1395         unsigned mem_max_burst_length_bytes;
1396         unsigned mem_row_size_in_kb;
1397         unsigned shader_engine_tile_size;
1398         unsigned num_gpus;
1399         unsigned multi_gpu_tile_size;
1400
1401         unsigned tile_config;
1402 };
1403
1404 union radeon_asic_config {
1405         struct r300_asic        r300;
1406         struct r100_asic        r100;
1407         struct r600_asic        r600;
1408         struct rv770_asic       rv770;
1409         struct evergreen_asic   evergreen;
1410         struct cayman_asic      cayman;
1411         struct si_asic          si;
1412 };
1413
1414 /*
1415  * asic initizalization from radeon_asic.c
1416  */
1417 void radeon_agp_disable(struct radeon_device *rdev);
1418 int radeon_asic_init(struct radeon_device *rdev);
1419
1420
1421 /*
1422  * IOCTL.
1423  */
1424 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1425                           struct drm_file *filp);
1426 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1427                             struct drm_file *filp);
1428 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1429                          struct drm_file *file_priv);
1430 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1431                            struct drm_file *file_priv);
1432 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1433                             struct drm_file *file_priv);
1434 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1435                            struct drm_file *file_priv);
1436 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1437                                 struct drm_file *filp);
1438 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1439                           struct drm_file *filp);
1440 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1441                           struct drm_file *filp);
1442 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1443                               struct drm_file *filp);
1444 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1445                           struct drm_file *filp);
1446 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1447 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1448                                 struct drm_file *filp);
1449 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1450                                 struct drm_file *filp);
1451
1452 /* VRAM scratch page for HDP bug, default vram page */
1453 struct r600_vram_scratch {
1454         struct radeon_bo                *robj;
1455         volatile uint32_t               *ptr;
1456         u64                             gpu_addr;
1457 };
1458
1459
1460 /*
1461  * Core structure, functions and helpers.
1462  */
1463 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1464 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1465
1466 struct radeon_device {
1467         struct device                   *dev;
1468         struct drm_device               *ddev;
1469         struct pci_dev                  *pdev;
1470         /* ASIC */
1471         union radeon_asic_config        config;
1472         enum radeon_family              family;
1473         unsigned long                   flags;
1474         int                             usec_timeout;
1475         enum radeon_pll_errata          pll_errata;
1476         int                             num_gb_pipes;
1477         int                             num_z_pipes;
1478         int                             disp_priority;
1479         /* BIOS */
1480         uint8_t                         *bios;
1481         bool                            is_atom_bios;
1482         uint16_t                        bios_header_start;
1483         struct radeon_bo                *stollen_vga_memory;
1484         /* Register mmio */
1485         resource_size_t                 rmmio_base;
1486         resource_size_t                 rmmio_size;
1487         void __iomem                    *rmmio;
1488         radeon_rreg_t                   mc_rreg;
1489         radeon_wreg_t                   mc_wreg;
1490         radeon_rreg_t                   pll_rreg;
1491         radeon_wreg_t                   pll_wreg;
1492         uint32_t                        pcie_reg_mask;
1493         radeon_rreg_t                   pciep_rreg;
1494         radeon_wreg_t                   pciep_wreg;
1495         /* io port */
1496         void __iomem                    *rio_mem;
1497         resource_size_t                 rio_mem_size;
1498         struct radeon_clock             clock;
1499         struct radeon_mc                mc;
1500         struct radeon_gart              gart;
1501         struct radeon_mode_info         mode_info;
1502         struct radeon_scratch           scratch;
1503         struct radeon_mman              mman;
1504         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
1505         wait_queue_head_t               fence_queue;
1506         struct mutex                    ring_lock;
1507         struct radeon_ring              ring[RADEON_NUM_RINGS];
1508         bool                            ib_pool_ready;
1509         struct radeon_sa_manager        ring_tmp_bo;
1510         struct radeon_irq               irq;
1511         struct radeon_asic              *asic;
1512         struct radeon_gem               gem;
1513         struct radeon_pm                pm;
1514         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1515         struct radeon_mutex             cs_mutex;
1516         struct radeon_wb                wb;
1517         struct radeon_dummy_page        dummy_page;
1518         bool                            shutdown;
1519         bool                            suspend;
1520         bool                            need_dma32;
1521         bool                            accel_working;
1522         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1523         const struct firmware *me_fw;   /* all family ME firmware */
1524         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
1525         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
1526         const struct firmware *mc_fw;   /* NI MC firmware */
1527         const struct firmware *ce_fw;   /* SI CE firmware */
1528         struct r600_blit r600_blit;
1529         struct r600_vram_scratch vram_scratch;
1530         int msi_enabled; /* msi enabled */
1531         struct r600_ih ih; /* r6/700 interrupt ring */
1532         struct si_rlc rlc;
1533         struct work_struct hotplug_work;
1534         struct work_struct audio_work;
1535         int num_crtc; /* number of crtcs */
1536         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1537         struct mutex vram_mutex;
1538         struct r600_audio audio; /* audio stuff */
1539         struct notifier_block acpi_nb;
1540         /* only one userspace can use Hyperz features or CMASK at a time */
1541         struct drm_file *hyperz_filp;
1542         struct drm_file *cmask_filp;
1543         /* i2c buses */
1544         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1545         /* debugfs */
1546         struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1547         unsigned                debugfs_count;
1548         /* virtual memory */
1549         struct radeon_vm_manager        vm_manager;
1550 };
1551
1552 int radeon_device_init(struct radeon_device *rdev,
1553                        struct drm_device *ddev,
1554                        struct pci_dev *pdev,
1555                        uint32_t flags);
1556 void radeon_device_fini(struct radeon_device *rdev);
1557 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1558
1559 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1560 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1561 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1562 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1563
1564 /*
1565  * Cast helper
1566  */
1567 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1568
1569 /*
1570  * Registers read & write functions.
1571  */
1572 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1573 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1574 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1575 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1576 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1577 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1578 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1579 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1580 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1581 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1582 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1583 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1584 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1585 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1586 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1587 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1588 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1589 #define WREG32_P(reg, val, mask)                                \
1590         do {                                                    \
1591                 uint32_t tmp_ = RREG32(reg);                    \
1592                 tmp_ &= (mask);                                 \
1593                 tmp_ |= ((val) & ~(mask));                      \
1594                 WREG32(reg, tmp_);                              \
1595         } while (0)
1596 #define WREG32_PLL_P(reg, val, mask)                            \
1597         do {                                                    \
1598                 uint32_t tmp_ = RREG32_PLL(reg);                \
1599                 tmp_ &= (mask);                                 \
1600                 tmp_ |= ((val) & ~(mask));                      \
1601                 WREG32_PLL(reg, tmp_);                          \
1602         } while (0)
1603 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1604 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1605 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1606
1607 /*
1608  * Indirect registers accessor
1609  */
1610 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1611 {
1612         uint32_t r;
1613
1614         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1615         r = RREG32(RADEON_PCIE_DATA);
1616         return r;
1617 }
1618
1619 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1620 {
1621         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1622         WREG32(RADEON_PCIE_DATA, (v));
1623 }
1624
1625 void r100_pll_errata_after_index(struct radeon_device *rdev);
1626
1627
1628 /*
1629  * ASICs helpers.
1630  */
1631 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1632                             (rdev->pdev->device == 0x5969))
1633 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1634                 (rdev->family == CHIP_RV200) || \
1635                 (rdev->family == CHIP_RS100) || \
1636                 (rdev->family == CHIP_RS200) || \
1637                 (rdev->family == CHIP_RV250) || \
1638                 (rdev->family == CHIP_RV280) || \
1639                 (rdev->family == CHIP_RS300))
1640 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
1641                 (rdev->family == CHIP_RV350) ||                 \
1642                 (rdev->family == CHIP_R350)  ||                 \
1643                 (rdev->family == CHIP_RV380) ||                 \
1644                 (rdev->family == CHIP_R420)  ||                 \
1645                 (rdev->family == CHIP_R423)  ||                 \
1646                 (rdev->family == CHIP_RV410) ||                 \
1647                 (rdev->family == CHIP_RS400) ||                 \
1648                 (rdev->family == CHIP_RS480))
1649 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1650                 (rdev->ddev->pdev->device == 0x9443) || \
1651                 (rdev->ddev->pdev->device == 0x944B) || \
1652                 (rdev->ddev->pdev->device == 0x9506) || \
1653                 (rdev->ddev->pdev->device == 0x9509) || \
1654                 (rdev->ddev->pdev->device == 0x950F) || \
1655                 (rdev->ddev->pdev->device == 0x689C) || \
1656                 (rdev->ddev->pdev->device == 0x689D))
1657 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1658 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
1659                             (rdev->family == CHIP_RS690)  ||    \
1660                             (rdev->family == CHIP_RS740)  ||    \
1661                             (rdev->family >= CHIP_R600))
1662 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1663 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1664 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1665 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1666                              (rdev->flags & RADEON_IS_IGP))
1667 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1668 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1669 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1670                              (rdev->flags & RADEON_IS_IGP))
1671
1672 /*
1673  * BIOS helpers.
1674  */
1675 #define RBIOS8(i) (rdev->bios[i])
1676 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1677 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1678
1679 int radeon_combios_init(struct radeon_device *rdev);
1680 void radeon_combios_fini(struct radeon_device *rdev);
1681 int radeon_atombios_init(struct radeon_device *rdev);
1682 void radeon_atombios_fini(struct radeon_device *rdev);
1683
1684
1685 /*
1686  * RING helpers.
1687  */
1688 #if DRM_DEBUG_CODE == 0
1689 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1690 {
1691         ring->ring[ring->wptr++] = v;
1692         ring->wptr &= ring->ptr_mask;
1693         ring->count_dw--;
1694         ring->ring_free_dw--;
1695 }
1696 #else
1697 /* With debugging this is just too big to inline */
1698 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1699 #endif
1700
1701 /*
1702  * ASICs macro.
1703  */
1704 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1705 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1706 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1707 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1708 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1709 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1710 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1711 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1712 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1713 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1714 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1715 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1716 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1717 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1718 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1719 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1720 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1721 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1722 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1723 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1724 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1725 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1726 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1727 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1728 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1729 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1730 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1731 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1732 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1733 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1734 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1735 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1736 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1737 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1738 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1739 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1740 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1741 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1742 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1743 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1744 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1745 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1746 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1747 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1748 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1749 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1750 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1751 #define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1752 #define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1753 #define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1754 #define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1755
1756 /* Common functions */
1757 /* AGP */
1758 extern int radeon_gpu_reset(struct radeon_device *rdev);
1759 extern void radeon_agp_disable(struct radeon_device *rdev);
1760 extern int radeon_modeset_init(struct radeon_device *rdev);
1761 extern void radeon_modeset_fini(struct radeon_device *rdev);
1762 extern bool radeon_card_posted(struct radeon_device *rdev);
1763 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1764 extern void radeon_update_display_priority(struct radeon_device *rdev);
1765 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1766 extern void radeon_scratch_init(struct radeon_device *rdev);
1767 extern void radeon_wb_fini(struct radeon_device *rdev);
1768 extern int radeon_wb_init(struct radeon_device *rdev);
1769 extern void radeon_wb_disable(struct radeon_device *rdev);
1770 extern void radeon_surface_init(struct radeon_device *rdev);
1771 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1772 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1773 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1774 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1775 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1776 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1777 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1778 extern int radeon_resume_kms(struct drm_device *dev);
1779 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1780 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1781
1782 /*
1783  * vm
1784  */
1785 int radeon_vm_manager_init(struct radeon_device *rdev);
1786 void radeon_vm_manager_fini(struct radeon_device *rdev);
1787 int radeon_vm_manager_start(struct radeon_device *rdev);
1788 int radeon_vm_manager_suspend(struct radeon_device *rdev);
1789 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1790 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1791 int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1792 void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1793 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1794                             struct radeon_vm *vm,
1795                             struct radeon_bo *bo,
1796                             struct ttm_mem_reg *mem);
1797 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1798                              struct radeon_bo *bo);
1799 int radeon_vm_bo_add(struct radeon_device *rdev,
1800                      struct radeon_vm *vm,
1801                      struct radeon_bo *bo,
1802                      uint64_t offset,
1803                      uint32_t flags);
1804 int radeon_vm_bo_rmv(struct radeon_device *rdev,
1805                      struct radeon_vm *vm,
1806                      struct radeon_bo *bo);
1807
1808 /* audio */
1809 void r600_audio_update_hdmi(struct work_struct *work);
1810
1811 /*
1812  * R600 vram scratch functions
1813  */
1814 int r600_vram_scratch_init(struct radeon_device *rdev);
1815 void r600_vram_scratch_fini(struct radeon_device *rdev);
1816
1817 /*
1818  * r600 cs checking helper
1819  */
1820 unsigned r600_mip_minify(unsigned size, unsigned level);
1821 bool r600_fmt_is_valid_color(u32 format);
1822 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1823 int r600_fmt_get_blocksize(u32 format);
1824 int r600_fmt_get_nblocksx(u32 format, u32 w);
1825 int r600_fmt_get_nblocksy(u32 format, u32 h);
1826
1827 /*
1828  * r600 functions used by radeon_encoder.c
1829  */
1830 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1831 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1832 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1833
1834 extern int ni_init_microcode(struct radeon_device *rdev);
1835 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1836
1837 /* radeon_acpi.c */
1838 #if defined(CONFIG_ACPI)
1839 extern int radeon_acpi_init(struct radeon_device *rdev);
1840 #else
1841 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1842 #endif
1843
1844 #include "radeon_object.h"
1845
1846 #endif