drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 #include "radeon_object.h"
  32
  33 /* TODO: Here are things that needs to be done :
  34  *      - surface allocator & initializer : (bit like scratch reg) should
  35  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  36  *        related to surface
  37  *      - WB : write back stuff (do it bit like scratch reg things)
  38  *      - Vblank : look at Jesse's rework and what we should do
  39  *      - r600/r700: gart & cp
  40  *      - cs : clean cs ioctl use bitmap & things like that.
  41  *      - power management stuff
  42  *      - Barrier in gart code
  43  *      - Unmappabled vram ?
  44  *      - TESTING, TESTING, TESTING
  45  */
  46
  47 #include <asm/atomic.h>
  48 #include <linux/wait.h>
  49 #include <linux/list.h>
  50 #include <linux/kref.h>
  51
  52 #include "radeon_family.h"
  53 #include "radeon_mode.h"
  54 #include "radeon_reg.h"
  55
  56 /*
  57  * Modules parameters.
  58  */
  59 extern int radeon_no_wb;
  60 extern int radeon_modeset;
  61 extern int radeon_dynclks;
  62 extern int radeon_r4xx_atom;
  63 extern int radeon_agpmode;
  64 extern int radeon_vram_limit;
  65 extern int radeon_gart_size;
  66 extern int radeon_benchmarking;
  67 extern int radeon_testing;
  68 extern int radeon_connector_table;
  69 extern int radeon_tv;
  70
  71 /*
  72  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  73  * symbol;
  74  */
  75 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  76 #define RADEON_IB_POOL_SIZE             16
  77 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  78 #define RADEONFB_CONN_LIMIT             4
  79 #define RADEON_BIOS_NUM_SCRATCH         8
  80
  81 /*
  82  * Errata workarounds.
  83  */
  84 enum radeon_pll_errata {
  85         CHIP_ERRATA_R300_CG             = 0x00000001,
  86         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  87         CHIP_ERRATA_PLL_DELAY           = 0x00000004
  88 };
  89
  90
  91 struct radeon_device;
  92
  93
  94 /*
  95  * BIOS.
  96  */
  97 bool radeon_get_bios(struct radeon_device *rdev);
  98
  99
 100 /*
 101  * Dummy page
 102  */
 103 struct radeon_dummy_page {
 104         struct page     *page;
 105         dma_addr_t      addr;
 106 };
 107 int radeon_dummy_page_init(struct radeon_device *rdev);
 108 void radeon_dummy_page_fini(struct radeon_device *rdev);
 109
 110
 111 /*
 112  * Clocks
 113  */
 114 struct radeon_clock {
 115         struct radeon_pll p1pll;
 116         struct radeon_pll p2pll;
 117         struct radeon_pll spll;
 118         struct radeon_pll mpll;
 119         /* 10 Khz units */
 120         uint32_t default_mclk;
 121         uint32_t default_sclk;
 122 };
 123
 124
 125 /*
 126  * Fences.
 127  */
 128 struct radeon_fence_driver {
 129         uint32_t                        scratch_reg;
 130         atomic_t                        seq;
 131         uint32_t                        last_seq;
 132         unsigned long                   count_timeout;
 133         wait_queue_head_t               queue;
 134         rwlock_t                        lock;
 135         struct list_head                created;
 136         struct list_head                emited;
 137         struct list_head                signaled;
 138 };
 139
 140 struct radeon_fence {
 141         struct radeon_device            *rdev;
 142         struct kref                     kref;
 143         struct list_head                list;
 144         /* protected by radeon_fence.lock */
 145         uint32_t                        seq;
 146         unsigned long                   timeout;
 147         bool                            emited;
 148         bool                            signaled;
 149 };
 150
 151 int radeon_fence_driver_init(struct radeon_device *rdev);
 152 void radeon_fence_driver_fini(struct radeon_device *rdev);
 153 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 154 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 155 void radeon_fence_process(struct radeon_device *rdev);
 156 bool radeon_fence_signaled(struct radeon_fence *fence);
 157 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 158 int radeon_fence_wait_next(struct radeon_device *rdev);
 159 int radeon_fence_wait_last(struct radeon_device *rdev);
 160 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 161 void radeon_fence_unref(struct radeon_fence **fence);
 162
 163 /*
 164  * Tiling registers
 165  */
 166 struct radeon_surface_reg {
 167         struct radeon_object *robj;
 168 };
 169
 170 #define RADEON_GEM_MAX_SURFACES 8
 171
 172 /*
 173  * Radeon buffer.
 174  */
 175 struct radeon_object;
 176
 177 struct radeon_object_list {
 178         struct list_head        list;
 179         struct radeon_object    *robj;
 180         uint64_t                gpu_offset;
 181         unsigned                rdomain;
 182         unsigned                wdomain;
 183         uint32_t                tiling_flags;
 184 };
 185
 186 int radeon_object_init(struct radeon_device *rdev);
 187 void radeon_object_fini(struct radeon_device *rdev);
 188 int radeon_object_create(struct radeon_device *rdev,
 189                          struct drm_gem_object *gobj,
 190                          unsigned long size,
 191                          bool kernel,
 192                          uint32_t domain,
 193                          bool interruptible,
 194                          struct radeon_object **robj_ptr);
 195 int radeon_object_kmap(struct radeon_object *robj, void **ptr);
 196 void radeon_object_kunmap(struct radeon_object *robj);
 197 void radeon_object_unref(struct radeon_object **robj);
 198 int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
 199                       uint64_t *gpu_addr);
 200 void radeon_object_unpin(struct radeon_object *robj);
 201 int radeon_object_wait(struct radeon_object *robj);
 202 int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
 203 int radeon_object_evict_vram(struct radeon_device *rdev);
 204 int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
 205 void radeon_object_force_delete(struct radeon_device *rdev);
 206 void radeon_object_list_add_object(struct radeon_object_list *lobj,
 207                                    struct list_head *head);
 208 int radeon_object_list_validate(struct list_head *head, void *fence);
 209 void radeon_object_list_unvalidate(struct list_head *head);
 210 void radeon_object_list_clean(struct list_head *head);
 211 int radeon_object_fbdev_mmap(struct radeon_object *robj,
 212                              struct vm_area_struct *vma);
 213 unsigned long radeon_object_size(struct radeon_object *robj);
 214 void radeon_object_clear_surface_reg(struct radeon_object *robj);
 215 int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
 216                                bool force_drop);
 217 void radeon_object_set_tiling_flags(struct radeon_object *robj,
 218                                     uint32_t tiling_flags, uint32_t pitch);
 219 void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
 220 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 221                            struct ttm_mem_reg *mem);
 222 void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 223 /*
 224  * GEM objects.
 225  */
 226 struct radeon_gem {
 227         struct list_head        objects;
 228 };
 229
 230 int radeon_gem_init(struct radeon_device *rdev);
 231 void radeon_gem_fini(struct radeon_device *rdev);
 232 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 233                              int alignment, int initial_domain,
 234                              bool discardable, bool kernel,
 235                              bool interruptible,
 236                              struct drm_gem_object **obj);
 237 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 238                           uint64_t *gpu_addr);
 239 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 240
 241
 242 /*
 243  * GART structures, functions & helpers
 244  */
 245 struct radeon_mc;
 246
 247 struct radeon_gart_table_ram {
 248         volatile uint32_t               *ptr;
 249 };
 250
 251 struct radeon_gart_table_vram {
 252         struct radeon_object            *robj;
 253         volatile uint32_t               *ptr;
 254 };
 255
 256 union radeon_gart_table {
 257         struct radeon_gart_table_ram    ram;
 258         struct radeon_gart_table_vram   vram;
 259 };
 260
 261 struct radeon_gart {
 262         dma_addr_t                      table_addr;
 263         unsigned                        num_gpu_pages;
 264         unsigned                        num_cpu_pages;
 265         unsigned                        table_size;
 266         union radeon_gart_table         table;
 267         struct page                     **pages;
 268         dma_addr_t                      *pages_addr;
 269         bool                            ready;
 270 };
 271
 272 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 273 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 274 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 275 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 276 int radeon_gart_init(struct radeon_device *rdev);
 277 void radeon_gart_fini(struct radeon_device *rdev);
 278 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 279                         int pages);
 280 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 281                      int pages, struct page **pagelist);
 282
 283
 284 /*
 285  * GPU MC structures, functions & helpers
 286  */
 287 struct radeon_mc {
 288         resource_size_t         aper_size;
 289         resource_size_t         aper_base;
 290         resource_size_t         agp_base;
 291         /* for some chips with <= 32MB we need to lie
 292          * about vram size near mc fb location */
 293         u64                     mc_vram_size;
 294         u64                     gtt_location;
 295         u64                     gtt_size;
 296         u64                     gtt_start;
 297         u64                     gtt_end;
 298         u64                     vram_location;
 299         u64                     vram_start;
 300         u64                     vram_end;
 301         unsigned                vram_width;
 302         u64                     real_vram_size;
 303         int                     vram_mtrr;
 304         bool                    vram_is_ddr;
 305 };
 306
 307 int radeon_mc_setup(struct radeon_device *rdev);
 308
 309
 310 /*
 311  * GPU scratch registers structures, functions & helpers
 312  */
 313 struct radeon_scratch {
 314         unsigned                num_reg;
 315         bool                    free[32];
 316         uint32_t                reg[32];
 317 };
 318
 319 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 320 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 321
 322
 323 /*
 324  * IRQS.
 325  */
 326 struct radeon_irq {
 327         bool            installed;
 328         bool            sw_int;
 329         /* FIXME: use a define max crtc rather than hardcode it */
 330         bool            crtc_vblank_int[2];
 331 };
 332
 333 int radeon_irq_kms_init(struct radeon_device *rdev);
 334 void radeon_irq_kms_fini(struct radeon_device *rdev);
 335
 336
 337 /*
 338  * CP & ring.
 339  */
 340 struct radeon_ib {
 341         struct list_head        list;
 342         unsigned long           idx;
 343         uint64_t                gpu_addr;
 344         struct radeon_fence     *fence;
 345         volatile uint32_t       *ptr;
 346         uint32_t                length_dw;
 347 };
 348
 349 /*
 350  * locking -
 351  * mutex protects scheduled_ibs, ready, alloc_bm
 352  */
 353 struct radeon_ib_pool {
 354         struct mutex            mutex;
 355         struct radeon_object    *robj;
 356         struct list_head        scheduled_ibs;
 357         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 358         bool                    ready;
 359         DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
 360 };
 361
 362 struct radeon_cp {
 363         struct radeon_object    *ring_obj;
 364         volatile uint32_t       *ring;
 365         unsigned                rptr;
 366         unsigned                wptr;
 367         unsigned                wptr_old;
 368         unsigned                ring_size;
 369         unsigned                ring_free_dw;
 370         int                     count_dw;
 371         uint64_t                gpu_addr;
 372         uint32_t                align_mask;
 373         uint32_t                ptr_mask;
 374         struct mutex            mutex;
 375         bool                    ready;
 376 };
 377
 378 struct r600_blit {
 379         struct radeon_object    *shader_obj;
 380         u64 shader_gpu_addr;
 381         u32 vs_offset, ps_offset;
 382         u32 state_offset;
 383         u32 state_len;
 384         u32 vb_used, vb_total;
 385         struct radeon_ib *vb_ib;
 386 };
 387
 388 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 389 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 390 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 391 int radeon_ib_pool_init(struct radeon_device *rdev);
 392 void radeon_ib_pool_fini(struct radeon_device *rdev);
 393 int radeon_ib_test(struct radeon_device *rdev);
 394 /* Ring access between begin & end cannot sleep */
 395 void radeon_ring_free_size(struct radeon_device *rdev);
 396 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 397 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 398 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 399 int radeon_ring_test(struct radeon_device *rdev);
 400 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 401 void radeon_ring_fini(struct radeon_device *rdev);
 402
 403
 404 /*
 405  * CS.
 406  */
 407 struct radeon_cs_reloc {
 408         struct drm_gem_object           *gobj;
 409         struct radeon_object            *robj;
 410         struct radeon_object_list       lobj;
 411         uint32_t                        handle;
 412         uint32_t                        flags;
 413 };
 414
 415 struct radeon_cs_chunk {
 416         uint32_t                chunk_id;
 417         uint32_t                length_dw;
 418         uint32_t                *kdata;
 419 };
 420
 421 struct radeon_cs_parser {
 422         struct radeon_device    *rdev;
 423         struct drm_file         *filp;
 424         /* chunks */
 425         unsigned                nchunks;
 426         struct radeon_cs_chunk  *chunks;
 427         uint64_t                *chunks_array;
 428         /* IB */
 429         unsigned                idx;
 430         /* relocations */
 431         unsigned                nrelocs;
 432         struct radeon_cs_reloc  *relocs;
 433         struct radeon_cs_reloc  **relocs_ptr;
 434         struct list_head        validated;
 435         /* indices of various chunks */
 436         int                     chunk_ib_idx;
 437         int                     chunk_relocs_idx;
 438         struct radeon_ib        *ib;
 439         void                    *track;
 440         unsigned                family;
 441 };
 442
 443 struct radeon_cs_packet {
 444         unsigned        idx;
 445         unsigned        type;
 446         unsigned        reg;
 447         unsigned        opcode;
 448         int             count;
 449         unsigned        one_reg_wr;
 450 };
 451
 452 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 453                                       struct radeon_cs_packet *pkt,
 454                                       unsigned idx, unsigned reg);
 455 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 456                                       struct radeon_cs_packet *pkt);
 457
 458
 459 /*
 460  * AGP
 461  */
 462 int radeon_agp_init(struct radeon_device *rdev);
 463 void radeon_agp_fini(struct radeon_device *rdev);
 464
 465
 466 /*
 467  * Writeback
 468  */
 469 struct radeon_wb {
 470         struct radeon_object    *wb_obj;
 471         volatile uint32_t       *wb;
 472         uint64_t                gpu_addr;
 473 };
 474
 475 /**
 476  * struct radeon_pm - power management datas
 477  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 478  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 479  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 480  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 481  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 482  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 483  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 484  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 485  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 486  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
 487  * @needed_bandwidth:   current bandwidth needs
 488  *
 489  * It keeps track of various data needed to take powermanagement decision.
 490  * Bandwith need is used to determine minimun clock of the GPU and memory.
 491  * Equation between gpu/memory clock and available bandwidth is hw dependent
 492  * (type of memory, bus size, efficiency, ...)
 493  */
 494 struct radeon_pm {
 495         fixed20_12              max_bandwidth;
 496         fixed20_12              igp_sideport_mclk;
 497         fixed20_12              igp_system_mclk;
 498         fixed20_12              igp_ht_link_clk;
 499         fixed20_12              igp_ht_link_width;
 500         fixed20_12              k8_bandwidth;
 501         fixed20_12              sideport_bandwidth;
 502         fixed20_12              ht_bandwidth;
 503         fixed20_12              core_bandwidth;
 504         fixed20_12              sclk;
 505         fixed20_12              needed_bandwidth;
 506 };
 507
 508
 509 /*
 510  * Benchmarking
 511  */
 512 void radeon_benchmark(struct radeon_device *rdev);
 513
 514
 515 /*
 516  * Testing
 517  */
 518 void radeon_test_moves(struct radeon_device *rdev);
 519
 520
 521 /*
 522  * Debugfs
 523  */
 524 int radeon_debugfs_add_files(struct radeon_device *rdev,
 525                              struct drm_info_list *files,
 526                              unsigned nfiles);
 527 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 528 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
 529 int r100_debugfs_cp_init(struct radeon_device *rdev);
 530
 531
 532 /*
 533  * ASIC specific functions.
 534  */
 535 struct radeon_asic {
 536         int (*init)(struct radeon_device *rdev);
 537         void (*fini)(struct radeon_device *rdev);
 538         int (*resume)(struct radeon_device *rdev);
 539         int (*suspend)(struct radeon_device *rdev);
 540         void (*errata)(struct radeon_device *rdev);
 541         void (*vram_info)(struct radeon_device *rdev);
 542         void (*vga_set_state)(struct radeon_device *rdev, bool state);
 543         int (*gpu_reset)(struct radeon_device *rdev);
 544         int (*mc_init)(struct radeon_device *rdev);
 545         void (*mc_fini)(struct radeon_device *rdev);
 546         int (*wb_init)(struct radeon_device *rdev);
 547         void (*wb_fini)(struct radeon_device *rdev);
 548         int (*gart_init)(struct radeon_device *rdev);
 549         void (*gart_fini)(struct radeon_device *rdev);
 550         int (*gart_enable)(struct radeon_device *rdev);
 551         void (*gart_disable)(struct radeon_device *rdev);
 552         void (*gart_tlb_flush)(struct radeon_device *rdev);
 553         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 554         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 555         void (*cp_fini)(struct radeon_device *rdev);
 556         void (*cp_disable)(struct radeon_device *rdev);
 557         void (*cp_commit)(struct radeon_device *rdev);
 558         void (*ring_start)(struct radeon_device *rdev);
 559         int (*ring_test)(struct radeon_device *rdev);
 560         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
 561         int (*ib_test)(struct radeon_device *rdev);
 562         int (*irq_set)(struct radeon_device *rdev);
 563         int (*irq_process)(struct radeon_device *rdev);
 564         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 565         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 566         int (*cs_parse)(struct radeon_cs_parser *p);
 567         int (*copy_blit)(struct radeon_device *rdev,
 568                          uint64_t src_offset,
 569                          uint64_t dst_offset,
 570                          unsigned num_pages,
 571                          struct radeon_fence *fence);
 572         int (*copy_dma)(struct radeon_device *rdev,
 573                         uint64_t src_offset,
 574                         uint64_t dst_offset,
 575                         unsigned num_pages,
 576                         struct radeon_fence *fence);
 577         int (*copy)(struct radeon_device *rdev,
 578                     uint64_t src_offset,
 579                     uint64_t dst_offset,
 580                     unsigned num_pages,
 581                     struct radeon_fence *fence);
 582         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 583         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 584         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 585         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 586         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 587                                uint32_t tiling_flags, uint32_t pitch,
 588                                uint32_t offset, uint32_t obj_size);
 589         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 590         void (*bandwidth_update)(struct radeon_device *rdev);
 591 };
 592
 593 /*
 594  * Asic structures
 595  */
 596 struct r100_asic {
 597         const unsigned  *reg_safe_bm;
 598         unsigned        reg_safe_bm_size;
 599 };
 600
 601 struct r300_asic {
 602         const unsigned  *reg_safe_bm;
 603         unsigned        reg_safe_bm_size;
 604 };
 605
 606 struct r600_asic {
 607         unsigned max_pipes;
 608         unsigned max_tile_pipes;
 609         unsigned max_simds;
 610         unsigned max_backends;
 611         unsigned max_gprs;
 612         unsigned max_threads;
 613         unsigned max_stack_entries;
 614         unsigned max_hw_contexts;
 615         unsigned max_gs_threads;
 616         unsigned sx_max_export_size;
 617         unsigned sx_max_export_pos_size;
 618         unsigned sx_max_export_smx_size;
 619         unsigned sq_num_cf_insts;
 620 };
 621
 622 struct rv770_asic {
 623         unsigned max_pipes;
 624         unsigned max_tile_pipes;
 625         unsigned max_simds;
 626         unsigned max_backends;
 627         unsigned max_gprs;
 628         unsigned max_threads;
 629         unsigned max_stack_entries;
 630         unsigned max_hw_contexts;
 631         unsigned max_gs_threads;
 632         unsigned sx_max_export_size;
 633         unsigned sx_max_export_pos_size;
 634         unsigned sx_max_export_smx_size;
 635         unsigned sq_num_cf_insts;
 636         unsigned sx_num_of_sets;
 637         unsigned sc_prim_fifo_size;
 638         unsigned sc_hiz_tile_fifo_size;
 639         unsigned sc_earlyz_tile_fifo_fize;
 640 };
 641
 642 union radeon_asic_config {
 643         struct r300_asic        r300;
 644         struct r100_asic        r100;
 645         struct r600_asic        r600;
 646         struct rv770_asic       rv770;
 647 };
 648
 649
 650 /*
 651  * IOCTL.
 652  */
 653 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
 654                           struct drm_file *filp);
 655 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
 656                             struct drm_file *filp);
 657 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
 658                          struct drm_file *file_priv);
 659 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
 660                            struct drm_file *file_priv);
 661 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 662                             struct drm_file *file_priv);
 663 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
 664                            struct drm_file *file_priv);
 665 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 666                                 struct drm_file *filp);
 667 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
 668                           struct drm_file *filp);
 669 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
 670                           struct drm_file *filp);
 671 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 672                               struct drm_file *filp);
 673 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 674 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
 675                                 struct drm_file *filp);
 676 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 677                                 struct drm_file *filp);
 678
 679
 680 /*
 681  * Core structure, functions and helpers.
 682  */
 683 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
 684 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 685
 686 struct radeon_device {
 687         struct device                   *dev;
 688         struct drm_device               *ddev;
 689         struct pci_dev                  *pdev;
 690         /* ASIC */
 691         union radeon_asic_config        config;
 692         enum radeon_family              family;
 693         unsigned long                   flags;
 694         int                             usec_timeout;
 695         enum radeon_pll_errata          pll_errata;
 696         int                             num_gb_pipes;
 697         int                             num_z_pipes;
 698         int                             disp_priority;
 699         /* BIOS */
 700         uint8_t                         *bios;
 701         bool                            is_atom_bios;
 702         uint16_t                        bios_header_start;
 703         struct radeon_object            *stollen_vga_memory;
 704         struct fb_info                  *fbdev_info;
 705         struct radeon_object            *fbdev_robj;
 706         struct radeon_framebuffer       *fbdev_rfb;
 707         /* Register mmio */
 708         resource_size_t                 rmmio_base;
 709         resource_size_t                 rmmio_size;
 710         void                            *rmmio;
 711         radeon_rreg_t                   mc_rreg;
 712         radeon_wreg_t                   mc_wreg;
 713         radeon_rreg_t                   pll_rreg;
 714         radeon_wreg_t                   pll_wreg;
 715         uint32_t                        pcie_reg_mask;
 716         radeon_rreg_t                   pciep_rreg;
 717         radeon_wreg_t                   pciep_wreg;
 718         struct radeon_clock             clock;
 719         struct radeon_mc                mc;
 720         struct radeon_gart              gart;
 721         struct radeon_mode_info         mode_info;
 722         struct radeon_scratch           scratch;
 723         struct radeon_mman              mman;
 724         struct radeon_fence_driver      fence_drv;
 725         struct radeon_cp                cp;
 726         struct radeon_ib_pool           ib_pool;
 727         struct radeon_irq               irq;
 728         struct radeon_asic              *asic;
 729         struct radeon_gem               gem;
 730         struct radeon_pm                pm;
 731         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
 732         struct mutex                    cs_mutex;
 733         struct radeon_wb                wb;
 734         struct radeon_dummy_page        dummy_page;
 735         bool                            gpu_lockup;
 736         bool                            shutdown;
 737         bool                            suspend;
 738         bool                            need_dma32;
 739         bool                            new_init_path;
 740         bool                            accel_working;
 741         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
 742         const struct firmware *me_fw;   /* all family ME firmware */
 743         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
 744         struct r600_blit r600_blit;
 745 };
 746
 747 int radeon_device_init(struct radeon_device *rdev,
 748                        struct drm_device *ddev,
 749                        struct pci_dev *pdev,
 750                        uint32_t flags);
 751 void radeon_device_fini(struct radeon_device *rdev);
 752 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
 753
 754 /* r600 blit */
 755 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
 756 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
 757 void r600_kms_blit_copy(struct radeon_device *rdev,
 758                         u64 src_gpu_addr, u64 dst_gpu_addr,
 759                         int size_bytes);
 760
 761 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
 762 {
 763         if (reg < 0x10000)
 764                 return readl(((void __iomem *)rdev->rmmio) + reg);
 765         else {
 766                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 767                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 768         }
 769 }
 770
 771 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 772 {
 773         if (reg < 0x10000)
 774                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
 775         else {
 776                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
 777                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
 778         }
 779 }
 780
 781
 782 /*
 783  * Registers read & write functions.
 784  */
 785 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
 786 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
 787 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
 788 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
 789 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
 790 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 791 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
 792 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
 793 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
 794 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
 795 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
 796 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
 797 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
 798 #define WREG32_P(reg, val, mask)                                \
 799         do {                                                    \
 800                 uint32_t tmp_ = RREG32(reg);                    \
 801                 tmp_ &= (mask);                                 \
 802                 tmp_ |= ((val) & ~(mask));                      \
 803                 WREG32(reg, tmp_);                              \
 804         } while (0)
 805 #define WREG32_PLL_P(reg, val, mask)                            \
 806         do {                                                    \
 807                 uint32_t tmp_ = RREG32_PLL(reg);                \
 808                 tmp_ &= (mask);                                 \
 809                 tmp_ |= ((val) & ~(mask));                      \
 810                 WREG32_PLL(reg, tmp_);                          \
 811         } while (0)
 812 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
 813
 814 /*
 815  * Indirect registers accessor
 816  */
 817 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
 818 {
 819         uint32_t r;
 820
 821         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 822         r = RREG32(RADEON_PCIE_DATA);
 823         return r;
 824 }
 825
 826 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 827 {
 828         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
 829         WREG32(RADEON_PCIE_DATA, (v));
 830 }
 831
 832 void r100_pll_errata_after_index(struct radeon_device *rdev);
 833
 834
 835 /*
 836  * ASICs helpers.
 837  */
 838 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
 839                             (rdev->pdev->device == 0x5969))
 840 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
 841                 (rdev->family == CHIP_RV200) || \
 842                 (rdev->family == CHIP_RS100) || \
 843                 (rdev->family == CHIP_RS200) || \
 844                 (rdev->family == CHIP_RV250) || \
 845                 (rdev->family == CHIP_RV280) || \
 846                 (rdev->family == CHIP_RS300))
 847 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
 848                 (rdev->family == CHIP_RV350) ||                 \
 849                 (rdev->family == CHIP_R350)  ||                 \
 850                 (rdev->family == CHIP_RV380) ||                 \
 851                 (rdev->family == CHIP_R420)  ||                 \
 852                 (rdev->family == CHIP_R423)  ||                 \
 853                 (rdev->family == CHIP_RV410) ||                 \
 854                 (rdev->family == CHIP_RS400) ||                 \
 855                 (rdev->family == CHIP_RS480))
 856 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
 857 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
 858 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
 859
 860
 861 /*
 862  * BIOS helpers.
 863  */
 864 #define RBIOS8(i) (rdev->bios[i])
 865 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
 866 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
 867
 868 int radeon_combios_init(struct radeon_device *rdev);
 869 void radeon_combios_fini(struct radeon_device *rdev);
 870 int radeon_atombios_init(struct radeon_device *rdev);
 871 void radeon_atombios_fini(struct radeon_device *rdev);
 872
 873
 874 /*
 875  * RING helpers.
 876  */
 877 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 878 {
 879 #if DRM_DEBUG_CODE
 880         if (rdev->cp.count_dw <= 0) {
 881                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
 882         }
 883 #endif
 884         rdev->cp.ring[rdev->cp.wptr++] = v;
 885         rdev->cp.wptr &= rdev->cp.ptr_mask;
 886         rdev->cp.count_dw--;
 887         rdev->cp.ring_free_dw--;
 888 }
 889
 890
 891 /*
 892  * ASICs macro.
 893  */
 894 #define radeon_init(rdev) (rdev)->asic->init((rdev))
 895 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
 896 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
 897 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
 898 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
 899 #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
 900 #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
 901 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
 902 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
 903 #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
 904 #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
 905 #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
 906 #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
 907 #define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
 908 #define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
 909 #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
 910 #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
 911 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
 912 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
 913 #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
 914 #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
 915 #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
 916 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
 917 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
 918 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
 919 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
 920 #define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
 921 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
 922 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
 923 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
 924 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
 925 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
 926 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
 927 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
 928 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
 929 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
 930 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
 931 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
 932 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
 933 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
 934 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
 935
 936 /* Common functions */
 937 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
 938 extern int radeon_modeset_init(struct radeon_device *rdev);
 939 extern void radeon_modeset_fini(struct radeon_device *rdev);
 940 extern bool radeon_card_posted(struct radeon_device *rdev);
 941 extern int radeon_clocks_init(struct radeon_device *rdev);
 942 extern void radeon_clocks_fini(struct radeon_device *rdev);
 943 extern void radeon_scratch_init(struct radeon_device *rdev);
 944 extern void radeon_surface_init(struct radeon_device *rdev);
 945 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
 946
 947 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
 948 struct r100_mc_save {
 949         u32     GENMO_WT;
 950         u32     CRTC_EXT_CNTL;
 951         u32     CRTC_GEN_CNTL;
 952         u32     CRTC2_GEN_CNTL;
 953         u32     CUR_OFFSET;
 954         u32     CUR2_OFFSET;
 955 };
 956 extern void r100_cp_disable(struct radeon_device *rdev);
 957 extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
 958 extern void r100_cp_fini(struct radeon_device *rdev);
 959 extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
 960 extern int r100_pci_gart_init(struct radeon_device *rdev);
 961 extern void r100_pci_gart_fini(struct radeon_device *rdev);
 962 extern int r100_pci_gart_enable(struct radeon_device *rdev);
 963 extern void r100_pci_gart_disable(struct radeon_device *rdev);
 964 extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 965 extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
 966 extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
 967 extern void r100_ib_fini(struct radeon_device *rdev);
 968 extern int r100_ib_init(struct radeon_device *rdev);
 969 extern void r100_irq_disable(struct radeon_device *rdev);
 970 extern int r100_irq_set(struct radeon_device *rdev);
 971 extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
 972 extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
 973 extern void r100_vram_init_sizes(struct radeon_device *rdev);
 974 extern void r100_wb_disable(struct radeon_device *rdev);
 975 extern void r100_wb_fini(struct radeon_device *rdev);
 976 extern int r100_wb_init(struct radeon_device *rdev);
 977
 978 /* r300,r350,rv350,rv370,rv380 */
 979 extern void r300_set_reg_safe(struct radeon_device *rdev);
 980 extern void r300_mc_program(struct radeon_device *rdev);
 981 extern void r300_vram_info(struct radeon_device *rdev);
 982 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
 983 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
 984 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
 985 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
 986
 987 /* r420,r423,rv410 */
 988 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
 989 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 990 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
 991
 992 /* rv515 */
 993 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
 994
 995 /* rs690, rs740 */
 996 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
 997                                         struct drm_display_mode *mode1,
 998                                         struct drm_display_mode *mode2);
 999
1000 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1001 extern bool r600_card_posted(struct radeon_device *rdev);
1002 extern void r600_cp_stop(struct radeon_device *rdev);
1003 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1004 extern int r600_cp_resume(struct radeon_device *rdev);
1005 extern int r600_count_pipe_bits(uint32_t val);
1006 extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1007 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1008 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1009 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1010 extern int r600_ib_test(struct radeon_device *rdev);
1011 extern int r600_ring_test(struct radeon_device *rdev);
1012 extern int r600_wb_init(struct radeon_device *rdev);
1013 extern void r600_wb_fini(struct radeon_device *rdev);
1014 extern void r600_scratch_init(struct radeon_device *rdev);
1015 extern int r600_blit_init(struct radeon_device *rdev);
1016 extern void r600_blit_fini(struct radeon_device *rdev);
1017 extern int r600_cp_init_microcode(struct radeon_device *rdev);
1018 extern int r600_gpu_reset(struct radeon_device *rdev);
1019
1020 #endif