drivers/gpu/drm/radeon/r600_blit_shaders.c

   1 /*
   2  * Copyright 2009 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include <linux/bug.h>
  28 #include <linux/types.h>
  29 #include <linux/kernel.h>
  30
  31 /*
  32  * R6xx+ cards need to use the 3D engine to blit data which requires
  33  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
  34  * (which normally generates the 3D state) into the DRM, we opt to use
  35  * statically generated state tables.  The regsiter state and shaders
  36  * were hand generated to support blitting functionality.  See the 3D
  37  * driver or documentation for descriptions of the registers and
  38  * shader instructions.
  39  */
  40
  41 const u32 r6xx_default_state[] =
  42 {
  43         0xc0002400, /* START_3D_CMDBUF */
  44         0x00000000,
  45
  46         0xc0012800, /* CONTEXT_CONTROL */
  47         0x80000000,
  48         0x80000000,
  49
  50         0xc0016800,
  51         0x00000010,
  52         0x00008000, /* WAIT_UNTIL */
  53
  54         0xc0016800,
  55         0x00000542,
  56         0x07000003, /* TA_CNTL_AUX */
  57
  58         0xc0016800,
  59         0x000005c5,
  60         0x00000000, /* VC_ENHANCE */
  61
  62         0xc0016800,
  63         0x00000363,
  64         0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
  65
  66         0xc0016800,
  67         0x0000060c,
  68         0x82000000, /* DB_DEBUG */
  69
  70         0xc0016800,
  71         0x0000060e,
  72         0x01020204, /* DB_WATERMARKS */
  73
  74         0xc0026f00,
  75         0x00000000,
  76         0x00000000, /* SQ_VTX_BASE_VTX_LOC */
  77         0x00000000, /* SQ_VTX_START_INST_LOC */
  78
  79         0xc0096900,
  80         0x0000022a,
  81         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
  82         0x00000000,
  83         0x00000000,
  84         0x00000000,
  85         0x00000000,
  86         0x00000000,
  87         0x00000000,
  88         0x00000000,
  89         0x00000000,
  90
  91         0xc0016900,
  92         0x00000004,
  93         0x00000000, /* DB_DEPTH_INFO */
  94
  95         0xc0026900,
  96         0x0000000a,
  97         0x00000000, /* DB_STENCIL_CLEAR */
  98         0x00000000, /* DB_DEPTH_CLEAR */
  99
 100         0xc0016900,
 101         0x00000200,
 102         0x00000000, /* DB_DEPTH_CONTROL */
 103
 104         0xc0026900,
 105         0x00000343,
 106         0x00000060, /* DB_RENDER_CONTROL */
 107         0x00000040, /* DB_RENDER_OVERRIDE */
 108
 109         0xc0016900,
 110         0x00000351,
 111         0x0000aa00, /* DB_ALPHA_TO_MASK */
 112
 113         0xc00f6900,
 114         0x00000100,
 115         0x00000800, /* VGT_MAX_VTX_INDX */
 116         0x00000000, /* VGT_MIN_VTX_INDX */
 117         0x00000000, /* VGT_INDX_OFFSET */
 118         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 119         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 120         0x00000000, /* CB_BLEND_RED */
 121         0x00000000,
 122         0x00000000,
 123         0x00000000,
 124         0x00000000, /* CB_FOG_RED */
 125         0x00000000,
 126         0x00000000,
 127         0x00000000, /* DB_STENCILREFMASK */
 128         0x00000000, /* DB_STENCILREFMASK_BF */
 129         0x00000000, /* SX_ALPHA_REF */
 130
 131         0xc0046900,
 132         0x0000030c,
 133         0x01000000, /* CB_CLRCMP_CNTL */
 134         0x00000000,
 135         0x00000000,
 136         0x00000000,
 137
 138         0xc0046900,
 139         0x00000048,
 140         0x3f800000, /* CB_CLEAR_RED */
 141         0x00000000,
 142         0x3f800000,
 143         0x3f800000,
 144
 145         0xc0016900,
 146         0x00000080,
 147         0x00000000, /* PA_SC_WINDOW_OFFSET */
 148
 149         0xc00a6900,
 150         0x00000083,
 151         0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
 152         0x00000000, /* PA_SC_CLIPRECT_0_TL */
 153         0x20002000,
 154         0x00000000,
 155         0x20002000,
 156         0x00000000,
 157         0x20002000,
 158         0x00000000,
 159         0x20002000,
 160         0x00000000, /* PA_SC_EDGERULE */
 161
 162         0xc0406900,
 163         0x00000094,
 164         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
 165         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
 166         0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
 167         0x20002000,
 168         0x80000000,
 169         0x20002000,
 170         0x80000000,
 171         0x20002000,
 172         0x80000000,
 173         0x20002000,
 174         0x80000000,
 175         0x20002000,
 176         0x80000000,
 177         0x20002000,
 178         0x80000000,
 179         0x20002000,
 180         0x80000000,
 181         0x20002000,
 182         0x80000000,
 183         0x20002000,
 184         0x80000000,
 185         0x20002000,
 186         0x80000000,
 187         0x20002000,
 188         0x80000000,
 189         0x20002000,
 190         0x80000000,
 191         0x20002000,
 192         0x80000000,
 193         0x20002000,
 194         0x80000000,
 195         0x20002000,
 196         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 197         0x3f800000,
 198         0x00000000,
 199         0x3f800000,
 200         0x00000000,
 201         0x3f800000,
 202         0x00000000,
 203         0x3f800000,
 204         0x00000000,
 205         0x3f800000,
 206         0x00000000,
 207         0x3f800000,
 208         0x00000000,
 209         0x3f800000,
 210         0x00000000,
 211         0x3f800000,
 212         0x00000000,
 213         0x3f800000,
 214         0x00000000,
 215         0x3f800000,
 216         0x00000000,
 217         0x3f800000,
 218         0x00000000,
 219         0x3f800000,
 220         0x00000000,
 221         0x3f800000,
 222         0x00000000,
 223         0x3f800000,
 224         0x00000000,
 225         0x3f800000,
 226         0x00000000,
 227         0x3f800000,
 228
 229         0xc0026900,
 230         0x00000292,
 231         0x00000000, /* PA_SC_MPASS_PS_CNTL */
 232         0x00004010, /* PA_SC_MODE_CNTL */
 233
 234         0xc0096900,
 235         0x00000300,
 236         0x00000000, /* PA_SC_LINE_CNTL */
 237         0x00000000, /* PA_SC_AA_CONFIG */
 238         0x0000002d, /* PA_SU_VTX_CNTL */
 239         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 240         0x3f800000,
 241         0x3f800000,
 242         0x3f800000,
 243         0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
 244         0x00000000,
 245
 246         0xc0016900,
 247         0x00000312,
 248         0xffffffff, /* PA_SC_AA_MASK */
 249
 250         0xc0066900,
 251         0x0000037e,
 252         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 253         0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
 254         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
 255         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
 256         0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
 257         0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
 258
 259         0xc0046900,
 260         0x000001b6,
 261         0x00000000, /* SPI_INPUT_Z */
 262         0x00000000, /* SPI_FOG_CNTL */
 263         0x00000000, /* SPI_FOG_FUNC_SCALE */
 264         0x00000000, /* SPI_FOG_FUNC_BIAS */
 265
 266         0xc0016900,
 267         0x00000225,
 268         0x00000000, /* SQ_PGM_START_FS */
 269
 270         0xc0016900,
 271         0x00000229,
 272         0x00000000, /* SQ_PGM_RESOURCES_FS */
 273
 274         0xc0016900,
 275         0x00000237,
 276         0x00000000, /* SQ_PGM_CF_OFFSET_FS */
 277
 278         0xc0026900,
 279         0x000002a8,
 280         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 281         0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
 282
 283         0xc0116900,
 284         0x00000280,
 285         0x00000000, /* PA_SU_POINT_SIZE */
 286         0x00000000, /* PA_SU_POINT_MINMAX */
 287         0x00000008, /* PA_SU_LINE_CNTL */
 288         0x00000000, /* PA_SC_LINE_STIPPLE */
 289         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 290         0x00000000, /* VGT_HOS_CNTL */
 291         0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
 292         0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
 293         0x00000000, /* VGT_HOS_REUSE_DEPTH */
 294         0x00000000, /* VGT_GROUP_PRIM_TYPE */
 295         0x00000000, /* VGT_GROUP_FIRST_DECR */
 296         0x00000000, /* VGT_GROUP_DECR */
 297         0x00000000, /* VGT_GROUP_VECT_0_CNTL */
 298         0x00000000, /* VGT_GROUP_VECT_1_CNTL */
 299         0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
 300         0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
 301         0x00000000, /* VGT_GS_MODE */
 302
 303         0xc0016900,
 304         0x000002a1,
 305         0x00000000, /* VGT_PRIMITIVEID_EN */
 306
 307         0xc0016900,
 308         0x000002a5,
 309         0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
 310
 311         0xc0036900,
 312         0x000002ac,
 313         0x00000000, /* VGT_STRMOUT_EN */
 314         0x00000000, /* VGT_REUSE_OFF */
 315         0x00000000, /* VGT_VTX_CNT_EN */
 316
 317         0xc0016900,
 318         0x000002c8,
 319         0x00000000, /* VGT_STRMOUT_BUFFER_EN */
 320
 321         0xc0076900,
 322         0x00000202,
 323         0x00cc0000, /* CB_COLOR_CONTROL */
 324         0x00000210, /* DB_SHADER_CNTL */
 325         0x00010000, /* PA_CL_CLIP_CNTL */
 326         0x00000244, /* PA_SU_SC_MODE_CNTL */
 327         0x00000100, /* PA_CL_VTE_CNTL */
 328         0x00000000, /* PA_CL_VS_OUT_CNTL */
 329         0x00000000, /* PA_CL_NANINF_CNTL */
 330
 331         0xc0026900,
 332         0x0000008e,
 333         0x0000000f, /* CB_TARGET_MASK */
 334         0x0000000f, /* CB_SHADER_MASK */
 335
 336         0xc0016900,
 337         0x000001e8,
 338         0x00000001, /* CB_SHADER_CONTROL */
 339
 340         0xc0016900,
 341         0x00000185,
 342         0x00000000, /* SPI_VS_OUT_ID_0 */
 343
 344         0xc0016900,
 345         0x00000191,
 346         0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
 347
 348         0xc0056900,
 349         0x000001b1,
 350         0x00000000, /* SPI_VS_OUT_CONFIG */
 351         0x00000000, /* SPI_THREAD_GROUPING */
 352         0x00000001, /* SPI_PS_IN_CONTROL_0 */
 353         0x00000000, /* SPI_PS_IN_CONTROL_1 */
 354         0x00000000, /* SPI_INTERP_CONTROL_0 */
 355
 356         0xc0036e00, /* SET_SAMPLER */
 357         0x00000000,
 358         0x00000012,
 359         0x00000000,
 360         0x00000000,
 361 };
 362
 363 const u32 r7xx_default_state[] =
 364 {
 365         0xc0012800, /* CONTEXT_CONTROL */
 366         0x80000000,
 367         0x80000000,
 368
 369         0xc0016800,
 370         0x00000010,
 371         0x00008000, /* WAIT_UNTIL */
 372
 373         0xc0016800,
 374         0x00000542,
 375         0x07000002, /* TA_CNTL_AUX */
 376
 377         0xc0016800,
 378         0x000005c5,
 379         0x00000000, /* VC_ENHANCE */
 380
 381         0xc0016800,
 382         0x00000363,
 383         0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
 384
 385         0xc0016800,
 386         0x0000060c,
 387         0x00000000, /* DB_DEBUG */
 388
 389         0xc0016800,
 390         0x0000060e,
 391         0x00420204, /* DB_WATERMARKS */
 392
 393         0xc0026f00,
 394         0x00000000,
 395         0x00000000, /* SQ_VTX_BASE_VTX_LOC */
 396         0x00000000, /* SQ_VTX_START_INST_LOC */
 397
 398         0xc0096900,
 399         0x0000022a,
 400         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
 401         0x00000000,
 402         0x00000000,
 403         0x00000000,
 404         0x00000000,
 405         0x00000000,
 406         0x00000000,
 407         0x00000000,
 408         0x00000000,
 409
 410         0xc0016900,
 411         0x00000004,
 412         0x00000000, /* DB_DEPTH_INFO */
 413
 414         0xc0026900,
 415         0x0000000a,
 416         0x00000000, /* DB_STENCIL_CLEAR */
 417         0x00000000, /* DB_DEPTH_CLEAR */
 418
 419         0xc0016900,
 420         0x00000200,
 421         0x00000000, /* DB_DEPTH_CONTROL */
 422
 423         0xc0026900,
 424         0x00000343,
 425         0x00000060, /* DB_RENDER_CONTROL */
 426         0x00000000, /* DB_RENDER_OVERRIDE */
 427
 428         0xc0016900,
 429         0x00000351,
 430         0x0000aa00, /* DB_ALPHA_TO_MASK */
 431
 432         0xc0096900,
 433         0x00000100,
 434         0x00000800, /* VGT_MAX_VTX_INDX */
 435         0x00000000, /* VGT_MIN_VTX_INDX */
 436         0x00000000, /* VGT_INDX_OFFSET */
 437         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 438         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 439         0x00000000, /* CB_BLEND_RED */
 440         0x00000000,
 441         0x00000000,
 442         0x00000000,
 443
 444         0xc0036900,
 445         0x0000010c,
 446         0x00000000, /* DB_STENCILREFMASK */
 447         0x00000000, /* DB_STENCILREFMASK_BF */
 448         0x00000000, /* SX_ALPHA_REF */
 449
 450         0xc0046900,
 451         0x0000030c, /* CB_CLRCMP_CNTL */
 452         0x01000000,
 453         0x00000000,
 454         0x00000000,
 455         0x00000000,
 456
 457         0xc0016900,
 458         0x00000080,
 459         0x00000000, /* PA_SC_WINDOW_OFFSET */
 460
 461         0xc00a6900,
 462         0x00000083,
 463         0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
 464         0x00000000, /* PA_SC_CLIPRECT_0_TL */
 465         0x20002000,
 466         0x00000000,
 467         0x20002000,
 468         0x00000000,
 469         0x20002000,
 470         0x00000000,
 471         0x20002000,
 472         0xaaaaaaaa, /* PA_SC_EDGERULE */
 473
 474         0xc0406900,
 475         0x00000094,
 476         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
 477         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
 478         0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
 479         0x20002000,
 480         0x80000000,
 481         0x20002000,
 482         0x80000000,
 483         0x20002000,
 484         0x80000000,
 485         0x20002000,
 486         0x80000000,
 487         0x20002000,
 488         0x80000000,
 489         0x20002000,
 490         0x80000000,
 491         0x20002000,
 492         0x80000000,
 493         0x20002000,
 494         0x80000000,
 495         0x20002000,
 496         0x80000000,
 497         0x20002000,
 498         0x80000000,
 499         0x20002000,
 500         0x80000000,
 501         0x20002000,
 502         0x80000000,
 503         0x20002000,
 504         0x80000000,
 505         0x20002000,
 506         0x80000000,
 507         0x20002000,
 508         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 509         0x3f800000,
 510         0x00000000,
 511         0x3f800000,
 512         0x00000000,
 513         0x3f800000,
 514         0x00000000,
 515         0x3f800000,
 516         0x00000000,
 517         0x3f800000,
 518         0x00000000,
 519         0x3f800000,
 520         0x00000000,
 521         0x3f800000,
 522         0x00000000,
 523         0x3f800000,
 524         0x00000000,
 525         0x3f800000,
 526         0x00000000,
 527         0x3f800000,
 528         0x00000000,
 529         0x3f800000,
 530         0x00000000,
 531         0x3f800000,
 532         0x00000000,
 533         0x3f800000,
 534         0x00000000,
 535         0x3f800000,
 536         0x00000000,
 537         0x3f800000,
 538         0x00000000,
 539         0x3f800000,
 540
 541         0xc0026900,
 542         0x00000292,
 543         0x00000000, /* PA_SC_MPASS_PS_CNTL */
 544         0x00514000, /* PA_SC_MODE_CNTL */
 545
 546         0xc0096900,
 547         0x00000300,
 548         0x00000000, /* PA_SC_LINE_CNTL */
 549         0x00000000, /* PA_SC_AA_CONFIG */
 550         0x0000002d, /* PA_SU_VTX_CNTL */
 551         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 552         0x3f800000,
 553         0x3f800000,
 554         0x3f800000,
 555         0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
 556         0x00000000,
 557
 558         0xc0016900,
 559         0x00000312,
 560         0xffffffff, /* PA_SC_AA_MASK */
 561
 562         0xc0066900,
 563         0x0000037e,
 564         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 565         0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
 566         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
 567         0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
 568         0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
 569         0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
 570
 571         0xc0046900,
 572         0x000001b6,
 573         0x00000000, /* SPI_INPUT_Z */
 574         0x00000000, /* SPI_FOG_CNTL */
 575         0x00000000, /* SPI_FOG_FUNC_SCALE */
 576         0x00000000, /* SPI_FOG_FUNC_BIAS */
 577
 578         0xc0016900,
 579         0x00000225,
 580         0x00000000, /* SQ_PGM_START_FS */
 581
 582         0xc0016900,
 583         0x00000229,
 584         0x00000000, /* SQ_PGM_RESOURCES_FS */
 585
 586         0xc0016900,
 587         0x00000237,
 588         0x00000000, /* SQ_PGM_CF_OFFSET_FS */
 589
 590         0xc0026900,
 591         0x000002a8,
 592         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 593         0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
 594
 595         0xc0116900,
 596         0x00000280,
 597         0x00000000, /* PA_SU_POINT_SIZE */
 598         0x00000000, /* PA_SU_POINT_MINMAX */
 599         0x00000008, /* PA_SU_LINE_CNTL */
 600         0x00000000, /* PA_SC_LINE_STIPPLE */
 601         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 602         0x00000000, /* VGT_HOS_CNTL */
 603         0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
 604         0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
 605         0x00000000, /* VGT_HOS_REUSE_DEPTH */
 606         0x00000000, /* VGT_GROUP_PRIM_TYPE */
 607         0x00000000, /* VGT_GROUP_FIRST_DECR */
 608         0x00000000, /* VGT_GROUP_DECR */
 609         0x00000000, /* VGT_GROUP_VECT_0_CNTL */
 610         0x00000000, /* VGT_GROUP_VECT_1_CNTL */
 611         0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
 612         0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
 613         0x00000000, /* VGT_GS_MODE */
 614
 615         0xc0016900,
 616         0x000002a1,
 617         0x00000000, /* VGT_PRIMITIVEID_EN */
 618
 619         0xc0016900,
 620         0x000002a5,
 621         0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
 622
 623         0xc0036900,
 624         0x000002ac,
 625         0x00000000, /* VGT_STRMOUT_EN */
 626         0x00000000, /* VGT_REUSE_OFF */
 627         0x00000000, /* VGT_VTX_CNT_EN */
 628
 629         0xc0016900,
 630         0x000002c8,
 631         0x00000000, /* VGT_STRMOUT_BUFFER_EN */
 632
 633         0xc0076900,
 634         0x00000202,
 635         0x00cc0000, /* CB_COLOR_CONTROL */
 636         0x00000210, /* DB_SHADER_CNTL */
 637         0x00010000, /* PA_CL_CLIP_CNTL */
 638         0x00000244, /* PA_SU_SC_MODE_CNTL */
 639         0x00000100, /* PA_CL_VTE_CNTL */
 640         0x00000000, /* PA_CL_VS_OUT_CNTL */
 641         0x00000000, /* PA_CL_NANINF_CNTL */
 642
 643         0xc0026900,
 644         0x0000008e,
 645         0x0000000f, /* CB_TARGET_MASK */
 646         0x0000000f, /* CB_SHADER_MASK */
 647
 648         0xc0016900,
 649         0x000001e8,
 650         0x00000001, /* CB_SHADER_CONTROL */
 651
 652         0xc0016900,
 653         0x00000185,
 654         0x00000000, /* SPI_VS_OUT_ID_0 */
 655
 656         0xc0016900,
 657         0x00000191,
 658         0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
 659
 660         0xc0056900,
 661         0x000001b1,
 662         0x00000000, /* SPI_VS_OUT_CONFIG */
 663         0x00000001, /* SPI_THREAD_GROUPING */
 664         0x00000001, /* SPI_PS_IN_CONTROL_0 */
 665         0x00000000, /* SPI_PS_IN_CONTROL_1 */
 666         0x00000000, /* SPI_INTERP_CONTROL_0 */
 667
 668         0xc0036e00, /* SET_SAMPLER */
 669         0x00000000,
 670         0x00000012,
 671         0x00000000,
 672         0x00000000,
 673 };
 674
 675 /* same for r6xx/r7xx */
 676 const u32 r6xx_vs[] =
 677 {
 678         0x00000004,
 679         0x81000000,
 680         0x0000203c,
 681         0x94000b08,
 682         0x00004000,
 683         0x14200b1a,
 684         0x00000000,
 685         0x00000000,
 686         0x3c000000,
 687         0x68cd1000,
 688 #ifdef __BIG_ENDIAN
 689         0x000a0000,
 690 #else
 691         0x00080000,
 692 #endif
 693         0x00000000,
 694 };
 695
 696 const u32 r6xx_ps[] =
 697 {
 698         0x00000002,
 699         0x80800000,
 700         0x00000000,
 701         0x94200688,
 702         0x00000010,
 703         0x000d1000,
 704         0xb0800000,
 705         0x00000000,
 706 };
 707
 708 const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
 709 const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
 710 const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
 711 const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);