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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / r600.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/firmware.h>
30 #include <linux/platform_device.h>
31 #include "drmP.h"
32 #include "radeon_drm.h"
33 #include "radeon.h"
34 #include "radeon_mode.h"
35 #include "r600d.h"
36 #include "atom.h"
37 #include "avivod.h"
38
39 #define PFP_UCODE_SIZE 576
40 #define PM4_UCODE_SIZE 1792
41 #define RLC_UCODE_SIZE 768
42 #define R700_PFP_UCODE_SIZE 848
43 #define R700_PM4_UCODE_SIZE 1360
44 #define R700_RLC_UCODE_SIZE 1024
45
46 /* Firmware Names */
47 MODULE_FIRMWARE("radeon/R600_pfp.bin");
48 MODULE_FIRMWARE("radeon/R600_me.bin");
49 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV610_me.bin");
51 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV630_me.bin");
53 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV620_me.bin");
55 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV635_me.bin");
57 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV670_me.bin");
59 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
60 MODULE_FIRMWARE("radeon/RS780_me.bin");
61 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV770_me.bin");
63 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV730_me.bin");
65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV710_me.bin");
67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
69
70 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
71
72 /* r600,rv610,rv630,rv620,rv635,rv670 */
73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
74 void r600_gpu_init(struct radeon_device *rdev);
75 void r600_fini(struct radeon_device *rdev);
76
77 /* hpd for digital panel detect/disconnect */
78 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
79 {
80 bool connected = false;
81
82 if (ASIC_IS_DCE3(rdev)) {
83 switch (hpd) {
84 case RADEON_HPD_1:
85 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
86 connected = true;
87 break;
88 case RADEON_HPD_2:
89 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
90 connected = true;
91 break;
92 case RADEON_HPD_3:
93 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
94 connected = true;
95 break;
96 case RADEON_HPD_4:
97 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
98 connected = true;
99 break;
100 /* DCE 3.2 */
101 case RADEON_HPD_5:
102 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
103 connected = true;
104 break;
105 case RADEON_HPD_6:
106 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
107 connected = true;
108 break;
109 default:
110 break;
111 }
112 } else {
113 switch (hpd) {
114 case RADEON_HPD_1:
115 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
116 connected = true;
117 break;
118 case RADEON_HPD_2:
119 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
120 connected = true;
121 break;
122 case RADEON_HPD_3:
123 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
124 connected = true;
125 break;
126 default:
127 break;
128 }
129 }
130 return connected;
131 }
132
133 void r600_hpd_set_polarity(struct radeon_device *rdev,
134 enum radeon_hpd_id hpd)
135 {
136 u32 tmp;
137 bool connected = r600_hpd_sense(rdev, hpd);
138
139 if (ASIC_IS_DCE3(rdev)) {
140 switch (hpd) {
141 case RADEON_HPD_1:
142 tmp = RREG32(DC_HPD1_INT_CONTROL);
143 if (connected)
144 tmp &= ~DC_HPDx_INT_POLARITY;
145 else
146 tmp |= DC_HPDx_INT_POLARITY;
147 WREG32(DC_HPD1_INT_CONTROL, tmp);
148 break;
149 case RADEON_HPD_2:
150 tmp = RREG32(DC_HPD2_INT_CONTROL);
151 if (connected)
152 tmp &= ~DC_HPDx_INT_POLARITY;
153 else
154 tmp |= DC_HPDx_INT_POLARITY;
155 WREG32(DC_HPD2_INT_CONTROL, tmp);
156 break;
157 case RADEON_HPD_3:
158 tmp = RREG32(DC_HPD3_INT_CONTROL);
159 if (connected)
160 tmp &= ~DC_HPDx_INT_POLARITY;
161 else
162 tmp |= DC_HPDx_INT_POLARITY;
163 WREG32(DC_HPD3_INT_CONTROL, tmp);
164 break;
165 case RADEON_HPD_4:
166 tmp = RREG32(DC_HPD4_INT_CONTROL);
167 if (connected)
168 tmp &= ~DC_HPDx_INT_POLARITY;
169 else
170 tmp |= DC_HPDx_INT_POLARITY;
171 WREG32(DC_HPD4_INT_CONTROL, tmp);
172 break;
173 case RADEON_HPD_5:
174 tmp = RREG32(DC_HPD5_INT_CONTROL);
175 if (connected)
176 tmp &= ~DC_HPDx_INT_POLARITY;
177 else
178 tmp |= DC_HPDx_INT_POLARITY;
179 WREG32(DC_HPD5_INT_CONTROL, tmp);
180 break;
181 /* DCE 3.2 */
182 case RADEON_HPD_6:
183 tmp = RREG32(DC_HPD6_INT_CONTROL);
184 if (connected)
185 tmp &= ~DC_HPDx_INT_POLARITY;
186 else
187 tmp |= DC_HPDx_INT_POLARITY;
188 WREG32(DC_HPD6_INT_CONTROL, tmp);
189 break;
190 default:
191 break;
192 }
193 } else {
194 switch (hpd) {
195 case RADEON_HPD_1:
196 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
197 if (connected)
198 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
199 else
200 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
201 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
202 break;
203 case RADEON_HPD_2:
204 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
205 if (connected)
206 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
207 else
208 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
209 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
210 break;
211 case RADEON_HPD_3:
212 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
213 if (connected)
214 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
215 else
216 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
217 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
218 break;
219 default:
220 break;
221 }
222 }
223 }
224
225 void r600_hpd_init(struct radeon_device *rdev)
226 {
227 struct drm_device *dev = rdev->ddev;
228 struct drm_connector *connector;
229
230 if (ASIC_IS_DCE3(rdev)) {
231 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
232 if (ASIC_IS_DCE32(rdev))
233 tmp |= DC_HPDx_EN;
234
235 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
236 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
237 switch (radeon_connector->hpd.hpd) {
238 case RADEON_HPD_1:
239 WREG32(DC_HPD1_CONTROL, tmp);
240 rdev->irq.hpd[0] = true;
241 break;
242 case RADEON_HPD_2:
243 WREG32(DC_HPD2_CONTROL, tmp);
244 rdev->irq.hpd[1] = true;
245 break;
246 case RADEON_HPD_3:
247 WREG32(DC_HPD3_CONTROL, tmp);
248 rdev->irq.hpd[2] = true;
249 break;
250 case RADEON_HPD_4:
251 WREG32(DC_HPD4_CONTROL, tmp);
252 rdev->irq.hpd[3] = true;
253 break;
254 /* DCE 3.2 */
255 case RADEON_HPD_5:
256 WREG32(DC_HPD5_CONTROL, tmp);
257 rdev->irq.hpd[4] = true;
258 break;
259 case RADEON_HPD_6:
260 WREG32(DC_HPD6_CONTROL, tmp);
261 rdev->irq.hpd[5] = true;
262 break;
263 default:
264 break;
265 }
266 }
267 } else {
268 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
269 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
270 switch (radeon_connector->hpd.hpd) {
271 case RADEON_HPD_1:
272 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
273 rdev->irq.hpd[0] = true;
274 break;
275 case RADEON_HPD_2:
276 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
277 rdev->irq.hpd[1] = true;
278 break;
279 case RADEON_HPD_3:
280 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
281 rdev->irq.hpd[2] = true;
282 break;
283 default:
284 break;
285 }
286 }
287 }
288 if (rdev->irq.installed)
289 r600_irq_set(rdev);
290 }
291
292 void r600_hpd_fini(struct radeon_device *rdev)
293 {
294 struct drm_device *dev = rdev->ddev;
295 struct drm_connector *connector;
296
297 if (ASIC_IS_DCE3(rdev)) {
298 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
299 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
300 switch (radeon_connector->hpd.hpd) {
301 case RADEON_HPD_1:
302 WREG32(DC_HPD1_CONTROL, 0);
303 rdev->irq.hpd[0] = false;
304 break;
305 case RADEON_HPD_2:
306 WREG32(DC_HPD2_CONTROL, 0);
307 rdev->irq.hpd[1] = false;
308 break;
309 case RADEON_HPD_3:
310 WREG32(DC_HPD3_CONTROL, 0);
311 rdev->irq.hpd[2] = false;
312 break;
313 case RADEON_HPD_4:
314 WREG32(DC_HPD4_CONTROL, 0);
315 rdev->irq.hpd[3] = false;
316 break;
317 /* DCE 3.2 */
318 case RADEON_HPD_5:
319 WREG32(DC_HPD5_CONTROL, 0);
320 rdev->irq.hpd[4] = false;
321 break;
322 case RADEON_HPD_6:
323 WREG32(DC_HPD6_CONTROL, 0);
324 rdev->irq.hpd[5] = false;
325 break;
326 default:
327 break;
328 }
329 }
330 } else {
331 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
332 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
333 switch (radeon_connector->hpd.hpd) {
334 case RADEON_HPD_1:
335 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
336 rdev->irq.hpd[0] = false;
337 break;
338 case RADEON_HPD_2:
339 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
340 rdev->irq.hpd[1] = false;
341 break;
342 case RADEON_HPD_3:
343 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
344 rdev->irq.hpd[2] = false;
345 break;
346 default:
347 break;
348 }
349 }
350 }
351 }
352
353 /*
354 * R600 PCIE GART
355 */
356 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
357 {
358 unsigned i;
359 u32 tmp;
360
361 /* flush hdp cache so updates hit vram */
362 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
363
364 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
365 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
366 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
367 for (i = 0; i < rdev->usec_timeout; i++) {
368 /* read MC_STATUS */
369 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
370 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
371 if (tmp == 2) {
372 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
373 return;
374 }
375 if (tmp) {
376 return;
377 }
378 udelay(1);
379 }
380 }
381
382 int r600_pcie_gart_init(struct radeon_device *rdev)
383 {
384 int r;
385
386 if (rdev->gart.table.vram.robj) {
387 WARN(1, "R600 PCIE GART already initialized.\n");
388 return 0;
389 }
390 /* Initialize common gart structure */
391 r = radeon_gart_init(rdev);
392 if (r)
393 return r;
394 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
395 return radeon_gart_table_vram_alloc(rdev);
396 }
397
398 int r600_pcie_gart_enable(struct radeon_device *rdev)
399 {
400 u32 tmp;
401 int r, i;
402
403 if (rdev->gart.table.vram.robj == NULL) {
404 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
405 return -EINVAL;
406 }
407 r = radeon_gart_table_vram_pin(rdev);
408 if (r)
409 return r;
410 radeon_gart_restore(rdev);
411
412 /* Setup L2 cache */
413 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
414 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
415 EFFECTIVE_L2_QUEUE_SIZE(7));
416 WREG32(VM_L2_CNTL2, 0);
417 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
418 /* Setup TLB control */
419 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
420 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
421 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
422 ENABLE_WAIT_L2_QUERY;
423 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
424 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
425 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
426 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
427 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
428 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
429 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
430 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
431 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
432 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
433 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
434 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
435 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
436 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
437 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
438 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
439 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
440 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
441 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
442 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
443 (u32)(rdev->dummy_page.addr >> 12));
444 for (i = 1; i < 7; i++)
445 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
446
447 r600_pcie_gart_tlb_flush(rdev);
448 rdev->gart.ready = true;
449 return 0;
450 }
451
452 void r600_pcie_gart_disable(struct radeon_device *rdev)
453 {
454 u32 tmp;
455 int i, r;
456
457 /* Disable all tables */
458 for (i = 0; i < 7; i++)
459 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
460
461 /* Disable L2 cache */
462 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
463 EFFECTIVE_L2_QUEUE_SIZE(7));
464 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
465 /* Setup L1 TLB control */
466 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
467 ENABLE_WAIT_L2_QUERY;
468 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
469 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
470 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
471 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
472 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
473 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
474 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
475 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
476 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
477 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
478 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
479 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
480 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
481 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
482 if (rdev->gart.table.vram.robj) {
483 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
484 if (likely(r == 0)) {
485 radeon_bo_kunmap(rdev->gart.table.vram.robj);
486 radeon_bo_unpin(rdev->gart.table.vram.robj);
487 radeon_bo_unreserve(rdev->gart.table.vram.robj);
488 }
489 }
490 }
491
492 void r600_pcie_gart_fini(struct radeon_device *rdev)
493 {
494 r600_pcie_gart_disable(rdev);
495 radeon_gart_table_vram_free(rdev);
496 radeon_gart_fini(rdev);
497 }
498
499 void r600_agp_enable(struct radeon_device *rdev)
500 {
501 u32 tmp;
502 int i;
503
504 /* Setup L2 cache */
505 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
506 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
507 EFFECTIVE_L2_QUEUE_SIZE(7));
508 WREG32(VM_L2_CNTL2, 0);
509 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
510 /* Setup TLB control */
511 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
512 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
513 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
514 ENABLE_WAIT_L2_QUERY;
515 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
516 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
517 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
518 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
519 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
520 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
521 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
522 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
523 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
524 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
525 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
526 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
527 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
528 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
529 for (i = 0; i < 7; i++)
530 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
531 }
532
533 int r600_mc_wait_for_idle(struct radeon_device *rdev)
534 {
535 unsigned i;
536 u32 tmp;
537
538 for (i = 0; i < rdev->usec_timeout; i++) {
539 /* read MC_STATUS */
540 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
541 if (!tmp)
542 return 0;
543 udelay(1);
544 }
545 return -1;
546 }
547
548 static void r600_mc_program(struct radeon_device *rdev)
549 {
550 struct rv515_mc_save save;
551 u32 tmp;
552 int i, j;
553
554 /* Initialize HDP */
555 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
556 WREG32((0x2c14 + j), 0x00000000);
557 WREG32((0x2c18 + j), 0x00000000);
558 WREG32((0x2c1c + j), 0x00000000);
559 WREG32((0x2c20 + j), 0x00000000);
560 WREG32((0x2c24 + j), 0x00000000);
561 }
562 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
563
564 rv515_mc_stop(rdev, &save);
565 if (r600_mc_wait_for_idle(rdev)) {
566 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
567 }
568 /* Lockout access through VGA aperture (doesn't exist before R600) */
569 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
570 /* Update configuration */
571 if (rdev->flags & RADEON_IS_AGP) {
572 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
573 /* VRAM before AGP */
574 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
575 rdev->mc.vram_start >> 12);
576 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
577 rdev->mc.gtt_end >> 12);
578 } else {
579 /* VRAM after AGP */
580 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
581 rdev->mc.gtt_start >> 12);
582 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
583 rdev->mc.vram_end >> 12);
584 }
585 } else {
586 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
587 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
588 }
589 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
590 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
591 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
592 WREG32(MC_VM_FB_LOCATION, tmp);
593 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
594 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
595 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
596 if (rdev->flags & RADEON_IS_AGP) {
597 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
598 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
599 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
600 } else {
601 WREG32(MC_VM_AGP_BASE, 0);
602 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
603 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
604 }
605 if (r600_mc_wait_for_idle(rdev)) {
606 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
607 }
608 rv515_mc_resume(rdev, &save);
609 /* we need to own VRAM, so turn off the VGA renderer here
610 * to stop it overwriting our objects */
611 rv515_vga_render_disable(rdev);
612 }
613
614 /**
615 * r600_vram_gtt_location - try to find VRAM & GTT location
616 * @rdev: radeon device structure holding all necessary informations
617 * @mc: memory controller structure holding memory informations
618 *
619 * Function will place try to place VRAM at same place as in CPU (PCI)
620 * address space as some GPU seems to have issue when we reprogram at
621 * different address space.
622 *
623 * If there is not enough space to fit the unvisible VRAM after the
624 * aperture then we limit the VRAM size to the aperture.
625 *
626 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
627 * them to be in one from GPU point of view so that we can program GPU to
628 * catch access outside them (weird GPU policy see ??).
629 *
630 * This function will never fails, worst case are limiting VRAM or GTT.
631 *
632 * Note: GTT start, end, size should be initialized before calling this
633 * function on AGP platform.
634 */
635 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
636 {
637 u64 size_bf, size_af;
638
639 if (mc->mc_vram_size > 0xE0000000) {
640 /* leave room for at least 512M GTT */
641 dev_warn(rdev->dev, "limiting VRAM\n");
642 mc->real_vram_size = 0xE0000000;
643 mc->mc_vram_size = 0xE0000000;
644 }
645 if (rdev->flags & RADEON_IS_AGP) {
646 size_bf = mc->gtt_start;
647 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
648 if (size_bf > size_af) {
649 if (mc->mc_vram_size > size_bf) {
650 dev_warn(rdev->dev, "limiting VRAM\n");
651 mc->real_vram_size = size_bf;
652 mc->mc_vram_size = size_bf;
653 }
654 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
655 } else {
656 if (mc->mc_vram_size > size_af) {
657 dev_warn(rdev->dev, "limiting VRAM\n");
658 mc->real_vram_size = size_af;
659 mc->mc_vram_size = size_af;
660 }
661 mc->vram_start = mc->gtt_end;
662 }
663 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
664 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
665 mc->mc_vram_size >> 20, mc->vram_start,
666 mc->vram_end, mc->real_vram_size >> 20);
667 } else {
668 u64 base = 0;
669 if (rdev->flags & RADEON_IS_IGP)
670 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
671 radeon_vram_location(rdev, &rdev->mc, base);
672 radeon_gtt_location(rdev, mc);
673 }
674 }
675
676 int r600_mc_init(struct radeon_device *rdev)
677 {
678 fixed20_12 a;
679 u32 tmp;
680 int chansize, numchan;
681
682 /* Get VRAM informations */
683 rdev->mc.vram_is_ddr = true;
684 tmp = RREG32(RAMCFG);
685 if (tmp & CHANSIZE_OVERRIDE) {
686 chansize = 16;
687 } else if (tmp & CHANSIZE_MASK) {
688 chansize = 64;
689 } else {
690 chansize = 32;
691 }
692 tmp = RREG32(CHMAP);
693 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
694 case 0:
695 default:
696 numchan = 1;
697 break;
698 case 1:
699 numchan = 2;
700 break;
701 case 2:
702 numchan = 4;
703 break;
704 case 3:
705 numchan = 8;
706 break;
707 }
708 rdev->mc.vram_width = numchan * chansize;
709 /* Could aper size report 0 ? */
710 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
711 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
712 /* Setup GPU memory space */
713 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
714 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
715 rdev->mc.visible_vram_size = rdev->mc.aper_size;
716 /* FIXME remove this once we support unmappable VRAM */
717 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
718 rdev->mc.mc_vram_size = rdev->mc.aper_size;
719 rdev->mc.real_vram_size = rdev->mc.aper_size;
720 }
721 r600_vram_gtt_location(rdev, &rdev->mc);
722 /* FIXME: we should enforce default clock in case GPU is not in
723 * default setup
724 */
725 a.full = rfixed_const(100);
726 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
727 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
728 if (rdev->flags & RADEON_IS_IGP)
729 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
730 return 0;
731 }
732
733 /* We doesn't check that the GPU really needs a reset we simply do the
734 * reset, it's up to the caller to determine if the GPU needs one. We
735 * might add an helper function to check that.
736 */
737 int r600_gpu_soft_reset(struct radeon_device *rdev)
738 {
739 struct rv515_mc_save save;
740 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
741 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
742 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
743 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
744 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
745 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
746 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
747 S_008010_GUI_ACTIVE(1);
748 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
749 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
750 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
751 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
752 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
753 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
754 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
755 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
756 u32 srbm_reset = 0;
757 u32 tmp;
758
759 dev_info(rdev->dev, "GPU softreset \n");
760 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
761 RREG32(R_008010_GRBM_STATUS));
762 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
763 RREG32(R_008014_GRBM_STATUS2));
764 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
765 RREG32(R_000E50_SRBM_STATUS));
766 rv515_mc_stop(rdev, &save);
767 if (r600_mc_wait_for_idle(rdev)) {
768 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
769 }
770 /* Disable CP parsing/prefetching */
771 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
772 /* Check if any of the rendering block is busy and reset it */
773 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
774 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
775 tmp = S_008020_SOFT_RESET_CR(1) |
776 S_008020_SOFT_RESET_DB(1) |
777 S_008020_SOFT_RESET_CB(1) |
778 S_008020_SOFT_RESET_PA(1) |
779 S_008020_SOFT_RESET_SC(1) |
780 S_008020_SOFT_RESET_SMX(1) |
781 S_008020_SOFT_RESET_SPI(1) |
782 S_008020_SOFT_RESET_SX(1) |
783 S_008020_SOFT_RESET_SH(1) |
784 S_008020_SOFT_RESET_TC(1) |
785 S_008020_SOFT_RESET_TA(1) |
786 S_008020_SOFT_RESET_VC(1) |
787 S_008020_SOFT_RESET_VGT(1);
788 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
789 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
790 (void)RREG32(R_008020_GRBM_SOFT_RESET);
791 udelay(50);
792 WREG32(R_008020_GRBM_SOFT_RESET, 0);
793 (void)RREG32(R_008020_GRBM_SOFT_RESET);
794 }
795 /* Reset CP (we always reset CP) */
796 tmp = S_008020_SOFT_RESET_CP(1);
797 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
798 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
799 (void)RREG32(R_008020_GRBM_SOFT_RESET);
800 udelay(50);
801 WREG32(R_008020_GRBM_SOFT_RESET, 0);
802 (void)RREG32(R_008020_GRBM_SOFT_RESET);
803 /* Reset others GPU block if necessary */
804 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
805 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
806 if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
807 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
808 if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
809 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
810 if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
811 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
812 if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
813 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
814 if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
815 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
816 if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
817 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
818 if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
819 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
820 if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
821 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
822 if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
823 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
824 if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
825 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
826 if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
827 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
828 dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
829 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
830 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
831 udelay(50);
832 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
833 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
834 WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
835 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
836 udelay(50);
837 WREG32(R_000E60_SRBM_SOFT_RESET, 0);
838 (void)RREG32(R_000E60_SRBM_SOFT_RESET);
839 /* Wait a little for things to settle down */
840 udelay(50);
841 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
842 RREG32(R_008010_GRBM_STATUS));
843 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
844 RREG32(R_008014_GRBM_STATUS2));
845 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
846 RREG32(R_000E50_SRBM_STATUS));
847 /* After reset we need to reinit the asic as GPU often endup in an
848 * incoherent state.
849 */
850 atom_asic_init(rdev->mode_info.atom_context);
851 rv515_mc_resume(rdev, &save);
852 return 0;
853 }
854
855 int r600_gpu_reset(struct radeon_device *rdev)
856 {
857 return r600_gpu_soft_reset(rdev);
858 }
859
860 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
861 u32 num_backends,
862 u32 backend_disable_mask)
863 {
864 u32 backend_map = 0;
865 u32 enabled_backends_mask;
866 u32 enabled_backends_count;
867 u32 cur_pipe;
868 u32 swizzle_pipe[R6XX_MAX_PIPES];
869 u32 cur_backend;
870 u32 i;
871
872 if (num_tile_pipes > R6XX_MAX_PIPES)
873 num_tile_pipes = R6XX_MAX_PIPES;
874 if (num_tile_pipes < 1)
875 num_tile_pipes = 1;
876 if (num_backends > R6XX_MAX_BACKENDS)
877 num_backends = R6XX_MAX_BACKENDS;
878 if (num_backends < 1)
879 num_backends = 1;
880
881 enabled_backends_mask = 0;
882 enabled_backends_count = 0;
883 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
884 if (((backend_disable_mask >> i) & 1) == 0) {
885 enabled_backends_mask |= (1 << i);
886 ++enabled_backends_count;
887 }
888 if (enabled_backends_count == num_backends)
889 break;
890 }
891
892 if (enabled_backends_count == 0) {
893 enabled_backends_mask = 1;
894 enabled_backends_count = 1;
895 }
896
897 if (enabled_backends_count != num_backends)
898 num_backends = enabled_backends_count;
899
900 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
901 switch (num_tile_pipes) {
902 case 1:
903 swizzle_pipe[0] = 0;
904 break;
905 case 2:
906 swizzle_pipe[0] = 0;
907 swizzle_pipe[1] = 1;
908 break;
909 case 3:
910 swizzle_pipe[0] = 0;
911 swizzle_pipe[1] = 1;
912 swizzle_pipe[2] = 2;
913 break;
914 case 4:
915 swizzle_pipe[0] = 0;
916 swizzle_pipe[1] = 1;
917 swizzle_pipe[2] = 2;
918 swizzle_pipe[3] = 3;
919 break;
920 case 5:
921 swizzle_pipe[0] = 0;
922 swizzle_pipe[1] = 1;
923 swizzle_pipe[2] = 2;
924 swizzle_pipe[3] = 3;
925 swizzle_pipe[4] = 4;
926 break;
927 case 6:
928 swizzle_pipe[0] = 0;
929 swizzle_pipe[1] = 2;
930 swizzle_pipe[2] = 4;
931 swizzle_pipe[3] = 5;
932 swizzle_pipe[4] = 1;
933 swizzle_pipe[5] = 3;
934 break;
935 case 7:
936 swizzle_pipe[0] = 0;
937 swizzle_pipe[1] = 2;
938 swizzle_pipe[2] = 4;
939 swizzle_pipe[3] = 6;
940 swizzle_pipe[4] = 1;
941 swizzle_pipe[5] = 3;
942 swizzle_pipe[6] = 5;
943 break;
944 case 8:
945 swizzle_pipe[0] = 0;
946 swizzle_pipe[1] = 2;
947 swizzle_pipe[2] = 4;
948 swizzle_pipe[3] = 6;
949 swizzle_pipe[4] = 1;
950 swizzle_pipe[5] = 3;
951 swizzle_pipe[6] = 5;
952 swizzle_pipe[7] = 7;
953 break;
954 }
955
956 cur_backend = 0;
957 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
958 while (((1 << cur_backend) & enabled_backends_mask) == 0)
959 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
960
961 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
962
963 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
964 }
965
966 return backend_map;
967 }
968
969 int r600_count_pipe_bits(uint32_t val)
970 {
971 int i, ret = 0;
972
973 for (i = 0; i < 32; i++) {
974 ret += val & 1;
975 val >>= 1;
976 }
977 return ret;
978 }
979
980 void r600_gpu_init(struct radeon_device *rdev)
981 {
982 u32 tiling_config;
983 u32 ramcfg;
984 u32 backend_map;
985 u32 cc_rb_backend_disable;
986 u32 cc_gc_shader_pipe_config;
987 u32 tmp;
988 int i, j;
989 u32 sq_config;
990 u32 sq_gpr_resource_mgmt_1 = 0;
991 u32 sq_gpr_resource_mgmt_2 = 0;
992 u32 sq_thread_resource_mgmt = 0;
993 u32 sq_stack_resource_mgmt_1 = 0;
994 u32 sq_stack_resource_mgmt_2 = 0;
995
996 /* FIXME: implement */
997 switch (rdev->family) {
998 case CHIP_R600:
999 rdev->config.r600.max_pipes = 4;
1000 rdev->config.r600.max_tile_pipes = 8;
1001 rdev->config.r600.max_simds = 4;
1002 rdev->config.r600.max_backends = 4;
1003 rdev->config.r600.max_gprs = 256;
1004 rdev->config.r600.max_threads = 192;
1005 rdev->config.r600.max_stack_entries = 256;
1006 rdev->config.r600.max_hw_contexts = 8;
1007 rdev->config.r600.max_gs_threads = 16;
1008 rdev->config.r600.sx_max_export_size = 128;
1009 rdev->config.r600.sx_max_export_pos_size = 16;
1010 rdev->config.r600.sx_max_export_smx_size = 128;
1011 rdev->config.r600.sq_num_cf_insts = 2;
1012 break;
1013 case CHIP_RV630:
1014 case CHIP_RV635:
1015 rdev->config.r600.max_pipes = 2;
1016 rdev->config.r600.max_tile_pipes = 2;
1017 rdev->config.r600.max_simds = 3;
1018 rdev->config.r600.max_backends = 1;
1019 rdev->config.r600.max_gprs = 128;
1020 rdev->config.r600.max_threads = 192;
1021 rdev->config.r600.max_stack_entries = 128;
1022 rdev->config.r600.max_hw_contexts = 8;
1023 rdev->config.r600.max_gs_threads = 4;
1024 rdev->config.r600.sx_max_export_size = 128;
1025 rdev->config.r600.sx_max_export_pos_size = 16;
1026 rdev->config.r600.sx_max_export_smx_size = 128;
1027 rdev->config.r600.sq_num_cf_insts = 2;
1028 break;
1029 case CHIP_RV610:
1030 case CHIP_RV620:
1031 case CHIP_RS780:
1032 case CHIP_RS880:
1033 rdev->config.r600.max_pipes = 1;
1034 rdev->config.r600.max_tile_pipes = 1;
1035 rdev->config.r600.max_simds = 2;
1036 rdev->config.r600.max_backends = 1;
1037 rdev->config.r600.max_gprs = 128;
1038 rdev->config.r600.max_threads = 192;
1039 rdev->config.r600.max_stack_entries = 128;
1040 rdev->config.r600.max_hw_contexts = 4;
1041 rdev->config.r600.max_gs_threads = 4;
1042 rdev->config.r600.sx_max_export_size = 128;
1043 rdev->config.r600.sx_max_export_pos_size = 16;
1044 rdev->config.r600.sx_max_export_smx_size = 128;
1045 rdev->config.r600.sq_num_cf_insts = 1;
1046 break;
1047 case CHIP_RV670:
1048 rdev->config.r600.max_pipes = 4;
1049 rdev->config.r600.max_tile_pipes = 4;
1050 rdev->config.r600.max_simds = 4;
1051 rdev->config.r600.max_backends = 4;
1052 rdev->config.r600.max_gprs = 192;
1053 rdev->config.r600.max_threads = 192;
1054 rdev->config.r600.max_stack_entries = 256;
1055 rdev->config.r600.max_hw_contexts = 8;
1056 rdev->config.r600.max_gs_threads = 16;
1057 rdev->config.r600.sx_max_export_size = 128;
1058 rdev->config.r600.sx_max_export_pos_size = 16;
1059 rdev->config.r600.sx_max_export_smx_size = 128;
1060 rdev->config.r600.sq_num_cf_insts = 2;
1061 break;
1062 default:
1063 break;
1064 }
1065
1066 /* Initialize HDP */
1067 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1068 WREG32((0x2c14 + j), 0x00000000);
1069 WREG32((0x2c18 + j), 0x00000000);
1070 WREG32((0x2c1c + j), 0x00000000);
1071 WREG32((0x2c20 + j), 0x00000000);
1072 WREG32((0x2c24 + j), 0x00000000);
1073 }
1074
1075 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1076
1077 /* Setup tiling */
1078 tiling_config = 0;
1079 ramcfg = RREG32(RAMCFG);
1080 switch (rdev->config.r600.max_tile_pipes) {
1081 case 1:
1082 tiling_config |= PIPE_TILING(0);
1083 break;
1084 case 2:
1085 tiling_config |= PIPE_TILING(1);
1086 break;
1087 case 4:
1088 tiling_config |= PIPE_TILING(2);
1089 break;
1090 case 8:
1091 tiling_config |= PIPE_TILING(3);
1092 break;
1093 default:
1094 break;
1095 }
1096 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1097 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1098 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1099 tiling_config |= GROUP_SIZE(0);
1100 rdev->config.r600.tiling_group_size = 256;
1101 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1102 if (tmp > 3) {
1103 tiling_config |= ROW_TILING(3);
1104 tiling_config |= SAMPLE_SPLIT(3);
1105 } else {
1106 tiling_config |= ROW_TILING(tmp);
1107 tiling_config |= SAMPLE_SPLIT(tmp);
1108 }
1109 tiling_config |= BANK_SWAPS(1);
1110
1111 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1112 cc_rb_backend_disable |=
1113 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1114
1115 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1116 cc_gc_shader_pipe_config |=
1117 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1118 cc_gc_shader_pipe_config |=
1119 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1120
1121 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1122 (R6XX_MAX_BACKENDS -
1123 r600_count_pipe_bits((cc_rb_backend_disable &
1124 R6XX_MAX_BACKENDS_MASK) >> 16)),
1125 (cc_rb_backend_disable >> 16));
1126
1127 tiling_config |= BACKEND_MAP(backend_map);
1128 WREG32(GB_TILING_CONFIG, tiling_config);
1129 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1130 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1131
1132 /* Setup pipes */
1133 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1134 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1135
1136 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1137 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1138 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1139
1140 /* Setup some CP states */
1141 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1142 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1143
1144 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1145 SYNC_WALKER | SYNC_ALIGNER));
1146 /* Setup various GPU states */
1147 if (rdev->family == CHIP_RV670)
1148 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1149
1150 tmp = RREG32(SX_DEBUG_1);
1151 tmp |= SMX_EVENT_RELEASE;
1152 if ((rdev->family > CHIP_R600))
1153 tmp |= ENABLE_NEW_SMX_ADDRESS;
1154 WREG32(SX_DEBUG_1, tmp);
1155
1156 if (((rdev->family) == CHIP_R600) ||
1157 ((rdev->family) == CHIP_RV630) ||
1158 ((rdev->family) == CHIP_RV610) ||
1159 ((rdev->family) == CHIP_RV620) ||
1160 ((rdev->family) == CHIP_RS780) ||
1161 ((rdev->family) == CHIP_RS880)) {
1162 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1163 } else {
1164 WREG32(DB_DEBUG, 0);
1165 }
1166 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1167 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1168
1169 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1170 WREG32(VGT_NUM_INSTANCES, 0);
1171
1172 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1173 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1174
1175 tmp = RREG32(SQ_MS_FIFO_SIZES);
1176 if (((rdev->family) == CHIP_RV610) ||
1177 ((rdev->family) == CHIP_RV620) ||
1178 ((rdev->family) == CHIP_RS780) ||
1179 ((rdev->family) == CHIP_RS880)) {
1180 tmp = (CACHE_FIFO_SIZE(0xa) |
1181 FETCH_FIFO_HIWATER(0xa) |
1182 DONE_FIFO_HIWATER(0xe0) |
1183 ALU_UPDATE_FIFO_HIWATER(0x8));
1184 } else if (((rdev->family) == CHIP_R600) ||
1185 ((rdev->family) == CHIP_RV630)) {
1186 tmp &= ~DONE_FIFO_HIWATER(0xff);
1187 tmp |= DONE_FIFO_HIWATER(0x4);
1188 }
1189 WREG32(SQ_MS_FIFO_SIZES, tmp);
1190
1191 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1192 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1193 */
1194 sq_config = RREG32(SQ_CONFIG);
1195 sq_config &= ~(PS_PRIO(3) |
1196 VS_PRIO(3) |
1197 GS_PRIO(3) |
1198 ES_PRIO(3));
1199 sq_config |= (DX9_CONSTS |
1200 VC_ENABLE |
1201 PS_PRIO(0) |
1202 VS_PRIO(1) |
1203 GS_PRIO(2) |
1204 ES_PRIO(3));
1205
1206 if ((rdev->family) == CHIP_R600) {
1207 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1208 NUM_VS_GPRS(124) |
1209 NUM_CLAUSE_TEMP_GPRS(4));
1210 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1211 NUM_ES_GPRS(0));
1212 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1213 NUM_VS_THREADS(48) |
1214 NUM_GS_THREADS(4) |
1215 NUM_ES_THREADS(4));
1216 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1217 NUM_VS_STACK_ENTRIES(128));
1218 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1219 NUM_ES_STACK_ENTRIES(0));
1220 } else if (((rdev->family) == CHIP_RV610) ||
1221 ((rdev->family) == CHIP_RV620) ||
1222 ((rdev->family) == CHIP_RS780) ||
1223 ((rdev->family) == CHIP_RS880)) {
1224 /* no vertex cache */
1225 sq_config &= ~VC_ENABLE;
1226
1227 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1228 NUM_VS_GPRS(44) |
1229 NUM_CLAUSE_TEMP_GPRS(2));
1230 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1231 NUM_ES_GPRS(17));
1232 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1233 NUM_VS_THREADS(78) |
1234 NUM_GS_THREADS(4) |
1235 NUM_ES_THREADS(31));
1236 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1237 NUM_VS_STACK_ENTRIES(40));
1238 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1239 NUM_ES_STACK_ENTRIES(16));
1240 } else if (((rdev->family) == CHIP_RV630) ||
1241 ((rdev->family) == CHIP_RV635)) {
1242 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1243 NUM_VS_GPRS(44) |
1244 NUM_CLAUSE_TEMP_GPRS(2));
1245 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1246 NUM_ES_GPRS(18));
1247 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1248 NUM_VS_THREADS(78) |
1249 NUM_GS_THREADS(4) |
1250 NUM_ES_THREADS(31));
1251 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1252 NUM_VS_STACK_ENTRIES(40));
1253 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1254 NUM_ES_STACK_ENTRIES(16));
1255 } else if ((rdev->family) == CHIP_RV670) {
1256 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1257 NUM_VS_GPRS(44) |
1258 NUM_CLAUSE_TEMP_GPRS(2));
1259 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1260 NUM_ES_GPRS(17));
1261 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1262 NUM_VS_THREADS(78) |
1263 NUM_GS_THREADS(4) |
1264 NUM_ES_THREADS(31));
1265 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1266 NUM_VS_STACK_ENTRIES(64));
1267 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1268 NUM_ES_STACK_ENTRIES(64));
1269 }
1270
1271 WREG32(SQ_CONFIG, sq_config);
1272 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1273 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1274 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1275 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1276 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1277
1278 if (((rdev->family) == CHIP_RV610) ||
1279 ((rdev->family) == CHIP_RV620) ||
1280 ((rdev->family) == CHIP_RS780) ||
1281 ((rdev->family) == CHIP_RS880)) {
1282 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1283 } else {
1284 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1285 }
1286
1287 /* More default values. 2D/3D driver should adjust as needed */
1288 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1289 S1_X(0x4) | S1_Y(0xc)));
1290 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1291 S1_X(0x2) | S1_Y(0x2) |
1292 S2_X(0xa) | S2_Y(0x6) |
1293 S3_X(0x6) | S3_Y(0xa)));
1294 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1295 S1_X(0x4) | S1_Y(0xc) |
1296 S2_X(0x1) | S2_Y(0x6) |
1297 S3_X(0xa) | S3_Y(0xe)));
1298 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1299 S5_X(0x0) | S5_Y(0x0) |
1300 S6_X(0xb) | S6_Y(0x4) |
1301 S7_X(0x7) | S7_Y(0x8)));
1302
1303 WREG32(VGT_STRMOUT_EN, 0);
1304 tmp = rdev->config.r600.max_pipes * 16;
1305 switch (rdev->family) {
1306 case CHIP_RV610:
1307 case CHIP_RV620:
1308 case CHIP_RS780:
1309 case CHIP_RS880:
1310 tmp += 32;
1311 break;
1312 case CHIP_RV670:
1313 tmp += 128;
1314 break;
1315 default:
1316 break;
1317 }
1318 if (tmp > 256) {
1319 tmp = 256;
1320 }
1321 WREG32(VGT_ES_PER_GS, 128);
1322 WREG32(VGT_GS_PER_ES, tmp);
1323 WREG32(VGT_GS_PER_VS, 2);
1324 WREG32(VGT_GS_VERTEX_REUSE, 16);
1325
1326 /* more default values. 2D/3D driver should adjust as needed */
1327 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1328 WREG32(VGT_STRMOUT_EN, 0);
1329 WREG32(SX_MISC, 0);
1330 WREG32(PA_SC_MODE_CNTL, 0);
1331 WREG32(PA_SC_AA_CONFIG, 0);
1332 WREG32(PA_SC_LINE_STIPPLE, 0);
1333 WREG32(SPI_INPUT_Z, 0);
1334 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1335 WREG32(CB_COLOR7_FRAG, 0);
1336
1337 /* Clear render buffer base addresses */
1338 WREG32(CB_COLOR0_BASE, 0);
1339 WREG32(CB_COLOR1_BASE, 0);
1340 WREG32(CB_COLOR2_BASE, 0);
1341 WREG32(CB_COLOR3_BASE, 0);
1342 WREG32(CB_COLOR4_BASE, 0);
1343 WREG32(CB_COLOR5_BASE, 0);
1344 WREG32(CB_COLOR6_BASE, 0);
1345 WREG32(CB_COLOR7_BASE, 0);
1346 WREG32(CB_COLOR7_FRAG, 0);
1347
1348 switch (rdev->family) {
1349 case CHIP_RV610:
1350 case CHIP_RV620:
1351 case CHIP_RS780:
1352 case CHIP_RS880:
1353 tmp = TC_L2_SIZE(8);
1354 break;
1355 case CHIP_RV630:
1356 case CHIP_RV635:
1357 tmp = TC_L2_SIZE(4);
1358 break;
1359 case CHIP_R600:
1360 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1361 break;
1362 default:
1363 tmp = TC_L2_SIZE(0);
1364 break;
1365 }
1366 WREG32(TC_CNTL, tmp);
1367
1368 tmp = RREG32(HDP_HOST_PATH_CNTL);
1369 WREG32(HDP_HOST_PATH_CNTL, tmp);
1370
1371 tmp = RREG32(ARB_POP);
1372 tmp |= ENABLE_TC128;
1373 WREG32(ARB_POP, tmp);
1374
1375 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1376 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1377 NUM_CLIP_SEQ(3)));
1378 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1379 }
1380
1381
1382 /*
1383 * Indirect registers accessor
1384 */
1385 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1386 {
1387 u32 r;
1388
1389 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1390 (void)RREG32(PCIE_PORT_INDEX);
1391 r = RREG32(PCIE_PORT_DATA);
1392 return r;
1393 }
1394
1395 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1396 {
1397 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1398 (void)RREG32(PCIE_PORT_INDEX);
1399 WREG32(PCIE_PORT_DATA, (v));
1400 (void)RREG32(PCIE_PORT_DATA);
1401 }
1402
1403 /*
1404 * CP & Ring
1405 */
1406 void r600_cp_stop(struct radeon_device *rdev)
1407 {
1408 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1409 }
1410
1411 int r600_init_microcode(struct radeon_device *rdev)
1412 {
1413 struct platform_device *pdev;
1414 const char *chip_name;
1415 const char *rlc_chip_name;
1416 size_t pfp_req_size, me_req_size, rlc_req_size;
1417 char fw_name[30];
1418 int err;
1419
1420 DRM_DEBUG("\n");
1421
1422 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1423 err = IS_ERR(pdev);
1424 if (err) {
1425 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1426 return -EINVAL;
1427 }
1428
1429 switch (rdev->family) {
1430 case CHIP_R600:
1431 chip_name = "R600";
1432 rlc_chip_name = "R600";
1433 break;
1434 case CHIP_RV610:
1435 chip_name = "RV610";
1436 rlc_chip_name = "R600";
1437 break;
1438 case CHIP_RV630:
1439 chip_name = "RV630";
1440 rlc_chip_name = "R600";
1441 break;
1442 case CHIP_RV620:
1443 chip_name = "RV620";
1444 rlc_chip_name = "R600";
1445 break;
1446 case CHIP_RV635:
1447 chip_name = "RV635";
1448 rlc_chip_name = "R600";
1449 break;
1450 case CHIP_RV670:
1451 chip_name = "RV670";
1452 rlc_chip_name = "R600";
1453 break;
1454 case CHIP_RS780:
1455 case CHIP_RS880:
1456 chip_name = "RS780";
1457 rlc_chip_name = "R600";
1458 break;
1459 case CHIP_RV770:
1460 chip_name = "RV770";
1461 rlc_chip_name = "R700";
1462 break;
1463 case CHIP_RV730:
1464 case CHIP_RV740:
1465 chip_name = "RV730";
1466 rlc_chip_name = "R700";
1467 break;
1468 case CHIP_RV710:
1469 chip_name = "RV710";
1470 rlc_chip_name = "R700";
1471 break;
1472 default: BUG();
1473 }
1474
1475 if (rdev->family >= CHIP_RV770) {
1476 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1477 me_req_size = R700_PM4_UCODE_SIZE * 4;
1478 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1479 } else {
1480 pfp_req_size = PFP_UCODE_SIZE * 4;
1481 me_req_size = PM4_UCODE_SIZE * 12;
1482 rlc_req_size = RLC_UCODE_SIZE * 4;
1483 }
1484
1485 DRM_INFO("Loading %s Microcode\n", chip_name);
1486
1487 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1488 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1489 if (err)
1490 goto out;
1491 if (rdev->pfp_fw->size != pfp_req_size) {
1492 printk(KERN_ERR
1493 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1494 rdev->pfp_fw->size, fw_name);
1495 err = -EINVAL;
1496 goto out;
1497 }
1498
1499 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1500 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1501 if (err)
1502 goto out;
1503 if (rdev->me_fw->size != me_req_size) {
1504 printk(KERN_ERR
1505 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1506 rdev->me_fw->size, fw_name);
1507 err = -EINVAL;
1508 }
1509
1510 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1511 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1512 if (err)
1513 goto out;
1514 if (rdev->rlc_fw->size != rlc_req_size) {
1515 printk(KERN_ERR
1516 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1517 rdev->rlc_fw->size, fw_name);
1518 err = -EINVAL;
1519 }
1520
1521 out:
1522 platform_device_unregister(pdev);
1523
1524 if (err) {
1525 if (err != -EINVAL)
1526 printk(KERN_ERR
1527 "r600_cp: Failed to load firmware \"%s\"\n",
1528 fw_name);
1529 release_firmware(rdev->pfp_fw);
1530 rdev->pfp_fw = NULL;
1531 release_firmware(rdev->me_fw);
1532 rdev->me_fw = NULL;
1533 release_firmware(rdev->rlc_fw);
1534 rdev->rlc_fw = NULL;
1535 }
1536 return err;
1537 }
1538
1539 static int r600_cp_load_microcode(struct radeon_device *rdev)
1540 {
1541 const __be32 *fw_data;
1542 int i;
1543
1544 if (!rdev->me_fw || !rdev->pfp_fw)
1545 return -EINVAL;
1546
1547 r600_cp_stop(rdev);
1548
1549 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1550
1551 /* Reset cp */
1552 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1553 RREG32(GRBM_SOFT_RESET);
1554 mdelay(15);
1555 WREG32(GRBM_SOFT_RESET, 0);
1556
1557 WREG32(CP_ME_RAM_WADDR, 0);
1558
1559 fw_data = (const __be32 *)rdev->me_fw->data;
1560 WREG32(CP_ME_RAM_WADDR, 0);
1561 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1562 WREG32(CP_ME_RAM_DATA,
1563 be32_to_cpup(fw_data++));
1564
1565 fw_data = (const __be32 *)rdev->pfp_fw->data;
1566 WREG32(CP_PFP_UCODE_ADDR, 0);
1567 for (i = 0; i < PFP_UCODE_SIZE; i++)
1568 WREG32(CP_PFP_UCODE_DATA,
1569 be32_to_cpup(fw_data++));
1570
1571 WREG32(CP_PFP_UCODE_ADDR, 0);
1572 WREG32(CP_ME_RAM_WADDR, 0);
1573 WREG32(CP_ME_RAM_RADDR, 0);
1574 return 0;
1575 }
1576
1577 int r600_cp_start(struct radeon_device *rdev)
1578 {
1579 int r;
1580 uint32_t cp_me;
1581
1582 r = radeon_ring_lock(rdev, 7);
1583 if (r) {
1584 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1585 return r;
1586 }
1587 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1588 radeon_ring_write(rdev, 0x1);
1589 if (rdev->family < CHIP_RV770) {
1590 radeon_ring_write(rdev, 0x3);
1591 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1592 } else {
1593 radeon_ring_write(rdev, 0x0);
1594 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1595 }
1596 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1597 radeon_ring_write(rdev, 0);
1598 radeon_ring_write(rdev, 0);
1599 radeon_ring_unlock_commit(rdev);
1600
1601 cp_me = 0xff;
1602 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1603 return 0;
1604 }
1605
1606 int r600_cp_resume(struct radeon_device *rdev)
1607 {
1608 u32 tmp;
1609 u32 rb_bufsz;
1610 int r;
1611
1612 /* Reset cp */
1613 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1614 RREG32(GRBM_SOFT_RESET);
1615 mdelay(15);
1616 WREG32(GRBM_SOFT_RESET, 0);
1617
1618 /* Set ring buffer size */
1619 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1620 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1621 #ifdef __BIG_ENDIAN
1622 tmp |= BUF_SWAP_32BIT;
1623 #endif
1624 WREG32(CP_RB_CNTL, tmp);
1625 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1626
1627 /* Set the write pointer delay */
1628 WREG32(CP_RB_WPTR_DELAY, 0);
1629
1630 /* Initialize the ring buffer's read and write pointers */
1631 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1632 WREG32(CP_RB_RPTR_WR, 0);
1633 WREG32(CP_RB_WPTR, 0);
1634 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1635 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1636 mdelay(1);
1637 WREG32(CP_RB_CNTL, tmp);
1638
1639 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1640 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1641
1642 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1643 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1644
1645 r600_cp_start(rdev);
1646 rdev->cp.ready = true;
1647 r = radeon_ring_test(rdev);
1648 if (r) {
1649 rdev->cp.ready = false;
1650 return r;
1651 }
1652 return 0;
1653 }
1654
1655 void r600_cp_commit(struct radeon_device *rdev)
1656 {
1657 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1658 (void)RREG32(CP_RB_WPTR);
1659 }
1660
1661 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1662 {
1663 u32 rb_bufsz;
1664
1665 /* Align ring size */
1666 rb_bufsz = drm_order(ring_size / 8);
1667 ring_size = (1 << (rb_bufsz + 1)) * 4;
1668 rdev->cp.ring_size = ring_size;
1669 rdev->cp.align_mask = 16 - 1;
1670 }
1671
1672 void r600_cp_fini(struct radeon_device *rdev)
1673 {
1674 r600_cp_stop(rdev);
1675 radeon_ring_fini(rdev);
1676 }
1677
1678
1679 /*
1680 * GPU scratch registers helpers function.
1681 */
1682 void r600_scratch_init(struct radeon_device *rdev)
1683 {
1684 int i;
1685
1686 rdev->scratch.num_reg = 7;
1687 for (i = 0; i < rdev->scratch.num_reg; i++) {
1688 rdev->scratch.free[i] = true;
1689 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1690 }
1691 }
1692
1693 int r600_ring_test(struct radeon_device *rdev)
1694 {
1695 uint32_t scratch;
1696 uint32_t tmp = 0;
1697 unsigned i;
1698 int r;
1699
1700 r = radeon_scratch_get(rdev, &scratch);
1701 if (r) {
1702 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1703 return r;
1704 }
1705 WREG32(scratch, 0xCAFEDEAD);
1706 r = radeon_ring_lock(rdev, 3);
1707 if (r) {
1708 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1709 radeon_scratch_free(rdev, scratch);
1710 return r;
1711 }
1712 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1713 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1714 radeon_ring_write(rdev, 0xDEADBEEF);
1715 radeon_ring_unlock_commit(rdev);
1716 for (i = 0; i < rdev->usec_timeout; i++) {
1717 tmp = RREG32(scratch);
1718 if (tmp == 0xDEADBEEF)
1719 break;
1720 DRM_UDELAY(1);
1721 }
1722 if (i < rdev->usec_timeout) {
1723 DRM_INFO("ring test succeeded in %d usecs\n", i);
1724 } else {
1725 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1726 scratch, tmp);
1727 r = -EINVAL;
1728 }
1729 radeon_scratch_free(rdev, scratch);
1730 return r;
1731 }
1732
1733 void r600_wb_disable(struct radeon_device *rdev)
1734 {
1735 int r;
1736
1737 WREG32(SCRATCH_UMSK, 0);
1738 if (rdev->wb.wb_obj) {
1739 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1740 if (unlikely(r != 0))
1741 return;
1742 radeon_bo_kunmap(rdev->wb.wb_obj);
1743 radeon_bo_unpin(rdev->wb.wb_obj);
1744 radeon_bo_unreserve(rdev->wb.wb_obj);
1745 }
1746 }
1747
1748 void r600_wb_fini(struct radeon_device *rdev)
1749 {
1750 r600_wb_disable(rdev);
1751 if (rdev->wb.wb_obj) {
1752 radeon_bo_unref(&rdev->wb.wb_obj);
1753 rdev->wb.wb = NULL;
1754 rdev->wb.wb_obj = NULL;
1755 }
1756 }
1757
1758 int r600_wb_enable(struct radeon_device *rdev)
1759 {
1760 int r;
1761
1762 if (rdev->wb.wb_obj == NULL) {
1763 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1764 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1765 if (r) {
1766 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1767 return r;
1768 }
1769 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1770 if (unlikely(r != 0)) {
1771 r600_wb_fini(rdev);
1772 return r;
1773 }
1774 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1775 &rdev->wb.gpu_addr);
1776 if (r) {
1777 radeon_bo_unreserve(rdev->wb.wb_obj);
1778 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1779 r600_wb_fini(rdev);
1780 return r;
1781 }
1782 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1783 radeon_bo_unreserve(rdev->wb.wb_obj);
1784 if (r) {
1785 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1786 r600_wb_fini(rdev);
1787 return r;
1788 }
1789 }
1790 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1791 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1792 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1793 WREG32(SCRATCH_UMSK, 0xff);
1794 return 0;
1795 }
1796
1797 void r600_fence_ring_emit(struct radeon_device *rdev,
1798 struct radeon_fence *fence)
1799 {
1800 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
1801
1802 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1803 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1804 /* wait for 3D idle clean */
1805 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1806 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1807 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1808 /* Emit fence sequence & fire IRQ */
1809 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1810 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1811 radeon_ring_write(rdev, fence->seq);
1812 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1813 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1814 radeon_ring_write(rdev, RB_INT_STAT);
1815 }
1816
1817 int r600_copy_blit(struct radeon_device *rdev,
1818 uint64_t src_offset, uint64_t dst_offset,
1819 unsigned num_pages, struct radeon_fence *fence)
1820 {
1821 int r;
1822
1823 mutex_lock(&rdev->r600_blit.mutex);
1824 rdev->r600_blit.vb_ib = NULL;
1825 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1826 if (r) {
1827 if (rdev->r600_blit.vb_ib)
1828 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1829 mutex_unlock(&rdev->r600_blit.mutex);
1830 return r;
1831 }
1832 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1833 r600_blit_done_copy(rdev, fence);
1834 mutex_unlock(&rdev->r600_blit.mutex);
1835 return 0;
1836 }
1837
1838 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1839 uint32_t tiling_flags, uint32_t pitch,
1840 uint32_t offset, uint32_t obj_size)
1841 {
1842 /* FIXME: implement */
1843 return 0;
1844 }
1845
1846 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1847 {
1848 /* FIXME: implement */
1849 }
1850
1851
1852 bool r600_card_posted(struct radeon_device *rdev)
1853 {
1854 uint32_t reg;
1855
1856 /* first check CRTCs */
1857 reg = RREG32(D1CRTC_CONTROL) |
1858 RREG32(D2CRTC_CONTROL);
1859 if (reg & CRTC_EN)
1860 return true;
1861
1862 /* then check MEM_SIZE, in case the crtcs are off */
1863 if (RREG32(CONFIG_MEMSIZE))
1864 return true;
1865
1866 return false;
1867 }
1868
1869 int r600_startup(struct radeon_device *rdev)
1870 {
1871 int r;
1872
1873 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1874 r = r600_init_microcode(rdev);
1875 if (r) {
1876 DRM_ERROR("Failed to load firmware!\n");
1877 return r;
1878 }
1879 }
1880
1881 r600_mc_program(rdev);
1882 if (rdev->flags & RADEON_IS_AGP) {
1883 r600_agp_enable(rdev);
1884 } else {
1885 r = r600_pcie_gart_enable(rdev);
1886 if (r)
1887 return r;
1888 }
1889 r600_gpu_init(rdev);
1890 r = r600_blit_init(rdev);
1891 if (r) {
1892 r600_blit_fini(rdev);
1893 rdev->asic->copy = NULL;
1894 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1895 }
1896 /* pin copy shader into vram */
1897 if (rdev->r600_blit.shader_obj) {
1898 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1899 if (unlikely(r != 0))
1900 return r;
1901 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1902 &rdev->r600_blit.shader_gpu_addr);
1903 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1904 if (r) {
1905 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1906 return r;
1907 }
1908 }
1909 /* Enable IRQ */
1910 r = r600_irq_init(rdev);
1911 if (r) {
1912 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1913 radeon_irq_kms_fini(rdev);
1914 return r;
1915 }
1916 r600_irq_set(rdev);
1917
1918 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1919 if (r)
1920 return r;
1921 r = r600_cp_load_microcode(rdev);
1922 if (r)
1923 return r;
1924 r = r600_cp_resume(rdev);
1925 if (r)
1926 return r;
1927 /* write back buffer are not vital so don't worry about failure */
1928 r600_wb_enable(rdev);
1929 return 0;
1930 }
1931
1932 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1933 {
1934 uint32_t temp;
1935
1936 temp = RREG32(CONFIG_CNTL);
1937 if (state == false) {
1938 temp &= ~(1<<0);
1939 temp |= (1<<1);
1940 } else {
1941 temp &= ~(1<<1);
1942 }
1943 WREG32(CONFIG_CNTL, temp);
1944 }
1945
1946 int r600_resume(struct radeon_device *rdev)
1947 {
1948 int r;
1949
1950 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1951 * posting will perform necessary task to bring back GPU into good
1952 * shape.
1953 */
1954 /* post card */
1955 atom_asic_init(rdev->mode_info.atom_context);
1956 /* Initialize clocks */
1957 r = radeon_clocks_init(rdev);
1958 if (r) {
1959 return r;
1960 }
1961
1962 r = r600_startup(rdev);
1963 if (r) {
1964 DRM_ERROR("r600 startup failed on resume\n");
1965 return r;
1966 }
1967
1968 r = r600_ib_test(rdev);
1969 if (r) {
1970 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1971 return r;
1972 }
1973
1974 r = r600_audio_init(rdev);
1975 if (r) {
1976 DRM_ERROR("radeon: audio resume failed\n");
1977 return r;
1978 }
1979
1980 return r;
1981 }
1982
1983 int r600_suspend(struct radeon_device *rdev)
1984 {
1985 int r;
1986
1987 r600_audio_fini(rdev);
1988 /* FIXME: we should wait for ring to be empty */
1989 r600_cp_stop(rdev);
1990 rdev->cp.ready = false;
1991 r600_irq_suspend(rdev);
1992 r600_wb_disable(rdev);
1993 r600_pcie_gart_disable(rdev);
1994 /* unpin shaders bo */
1995 if (rdev->r600_blit.shader_obj) {
1996 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1997 if (!r) {
1998 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1999 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2000 }
2001 }
2002 return 0;
2003 }
2004
2005 /* Plan is to move initialization in that function and use
2006 * helper function so that radeon_device_init pretty much
2007 * do nothing more than calling asic specific function. This
2008 * should also allow to remove a bunch of callback function
2009 * like vram_info.
2010 */
2011 int r600_init(struct radeon_device *rdev)
2012 {
2013 int r;
2014
2015 r = radeon_dummy_page_init(rdev);
2016 if (r)
2017 return r;
2018 if (r600_debugfs_mc_info_init(rdev)) {
2019 DRM_ERROR("Failed to register debugfs file for mc !\n");
2020 }
2021 /* This don't do much */
2022 r = radeon_gem_init(rdev);
2023 if (r)
2024 return r;
2025 /* Read BIOS */
2026 if (!radeon_get_bios(rdev)) {
2027 if (ASIC_IS_AVIVO(rdev))
2028 return -EINVAL;
2029 }
2030 /* Must be an ATOMBIOS */
2031 if (!rdev->is_atom_bios) {
2032 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2033 return -EINVAL;
2034 }
2035 r = radeon_atombios_init(rdev);
2036 if (r)
2037 return r;
2038 /* Post card if necessary */
2039 if (!r600_card_posted(rdev)) {
2040 if (!rdev->bios) {
2041 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2042 return -EINVAL;
2043 }
2044 DRM_INFO("GPU not posted. posting now...\n");
2045 atom_asic_init(rdev->mode_info.atom_context);
2046 }
2047 /* Initialize scratch registers */
2048 r600_scratch_init(rdev);
2049 /* Initialize surface registers */
2050 radeon_surface_init(rdev);
2051 /* Initialize clocks */
2052 radeon_get_clock_info(rdev->ddev);
2053 r = radeon_clocks_init(rdev);
2054 if (r)
2055 return r;
2056 /* Initialize power management */
2057 radeon_pm_init(rdev);
2058 /* Fence driver */
2059 r = radeon_fence_driver_init(rdev);
2060 if (r)
2061 return r;
2062 if (rdev->flags & RADEON_IS_AGP) {
2063 r = radeon_agp_init(rdev);
2064 if (r)
2065 radeon_agp_disable(rdev);
2066 }
2067 r = r600_mc_init(rdev);
2068 if (r)
2069 return r;
2070 /* Memory manager */
2071 r = radeon_bo_init(rdev);
2072 if (r)
2073 return r;
2074
2075 r = radeon_irq_kms_init(rdev);
2076 if (r)
2077 return r;
2078
2079 rdev->cp.ring_obj = NULL;
2080 r600_ring_init(rdev, 1024 * 1024);
2081
2082 rdev->ih.ring_obj = NULL;
2083 r600_ih_ring_init(rdev, 64 * 1024);
2084
2085 r = r600_pcie_gart_init(rdev);
2086 if (r)
2087 return r;
2088
2089 rdev->accel_working = true;
2090 r = r600_startup(rdev);
2091 if (r) {
2092 dev_err(rdev->dev, "disabling GPU acceleration\n");
2093 r600_cp_fini(rdev);
2094 r600_wb_fini(rdev);
2095 r600_irq_fini(rdev);
2096 radeon_irq_kms_fini(rdev);
2097 r600_pcie_gart_fini(rdev);
2098 rdev->accel_working = false;
2099 }
2100 if (rdev->accel_working) {
2101 r = radeon_ib_pool_init(rdev);
2102 if (r) {
2103 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2104 rdev->accel_working = false;
2105 } else {
2106 r = r600_ib_test(rdev);
2107 if (r) {
2108 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2109 rdev->accel_working = false;
2110 }
2111 }
2112 }
2113
2114 r = r600_audio_init(rdev);
2115 if (r)
2116 return r; /* TODO error handling */
2117 return 0;
2118 }
2119
2120 void r600_fini(struct radeon_device *rdev)
2121 {
2122 r600_audio_fini(rdev);
2123 r600_blit_fini(rdev);
2124 r600_cp_fini(rdev);
2125 r600_wb_fini(rdev);
2126 r600_irq_fini(rdev);
2127 radeon_irq_kms_fini(rdev);
2128 r600_pcie_gart_fini(rdev);
2129 radeon_agp_fini(rdev);
2130 radeon_gem_fini(rdev);
2131 radeon_fence_driver_fini(rdev);
2132 radeon_clocks_fini(rdev);
2133 radeon_bo_fini(rdev);
2134 radeon_atombios_fini(rdev);
2135 kfree(rdev->bios);
2136 rdev->bios = NULL;
2137 radeon_dummy_page_fini(rdev);
2138 }
2139
2140
2141 /*
2142 * CS stuff
2143 */
2144 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2145 {
2146 /* FIXME: implement */
2147 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2148 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2149 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2150 radeon_ring_write(rdev, ib->length_dw);
2151 }
2152
2153 int r600_ib_test(struct radeon_device *rdev)
2154 {
2155 struct radeon_ib *ib;
2156 uint32_t scratch;
2157 uint32_t tmp = 0;
2158 unsigned i;
2159 int r;
2160
2161 r = radeon_scratch_get(rdev, &scratch);
2162 if (r) {
2163 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2164 return r;
2165 }
2166 WREG32(scratch, 0xCAFEDEAD);
2167 r = radeon_ib_get(rdev, &ib);
2168 if (r) {
2169 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2170 return r;
2171 }
2172 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2173 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2174 ib->ptr[2] = 0xDEADBEEF;
2175 ib->ptr[3] = PACKET2(0);
2176 ib->ptr[4] = PACKET2(0);
2177 ib->ptr[5] = PACKET2(0);
2178 ib->ptr[6] = PACKET2(0);
2179 ib->ptr[7] = PACKET2(0);
2180 ib->ptr[8] = PACKET2(0);
2181 ib->ptr[9] = PACKET2(0);
2182 ib->ptr[10] = PACKET2(0);
2183 ib->ptr[11] = PACKET2(0);
2184 ib->ptr[12] = PACKET2(0);
2185 ib->ptr[13] = PACKET2(0);
2186 ib->ptr[14] = PACKET2(0);
2187 ib->ptr[15] = PACKET2(0);
2188 ib->length_dw = 16;
2189 r = radeon_ib_schedule(rdev, ib);
2190 if (r) {
2191 radeon_scratch_free(rdev, scratch);
2192 radeon_ib_free(rdev, &ib);
2193 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2194 return r;
2195 }
2196 r = radeon_fence_wait(ib->fence, false);
2197 if (r) {
2198 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2199 return r;
2200 }
2201 for (i = 0; i < rdev->usec_timeout; i++) {
2202 tmp = RREG32(scratch);
2203 if (tmp == 0xDEADBEEF)
2204 break;
2205 DRM_UDELAY(1);
2206 }
2207 if (i < rdev->usec_timeout) {
2208 DRM_INFO("ib test succeeded in %u usecs\n", i);
2209 } else {
2210 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2211 scratch, tmp);
2212 r = -EINVAL;
2213 }
2214 radeon_scratch_free(rdev, scratch);
2215 radeon_ib_free(rdev, &ib);
2216 return r;
2217 }
2218
2219 /*
2220 * Interrupts
2221 *
2222 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2223 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2224 * writing to the ring and the GPU consuming, the GPU writes to the ring
2225 * and host consumes. As the host irq handler processes interrupts, it
2226 * increments the rptr. When the rptr catches up with the wptr, all the
2227 * current interrupts have been processed.
2228 */
2229
2230 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2231 {
2232 u32 rb_bufsz;
2233
2234 /* Align ring size */
2235 rb_bufsz = drm_order(ring_size / 4);
2236 ring_size = (1 << rb_bufsz) * 4;
2237 rdev->ih.ring_size = ring_size;
2238 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2239 rdev->ih.rptr = 0;
2240 }
2241
2242 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2243 {
2244 int r;
2245
2246 /* Allocate ring buffer */
2247 if (rdev->ih.ring_obj == NULL) {
2248 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2249 true,
2250 RADEON_GEM_DOMAIN_GTT,
2251 &rdev->ih.ring_obj);
2252 if (r) {
2253 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2254 return r;
2255 }
2256 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2257 if (unlikely(r != 0))
2258 return r;
2259 r = radeon_bo_pin(rdev->ih.ring_obj,
2260 RADEON_GEM_DOMAIN_GTT,
2261 &rdev->ih.gpu_addr);
2262 if (r) {
2263 radeon_bo_unreserve(rdev->ih.ring_obj);
2264 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2265 return r;
2266 }
2267 r = radeon_bo_kmap(rdev->ih.ring_obj,
2268 (void **)&rdev->ih.ring);
2269 radeon_bo_unreserve(rdev->ih.ring_obj);
2270 if (r) {
2271 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2272 return r;
2273 }
2274 }
2275 return 0;
2276 }
2277
2278 static void r600_ih_ring_fini(struct radeon_device *rdev)
2279 {
2280 int r;
2281 if (rdev->ih.ring_obj) {
2282 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2283 if (likely(r == 0)) {
2284 radeon_bo_kunmap(rdev->ih.ring_obj);
2285 radeon_bo_unpin(rdev->ih.ring_obj);
2286 radeon_bo_unreserve(rdev->ih.ring_obj);
2287 }
2288 radeon_bo_unref(&rdev->ih.ring_obj);
2289 rdev->ih.ring = NULL;
2290 rdev->ih.ring_obj = NULL;
2291 }
2292 }
2293
2294 static void r600_rlc_stop(struct radeon_device *rdev)
2295 {
2296
2297 if (rdev->family >= CHIP_RV770) {
2298 /* r7xx asics need to soft reset RLC before halting */
2299 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2300 RREG32(SRBM_SOFT_RESET);
2301 udelay(15000);
2302 WREG32(SRBM_SOFT_RESET, 0);
2303 RREG32(SRBM_SOFT_RESET);
2304 }
2305
2306 WREG32(RLC_CNTL, 0);
2307 }
2308
2309 static void r600_rlc_start(struct radeon_device *rdev)
2310 {
2311 WREG32(RLC_CNTL, RLC_ENABLE);
2312 }
2313
2314 static int r600_rlc_init(struct radeon_device *rdev)
2315 {
2316 u32 i;
2317 const __be32 *fw_data;
2318
2319 if (!rdev->rlc_fw)
2320 return -EINVAL;
2321
2322 r600_rlc_stop(rdev);
2323
2324 WREG32(RLC_HB_BASE, 0);
2325 WREG32(RLC_HB_CNTL, 0);
2326 WREG32(RLC_HB_RPTR, 0);
2327 WREG32(RLC_HB_WPTR, 0);
2328 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2329 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2330 WREG32(RLC_MC_CNTL, 0);
2331 WREG32(RLC_UCODE_CNTL, 0);
2332
2333 fw_data = (const __be32 *)rdev->rlc_fw->data;
2334 if (rdev->family >= CHIP_RV770) {
2335 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2336 WREG32(RLC_UCODE_ADDR, i);
2337 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2338 }
2339 } else {
2340 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2341 WREG32(RLC_UCODE_ADDR, i);
2342 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2343 }
2344 }
2345 WREG32(RLC_UCODE_ADDR, 0);
2346
2347 r600_rlc_start(rdev);
2348
2349 return 0;
2350 }
2351
2352 static void r600_enable_interrupts(struct radeon_device *rdev)
2353 {
2354 u32 ih_cntl = RREG32(IH_CNTL);
2355 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2356
2357 ih_cntl |= ENABLE_INTR;
2358 ih_rb_cntl |= IH_RB_ENABLE;
2359 WREG32(IH_CNTL, ih_cntl);
2360 WREG32(IH_RB_CNTL, ih_rb_cntl);
2361 rdev->ih.enabled = true;
2362 }
2363
2364 static void r600_disable_interrupts(struct radeon_device *rdev)
2365 {
2366 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2367 u32 ih_cntl = RREG32(IH_CNTL);
2368
2369 ih_rb_cntl &= ~IH_RB_ENABLE;
2370 ih_cntl &= ~ENABLE_INTR;
2371 WREG32(IH_RB_CNTL, ih_rb_cntl);
2372 WREG32(IH_CNTL, ih_cntl);
2373 /* set rptr, wptr to 0 */
2374 WREG32(IH_RB_RPTR, 0);
2375 WREG32(IH_RB_WPTR, 0);
2376 rdev->ih.enabled = false;
2377 rdev->ih.wptr = 0;
2378 rdev->ih.rptr = 0;
2379 }
2380
2381 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2382 {
2383 u32 tmp;
2384
2385 WREG32(CP_INT_CNTL, 0);
2386 WREG32(GRBM_INT_CNTL, 0);
2387 WREG32(DxMODE_INT_MASK, 0);
2388 if (ASIC_IS_DCE3(rdev)) {
2389 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2390 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2391 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2392 WREG32(DC_HPD1_INT_CONTROL, tmp);
2393 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2394 WREG32(DC_HPD2_INT_CONTROL, tmp);
2395 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2396 WREG32(DC_HPD3_INT_CONTROL, tmp);
2397 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2398 WREG32(DC_HPD4_INT_CONTROL, tmp);
2399 if (ASIC_IS_DCE32(rdev)) {
2400 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2401 WREG32(DC_HPD5_INT_CONTROL, 0);
2402 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2403 WREG32(DC_HPD6_INT_CONTROL, 0);
2404 }
2405 } else {
2406 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2407 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2408 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2409 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2410 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2411 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2412 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2413 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2414 }
2415 }
2416
2417 int r600_irq_init(struct radeon_device *rdev)
2418 {
2419 int ret = 0;
2420 int rb_bufsz;
2421 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2422
2423 /* allocate ring */
2424 ret = r600_ih_ring_alloc(rdev);
2425 if (ret)
2426 return ret;
2427
2428 /* disable irqs */
2429 r600_disable_interrupts(rdev);
2430
2431 /* init rlc */
2432 ret = r600_rlc_init(rdev);
2433 if (ret) {
2434 r600_ih_ring_fini(rdev);
2435 return ret;
2436 }
2437
2438 /* setup interrupt control */
2439 /* set dummy read address to ring address */
2440 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2441 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2442 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2443 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2444 */
2445 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2446 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2447 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2448 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2449
2450 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2451 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2452
2453 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2454 IH_WPTR_OVERFLOW_CLEAR |
2455 (rb_bufsz << 1));
2456 /* WPTR writeback, not yet */
2457 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2458 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2459 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2460
2461 WREG32(IH_RB_CNTL, ih_rb_cntl);
2462
2463 /* set rptr, wptr to 0 */
2464 WREG32(IH_RB_RPTR, 0);
2465 WREG32(IH_RB_WPTR, 0);
2466
2467 /* Default settings for IH_CNTL (disabled at first) */
2468 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2469 /* RPTR_REARM only works if msi's are enabled */
2470 if (rdev->msi_enabled)
2471 ih_cntl |= RPTR_REARM;
2472
2473 #ifdef __BIG_ENDIAN
2474 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2475 #endif
2476 WREG32(IH_CNTL, ih_cntl);
2477
2478 /* force the active interrupt state to all disabled */
2479 r600_disable_interrupt_state(rdev);
2480
2481 /* enable irqs */
2482 r600_enable_interrupts(rdev);
2483
2484 return ret;
2485 }
2486
2487 void r600_irq_suspend(struct radeon_device *rdev)
2488 {
2489 r600_disable_interrupts(rdev);
2490 r600_rlc_stop(rdev);
2491 }
2492
2493 void r600_irq_fini(struct radeon_device *rdev)
2494 {
2495 r600_irq_suspend(rdev);
2496 r600_ih_ring_fini(rdev);
2497 }
2498
2499 int r600_irq_set(struct radeon_device *rdev)
2500 {
2501 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2502 u32 mode_int = 0;
2503 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2504
2505 if (!rdev->irq.installed) {
2506 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2507 return -EINVAL;
2508 }
2509 /* don't enable anything if the ih is disabled */
2510 if (!rdev->ih.enabled) {
2511 r600_disable_interrupts(rdev);
2512 /* force the active interrupt state to all disabled */
2513 r600_disable_interrupt_state(rdev);
2514 return 0;
2515 }
2516
2517 if (ASIC_IS_DCE3(rdev)) {
2518 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2519 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2520 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2521 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2522 if (ASIC_IS_DCE32(rdev)) {
2523 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2524 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2525 }
2526 } else {
2527 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2528 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2529 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2530 }
2531
2532 if (rdev->irq.sw_int) {
2533 DRM_DEBUG("r600_irq_set: sw int\n");
2534 cp_int_cntl |= RB_INT_ENABLE;
2535 }
2536 if (rdev->irq.crtc_vblank_int[0]) {
2537 DRM_DEBUG("r600_irq_set: vblank 0\n");
2538 mode_int |= D1MODE_VBLANK_INT_MASK;
2539 }
2540 if (rdev->irq.crtc_vblank_int[1]) {
2541 DRM_DEBUG("r600_irq_set: vblank 1\n");
2542 mode_int |= D2MODE_VBLANK_INT_MASK;
2543 }
2544 if (rdev->irq.hpd[0]) {
2545 DRM_DEBUG("r600_irq_set: hpd 1\n");
2546 hpd1 |= DC_HPDx_INT_EN;
2547 }
2548 if (rdev->irq.hpd[1]) {
2549 DRM_DEBUG("r600_irq_set: hpd 2\n");
2550 hpd2 |= DC_HPDx_INT_EN;
2551 }
2552 if (rdev->irq.hpd[2]) {
2553 DRM_DEBUG("r600_irq_set: hpd 3\n");
2554 hpd3 |= DC_HPDx_INT_EN;
2555 }
2556 if (rdev->irq.hpd[3]) {
2557 DRM_DEBUG("r600_irq_set: hpd 4\n");
2558 hpd4 |= DC_HPDx_INT_EN;
2559 }
2560 if (rdev->irq.hpd[4]) {
2561 DRM_DEBUG("r600_irq_set: hpd 5\n");
2562 hpd5 |= DC_HPDx_INT_EN;
2563 }
2564 if (rdev->irq.hpd[5]) {
2565 DRM_DEBUG("r600_irq_set: hpd 6\n");
2566 hpd6 |= DC_HPDx_INT_EN;
2567 }
2568
2569 WREG32(CP_INT_CNTL, cp_int_cntl);
2570 WREG32(DxMODE_INT_MASK, mode_int);
2571 if (ASIC_IS_DCE3(rdev)) {
2572 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2573 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2574 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2575 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2576 if (ASIC_IS_DCE32(rdev)) {
2577 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2578 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2579 }
2580 } else {
2581 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2582 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2583 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2584 }
2585
2586 return 0;
2587 }
2588
2589 static inline void r600_irq_ack(struct radeon_device *rdev,
2590 u32 *disp_int,
2591 u32 *disp_int_cont,
2592 u32 *disp_int_cont2)
2593 {
2594 u32 tmp;
2595
2596 if (ASIC_IS_DCE3(rdev)) {
2597 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2598 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2599 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2600 } else {
2601 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2602 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2603 *disp_int_cont2 = 0;
2604 }
2605
2606 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2607 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2608 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2609 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2610 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2611 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2612 if (*disp_int & LB_D2_VLINE_INTERRUPT)
2613 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2614 if (*disp_int & DC_HPD1_INTERRUPT) {
2615 if (ASIC_IS_DCE3(rdev)) {
2616 tmp = RREG32(DC_HPD1_INT_CONTROL);
2617 tmp |= DC_HPDx_INT_ACK;
2618 WREG32(DC_HPD1_INT_CONTROL, tmp);
2619 } else {
2620 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2621 tmp |= DC_HPDx_INT_ACK;
2622 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2623 }
2624 }
2625 if (*disp_int & DC_HPD2_INTERRUPT) {
2626 if (ASIC_IS_DCE3(rdev)) {
2627 tmp = RREG32(DC_HPD2_INT_CONTROL);
2628 tmp |= DC_HPDx_INT_ACK;
2629 WREG32(DC_HPD2_INT_CONTROL, tmp);
2630 } else {
2631 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2632 tmp |= DC_HPDx_INT_ACK;
2633 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2634 }
2635 }
2636 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2637 if (ASIC_IS_DCE3(rdev)) {
2638 tmp = RREG32(DC_HPD3_INT_CONTROL);
2639 tmp |= DC_HPDx_INT_ACK;
2640 WREG32(DC_HPD3_INT_CONTROL, tmp);
2641 } else {
2642 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2643 tmp |= DC_HPDx_INT_ACK;
2644 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2645 }
2646 }
2647 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2648 tmp = RREG32(DC_HPD4_INT_CONTROL);
2649 tmp |= DC_HPDx_INT_ACK;
2650 WREG32(DC_HPD4_INT_CONTROL, tmp);
2651 }
2652 if (ASIC_IS_DCE32(rdev)) {
2653 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2654 tmp = RREG32(DC_HPD5_INT_CONTROL);
2655 tmp |= DC_HPDx_INT_ACK;
2656 WREG32(DC_HPD5_INT_CONTROL, tmp);
2657 }
2658 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2659 tmp = RREG32(DC_HPD5_INT_CONTROL);
2660 tmp |= DC_HPDx_INT_ACK;
2661 WREG32(DC_HPD6_INT_CONTROL, tmp);
2662 }
2663 }
2664 }
2665
2666 void r600_irq_disable(struct radeon_device *rdev)
2667 {
2668 u32 disp_int, disp_int_cont, disp_int_cont2;
2669
2670 r600_disable_interrupts(rdev);
2671 /* Wait and acknowledge irq */
2672 mdelay(1);
2673 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2674 r600_disable_interrupt_state(rdev);
2675 }
2676
2677 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2678 {
2679 u32 wptr, tmp;
2680
2681 /* XXX use writeback */
2682 wptr = RREG32(IH_RB_WPTR);
2683
2684 if (wptr & RB_OVERFLOW) {
2685 /* When a ring buffer overflow happen start parsing interrupt
2686 * from the last not overwritten vector (wptr + 16). Hopefully
2687 * this should allow us to catchup.
2688 */
2689 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2690 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2691 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2692 tmp = RREG32(IH_RB_CNTL);
2693 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2694 WREG32(IH_RB_CNTL, tmp);
2695 }
2696 return (wptr & rdev->ih.ptr_mask);
2697 }
2698
2699 /* r600 IV Ring
2700 * Each IV ring entry is 128 bits:
2701 * [7:0] - interrupt source id
2702 * [31:8] - reserved
2703 * [59:32] - interrupt source data
2704 * [127:60] - reserved
2705 *
2706 * The basic interrupt vector entries
2707 * are decoded as follows:
2708 * src_id src_data description
2709 * 1 0 D1 Vblank
2710 * 1 1 D1 Vline
2711 * 5 0 D2 Vblank
2712 * 5 1 D2 Vline
2713 * 19 0 FP Hot plug detection A
2714 * 19 1 FP Hot plug detection B
2715 * 19 2 DAC A auto-detection
2716 * 19 3 DAC B auto-detection
2717 * 176 - CP_INT RB
2718 * 177 - CP_INT IB1
2719 * 178 - CP_INT IB2
2720 * 181 - EOP Interrupt
2721 * 233 - GUI Idle
2722 *
2723 * Note, these are based on r600 and may need to be
2724 * adjusted or added to on newer asics
2725 */
2726
2727 int r600_irq_process(struct radeon_device *rdev)
2728 {
2729 u32 wptr = r600_get_ih_wptr(rdev);
2730 u32 rptr = rdev->ih.rptr;
2731 u32 src_id, src_data;
2732 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2733 unsigned long flags;
2734 bool queue_hotplug = false;
2735
2736 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2737 if (!rdev->ih.enabled)
2738 return IRQ_NONE;
2739
2740 spin_lock_irqsave(&rdev->ih.lock, flags);
2741
2742 if (rptr == wptr) {
2743 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2744 return IRQ_NONE;
2745 }
2746 if (rdev->shutdown) {
2747 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2748 return IRQ_NONE;
2749 }
2750
2751 restart_ih:
2752 /* display interrupts */
2753 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2754
2755 rdev->ih.wptr = wptr;
2756 while (rptr != wptr) {
2757 /* wptr/rptr are in bytes! */
2758 ring_index = rptr / 4;
2759 src_id = rdev->ih.ring[ring_index] & 0xff;
2760 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2761
2762 switch (src_id) {
2763 case 1: /* D1 vblank/vline */
2764 switch (src_data) {
2765 case 0: /* D1 vblank */
2766 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2767 drm_handle_vblank(rdev->ddev, 0);
2768 wake_up(&rdev->irq.vblank_queue);
2769 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2770 DRM_DEBUG("IH: D1 vblank\n");
2771 }
2772 break;
2773 case 1: /* D1 vline */
2774 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2775 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2776 DRM_DEBUG("IH: D1 vline\n");
2777 }
2778 break;
2779 default:
2780 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2781 break;
2782 }
2783 break;
2784 case 5: /* D2 vblank/vline */
2785 switch (src_data) {
2786 case 0: /* D2 vblank */
2787 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2788 drm_handle_vblank(rdev->ddev, 1);
2789 wake_up(&rdev->irq.vblank_queue);
2790 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2791 DRM_DEBUG("IH: D2 vblank\n");
2792 }
2793 break;
2794 case 1: /* D1 vline */
2795 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2796 disp_int &= ~LB_D2_VLINE_INTERRUPT;
2797 DRM_DEBUG("IH: D2 vline\n");
2798 }
2799 break;
2800 default:
2801 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2802 break;
2803 }
2804 break;
2805 case 19: /* HPD/DAC hotplug */
2806 switch (src_data) {
2807 case 0:
2808 if (disp_int & DC_HPD1_INTERRUPT) {
2809 disp_int &= ~DC_HPD1_INTERRUPT;
2810 queue_hotplug = true;
2811 DRM_DEBUG("IH: HPD1\n");
2812 }
2813 break;
2814 case 1:
2815 if (disp_int & DC_HPD2_INTERRUPT) {
2816 disp_int &= ~DC_HPD2_INTERRUPT;
2817 queue_hotplug = true;
2818 DRM_DEBUG("IH: HPD2\n");
2819 }
2820 break;
2821 case 4:
2822 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2823 disp_int_cont &= ~DC_HPD3_INTERRUPT;
2824 queue_hotplug = true;
2825 DRM_DEBUG("IH: HPD3\n");
2826 }
2827 break;
2828 case 5:
2829 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2830 disp_int_cont &= ~DC_HPD4_INTERRUPT;
2831 queue_hotplug = true;
2832 DRM_DEBUG("IH: HPD4\n");
2833 }
2834 break;
2835 case 10:
2836 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2837 disp_int_cont &= ~DC_HPD5_INTERRUPT;
2838 queue_hotplug = true;
2839 DRM_DEBUG("IH: HPD5\n");
2840 }
2841 break;
2842 case 12:
2843 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2844 disp_int_cont &= ~DC_HPD6_INTERRUPT;
2845 queue_hotplug = true;
2846 DRM_DEBUG("IH: HPD6\n");
2847 }
2848 break;
2849 default:
2850 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2851 break;
2852 }
2853 break;
2854 case 176: /* CP_INT in ring buffer */
2855 case 177: /* CP_INT in IB1 */
2856 case 178: /* CP_INT in IB2 */
2857 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2858 radeon_fence_process(rdev);
2859 break;
2860 case 181: /* CP EOP event */
2861 DRM_DEBUG("IH: CP EOP\n");
2862 break;
2863 default:
2864 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2865 break;
2866 }
2867
2868 /* wptr/rptr are in bytes! */
2869 rptr += 16;
2870 rptr &= rdev->ih.ptr_mask;
2871 }
2872 /* make sure wptr hasn't changed while processing */
2873 wptr = r600_get_ih_wptr(rdev);
2874 if (wptr != rdev->ih.wptr)
2875 goto restart_ih;
2876 if (queue_hotplug)
2877 queue_work(rdev->wq, &rdev->hotplug_work);
2878 rdev->ih.rptr = rptr;
2879 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2880 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2881 return IRQ_HANDLED;
2882 }
2883
2884 /*
2885 * Debugfs info
2886 */
2887 #if defined(CONFIG_DEBUG_FS)
2888
2889 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2890 {
2891 struct drm_info_node *node = (struct drm_info_node *) m->private;
2892 struct drm_device *dev = node->minor->dev;
2893 struct radeon_device *rdev = dev->dev_private;
2894 unsigned count, i, j;
2895
2896 radeon_ring_free_size(rdev);
2897 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2898 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2899 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2900 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2901 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2902 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2903 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2904 seq_printf(m, "%u dwords in ring\n", count);
2905 i = rdev->cp.rptr;
2906 for (j = 0; j <= count; j++) {
2907 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2908 i = (i + 1) & rdev->cp.ptr_mask;
2909 }
2910 return 0;
2911 }
2912
2913 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2914 {
2915 struct drm_info_node *node = (struct drm_info_node *) m->private;
2916 struct drm_device *dev = node->minor->dev;
2917 struct radeon_device *rdev = dev->dev_private;
2918
2919 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2920 DREG32_SYS(m, rdev, VM_L2_STATUS);
2921 return 0;
2922 }
2923
2924 static struct drm_info_list r600_mc_info_list[] = {
2925 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2926 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2927 };
2928 #endif
2929
2930 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2931 {
2932 #if defined(CONFIG_DEBUG_FS)
2933 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2934 #else
2935 return 0;
2936 #endif
2937 }
2938
2939 /**
2940 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2941 * rdev: radeon device structure
2942 * bo: buffer object struct which userspace is waiting for idle
2943 *
2944 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2945 * through ring buffer, this leads to corruption in rendering, see
2946 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2947 * directly perform HDP flush by writing register through MMIO.
2948 */
2949 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2950 {
2951 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2952 }
kernel source for telekom puls (alcatel/mediatek)