2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
31 #include "radeon_reg.h"
33 #include "radeon_drm.h"
34 #include "r100_track.h"
37 #include "r300_reg_safe.h"
39 /* r300,r350,rv350,rv370,rv380 depends on : */
40 void r100_hdp_reset(struct radeon_device
*rdev
);
41 int r100_cp_reset(struct radeon_device
*rdev
);
42 int r100_rb2d_reset(struct radeon_device
*rdev
);
43 int r100_cp_init(struct radeon_device
*rdev
, unsigned ring_size
);
44 int r100_pci_gart_enable(struct radeon_device
*rdev
);
45 void r100_mc_setup(struct radeon_device
*rdev
);
46 void r100_mc_disable_clients(struct radeon_device
*rdev
);
47 int r100_gui_wait_for_idle(struct radeon_device
*rdev
);
48 int r100_cs_packet_parse(struct radeon_cs_parser
*p
,
49 struct radeon_cs_packet
*pkt
,
51 int r100_cs_packet_parse_vline(struct radeon_cs_parser
*p
);
52 int r100_cs_parse_packet0(struct radeon_cs_parser
*p
,
53 struct radeon_cs_packet
*pkt
,
54 const unsigned *auth
, unsigned n
,
55 radeon_packet0_check_t check
);
56 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser
*p
,
57 struct radeon_cs_packet
*pkt
,
58 struct radeon_object
*robj
);
60 /* This files gather functions specifics to:
61 * r300,r350,rv350,rv370,rv380
63 * Some of these functions might be used by newer ASICs.
65 void r300_gpu_init(struct radeon_device
*rdev
);
66 int r300_mc_wait_for_idle(struct radeon_device
*rdev
);
67 int rv370_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
);
71 * rv370,rv380 PCIE GART
73 void rv370_pcie_gart_tlb_flush(struct radeon_device
*rdev
)
78 /* Workaround HW bug do flush 2 times */
79 for (i
= 0; i
< 2; i
++) {
80 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
81 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
| RADEON_PCIE_TX_GART_INVALIDATE_TLB
);
82 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
83 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
);
88 int rv370_pcie_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
90 void __iomem
*ptr
= (void *)rdev
->gart
.table
.vram
.ptr
;
92 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
95 addr
= (lower_32_bits(addr
) >> 8) |
96 ((upper_32_bits(addr
) & 0xff) << 24) |
98 /* on x86 we want this to be CPU endian, on powerpc
99 * on powerpc without HW swappers, it'll get swapped on way
100 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
101 writel(addr
, ((void __iomem
*)ptr
) + (i
* 4));
105 int rv370_pcie_gart_init(struct radeon_device
*rdev
)
109 if (rdev
->gart
.table
.vram
.robj
) {
110 WARN(1, "RV370 PCIE GART already initialized.\n");
113 /* Initialize common gart structure */
114 r
= radeon_gart_init(rdev
);
117 r
= rv370_debugfs_pcie_gart_info_init(rdev
);
119 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
120 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 4;
121 rdev
->asic
->gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
;
122 rdev
->asic
->gart_set_page
= &rv370_pcie_gart_set_page
;
123 return radeon_gart_table_vram_alloc(rdev
);
126 int rv370_pcie_gart_enable(struct radeon_device
*rdev
)
132 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
133 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
136 r
= radeon_gart_table_vram_pin(rdev
);
139 /* discard memory request outside of configured range */
140 tmp
= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD
;
141 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
);
142 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO
, rdev
->mc
.gtt_location
);
143 tmp
= rdev
->mc
.gtt_location
+ rdev
->mc
.gtt_size
- 4096;
144 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO
, tmp
);
145 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI
, 0);
146 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI
, 0);
147 table_addr
= rdev
->gart
.table_addr
;
148 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE
, table_addr
);
149 /* FIXME: setup default page */
150 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO
, rdev
->mc
.vram_location
);
151 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI
, 0);
153 WREG32_PCIE(0x18, 0);
154 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
155 tmp
|= RADEON_PCIE_TX_GART_EN
;
156 tmp
|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD
;
157 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
);
158 rv370_pcie_gart_tlb_flush(rdev
);
159 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
160 (unsigned)(rdev
->mc
.gtt_size
>> 20), table_addr
);
161 rdev
->gart
.ready
= true;
165 void rv370_pcie_gart_disable(struct radeon_device
*rdev
)
169 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
170 tmp
|= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD
;
171 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
, tmp
& ~RADEON_PCIE_TX_GART_EN
);
172 if (rdev
->gart
.table
.vram
.robj
) {
173 radeon_object_kunmap(rdev
->gart
.table
.vram
.robj
);
174 radeon_object_unpin(rdev
->gart
.table
.vram
.robj
);
178 void rv370_pcie_gart_fini(struct radeon_device
*rdev
)
180 rv370_pcie_gart_disable(rdev
);
181 radeon_gart_table_vram_free(rdev
);
182 radeon_gart_fini(rdev
);
188 int r300_mc_init(struct radeon_device
*rdev
)
192 if (r100_debugfs_rbbm_init(rdev
)) {
193 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
197 r100_pci_gart_disable(rdev
);
198 if (rdev
->flags
& RADEON_IS_PCIE
) {
199 rv370_pcie_gart_disable(rdev
);
202 /* Setup GPU memory space */
203 rdev
->mc
.vram_location
= 0xFFFFFFFFUL
;
204 rdev
->mc
.gtt_location
= 0xFFFFFFFFUL
;
205 if (rdev
->flags
& RADEON_IS_AGP
) {
206 r
= radeon_agp_init(rdev
);
208 printk(KERN_WARNING
"[drm] Disabling AGP\n");
209 rdev
->flags
&= ~RADEON_IS_AGP
;
210 rdev
->mc
.gtt_size
= radeon_gart_size
* 1024 * 1024;
212 rdev
->mc
.gtt_location
= rdev
->mc
.agp_base
;
215 r
= radeon_mc_setup(rdev
);
220 /* Program GPU memory space */
221 r100_mc_disable_clients(rdev
);
222 if (r300_mc_wait_for_idle(rdev
)) {
223 printk(KERN_WARNING
"Failed to wait MC idle while "
224 "programming pipes. Bad things might happen.\n");
230 void r300_mc_fini(struct radeon_device
*rdev
)
238 void r300_fence_ring_emit(struct radeon_device
*rdev
,
239 struct radeon_fence
*fence
)
241 /* Who ever call radeon_fence_emit should call ring_lock and ask
242 * for enough space (today caller are ib schedule and buffer move) */
243 /* Write SC register so SC & US assert idle */
244 radeon_ring_write(rdev
, PACKET0(0x43E0, 0));
245 radeon_ring_write(rdev
, 0);
246 radeon_ring_write(rdev
, PACKET0(0x43E4, 0));
247 radeon_ring_write(rdev
, 0);
249 radeon_ring_write(rdev
, PACKET0(0x4E4C, 0));
250 radeon_ring_write(rdev
, (2 << 0));
251 radeon_ring_write(rdev
, PACKET0(0x4F18, 0));
252 radeon_ring_write(rdev
, (1 << 0));
253 /* Wait until IDLE & CLEAN */
254 radeon_ring_write(rdev
, PACKET0(0x1720, 0));
255 radeon_ring_write(rdev
, (1 << 17) | (1 << 16) | (1 << 9));
256 /* Emit fence sequence & fire IRQ */
257 radeon_ring_write(rdev
, PACKET0(rdev
->fence_drv
.scratch_reg
, 0));
258 radeon_ring_write(rdev
, fence
->seq
);
259 radeon_ring_write(rdev
, PACKET0(RADEON_GEN_INT_STATUS
, 0));
260 radeon_ring_write(rdev
, RADEON_SW_INT_FIRE
);
265 * Global GPU functions
267 int r300_copy_dma(struct radeon_device
*rdev
,
271 struct radeon_fence
*fence
)
278 /* radeon pitch is /64 */
279 size
= num_pages
<< PAGE_SHIFT
;
280 num_loops
= DIV_ROUND_UP(size
, 0x1FFFFF);
281 r
= radeon_ring_lock(rdev
, num_loops
* 4 + 64);
283 DRM_ERROR("radeon: moving bo (%d).\n", r
);
286 /* Must wait for 2D idle & clean before DMA or hangs might happen */
287 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0 ));
288 radeon_ring_write(rdev
, (1 << 16));
289 for (i
= 0; i
< num_loops
; i
++) {
291 if (cur_size
> 0x1FFFFF) {
295 radeon_ring_write(rdev
, PACKET0(0x720, 2));
296 radeon_ring_write(rdev
, src_offset
);
297 radeon_ring_write(rdev
, dst_offset
);
298 radeon_ring_write(rdev
, cur_size
| (1 << 31) | (1 << 30));
299 src_offset
+= cur_size
;
300 dst_offset
+= cur_size
;
302 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
303 radeon_ring_write(rdev
, RADEON_WAIT_DMA_GUI_IDLE
);
305 r
= radeon_fence_emit(rdev
, fence
);
307 radeon_ring_unlock_commit(rdev
);
311 void r300_ring_start(struct radeon_device
*rdev
)
313 unsigned gb_tile_config
;
316 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
317 gb_tile_config
= (R300_ENABLE_TILING
| R300_TILE_SIZE_16
);
318 switch(rdev
->num_gb_pipes
) {
320 gb_tile_config
|= R300_PIPE_COUNT_R300
;
323 gb_tile_config
|= R300_PIPE_COUNT_R420_3P
;
326 gb_tile_config
|= R300_PIPE_COUNT_R420
;
330 gb_tile_config
|= R300_PIPE_COUNT_RV350
;
334 r
= radeon_ring_lock(rdev
, 64);
338 radeon_ring_write(rdev
, PACKET0(RADEON_ISYNC_CNTL
, 0));
339 radeon_ring_write(rdev
,
340 RADEON_ISYNC_ANY2D_IDLE3D
|
341 RADEON_ISYNC_ANY3D_IDLE2D
|
342 RADEON_ISYNC_WAIT_IDLEGUI
|
343 RADEON_ISYNC_CPSCRATCH_IDLEGUI
);
344 radeon_ring_write(rdev
, PACKET0(R300_GB_TILE_CONFIG
, 0));
345 radeon_ring_write(rdev
, gb_tile_config
);
346 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
347 radeon_ring_write(rdev
,
348 RADEON_WAIT_2D_IDLECLEAN
|
349 RADEON_WAIT_3D_IDLECLEAN
);
350 radeon_ring_write(rdev
, PACKET0(0x170C, 0));
351 radeon_ring_write(rdev
, 1 << 31);
352 radeon_ring_write(rdev
, PACKET0(R300_GB_SELECT
, 0));
353 radeon_ring_write(rdev
, 0);
354 radeon_ring_write(rdev
, PACKET0(R300_GB_ENABLE
, 0));
355 radeon_ring_write(rdev
, 0);
356 radeon_ring_write(rdev
, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
357 radeon_ring_write(rdev
, R300_RB3D_DC_FLUSH
| R300_RB3D_DC_FREE
);
358 radeon_ring_write(rdev
, PACKET0(R300_RB3D_ZCACHE_CTLSTAT
, 0));
359 radeon_ring_write(rdev
, R300_ZC_FLUSH
| R300_ZC_FREE
);
360 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
361 radeon_ring_write(rdev
,
362 RADEON_WAIT_2D_IDLECLEAN
|
363 RADEON_WAIT_3D_IDLECLEAN
);
364 radeon_ring_write(rdev
, PACKET0(R300_GB_AA_CONFIG
, 0));
365 radeon_ring_write(rdev
, 0);
366 radeon_ring_write(rdev
, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT
, 0));
367 radeon_ring_write(rdev
, R300_RB3D_DC_FLUSH
| R300_RB3D_DC_FREE
);
368 radeon_ring_write(rdev
, PACKET0(R300_RB3D_ZCACHE_CTLSTAT
, 0));
369 radeon_ring_write(rdev
, R300_ZC_FLUSH
| R300_ZC_FREE
);
370 radeon_ring_write(rdev
, PACKET0(R300_GB_MSPOS0
, 0));
371 radeon_ring_write(rdev
,
372 ((6 << R300_MS_X0_SHIFT
) |
373 (6 << R300_MS_Y0_SHIFT
) |
374 (6 << R300_MS_X1_SHIFT
) |
375 (6 << R300_MS_Y1_SHIFT
) |
376 (6 << R300_MS_X2_SHIFT
) |
377 (6 << R300_MS_Y2_SHIFT
) |
378 (6 << R300_MSBD0_Y_SHIFT
) |
379 (6 << R300_MSBD0_X_SHIFT
)));
380 radeon_ring_write(rdev
, PACKET0(R300_GB_MSPOS1
, 0));
381 radeon_ring_write(rdev
,
382 ((6 << R300_MS_X3_SHIFT
) |
383 (6 << R300_MS_Y3_SHIFT
) |
384 (6 << R300_MS_X4_SHIFT
) |
385 (6 << R300_MS_Y4_SHIFT
) |
386 (6 << R300_MS_X5_SHIFT
) |
387 (6 << R300_MS_Y5_SHIFT
) |
388 (6 << R300_MSBD1_SHIFT
)));
389 radeon_ring_write(rdev
, PACKET0(R300_GA_ENHANCE
, 0));
390 radeon_ring_write(rdev
, R300_GA_DEADLOCK_CNTL
| R300_GA_FASTSYNC_CNTL
);
391 radeon_ring_write(rdev
, PACKET0(R300_GA_POLY_MODE
, 0));
392 radeon_ring_write(rdev
,
393 R300_FRONT_PTYPE_TRIANGE
| R300_BACK_PTYPE_TRIANGE
);
394 radeon_ring_write(rdev
, PACKET0(R300_GA_ROUND_MODE
, 0));
395 radeon_ring_write(rdev
,
396 R300_GEOMETRY_ROUND_NEAREST
|
397 R300_COLOR_ROUND_NEAREST
);
398 radeon_ring_unlock_commit(rdev
);
401 void r300_errata(struct radeon_device
*rdev
)
403 rdev
->pll_errata
= 0;
405 if (rdev
->family
== CHIP_R300
&&
406 (RREG32(RADEON_CONFIG_CNTL
) & RADEON_CFG_ATI_REV_ID_MASK
) == RADEON_CFG_ATI_REV_A11
) {
407 rdev
->pll_errata
|= CHIP_ERRATA_R300_CG
;
411 int r300_mc_wait_for_idle(struct radeon_device
*rdev
)
416 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
418 tmp
= RREG32(0x0150);
419 if (tmp
& (1 << 4)) {
427 void r300_gpu_init(struct radeon_device
*rdev
)
429 uint32_t gb_tile_config
, tmp
;
431 r100_hdp_reset(rdev
);
432 /* FIXME: rv380 one pipes ? */
433 if ((rdev
->family
== CHIP_R300
) || (rdev
->family
== CHIP_R350
)) {
435 rdev
->num_gb_pipes
= 2;
437 /* rv350,rv370,rv380 */
438 rdev
->num_gb_pipes
= 1;
440 rdev
->num_z_pipes
= 1;
441 gb_tile_config
= (R300_ENABLE_TILING
| R300_TILE_SIZE_16
);
442 switch (rdev
->num_gb_pipes
) {
444 gb_tile_config
|= R300_PIPE_COUNT_R300
;
447 gb_tile_config
|= R300_PIPE_COUNT_R420_3P
;
450 gb_tile_config
|= R300_PIPE_COUNT_R420
;
454 gb_tile_config
|= R300_PIPE_COUNT_RV350
;
457 WREG32(R300_GB_TILE_CONFIG
, gb_tile_config
);
459 if (r100_gui_wait_for_idle(rdev
)) {
460 printk(KERN_WARNING
"Failed to wait GUI idle while "
461 "programming pipes. Bad things might happen.\n");
464 tmp
= RREG32(0x170C);
465 WREG32(0x170C, tmp
| (1 << 31));
467 WREG32(R300_RB2D_DSTCACHE_MODE
,
468 R300_DC_AUTOFLUSH_ENABLE
|
469 R300_DC_DC_DISABLE_IGNORE_PE
);
471 if (r100_gui_wait_for_idle(rdev
)) {
472 printk(KERN_WARNING
"Failed to wait GUI idle while "
473 "programming pipes. Bad things might happen.\n");
475 if (r300_mc_wait_for_idle(rdev
)) {
476 printk(KERN_WARNING
"Failed to wait MC idle while "
477 "programming pipes. Bad things might happen.\n");
479 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
480 rdev
->num_gb_pipes
, rdev
->num_z_pipes
);
483 int r300_ga_reset(struct radeon_device
*rdev
)
489 reinit_cp
= rdev
->cp
.ready
;
490 rdev
->cp
.ready
= false;
491 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
492 WREG32(RADEON_CP_CSQ_MODE
, 0);
493 WREG32(RADEON_CP_CSQ_CNTL
, 0);
494 WREG32(RADEON_RBBM_SOFT_RESET
, 0x32005);
495 (void)RREG32(RADEON_RBBM_SOFT_RESET
);
497 WREG32(RADEON_RBBM_SOFT_RESET
, 0);
498 /* Wait to prevent race in RBBM_STATUS */
500 tmp
= RREG32(RADEON_RBBM_STATUS
);
501 if (tmp
& ((1 << 20) | (1 << 26))) {
502 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp
);
503 /* GA still busy soft reset it */
504 WREG32(0x429C, 0x200);
505 WREG32(R300_VAP_PVS_STATE_FLUSH_REG
, 0);
510 /* Wait to prevent race in RBBM_STATUS */
512 tmp
= RREG32(RADEON_RBBM_STATUS
);
513 if (!(tmp
& ((1 << 20) | (1 << 26)))) {
517 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
518 tmp
= RREG32(RADEON_RBBM_STATUS
);
519 if (!(tmp
& ((1 << 20) | (1 << 26)))) {
520 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
523 return r100_cp_init(rdev
, rdev
->cp
.ring_size
);
529 tmp
= RREG32(RADEON_RBBM_STATUS
);
530 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp
);
534 int r300_gpu_reset(struct radeon_device
*rdev
)
538 /* reset order likely matter */
539 status
= RREG32(RADEON_RBBM_STATUS
);
541 r100_hdp_reset(rdev
);
543 if (status
& ((1 << 17) | (1 << 18) | (1 << 27))) {
544 r100_rb2d_reset(rdev
);
547 if (status
& ((1 << 20) | (1 << 26))) {
551 status
= RREG32(RADEON_RBBM_STATUS
);
552 if (status
& (1 << 16)) {
555 /* Check if GPU is idle */
556 status
= RREG32(RADEON_RBBM_STATUS
);
557 if (status
& (1 << 31)) {
558 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status
);
561 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status
);
567 * r300,r350,rv350,rv380 VRAM info
569 void r300_vram_info(struct radeon_device
*rdev
)
573 /* DDR for all card after R300 & IGP */
574 rdev
->mc
.vram_is_ddr
= true;
575 tmp
= RREG32(RADEON_MEM_CNTL
);
576 if (tmp
& R300_MEM_NUM_CHANNELS_MASK
) {
577 rdev
->mc
.vram_width
= 128;
579 rdev
->mc
.vram_width
= 64;
582 r100_vram_init_sizes(rdev
);
590 void rv370_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
)
592 uint32_t link_width_cntl
, mask
;
594 if (rdev
->flags
& RADEON_IS_IGP
)
597 if (!(rdev
->flags
& RADEON_IS_PCIE
))
600 /* FIXME wait for idle */
604 mask
= RADEON_PCIE_LC_LINK_WIDTH_X0
;
607 mask
= RADEON_PCIE_LC_LINK_WIDTH_X1
;
610 mask
= RADEON_PCIE_LC_LINK_WIDTH_X2
;
613 mask
= RADEON_PCIE_LC_LINK_WIDTH_X4
;
616 mask
= RADEON_PCIE_LC_LINK_WIDTH_X8
;
619 mask
= RADEON_PCIE_LC_LINK_WIDTH_X12
;
623 mask
= RADEON_PCIE_LC_LINK_WIDTH_X16
;
627 link_width_cntl
= RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
629 if ((link_width_cntl
& RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
) ==
630 (mask
<< RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
))
633 link_width_cntl
&= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK
|
634 RADEON_PCIE_LC_RECONFIG_NOW
|
635 RADEON_PCIE_LC_RECONFIG_LATER
|
636 RADEON_PCIE_LC_SHORT_RECONFIG_EN
);
637 link_width_cntl
|= mask
;
638 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, link_width_cntl
);
639 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
, (link_width_cntl
|
640 RADEON_PCIE_LC_RECONFIG_NOW
));
642 /* wait for lane set to complete */
643 link_width_cntl
= RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
644 while (link_width_cntl
== 0xffffffff)
645 link_width_cntl
= RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL
);
653 #if defined(CONFIG_DEBUG_FS)
654 static int rv370_debugfs_pcie_gart_info(struct seq_file
*m
, void *data
)
656 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
657 struct drm_device
*dev
= node
->minor
->dev
;
658 struct radeon_device
*rdev
= dev
->dev_private
;
661 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL
);
662 seq_printf(m
, "PCIE_TX_GART_CNTL 0x%08x\n", tmp
);
663 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_BASE
);
664 seq_printf(m
, "PCIE_TX_GART_BASE 0x%08x\n", tmp
);
665 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO
);
666 seq_printf(m
, "PCIE_TX_GART_START_LO 0x%08x\n", tmp
);
667 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI
);
668 seq_printf(m
, "PCIE_TX_GART_START_HI 0x%08x\n", tmp
);
669 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO
);
670 seq_printf(m
, "PCIE_TX_GART_END_LO 0x%08x\n", tmp
);
671 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI
);
672 seq_printf(m
, "PCIE_TX_GART_END_HI 0x%08x\n", tmp
);
673 tmp
= RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR
);
674 seq_printf(m
, "PCIE_TX_GART_ERROR 0x%08x\n", tmp
);
678 static struct drm_info_list rv370_pcie_gart_info_list
[] = {
679 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info
, 0, NULL
},
683 int rv370_debugfs_pcie_gart_info_init(struct radeon_device
*rdev
)
685 #if defined(CONFIG_DEBUG_FS)
686 return radeon_debugfs_add_files(rdev
, rv370_pcie_gart_info_list
, 1);
696 static int r300_packet0_check(struct radeon_cs_parser
*p
,
697 struct radeon_cs_packet
*pkt
,
698 unsigned idx
, unsigned reg
)
700 struct radeon_cs_reloc
*reloc
;
701 struct r100_cs_track
*track
;
702 volatile uint32_t *ib
;
703 uint32_t tmp
, tile_flags
= 0;
709 track
= (struct r100_cs_track
*)p
->track
;
710 idx_value
= radeon_get_ib_value(p
, idx
);
713 case AVIVO_D1MODE_VLINE_START_END
:
714 case RADEON_CRTC_GUI_TRIG_VLINE
:
715 r
= r100_cs_packet_parse_vline(p
);
717 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
719 r100_cs_dump_packet(p
, pkt
);
723 case RADEON_DST_PITCH_OFFSET
:
724 case RADEON_SRC_PITCH_OFFSET
:
725 r
= r100_reloc_pitch_offset(p
, pkt
, idx
, reg
);
729 case R300_RB3D_COLOROFFSET0
:
730 case R300_RB3D_COLOROFFSET1
:
731 case R300_RB3D_COLOROFFSET2
:
732 case R300_RB3D_COLOROFFSET3
:
733 i
= (reg
- R300_RB3D_COLOROFFSET0
) >> 2;
734 r
= r100_cs_packet_next_reloc(p
, &reloc
);
736 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
738 r100_cs_dump_packet(p
, pkt
);
741 track
->cb
[i
].robj
= reloc
->robj
;
742 track
->cb
[i
].offset
= idx_value
;
743 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
745 case R300_ZB_DEPTHOFFSET
:
746 r
= r100_cs_packet_next_reloc(p
, &reloc
);
748 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
750 r100_cs_dump_packet(p
, pkt
);
753 track
->zb
.robj
= reloc
->robj
;
754 track
->zb
.offset
= idx_value
;
755 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
757 case R300_TX_OFFSET_0
:
758 case R300_TX_OFFSET_0
+4:
759 case R300_TX_OFFSET_0
+8:
760 case R300_TX_OFFSET_0
+12:
761 case R300_TX_OFFSET_0
+16:
762 case R300_TX_OFFSET_0
+20:
763 case R300_TX_OFFSET_0
+24:
764 case R300_TX_OFFSET_0
+28:
765 case R300_TX_OFFSET_0
+32:
766 case R300_TX_OFFSET_0
+36:
767 case R300_TX_OFFSET_0
+40:
768 case R300_TX_OFFSET_0
+44:
769 case R300_TX_OFFSET_0
+48:
770 case R300_TX_OFFSET_0
+52:
771 case R300_TX_OFFSET_0
+56:
772 case R300_TX_OFFSET_0
+60:
773 i
= (reg
- R300_TX_OFFSET_0
) >> 2;
774 r
= r100_cs_packet_next_reloc(p
, &reloc
);
776 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
778 r100_cs_dump_packet(p
, pkt
);
781 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
782 track
->textures
[i
].robj
= reloc
->robj
;
784 /* Tracked registers */
787 track
->vap_vf_cntl
= idx_value
;
791 track
->vtx_size
= idx_value
& 0x7F;
794 /* VAP_VF_MAX_VTX_INDX */
795 track
->max_indx
= idx_value
& 0x00FFFFFFUL
;
799 track
->maxy
= ((idx_value
>> 13) & 0x1FFF) + 1;
800 if (p
->rdev
->family
< CHIP_RV515
) {
806 track
->num_cb
= ((idx_value
>> 5) & 0x3) + 1;
812 /* RB3D_COLORPITCH0 */
813 /* RB3D_COLORPITCH1 */
814 /* RB3D_COLORPITCH2 */
815 /* RB3D_COLORPITCH3 */
816 r
= r100_cs_packet_next_reloc(p
, &reloc
);
818 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
820 r100_cs_dump_packet(p
, pkt
);
824 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
825 tile_flags
|= R300_COLOR_TILE_ENABLE
;
826 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
827 tile_flags
|= R300_COLOR_MICROTILE_ENABLE
;
829 tmp
= idx_value
& ~(0x7 << 16);
833 i
= (reg
- 0x4E38) >> 2;
834 track
->cb
[i
].pitch
= idx_value
& 0x3FFE;
835 switch (((idx_value
>> 21) & 0xF)) {
839 track
->cb
[i
].cpp
= 1;
845 track
->cb
[i
].cpp
= 2;
848 track
->cb
[i
].cpp
= 4;
851 track
->cb
[i
].cpp
= 8;
854 track
->cb
[i
].cpp
= 16;
857 DRM_ERROR("Invalid color buffer format (%d) !\n",
858 ((idx_value
>> 21) & 0xF));
865 track
->z_enabled
= true;
867 track
->z_enabled
= false;
872 switch ((idx_value
& 0xF)) {
881 DRM_ERROR("Invalid z buffer format (%d) !\n",
888 r
= r100_cs_packet_next_reloc(p
, &reloc
);
890 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
892 r100_cs_dump_packet(p
, pkt
);
896 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
897 tile_flags
|= R300_DEPTHMACROTILE_ENABLE
;
898 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
899 tile_flags
|= R300_DEPTHMICROTILE_TILED
;;
901 tmp
= idx_value
& ~(0x7 << 16);
905 track
->zb
.pitch
= idx_value
& 0x3FFC;
908 for (i
= 0; i
< 16; i
++) {
911 enabled
= !!(idx_value
& (1 << i
));
912 track
->textures
[i
].enabled
= enabled
;
931 /* TX_FORMAT1_[0-15] */
932 i
= (reg
- 0x44C0) >> 2;
933 tmp
= (idx_value
>> 25) & 0x3;
934 track
->textures
[i
].tex_coord_type
= tmp
;
935 switch ((idx_value
& 0x1F)) {
936 case R300_TX_FORMAT_X8
:
937 case R300_TX_FORMAT_Y4X4
:
938 case R300_TX_FORMAT_Z3Y3X2
:
939 track
->textures
[i
].cpp
= 1;
941 case R300_TX_FORMAT_X16
:
942 case R300_TX_FORMAT_Y8X8
:
943 case R300_TX_FORMAT_Z5Y6X5
:
944 case R300_TX_FORMAT_Z6Y5X5
:
945 case R300_TX_FORMAT_W4Z4Y4X4
:
946 case R300_TX_FORMAT_W1Z5Y5X5
:
947 case R300_TX_FORMAT_DXT1
:
948 case R300_TX_FORMAT_D3DMFT_CxV8U8
:
949 case R300_TX_FORMAT_B8G8_B8G8
:
950 case R300_TX_FORMAT_G8R8_G8B8
:
951 track
->textures
[i
].cpp
= 2;
953 case R300_TX_FORMAT_Y16X16
:
954 case R300_TX_FORMAT_Z11Y11X10
:
955 case R300_TX_FORMAT_Z10Y11X11
:
956 case R300_TX_FORMAT_W8Z8Y8X8
:
957 case R300_TX_FORMAT_W2Z10Y10X10
:
959 case R300_TX_FORMAT_FL_I32
:
961 case R300_TX_FORMAT_DXT3
:
962 case R300_TX_FORMAT_DXT5
:
963 track
->textures
[i
].cpp
= 4;
965 case R300_TX_FORMAT_W16Z16Y16X16
:
966 case R300_TX_FORMAT_FL_R16G16B16A16
:
967 case R300_TX_FORMAT_FL_I32A32
:
968 track
->textures
[i
].cpp
= 8;
970 case R300_TX_FORMAT_FL_R32G32B32A32
:
971 track
->textures
[i
].cpp
= 16;
974 DRM_ERROR("Invalid texture format %u\n",
996 /* TX_FILTER0_[0-15] */
997 i
= (reg
- 0x4400) >> 2;
998 tmp
= idx_value
& 0x7;
999 if (tmp
== 2 || tmp
== 4 || tmp
== 6) {
1000 track
->textures
[i
].roundup_w
= false;
1002 tmp
= (idx_value
>> 3) & 0x7;
1003 if (tmp
== 2 || tmp
== 4 || tmp
== 6) {
1004 track
->textures
[i
].roundup_h
= false;
1023 /* TX_FORMAT2_[0-15] */
1024 i
= (reg
- 0x4500) >> 2;
1025 tmp
= idx_value
& 0x3FFF;
1026 track
->textures
[i
].pitch
= tmp
+ 1;
1027 if (p
->rdev
->family
>= CHIP_RV515
) {
1028 tmp
= ((idx_value
>> 15) & 1) << 11;
1029 track
->textures
[i
].width_11
= tmp
;
1030 tmp
= ((idx_value
>> 16) & 1) << 11;
1031 track
->textures
[i
].height_11
= tmp
;
1050 /* TX_FORMAT0_[0-15] */
1051 i
= (reg
- 0x4480) >> 2;
1052 tmp
= idx_value
& 0x7FF;
1053 track
->textures
[i
].width
= tmp
+ 1;
1054 tmp
= (idx_value
>> 11) & 0x7FF;
1055 track
->textures
[i
].height
= tmp
+ 1;
1056 tmp
= (idx_value
>> 26) & 0xF;
1057 track
->textures
[i
].num_levels
= tmp
;
1058 tmp
= idx_value
& (1 << 31);
1059 track
->textures
[i
].use_pitch
= !!tmp
;
1060 tmp
= (idx_value
>> 22) & 0xF;
1061 track
->textures
[i
].txdepth
= tmp
;
1063 case R300_ZB_ZPASS_ADDR
:
1064 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1066 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1068 r100_cs_dump_packet(p
, pkt
);
1071 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1074 /* valid register only on RV530 */
1075 if (p
->rdev
->family
== CHIP_RV530
)
1077 /* fallthrough do not move */
1079 printk(KERN_ERR
"Forbidden register 0x%04X in cs at %d\n",
1086 static int r300_packet3_check(struct radeon_cs_parser
*p
,
1087 struct radeon_cs_packet
*pkt
)
1089 struct radeon_cs_reloc
*reloc
;
1090 struct r100_cs_track
*track
;
1091 volatile uint32_t *ib
;
1097 track
= (struct r100_cs_track
*)p
->track
;
1098 switch(pkt
->opcode
) {
1099 case PACKET3_3D_LOAD_VBPNTR
:
1100 r
= r100_packet3_load_vbpntr(p
, pkt
, idx
);
1104 case PACKET3_INDX_BUFFER
:
1105 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1107 DRM_ERROR("No reloc for packet3 %d\n", pkt
->opcode
);
1108 r100_cs_dump_packet(p
, pkt
);
1111 ib
[idx
+1] = radeon_get_ib_value(p
, idx
+ 1) + ((u32
)reloc
->lobj
.gpu_offset
);
1112 r
= r100_cs_track_check_pkt3_indx_buffer(p
, pkt
, reloc
->robj
);
1118 case PACKET3_3D_DRAW_IMMD
:
1119 /* Number of dwords is vtx_size * (num_vertices - 1)
1120 * PRIM_WALK must be equal to 3 vertex data in embedded
1122 if (((radeon_get_ib_value(p
, idx
+ 1) >> 4) & 0x3) != 3) {
1123 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1126 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1127 track
->immd_dwords
= pkt
->count
- 1;
1128 r
= r100_cs_track_check(p
->rdev
, track
);
1133 case PACKET3_3D_DRAW_IMMD_2
:
1134 /* Number of dwords is vtx_size * (num_vertices - 1)
1135 * PRIM_WALK must be equal to 3 vertex data in embedded
1137 if (((radeon_get_ib_value(p
, idx
) >> 4) & 0x3) != 3) {
1138 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1141 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1142 track
->immd_dwords
= pkt
->count
;
1143 r
= r100_cs_track_check(p
->rdev
, track
);
1148 case PACKET3_3D_DRAW_VBUF
:
1149 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1150 r
= r100_cs_track_check(p
->rdev
, track
);
1155 case PACKET3_3D_DRAW_VBUF_2
:
1156 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1157 r
= r100_cs_track_check(p
->rdev
, track
);
1162 case PACKET3_3D_DRAW_INDX
:
1163 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1164 r
= r100_cs_track_check(p
->rdev
, track
);
1169 case PACKET3_3D_DRAW_INDX_2
:
1170 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1171 r
= r100_cs_track_check(p
->rdev
, track
);
1179 DRM_ERROR("Packet3 opcode %x not supported\n", pkt
->opcode
);
1185 int r300_cs_parse(struct radeon_cs_parser
*p
)
1187 struct radeon_cs_packet pkt
;
1188 struct r100_cs_track
*track
;
1191 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
1192 r100_cs_track_clear(p
->rdev
, track
);
1195 r
= r100_cs_packet_parse(p
, &pkt
, p
->idx
);
1199 p
->idx
+= pkt
.count
+ 2;
1202 r
= r100_cs_parse_packet0(p
, &pkt
,
1203 p
->rdev
->config
.r300
.reg_safe_bm
,
1204 p
->rdev
->config
.r300
.reg_safe_bm_size
,
1205 &r300_packet0_check
);
1210 r
= r300_packet3_check(p
, &pkt
);
1213 DRM_ERROR("Unknown packet type %d !\n", pkt
.type
);
1219 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
1223 void r300_set_reg_safe(struct radeon_device
*rdev
)
1225 rdev
->config
.r300
.reg_safe_bm
= r300_reg_safe_bm
;
1226 rdev
->config
.r300
.reg_safe_bm_size
= ARRAY_SIZE(r300_reg_safe_bm
);
1229 int r300_init(struct radeon_device
*rdev
)
1231 r300_set_reg_safe(rdev
);
1235 void r300_mc_program(struct radeon_device
*rdev
)
1237 struct r100_mc_save save
;
1240 r
= r100_debugfs_mc_info_init(rdev
);
1242 dev_err(rdev
->dev
, "Failed to create r100_mc debugfs file.\n");
1245 /* Stops all mc clients */
1246 r100_mc_stop(rdev
, &save
);
1247 if (rdev
->flags
& RADEON_IS_AGP
) {
1248 WREG32(R_00014C_MC_AGP_LOCATION
,
1249 S_00014C_MC_AGP_START(rdev
->mc
.gtt_start
>> 16) |
1250 S_00014C_MC_AGP_TOP(rdev
->mc
.gtt_end
>> 16));
1251 WREG32(R_000170_AGP_BASE
, lower_32_bits(rdev
->mc
.agp_base
));
1252 WREG32(R_00015C_AGP_BASE_2
,
1253 upper_32_bits(rdev
->mc
.agp_base
) & 0xff);
1255 WREG32(R_00014C_MC_AGP_LOCATION
, 0x0FFFFFFF);
1256 WREG32(R_000170_AGP_BASE
, 0);
1257 WREG32(R_00015C_AGP_BASE_2
, 0);
1259 /* Wait for mc idle */
1260 if (r300_mc_wait_for_idle(rdev
))
1261 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1262 /* Program MC, should be a 32bits limited address space */
1263 WREG32(R_000148_MC_FB_LOCATION
,
1264 S_000148_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
1265 S_000148_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
1266 r100_mc_resume(rdev
, &save
);