150e3186bec049d12e27eb60cfaad83104fd390a
2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define EVERGREEN_MAX_SH_GPRS 256
28 #define EVERGREEN_MAX_TEMP_GPRS 16
29 #define EVERGREEN_MAX_SH_THREADS 256
30 #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
31 #define EVERGREEN_MAX_FRC_EOV_CNT 16384
32 #define EVERGREEN_MAX_BACKENDS 8
33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
34 #define EVERGREEN_MAX_SIMDS 16
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
36 #define EVERGREEN_MAX_PIPES 8
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
46 #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001
47 #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001
48 #define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002
49 #define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002
53 #define RCU_IND_INDEX 0x100
54 #define RCU_IND_DATA 0x104
56 /* discrete uvd clocks */
57 #define CG_UPLL_FUNC_CNTL 0x718
58 # define UPLL_RESET_MASK 0x00000001
59 # define UPLL_SLEEP_MASK 0x00000002
60 # define UPLL_BYPASS_EN_MASK 0x00000004
61 # define UPLL_CTLREQ_MASK 0x00000008
62 # define UPLL_REF_DIV_MASK 0x003F0000
63 # define UPLL_VCO_MODE_MASK 0x00000200
64 # define UPLL_CTLACK_MASK 0x40000000
65 # define UPLL_CTLACK2_MASK 0x80000000
66 #define CG_UPLL_FUNC_CNTL_2 0x71c
67 # define UPLL_PDIV_A(x) ((x) << 0)
68 # define UPLL_PDIV_A_MASK 0x0000007F
69 # define UPLL_PDIV_B(x) ((x) << 8)
70 # define UPLL_PDIV_B_MASK 0x00007F00
71 # define VCLK_SRC_SEL(x) ((x) << 20)
72 # define VCLK_SRC_SEL_MASK 0x01F00000
73 # define DCLK_SRC_SEL(x) ((x) << 25)
74 # define DCLK_SRC_SEL_MASK 0x3E000000
75 #define CG_UPLL_FUNC_CNTL_3 0x720
76 # define UPLL_FB_DIV(x) ((x) << 0)
77 # define UPLL_FB_DIV_MASK 0x01FFFFFF
78 #define CG_UPLL_FUNC_CNTL_4 0x854
79 # define UPLL_SPARE_ISPARE9 0x00020000
80 #define CG_UPLL_SPREAD_SPECTRUM 0x79c
81 # define SSEN_MASK 0x00000001
83 /* fusion uvd clocks */
84 #define CG_DCLK_CNTL 0x610
85 # define DCLK_DIVIDER_MASK 0x7f
86 # define DCLK_DIR_CNTL_EN (1 << 8)
87 #define CG_DCLK_STATUS 0x614
88 # define DCLK_STATUS (1 << 0)
89 #define CG_VCLK_CNTL 0x618
90 #define CG_VCLK_STATUS 0x61c
91 #define CG_SCRATCH1 0x820
93 #define GRBM_GFX_INDEX 0x802C
94 #define INSTANCE_INDEX(x) ((x) << 0)
95 #define SE_INDEX(x) ((x) << 16)
96 #define INSTANCE_BROADCAST_WRITES (1 << 30)
97 #define SE_BROADCAST_WRITES (1 << 31)
98 #define RLC_GFX_INDEX 0x3fC4
99 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
100 #define WRITE_DIS (1 << 0)
101 #define CC_RB_BACKEND_DISABLE 0x98F4
102 #define BACKEND_DISABLE(x) ((x) << 16)
103 #define GB_ADDR_CONFIG 0x98F8
104 #define NUM_PIPES(x) ((x) << 0)
105 #define NUM_PIPES_MASK 0x0000000f
106 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
107 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
108 #define NUM_SHADER_ENGINES(x) ((x) << 12)
109 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
110 #define NUM_GPUS(x) ((x) << 20)
111 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
112 #define ROW_SIZE(x) ((x) << 28)
113 #define GB_BACKEND_MAP 0x98FC
114 #define DMIF_ADDR_CONFIG 0xBD4
115 #define HDP_ADDR_CONFIG 0x2F48
116 #define HDP_MISC_CNTL 0x2F4C
117 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
119 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
120 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
122 #define CGTS_SYS_TCC_DISABLE 0x3F90
123 #define CGTS_TCC_DISABLE 0x9148
124 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94
125 #define CGTS_USER_TCC_DISABLE 0x914C
127 #define CONFIG_MEMSIZE 0x5428
129 #define BIF_FB_EN 0x5490
130 #define FB_READ_EN (1 << 0)
131 #define FB_WRITE_EN (1 << 1)
133 #define CP_STRMOUT_CNTL 0x84FC
135 #define CP_COHER_CNTL 0x85F0
136 #define CP_COHER_SIZE 0x85F4
137 #define CP_COHER_BASE 0x85F8
138 #define CP_STALLED_STAT1 0x8674
139 #define CP_STALLED_STAT2 0x8678
140 #define CP_BUSY_STAT 0x867C
141 #define CP_STAT 0x8680
142 #define CP_ME_CNTL 0x86D8
143 #define CP_ME_HALT (1 << 28)
144 #define CP_PFP_HALT (1 << 26)
145 #define CP_ME_RAM_DATA 0xC160
146 #define CP_ME_RAM_RADDR 0xC158
147 #define CP_ME_RAM_WADDR 0xC15C
148 #define CP_MEQ_THRESHOLDS 0x8764
149 #define STQ_SPLIT(x) ((x) << 0)
150 #define CP_PERFMON_CNTL 0x87FC
151 #define CP_PFP_UCODE_ADDR 0xC150
152 #define CP_PFP_UCODE_DATA 0xC154
153 #define CP_QUEUE_THRESHOLDS 0x8760
154 #define ROQ_IB1_START(x) ((x) << 0)
155 #define ROQ_IB2_START(x) ((x) << 8)
156 #define CP_RB_BASE 0xC100
157 #define CP_RB_CNTL 0xC104
158 #define RB_BUFSZ(x) ((x) << 0)
159 #define RB_BLKSZ(x) ((x) << 8)
160 #define RB_NO_UPDATE (1 << 27)
161 #define RB_RPTR_WR_ENA (1 << 31)
162 #define BUF_SWAP_32BIT (2 << 16)
163 #define CP_RB_RPTR 0x8700
164 #define CP_RB_RPTR_ADDR 0xC10C
165 #define RB_RPTR_SWAP(x) ((x) << 0)
166 #define CP_RB_RPTR_ADDR_HI 0xC110
167 #define CP_RB_RPTR_WR 0xC108
168 #define CP_RB_WPTR 0xC114
169 #define CP_RB_WPTR_ADDR 0xC118
170 #define CP_RB_WPTR_ADDR_HI 0xC11C
171 #define CP_RB_WPTR_DELAY 0x8704
172 #define CP_SEM_WAIT_TIMER 0x85BC
173 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
174 #define CP_DEBUG 0xC1FC
177 #define DCCG_AUDIO_DTO_SOURCE 0x05ac
178 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
179 # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */
181 #define DCCG_AUDIO_DTO0_PHASE 0x05b0
182 #define DCCG_AUDIO_DTO0_MODULE 0x05b4
183 #define DCCG_AUDIO_DTO0_LOAD 0x05b8
184 #define DCCG_AUDIO_DTO0_CNTL 0x05bc
186 #define DCCG_AUDIO_DTO1_PHASE 0x05c0
187 #define DCCG_AUDIO_DTO1_MODULE 0x05c4
188 #define DCCG_AUDIO_DTO1_LOAD 0x05c8
189 #define DCCG_AUDIO_DTO1_CNTL 0x05cc
192 #define HDMI_CONTROL 0x7030
193 # define HDMI_KEEPOUT_MODE (1 << 0)
194 # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */
195 # define HDMI_ERROR_ACK (1 << 8)
196 # define HDMI_ERROR_MASK (1 << 9)
197 # define HDMI_DEEP_COLOR_ENABLE (1 << 24)
198 # define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28)
199 # define HDMI_24BIT_DEEP_COLOR 0
200 # define HDMI_30BIT_DEEP_COLOR 1
201 # define HDMI_36BIT_DEEP_COLOR 2
202 #define HDMI_STATUS 0x7034
203 # define HDMI_ACTIVE_AVMUTE (1 << 0)
204 # define HDMI_AUDIO_PACKET_ERROR (1 << 16)
205 # define HDMI_VBI_PACKET_ERROR (1 << 20)
206 #define HDMI_AUDIO_PACKET_CONTROL 0x7038
207 # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
208 # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
209 #define HDMI_ACR_PACKET_CONTROL 0x703c
210 # define HDMI_ACR_SEND (1 << 0)
211 # define HDMI_ACR_CONT (1 << 1)
212 # define HDMI_ACR_SELECT(x) (((x) & 3) << 4)
213 # define HDMI_ACR_HW 0
214 # define HDMI_ACR_32 1
215 # define HDMI_ACR_44 2
216 # define HDMI_ACR_48 3
217 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
218 # define HDMI_ACR_AUTO_SEND (1 << 12)
219 # define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16)
220 # define HDMI_ACR_X1 1
221 # define HDMI_ACR_X2 2
222 # define HDMI_ACR_X4 4
223 # define HDMI_ACR_AUDIO_PRIORITY (1 << 31)
224 #define HDMI_VBI_PACKET_CONTROL 0x7040
225 # define HDMI_NULL_SEND (1 << 0)
226 # define HDMI_GC_SEND (1 << 4)
227 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
228 #define HDMI_INFOFRAME_CONTROL0 0x7044
229 # define HDMI_AVI_INFO_SEND (1 << 0)
230 # define HDMI_AVI_INFO_CONT (1 << 1)
231 # define HDMI_AUDIO_INFO_SEND (1 << 4)
232 # define HDMI_AUDIO_INFO_CONT (1 << 5)
233 # define HDMI_MPEG_INFO_SEND (1 << 8)
234 # define HDMI_MPEG_INFO_CONT (1 << 9)
235 #define HDMI_INFOFRAME_CONTROL1 0x7048
236 # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
237 # define HDMI_AVI_INFO_LINE_MASK (0x3f << 0)
238 # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
239 # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
240 #define HDMI_GENERIC_PACKET_CONTROL 0x704c
241 # define HDMI_GENERIC0_SEND (1 << 0)
242 # define HDMI_GENERIC0_CONT (1 << 1)
243 # define HDMI_GENERIC1_SEND (1 << 4)
244 # define HDMI_GENERIC1_CONT (1 << 5)
245 # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
246 # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
247 #define HDMI_GC 0x7058
248 # define HDMI_GC_AVMUTE (1 << 0)
249 # define HDMI_GC_AVMUTE_CONT (1 << 2)
250 #define AFMT_AUDIO_PACKET_CONTROL2 0x705c
251 # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0)
252 # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1)
253 # define AFMT_60958_CS_SOURCE (1 << 4)
254 # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8)
255 # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16)
256 #define AFMT_AVI_INFO0 0x7084
257 # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
258 # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8)
259 # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10)
260 # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12)
261 # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13)
262 # define AFMT_AVI_INFO_Y_RGB 0
263 # define AFMT_AVI_INFO_Y_YCBCR422 1
264 # define AFMT_AVI_INFO_Y_YCBCR444 2
265 # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
266 # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16)
267 # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20)
268 # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22)
269 # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
270 # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24)
271 # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26)
272 # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28)
273 # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)
274 # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
275 #define AFMT_AVI_INFO1 0x7088
276 # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
277 # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
278 # define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12)
279 # define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14)
280 # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
281 #define AFMT_AVI_INFO2 0x708c
282 # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
283 # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
284 #define AFMT_AVI_INFO3 0x7090
285 # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
286 # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24)
287 #define AFMT_MPEG_INFO0 0x7094
288 # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
289 # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
290 # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
291 # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
292 #define AFMT_MPEG_INFO1 0x7098
293 # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
294 # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8)
295 # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12)
296 #define AFMT_GENERIC0_HDR 0x709c
297 #define AFMT_GENERIC0_0 0x70a0
298 #define AFMT_GENERIC0_1 0x70a4
299 #define AFMT_GENERIC0_2 0x70a8
300 #define AFMT_GENERIC0_3 0x70ac
301 #define AFMT_GENERIC0_4 0x70b0
302 #define AFMT_GENERIC0_5 0x70b4
303 #define AFMT_GENERIC0_6 0x70b8
304 #define AFMT_GENERIC1_HDR 0x70bc
305 #define AFMT_GENERIC1_0 0x70c0
306 #define AFMT_GENERIC1_1 0x70c4
307 #define AFMT_GENERIC1_2 0x70c8
308 #define AFMT_GENERIC1_3 0x70cc
309 #define AFMT_GENERIC1_4 0x70d0
310 #define AFMT_GENERIC1_5 0x70d4
311 #define AFMT_GENERIC1_6 0x70d8
312 #define HDMI_ACR_32_0 0x70dc
313 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
314 #define HDMI_ACR_32_1 0x70e0
315 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0)
316 #define HDMI_ACR_44_0 0x70e4
317 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
318 #define HDMI_ACR_44_1 0x70e8
319 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0)
320 #define HDMI_ACR_48_0 0x70ec
321 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
322 #define HDMI_ACR_48_1 0x70f0
323 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0)
324 #define HDMI_ACR_STATUS_0 0x70f4
325 #define HDMI_ACR_STATUS_1 0x70f8
326 #define AFMT_AUDIO_INFO0 0x70fc
327 # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
328 # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8)
329 # define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11)
330 # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16)
331 # define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24)
332 #define AFMT_AUDIO_INFO1 0x7100
333 # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
334 # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
335 # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
336 # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
337 # define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16)
338 #define AFMT_60958_0 0x7104
339 # define AFMT_60958_CS_A(x) (((x) & 1) << 0)
340 # define AFMT_60958_CS_B(x) (((x) & 1) << 1)
341 # define AFMT_60958_CS_C(x) (((x) & 1) << 2)
342 # define AFMT_60958_CS_D(x) (((x) & 3) << 3)
343 # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6)
344 # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
345 # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
346 # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
347 # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
348 # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
349 #define AFMT_60958_1 0x7108
350 # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
351 # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
352 # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16)
353 # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18)
354 # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
355 #define AFMT_AUDIO_CRC_CONTROL 0x710c
356 # define AFMT_AUDIO_CRC_EN (1 << 0)
357 #define AFMT_RAMP_CONTROL0 0x7110
358 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
359 # define AFMT_RAMP_DATA_SIGN (1 << 31)
360 #define AFMT_RAMP_CONTROL1 0x7114
361 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
362 # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
363 #define AFMT_RAMP_CONTROL2 0x7118
364 # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
365 #define AFMT_RAMP_CONTROL3 0x711c
366 # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
367 #define AFMT_60958_2 0x7120
368 # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
369 # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
370 # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
371 # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
372 # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
373 # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
374 #define AFMT_STATUS 0x7128
375 # define AFMT_AUDIO_ENABLE (1 << 4)
376 # define AFMT_AUDIO_HBR_ENABLE (1 << 8)
377 # define AFMT_AZ_FORMAT_WTRIG (1 << 28)
378 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
379 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
380 #define AFMT_AUDIO_PACKET_CONTROL 0x712c
381 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
382 # define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */
383 # define AFMT_AUDIO_TEST_EN (1 << 12)
384 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
385 # define AFMT_60958_CS_UPDATE (1 << 26)
386 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
387 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
388 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
389 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
390 #define AFMT_VBI_PACKET_CONTROL 0x7130
391 # define AFMT_GENERIC0_UPDATE (1 << 2)
392 #define AFMT_INFOFRAME_CONTROL0 0x7134
393 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */
394 # define AFMT_AUDIO_INFO_UPDATE (1 << 7)
395 # define AFMT_MPEG_INFO_UPDATE (1 << 10)
396 #define AFMT_GENERIC0_7 0x7138
398 /* DCE4/5 ELD audio interface */
399 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */
400 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */
401 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */
402 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */
403 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */
404 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */
405 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */
406 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */
407 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */
408 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */
409 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */
410 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */
411 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */
412 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */
413 # define MAX_CHANNELS(x) (((x) & 0x7) << 0)
414 /* max channels minus one. 7 = 8 channels */
415 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
416 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
417 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
418 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
428 #define AZ_HOT_PLUG_CONTROL 0x5e78
429 # define AZ_FORCE_CODEC_WAKE (1 << 0)
430 # define PIN0_JACK_DETECTION_ENABLE (1 << 4)
431 # define PIN1_JACK_DETECTION_ENABLE (1 << 5)
432 # define PIN2_JACK_DETECTION_ENABLE (1 << 6)
433 # define PIN3_JACK_DETECTION_ENABLE (1 << 7)
434 # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)
435 # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)
436 # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)
437 # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)
438 # define CODEC_HOT_PLUG_ENABLE (1 << 12)
439 # define PIN0_AUDIO_ENABLED (1 << 24)
440 # define PIN1_AUDIO_ENABLED (1 << 25)
441 # define PIN2_AUDIO_ENABLED (1 << 26)
442 # define PIN3_AUDIO_ENABLED (1 << 27)
443 # define AUDIO_ENABLED (1 << 31)
446 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
447 #define INACTIVE_QD_PIPES(x) ((x) << 8)
448 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
449 #define INACTIVE_SIMDS(x) ((x) << 16)
450 #define INACTIVE_SIMDS_MASK 0x00FF0000
452 #define GRBM_CNTL 0x8000
453 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
454 #define GRBM_SOFT_RESET 0x8020
455 #define SOFT_RESET_CP (1 << 0)
456 #define SOFT_RESET_CB (1 << 1)
457 #define SOFT_RESET_DB (1 << 3)
458 #define SOFT_RESET_PA (1 << 5)
459 #define SOFT_RESET_SC (1 << 6)
460 #define SOFT_RESET_SPI (1 << 8)
461 #define SOFT_RESET_SH (1 << 9)
462 #define SOFT_RESET_SX (1 << 10)
463 #define SOFT_RESET_TC (1 << 11)
464 #define SOFT_RESET_TA (1 << 12)
465 #define SOFT_RESET_VC (1 << 13)
466 #define SOFT_RESET_VGT (1 << 14)
468 #define GRBM_STATUS 0x8010
469 #define CMDFIFO_AVAIL_MASK 0x0000000F
470 #define SRBM_RQ_PENDING (1 << 5)
471 #define CF_RQ_PENDING (1 << 7)
472 #define PF_RQ_PENDING (1 << 8)
473 #define GRBM_EE_BUSY (1 << 10)
474 #define SX_CLEAN (1 << 11)
475 #define DB_CLEAN (1 << 12)
476 #define CB_CLEAN (1 << 13)
477 #define TA_BUSY (1 << 14)
478 #define VGT_BUSY_NO_DMA (1 << 16)
479 #define VGT_BUSY (1 << 17)
480 #define SX_BUSY (1 << 20)
481 #define SH_BUSY (1 << 21)
482 #define SPI_BUSY (1 << 22)
483 #define SC_BUSY (1 << 24)
484 #define PA_BUSY (1 << 25)
485 #define DB_BUSY (1 << 26)
486 #define CP_COHERENCY_BUSY (1 << 28)
487 #define CP_BUSY (1 << 29)
488 #define CB_BUSY (1 << 30)
489 #define GUI_ACTIVE (1 << 31)
490 #define GRBM_STATUS_SE0 0x8014
491 #define GRBM_STATUS_SE1 0x8018
492 #define SE_SX_CLEAN (1 << 0)
493 #define SE_DB_CLEAN (1 << 1)
494 #define SE_CB_CLEAN (1 << 2)
495 #define SE_TA_BUSY (1 << 25)
496 #define SE_SX_BUSY (1 << 26)
497 #define SE_SPI_BUSY (1 << 27)
498 #define SE_SH_BUSY (1 << 28)
499 #define SE_SC_BUSY (1 << 29)
500 #define SE_DB_BUSY (1 << 30)
501 #define SE_CB_BUSY (1 << 31)
503 #define CG_THERMAL_CTRL 0x72c
504 #define TOFFSET_MASK 0x00003FE0
505 #define TOFFSET_SHIFT 5
506 #define CG_MULT_THERMAL_STATUS 0x740
507 #define ASIC_T(x) ((x) << 16)
508 #define ASIC_T_MASK 0x07FF0000
509 #define ASIC_T_SHIFT 16
510 #define CG_TS0_STATUS 0x760
511 #define TS0_ADC_DOUT_MASK 0x000003FF
512 #define TS0_ADC_DOUT_SHIFT 0
514 #define CG_THERMAL_STATUS 0x678
516 #define HDP_HOST_PATH_CNTL 0x2C00
517 #define HDP_NONSURFACE_BASE 0x2C04
518 #define HDP_NONSURFACE_INFO 0x2C08
519 #define HDP_NONSURFACE_SIZE 0x2C0C
520 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
521 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
522 #define HDP_TILING_CONFIG 0x2F3C
524 #define MC_SHARED_CHMAP 0x2004
525 #define NOOFCHAN_SHIFT 12
526 #define NOOFCHAN_MASK 0x00003000
527 #define MC_SHARED_CHREMAP 0x2008
529 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
530 #define BLACKOUT_MODE_MASK 0x00000007
532 #define MC_ARB_RAMCFG 0x2760
533 #define NOOFBANK_SHIFT 0
534 #define NOOFBANK_MASK 0x00000003
535 #define NOOFRANK_SHIFT 2
536 #define NOOFRANK_MASK 0x00000004
537 #define NOOFROWS_SHIFT 3
538 #define NOOFROWS_MASK 0x00000038
539 #define NOOFCOLS_SHIFT 6
540 #define NOOFCOLS_MASK 0x000000C0
541 #define CHANSIZE_SHIFT 8
542 #define CHANSIZE_MASK 0x00000100
543 #define BURSTLENGTH_SHIFT 9
544 #define BURSTLENGTH_MASK 0x00000200
545 #define CHANSIZE_OVERRIDE (1 << 11)
546 #define FUS_MC_ARB_RAMCFG 0x2768
547 #define MC_VM_AGP_TOP 0x2028
548 #define MC_VM_AGP_BOT 0x202C
549 #define MC_VM_AGP_BASE 0x2030
550 #define MC_VM_FB_LOCATION 0x2024
551 #define MC_FUS_VM_FB_OFFSET 0x2898
552 #define MC_VM_MB_L1_TLB0_CNTL 0x2234
553 #define MC_VM_MB_L1_TLB1_CNTL 0x2238
554 #define MC_VM_MB_L1_TLB2_CNTL 0x223C
555 #define MC_VM_MB_L1_TLB3_CNTL 0x2240
556 #define ENABLE_L1_TLB (1 << 0)
557 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
558 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
559 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
560 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
561 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
562 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
563 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
564 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
565 #define MC_VM_MD_L1_TLB0_CNTL 0x2654
566 #define MC_VM_MD_L1_TLB1_CNTL 0x2658
567 #define MC_VM_MD_L1_TLB2_CNTL 0x265C
568 #define MC_VM_MD_L1_TLB3_CNTL 0x2698
570 #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
571 #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
572 #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
574 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
575 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
576 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
578 #define PA_CL_ENHANCE 0x8A14
579 #define CLIP_VTX_REORDER_ENA (1 << 0)
580 #define NUM_CLIP_SEQ(x) ((x) << 1)
581 #define PA_SC_ENHANCE 0x8BF0
582 #define PA_SC_AA_CONFIG 0x28C04
583 #define MSAA_NUM_SAMPLES_SHIFT 0
584 #define MSAA_NUM_SAMPLES_MASK 0x3
585 #define PA_SC_CLIPRECT_RULE 0x2820C
586 #define PA_SC_EDGERULE 0x28230
587 #define PA_SC_FIFO_SIZE 0x8BCC
588 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
589 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
590 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
591 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
592 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
593 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
594 #define PA_SC_LINE_STIPPLE 0x28A0C
595 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60
596 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
598 #define SCRATCH_REG0 0x8500
599 #define SCRATCH_REG1 0x8504
600 #define SCRATCH_REG2 0x8508
601 #define SCRATCH_REG3 0x850C
602 #define SCRATCH_REG4 0x8510
603 #define SCRATCH_REG5 0x8514
604 #define SCRATCH_REG6 0x8518
605 #define SCRATCH_REG7 0x851C
606 #define SCRATCH_UMSK 0x8540
607 #define SCRATCH_ADDR 0x8544
609 #define SMX_SAR_CTL0 0xA008
610 #define SMX_DC_CTL0 0xA020
611 #define USE_HASH_FUNCTION (1 << 0)
612 #define NUMBER_OF_SETS(x) ((x) << 1)
613 #define FLUSH_ALL_ON_EVENT (1 << 10)
614 #define STALL_ON_EVENT (1 << 11)
615 #define SMX_EVENT_CTL 0xA02C
616 #define ES_FLUSH_CTL(x) ((x) << 0)
617 #define GS_FLUSH_CTL(x) ((x) << 3)
618 #define ACK_FLUSH_CTL(x) ((x) << 6)
619 #define SYNC_FLUSH_CTL (1 << 8)
621 #define SPI_CONFIG_CNTL 0x9100
622 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
623 #define SPI_CONFIG_CNTL_1 0x913C
624 #define VTX_DONE_DELAY(x) ((x) << 0)
625 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
626 #define SPI_INPUT_Z 0x286D8
627 #define SPI_PS_IN_CONTROL_0 0x286CC
628 #define NUM_INTERP(x) ((x)<<0)
629 #define POSITION_ENA (1<<8)
630 #define POSITION_CENTROID (1<<9)
631 #define POSITION_ADDR(x) ((x)<<10)
632 #define PARAM_GEN(x) ((x)<<15)
633 #define PARAM_GEN_ADDR(x) ((x)<<19)
634 #define BARYC_SAMPLE_CNTL(x) ((x)<<26)
635 #define PERSP_GRADIENT_ENA (1<<28)
636 #define LINEAR_GRADIENT_ENA (1<<29)
637 #define POSITION_SAMPLE (1<<30)
638 #define BARYC_AT_SAMPLE_ENA (1<<31)
640 #define SQ_CONFIG 0x8C00
641 #define VC_ENABLE (1 << 0)
642 #define EXPORT_SRC_C (1 << 1)
643 #define CS_PRIO(x) ((x) << 18)
644 #define LS_PRIO(x) ((x) << 20)
645 #define HS_PRIO(x) ((x) << 22)
646 #define PS_PRIO(x) ((x) << 24)
647 #define VS_PRIO(x) ((x) << 26)
648 #define GS_PRIO(x) ((x) << 28)
649 #define ES_PRIO(x) ((x) << 30)
650 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04
651 #define NUM_PS_GPRS(x) ((x) << 0)
652 #define NUM_VS_GPRS(x) ((x) << 16)
653 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
654 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08
655 #define NUM_GS_GPRS(x) ((x) << 0)
656 #define NUM_ES_GPRS(x) ((x) << 16)
657 #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
658 #define NUM_HS_GPRS(x) ((x) << 0)
659 #define NUM_LS_GPRS(x) ((x) << 16)
660 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10
661 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14
662 #define SQ_THREAD_RESOURCE_MGMT 0x8C18
663 #define NUM_PS_THREADS(x) ((x) << 0)
664 #define NUM_VS_THREADS(x) ((x) << 8)
665 #define NUM_GS_THREADS(x) ((x) << 16)
666 #define NUM_ES_THREADS(x) ((x) << 24)
667 #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
668 #define NUM_HS_THREADS(x) ((x) << 0)
669 #define NUM_LS_THREADS(x) ((x) << 8)
670 #define SQ_STACK_RESOURCE_MGMT_1 0x8C20
671 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
672 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
673 #define SQ_STACK_RESOURCE_MGMT_2 0x8C24
674 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
675 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
676 #define SQ_STACK_RESOURCE_MGMT_3 0x8C28
677 #define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
678 #define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
679 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
680 #define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94
681 #define SQ_STATIC_THREAD_MGMT_1 0x8E20
682 #define SQ_STATIC_THREAD_MGMT_2 0x8E24
683 #define SQ_STATIC_THREAD_MGMT_3 0x8E28
684 #define SQ_LDS_RESOURCE_MGMT 0x8E2C
686 #define SQ_MS_FIFO_SIZES 0x8CF0
687 #define CACHE_FIFO_SIZE(x) ((x) << 0)
688 #define FETCH_FIFO_HIWATER(x) ((x) << 8)
689 #define DONE_FIFO_HIWATER(x) ((x) << 16)
690 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
692 #define SX_DEBUG_1 0x9058
693 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
694 #define SX_EXPORT_BUFFER_SIZES 0x900C
695 #define COLOR_BUFFER_SIZE(x) ((x) << 0)
696 #define POSITION_BUFFER_SIZE(x) ((x) << 8)
697 #define SMX_BUFFER_SIZE(x) ((x) << 16)
698 #define SX_MEMORY_EXPORT_BASE 0x9010
699 #define SX_MISC 0x28350
701 #define CB_PERF_CTR0_SEL_0 0x9A20
702 #define CB_PERF_CTR0_SEL_1 0x9A24
703 #define CB_PERF_CTR1_SEL_0 0x9A28
704 #define CB_PERF_CTR1_SEL_1 0x9A2C
705 #define CB_PERF_CTR2_SEL_0 0x9A30
706 #define CB_PERF_CTR2_SEL_1 0x9A34
707 #define CB_PERF_CTR3_SEL_0 0x9A38
708 #define CB_PERF_CTR3_SEL_1 0x9A3C
710 #define TA_CNTL_AUX 0x9508
711 #define DISABLE_CUBE_WRAP (1 << 0)
712 #define DISABLE_CUBE_ANISO (1 << 1)
713 #define SYNC_GRADIENT (1 << 24)
714 #define SYNC_WALKER (1 << 25)
715 #define SYNC_ALIGNER (1 << 26)
717 #define TCP_CHAN_STEER_LO 0x960c
718 #define TCP_CHAN_STEER_HI 0x9610
720 #define VGT_CACHE_INVALIDATION 0x88C4
721 #define CACHE_INVALIDATION(x) ((x) << 0)
725 #define AUTO_INVLD_EN(x) ((x) << 6)
729 #define ES_AND_GS_AUTO 3
730 #define VGT_GS_VERTEX_REUSE 0x88D4
731 #define VGT_NUM_INSTANCES 0x8974
732 #define VGT_OUT_DEALLOC_CNTL 0x28C5C
733 #define DEALLOC_DIST_MASK 0x0000007F
734 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
735 #define VTX_REUSE_DEPTH_MASK 0x000000FF
737 #define VM_CONTEXT0_CNTL 0x1410
738 #define ENABLE_CONTEXT (1 << 0)
739 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
740 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
741 #define VM_CONTEXT1_CNTL 0x1414
742 #define VM_CONTEXT1_CNTL2 0x1434
743 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
744 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
745 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
746 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
747 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
748 #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
749 #define RESPONSE_TYPE_MASK 0x000000F0
750 #define RESPONSE_TYPE_SHIFT 4
751 #define VM_L2_CNTL 0x1400
752 #define ENABLE_L2_CACHE (1 << 0)
753 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
754 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
755 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
756 #define VM_L2_CNTL2 0x1404
757 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
758 #define INVALIDATE_L2_CACHE (1 << 1)
759 #define VM_L2_CNTL3 0x1408
760 #define BANK_SELECT(x) ((x) << 0)
761 #define CACHE_UPDATE_MODE(x) ((x) << 6)
762 #define VM_L2_STATUS 0x140C
763 #define L2_BUSY (1 << 0)
764 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
765 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
767 #define WAIT_UNTIL 0x8040
769 #define SRBM_STATUS 0x0E50
770 #define RLC_RQ_PENDING (1 << 3)
771 #define GRBM_RQ_PENDING (1 << 5)
772 #define VMC_BUSY (1 << 8)
773 #define MCB_BUSY (1 << 9)
774 #define MCB_NON_DISPLAY_BUSY (1 << 10)
775 #define MCC_BUSY (1 << 11)
776 #define MCD_BUSY (1 << 12)
777 #define SEM_BUSY (1 << 14)
778 #define RLC_BUSY (1 << 15)
779 #define IH_BUSY (1 << 17)
780 #define SRBM_STATUS2 0x0EC4
781 #define DMA_BUSY (1 << 5)
782 #define SRBM_SOFT_RESET 0x0E60
783 #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
784 #define SOFT_RESET_BIF (1 << 1)
785 #define SOFT_RESET_CG (1 << 2)
786 #define SOFT_RESET_DC (1 << 5)
787 #define SOFT_RESET_GRBM (1 << 8)
788 #define SOFT_RESET_HDP (1 << 9)
789 #define SOFT_RESET_IH (1 << 10)
790 #define SOFT_RESET_MC (1 << 11)
791 #define SOFT_RESET_RLC (1 << 13)
792 #define SOFT_RESET_ROM (1 << 14)
793 #define SOFT_RESET_SEM (1 << 15)
794 #define SOFT_RESET_VMC (1 << 17)
795 #define SOFT_RESET_DMA (1 << 20)
796 #define SOFT_RESET_TST (1 << 21)
797 #define SOFT_RESET_REGBB (1 << 22)
798 #define SOFT_RESET_ORB (1 << 23)
800 /* display watermarks */
801 #define DC_LB_MEMORY_SPLIT 0x6b0c
802 #define PRIORITY_A_CNT 0x6b18
803 #define PRIORITY_MARK_MASK 0x7fff
804 #define PRIORITY_OFF (1 << 16)
805 #define PRIORITY_ALWAYS_ON (1 << 20)
806 #define PRIORITY_B_CNT 0x6b1c
807 #define PIPE0_ARBITRATION_CONTROL3 0x0bf0
808 # define LATENCY_WATERMARK_MASK(x) ((x) << 16)
809 #define PIPE0_LATENCY_CONTROL 0x0bf4
810 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
811 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
813 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
814 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
815 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
817 #define IH_RB_CNTL 0x3e00
818 # define IH_RB_ENABLE (1 << 0)
819 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
820 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
821 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
822 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
823 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
824 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
825 #define IH_RB_BASE 0x3e04
826 #define IH_RB_RPTR 0x3e08
827 #define IH_RB_WPTR 0x3e0c
828 # define RB_OVERFLOW (1 << 0)
829 # define WPTR_OFFSET_MASK 0x3fffc
830 #define IH_RB_WPTR_ADDR_HI 0x3e10
831 #define IH_RB_WPTR_ADDR_LO 0x3e14
832 #define IH_CNTL 0x3e18
833 # define ENABLE_INTR (1 << 0)
834 # define IH_MC_SWAP(x) ((x) << 1)
835 # define IH_MC_SWAP_NONE 0
836 # define IH_MC_SWAP_16BIT 1
837 # define IH_MC_SWAP_32BIT 2
838 # define IH_MC_SWAP_64BIT 3
839 # define RPTR_REARM (1 << 4)
840 # define MC_WRREQ_CREDIT(x) ((x) << 15)
841 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
843 #define CP_INT_CNTL 0xc124
844 # define CNTX_BUSY_INT_ENABLE (1 << 19)
845 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
846 # define SCRATCH_INT_ENABLE (1 << 25)
847 # define TIME_STAMP_INT_ENABLE (1 << 26)
848 # define IB2_INT_ENABLE (1 << 29)
849 # define IB1_INT_ENABLE (1 << 30)
850 # define RB_INT_ENABLE (1 << 31)
851 #define CP_INT_STATUS 0xc128
852 # define SCRATCH_INT_STAT (1 << 25)
853 # define TIME_STAMP_INT_STAT (1 << 26)
854 # define IB2_INT_STAT (1 << 29)
855 # define IB1_INT_STAT (1 << 30)
856 # define RB_INT_STAT (1 << 31)
858 #define GRBM_INT_CNTL 0x8060
859 # define RDERR_INT_ENABLE (1 << 0)
860 # define GUI_IDLE_INT_ENABLE (1 << 19)
862 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
863 #define CRTC_STATUS_FRAME_COUNT 0x6e98
865 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
866 #define VLINE_STATUS 0x6bb8
867 # define VLINE_OCCURRED (1 << 0)
868 # define VLINE_ACK (1 << 4)
869 # define VLINE_STAT (1 << 12)
870 # define VLINE_INTERRUPT (1 << 16)
871 # define VLINE_INTERRUPT_TYPE (1 << 17)
872 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
873 #define VBLANK_STATUS 0x6bbc
874 # define VBLANK_OCCURRED (1 << 0)
875 # define VBLANK_ACK (1 << 4)
876 # define VBLANK_STAT (1 << 12)
877 # define VBLANK_INTERRUPT (1 << 16)
878 # define VBLANK_INTERRUPT_TYPE (1 << 17)
880 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
881 #define INT_MASK 0x6b40
882 # define VBLANK_INT_MASK (1 << 0)
883 # define VLINE_INT_MASK (1 << 4)
885 #define DISP_INTERRUPT_STATUS 0x60f4
886 # define LB_D1_VLINE_INTERRUPT (1 << 2)
887 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
888 # define DC_HPD1_INTERRUPT (1 << 17)
889 # define DC_HPD1_RX_INTERRUPT (1 << 18)
890 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
891 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
892 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
893 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
894 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
895 # define LB_D2_VLINE_INTERRUPT (1 << 2)
896 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
897 # define DC_HPD2_INTERRUPT (1 << 17)
898 # define DC_HPD2_RX_INTERRUPT (1 << 18)
899 # define DISP_TIMER_INTERRUPT (1 << 24)
900 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
901 # define LB_D3_VLINE_INTERRUPT (1 << 2)
902 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
903 # define DC_HPD3_INTERRUPT (1 << 17)
904 # define DC_HPD3_RX_INTERRUPT (1 << 18)
905 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
906 # define LB_D4_VLINE_INTERRUPT (1 << 2)
907 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
908 # define DC_HPD4_INTERRUPT (1 << 17)
909 # define DC_HPD4_RX_INTERRUPT (1 << 18)
910 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
911 # define LB_D5_VLINE_INTERRUPT (1 << 2)
912 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
913 # define DC_HPD5_INTERRUPT (1 << 17)
914 # define DC_HPD5_RX_INTERRUPT (1 << 18)
915 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
916 # define LB_D6_VLINE_INTERRUPT (1 << 2)
917 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
918 # define DC_HPD6_INTERRUPT (1 << 17)
919 # define DC_HPD6_RX_INTERRUPT (1 << 18)
921 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
922 #define GRPH_INT_STATUS 0x6858
923 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
924 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
925 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
926 #define GRPH_INT_CONTROL 0x685c
927 # define GRPH_PFLIP_INT_MASK (1 << 0)
928 # define GRPH_PFLIP_INT_TYPE (1 << 8)
930 #define DACA_AUTODETECT_INT_CONTROL 0x66c8
931 #define DACB_AUTODETECT_INT_CONTROL 0x67c8
933 #define DC_HPD1_INT_STATUS 0x601c
934 #define DC_HPD2_INT_STATUS 0x6028
935 #define DC_HPD3_INT_STATUS 0x6034
936 #define DC_HPD4_INT_STATUS 0x6040
937 #define DC_HPD5_INT_STATUS 0x604c
938 #define DC_HPD6_INT_STATUS 0x6058
939 # define DC_HPDx_INT_STATUS (1 << 0)
940 # define DC_HPDx_SENSE (1 << 1)
941 # define DC_HPDx_RX_INT_STATUS (1 << 8)
943 #define DC_HPD1_INT_CONTROL 0x6020
944 #define DC_HPD2_INT_CONTROL 0x602c
945 #define DC_HPD3_INT_CONTROL 0x6038
946 #define DC_HPD4_INT_CONTROL 0x6044
947 #define DC_HPD5_INT_CONTROL 0x6050
948 #define DC_HPD6_INT_CONTROL 0x605c
949 # define DC_HPDx_INT_ACK (1 << 0)
950 # define DC_HPDx_INT_POLARITY (1 << 8)
951 # define DC_HPDx_INT_EN (1 << 16)
952 # define DC_HPDx_RX_INT_ACK (1 << 20)
953 # define DC_HPDx_RX_INT_EN (1 << 24)
955 #define DC_HPD1_CONTROL 0x6024
956 #define DC_HPD2_CONTROL 0x6030
957 #define DC_HPD3_CONTROL 0x603c
958 #define DC_HPD4_CONTROL 0x6048
959 #define DC_HPD5_CONTROL 0x6054
960 #define DC_HPD6_CONTROL 0x6060
961 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
962 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
963 # define DC_HPDx_EN (1 << 28)
966 #define DMA_RB_RPTR 0xd008
967 #define DMA_RB_WPTR 0xd00c
969 #define DMA_CNTL 0xd02c
970 # define TRAP_ENABLE (1 << 0)
971 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
972 # define SEM_WAIT_INT_ENABLE (1 << 2)
973 # define DATA_SWAP_ENABLE (1 << 3)
974 # define FENCE_SWAP_ENABLE (1 << 4)
975 # define CTXEMPTY_INT_ENABLE (1 << 28)
976 #define DMA_TILING_CONFIG 0xD0B8
978 #define CAYMAN_DMA1_CNTL 0xd82c
980 /* async DMA packets */
981 #define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \
982 (((sub_cmd) & 0xFF) << 20) |\
983 (((n) & 0xFFFFF) << 0))
984 #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
985 #define GET_DMA_COUNT(h) ((h) & 0x000fffff)
986 #define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20)
988 /* async DMA Packet types */
989 #define DMA_PACKET_WRITE 0x2
990 #define DMA_PACKET_COPY 0x3
991 #define DMA_PACKET_INDIRECT_BUFFER 0x4
992 #define DMA_PACKET_SEMAPHORE 0x5
993 #define DMA_PACKET_FENCE 0x6
994 #define DMA_PACKET_TRAP 0x7
995 #define DMA_PACKET_SRBM_WRITE 0x9
996 #define DMA_PACKET_CONSTANT_FILL 0xd
997 #define DMA_PACKET_NOP 0xf
999 /* PCIE link stuff */
1000 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
1001 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
1002 # define LC_LINK_WIDTH_SHIFT 0
1003 # define LC_LINK_WIDTH_MASK 0x7
1004 # define LC_LINK_WIDTH_X0 0
1005 # define LC_LINK_WIDTH_X1 1
1006 # define LC_LINK_WIDTH_X2 2
1007 # define LC_LINK_WIDTH_X4 3
1008 # define LC_LINK_WIDTH_X8 4
1009 # define LC_LINK_WIDTH_X16 6
1010 # define LC_LINK_WIDTH_RD_SHIFT 4
1011 # define LC_LINK_WIDTH_RD_MASK 0x70
1012 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1013 # define LC_RECONFIG_NOW (1 << 8)
1014 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
1015 # define LC_RENEGOTIATE_EN (1 << 10)
1016 # define LC_SHORT_RECONFIG_EN (1 << 11)
1017 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
1018 # define LC_UPCONFIGURE_DIS (1 << 13)
1019 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
1020 # define LC_GEN2_EN_STRAP (1 << 0)
1021 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
1022 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
1023 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
1024 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
1025 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
1026 # define LC_CURRENT_DATA_RATE (1 << 11)
1027 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
1028 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
1029 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
1030 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
1031 #define MM_CFGREGS_CNTL 0x544c
1032 # define MM_WR_TO_CFG_EN (1 << 3)
1033 #define LINK_CNTL2 0x88 /* F0 */
1034 # define TARGET_LINK_SPEED_MASK (0xf << 0)
1035 # define SELECTABLE_DEEMPHASIS (1 << 6)
1041 #define UVD_UDEC_ADDR_CONFIG 0xef4c
1042 #define UVD_UDEC_DB_ADDR_CONFIG 0xef50
1043 #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
1044 #define UVD_RBC_RB_RPTR 0xf690
1045 #define UVD_RBC_RB_WPTR 0xf694
1050 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
1051 (((reg) >> 2) & 0xFFFF) | \
1052 ((n) & 0x3FFF) << 16)
1053 #define CP_PACKET2 0x80000000
1054 #define PACKET2_PAD_SHIFT 0
1055 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1057 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1059 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1060 (((op) & 0xFF) << 8) | \
1061 ((n) & 0x3FFF) << 16)
1063 /* Packet 3 types */
1064 #define PACKET3_NOP 0x10
1065 #define PACKET3_SET_BASE 0x11
1066 #define PACKET3_CLEAR_STATE 0x12
1067 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1068 #define PACKET3_DISPATCH_DIRECT 0x15
1069 #define PACKET3_DISPATCH_INDIRECT 0x16
1070 #define PACKET3_INDIRECT_BUFFER_END 0x17
1071 #define PACKET3_MODE_CONTROL 0x18
1072 #define PACKET3_SET_PREDICATION 0x20
1073 #define PACKET3_REG_RMW 0x21
1074 #define PACKET3_COND_EXEC 0x22
1075 #define PACKET3_PRED_EXEC 0x23
1076 #define PACKET3_DRAW_INDIRECT 0x24
1077 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1078 #define PACKET3_INDEX_BASE 0x26
1079 #define PACKET3_DRAW_INDEX_2 0x27
1080 #define PACKET3_CONTEXT_CONTROL 0x28
1081 #define PACKET3_DRAW_INDEX_OFFSET 0x29
1082 #define PACKET3_INDEX_TYPE 0x2A
1083 #define PACKET3_DRAW_INDEX 0x2B
1084 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1085 #define PACKET3_DRAW_INDEX_IMMD 0x2E
1086 #define PACKET3_NUM_INSTANCES 0x2F
1087 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1088 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1089 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1090 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1091 #define PACKET3_MEM_SEMAPHORE 0x39
1092 #define PACKET3_MPEG_INDEX 0x3A
1093 #define PACKET3_COPY_DW 0x3B
1094 #define PACKET3_WAIT_REG_MEM 0x3C
1095 #define PACKET3_MEM_WRITE 0x3D
1096 #define PACKET3_INDIRECT_BUFFER 0x32
1097 #define PACKET3_CP_DMA 0x41
1099 * 2. SRC_ADDR_LO or DATA [31:0]
1100 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
1102 * 4. DST_ADDR_LO [31:0]
1103 * 5. DST_ADDR_HI [7:0]
1104 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
1106 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1110 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
1114 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
1119 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1121 # define PACKET3_CP_DMA_DIS_WC (1 << 21)
1122 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
1128 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1134 # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1138 # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1142 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1143 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1144 #define PACKET3_SURFACE_SYNC 0x43
1145 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1146 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1147 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1148 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1149 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1150 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1151 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1152 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1153 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1154 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
1155 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
1156 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
1157 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
1158 # define PACKET3_FULL_CACHE_ENA (1 << 20)
1159 # define PACKET3_TC_ACTION_ENA (1 << 23)
1160 # define PACKET3_VC_ACTION_ENA (1 << 24)
1161 # define PACKET3_CB_ACTION_ENA (1 << 25)
1162 # define PACKET3_DB_ACTION_ENA (1 << 26)
1163 # define PACKET3_SH_ACTION_ENA (1 << 27)
1164 # define PACKET3_SX_ACTION_ENA (1 << 28)
1165 #define PACKET3_ME_INITIALIZE 0x44
1166 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1167 #define PACKET3_COND_WRITE 0x45
1168 #define PACKET3_EVENT_WRITE 0x46
1169 #define PACKET3_EVENT_WRITE_EOP 0x47
1170 #define PACKET3_EVENT_WRITE_EOS 0x48
1171 #define PACKET3_PREAMBLE_CNTL 0x4A
1172 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1173 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1174 #define PACKET3_RB_OFFSET 0x4B
1175 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
1176 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
1177 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E
1178 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F
1179 #define PACKET3_ONE_REG_WRITE 0x57
1180 #define PACKET3_SET_CONFIG_REG 0x68
1181 #define PACKET3_SET_CONFIG_REG_START 0x00008000
1182 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00
1183 #define PACKET3_SET_CONTEXT_REG 0x69
1184 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
1185 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1186 #define PACKET3_SET_ALU_CONST 0x6A
1187 /* alu const buffers only; no reg file */
1188 #define PACKET3_SET_BOOL_CONST 0x6B
1189 #define PACKET3_SET_BOOL_CONST_START 0x0003a500
1190 #define PACKET3_SET_BOOL_CONST_END 0x0003a518
1191 #define PACKET3_SET_LOOP_CONST 0x6C
1192 #define PACKET3_SET_LOOP_CONST_START 0x0003a200
1193 #define PACKET3_SET_LOOP_CONST_END 0x0003a500
1194 #define PACKET3_SET_RESOURCE 0x6D
1195 #define PACKET3_SET_RESOURCE_START 0x00030000
1196 #define PACKET3_SET_RESOURCE_END 0x00038000
1197 #define PACKET3_SET_SAMPLER 0x6E
1198 #define PACKET3_SET_SAMPLER_START 0x0003c000
1199 #define PACKET3_SET_SAMPLER_END 0x0003c600
1200 #define PACKET3_SET_CTL_CONST 0x6F
1201 #define PACKET3_SET_CTL_CONST_START 0x0003cff0
1202 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c
1203 #define PACKET3_SET_RESOURCE_OFFSET 0x70
1204 #define PACKET3_SET_ALU_CONST_VS 0x71
1205 #define PACKET3_SET_ALU_CONST_DI 0x72
1206 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1207 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
1208 #define PACKET3_SET_APPEND_CNT 0x75
1210 #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c
1211 #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)
1212 #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)
1213 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0
1214 #define SQ_TEX_VTX_INVALID_BUFFER 0x1
1215 #define SQ_TEX_VTX_VALID_TEXTURE 0x2
1216 #define SQ_TEX_VTX_VALID_BUFFER 0x3
1218 #define VGT_VTX_VECT_EJECT_REG 0x88b0
1220 #define SQ_CONST_MEM_BASE 0x8df8
1222 #define SQ_ESGS_RING_BASE 0x8c40
1223 #define SQ_ESGS_RING_SIZE 0x8c44
1224 #define SQ_GSVS_RING_BASE 0x8c48
1225 #define SQ_GSVS_RING_SIZE 0x8c4c
1226 #define SQ_ESTMP_RING_BASE 0x8c50
1227 #define SQ_ESTMP_RING_SIZE 0x8c54
1228 #define SQ_GSTMP_RING_BASE 0x8c58
1229 #define SQ_GSTMP_RING_SIZE 0x8c5c
1230 #define SQ_VSTMP_RING_BASE 0x8c60
1231 #define SQ_VSTMP_RING_SIZE 0x8c64
1232 #define SQ_PSTMP_RING_BASE 0x8c68
1233 #define SQ_PSTMP_RING_SIZE 0x8c6c
1234 #define SQ_LSTMP_RING_BASE 0x8e10
1235 #define SQ_LSTMP_RING_SIZE 0x8e14
1236 #define SQ_HSTMP_RING_BASE 0x8e18
1237 #define SQ_HSTMP_RING_SIZE 0x8e1c
1238 #define VGT_TF_RING_SIZE 0x8988
1240 #define SQ_ESGS_RING_ITEMSIZE 0x28900
1241 #define SQ_GSVS_RING_ITEMSIZE 0x28904
1242 #define SQ_ESTMP_RING_ITEMSIZE 0x28908
1243 #define SQ_GSTMP_RING_ITEMSIZE 0x2890c
1244 #define SQ_VSTMP_RING_ITEMSIZE 0x28910
1245 #define SQ_PSTMP_RING_ITEMSIZE 0x28914
1246 #define SQ_LSTMP_RING_ITEMSIZE 0x28830
1247 #define SQ_HSTMP_RING_ITEMSIZE 0x28834
1249 #define SQ_GS_VERT_ITEMSIZE 0x2891c
1250 #define SQ_GS_VERT_ITEMSIZE_1 0x28920
1251 #define SQ_GS_VERT_ITEMSIZE_2 0x28924
1252 #define SQ_GS_VERT_ITEMSIZE_3 0x28928
1253 #define SQ_GSVS_RING_OFFSET_1 0x2892c
1254 #define SQ_GSVS_RING_OFFSET_2 0x28930
1255 #define SQ_GSVS_RING_OFFSET_3 0x28934
1257 #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140
1258 #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80
1260 #define SQ_ALU_CONST_CACHE_PS_0 0x28940
1261 #define SQ_ALU_CONST_CACHE_PS_1 0x28944
1262 #define SQ_ALU_CONST_CACHE_PS_2 0x28948
1263 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c
1264 #define SQ_ALU_CONST_CACHE_PS_4 0x28950
1265 #define SQ_ALU_CONST_CACHE_PS_5 0x28954
1266 #define SQ_ALU_CONST_CACHE_PS_6 0x28958
1267 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c
1268 #define SQ_ALU_CONST_CACHE_PS_8 0x28960
1269 #define SQ_ALU_CONST_CACHE_PS_9 0x28964
1270 #define SQ_ALU_CONST_CACHE_PS_10 0x28968
1271 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c
1272 #define SQ_ALU_CONST_CACHE_PS_12 0x28970
1273 #define SQ_ALU_CONST_CACHE_PS_13 0x28974
1274 #define SQ_ALU_CONST_CACHE_PS_14 0x28978
1275 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c
1276 #define SQ_ALU_CONST_CACHE_VS_0 0x28980
1277 #define SQ_ALU_CONST_CACHE_VS_1 0x28984
1278 #define SQ_ALU_CONST_CACHE_VS_2 0x28988
1279 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c
1280 #define SQ_ALU_CONST_CACHE_VS_4 0x28990
1281 #define SQ_ALU_CONST_CACHE_VS_5 0x28994
1282 #define SQ_ALU_CONST_CACHE_VS_6 0x28998
1283 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c
1284 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0
1285 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4
1286 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8
1287 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac
1288 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0
1289 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4
1290 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8
1291 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc
1292 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0
1293 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4
1294 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8
1295 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc
1296 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0
1297 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4
1298 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8
1299 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc
1300 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0
1301 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4
1302 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8
1303 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec
1304 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0
1305 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4
1306 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8
1307 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc
1308 #define SQ_ALU_CONST_CACHE_HS_0 0x28f00
1309 #define SQ_ALU_CONST_CACHE_HS_1 0x28f04
1310 #define SQ_ALU_CONST_CACHE_HS_2 0x28f08
1311 #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c
1312 #define SQ_ALU_CONST_CACHE_HS_4 0x28f10
1313 #define SQ_ALU_CONST_CACHE_HS_5 0x28f14
1314 #define SQ_ALU_CONST_CACHE_HS_6 0x28f18
1315 #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c
1316 #define SQ_ALU_CONST_CACHE_HS_8 0x28f20
1317 #define SQ_ALU_CONST_CACHE_HS_9 0x28f24
1318 #define SQ_ALU_CONST_CACHE_HS_10 0x28f28
1319 #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c
1320 #define SQ_ALU_CONST_CACHE_HS_12 0x28f30
1321 #define SQ_ALU_CONST_CACHE_HS_13 0x28f34
1322 #define SQ_ALU_CONST_CACHE_HS_14 0x28f38
1323 #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c
1324 #define SQ_ALU_CONST_CACHE_LS_0 0x28f40
1325 #define SQ_ALU_CONST_CACHE_LS_1 0x28f44
1326 #define SQ_ALU_CONST_CACHE_LS_2 0x28f48
1327 #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c
1328 #define SQ_ALU_CONST_CACHE_LS_4 0x28f50
1329 #define SQ_ALU_CONST_CACHE_LS_5 0x28f54
1330 #define SQ_ALU_CONST_CACHE_LS_6 0x28f58
1331 #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c
1332 #define SQ_ALU_CONST_CACHE_LS_8 0x28f60
1333 #define SQ_ALU_CONST_CACHE_LS_9 0x28f64
1334 #define SQ_ALU_CONST_CACHE_LS_10 0x28f68
1335 #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c
1336 #define SQ_ALU_CONST_CACHE_LS_12 0x28f70
1337 #define SQ_ALU_CONST_CACHE_LS_13 0x28f74
1338 #define SQ_ALU_CONST_CACHE_LS_14 0x28f78
1339 #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c
1341 #define PA_SC_SCREEN_SCISSOR_TL 0x28030
1342 #define PA_SC_GENERIC_SCISSOR_TL 0x28240
1343 #define PA_SC_WINDOW_SCISSOR_TL 0x28204
1345 #define VGT_PRIMITIVE_TYPE 0x8958
1346 #define VGT_INDEX_TYPE 0x895C
1348 #define VGT_NUM_INDICES 0x8970
1350 #define VGT_COMPUTE_DIM_X 0x8990
1351 #define VGT_COMPUTE_DIM_Y 0x8994
1352 #define VGT_COMPUTE_DIM_Z 0x8998
1353 #define VGT_COMPUTE_START_X 0x899C
1354 #define VGT_COMPUTE_START_Y 0x89A0
1355 #define VGT_COMPUTE_START_Z 0x89A4
1356 #define VGT_COMPUTE_INDEX 0x89A8
1357 #define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC
1358 #define VGT_HS_OFFCHIP_PARAM 0x89B0
1360 #define DB_DEBUG 0x9830
1361 #define DB_DEBUG2 0x9834
1362 #define DB_DEBUG3 0x9838
1363 #define DB_DEBUG4 0x983C
1364 #define DB_WATERMARKS 0x9854
1365 #define DB_DEPTH_CONTROL 0x28800
1366 #define R_028800_DB_DEPTH_CONTROL 0x028800
1367 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
1368 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
1369 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE
1370 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
1371 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
1372 #define C_028800_Z_ENABLE 0xFFFFFFFD
1373 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
1374 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
1375 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
1376 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
1377 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
1378 #define C_028800_ZFUNC 0xFFFFFF8F
1379 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
1380 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
1381 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
1382 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
1383 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
1384 #define C_028800_STENCILFUNC 0xFFFFF8FF
1385 #define V_028800_STENCILFUNC_NEVER 0x00000000
1386 #define V_028800_STENCILFUNC_LESS 0x00000001
1387 #define V_028800_STENCILFUNC_EQUAL 0x00000002
1388 #define V_028800_STENCILFUNC_LEQUAL 0x00000003
1389 #define V_028800_STENCILFUNC_GREATER 0x00000004
1390 #define V_028800_STENCILFUNC_NOTEQUAL 0x00000005
1391 #define V_028800_STENCILFUNC_GEQUAL 0x00000006
1392 #define V_028800_STENCILFUNC_ALWAYS 0x00000007
1393 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
1394 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
1395 #define C_028800_STENCILFAIL 0xFFFFC7FF
1396 #define V_028800_STENCIL_KEEP 0x00000000
1397 #define V_028800_STENCIL_ZERO 0x00000001
1398 #define V_028800_STENCIL_REPLACE 0x00000002
1399 #define V_028800_STENCIL_INCR 0x00000003
1400 #define V_028800_STENCIL_DECR 0x00000004
1401 #define V_028800_STENCIL_INVERT 0x00000005
1402 #define V_028800_STENCIL_INCR_WRAP 0x00000006
1403 #define V_028800_STENCIL_DECR_WRAP 0x00000007
1404 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
1405 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
1406 #define C_028800_STENCILZPASS 0xFFFE3FFF
1407 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
1408 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
1409 #define C_028800_STENCILZFAIL 0xFFF1FFFF
1410 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
1411 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
1412 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF
1413 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
1414 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
1415 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF
1416 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
1417 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
1418 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF
1419 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
1420 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
1421 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF
1422 #define DB_DEPTH_VIEW 0x28008
1423 #define R_028008_DB_DEPTH_VIEW 0x00028008
1424 #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0)
1425 #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF)
1426 #define C_028008_SLICE_START 0xFFFFF800
1427 #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1428 #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1429 #define C_028008_SLICE_MAX 0xFF001FFF
1430 #define DB_HTILE_DATA_BASE 0x28014
1431 #define DB_HTILE_SURFACE 0x28abc
1432 #define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0)
1433 #define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
1434 #define C_028ABC_HTILE_WIDTH 0xFFFFFFFE
1435 #define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
1436 #define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
1437 #define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD
1438 #define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1)
1439 #define DB_Z_INFO 0x28040
1440 # define Z_ARRAY_MODE(x) ((x) << 4)
1441 # define DB_TILE_SPLIT(x) (((x) & 0x7) << 8)
1442 # define DB_NUM_BANKS(x) (((x) & 0x3) << 12)
1443 # define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)
1444 # define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)
1445 # define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1446 #define R_028040_DB_Z_INFO 0x028040
1447 #define S_028040_FORMAT(x) (((x) & 0x3) << 0)
1448 #define G_028040_FORMAT(x) (((x) >> 0) & 0x3)
1449 #define C_028040_FORMAT 0xFFFFFFFC
1450 #define V_028040_Z_INVALID 0x00000000
1451 #define V_028040_Z_16 0x00000001
1452 #define V_028040_Z_24 0x00000002
1453 #define V_028040_Z_32_FLOAT 0x00000003
1454 #define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4)
1455 #define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF)
1456 #define C_028040_ARRAY_MODE 0xFFFFFF0F
1457 #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28)
1458 #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1)
1459 #define C_028040_READ_SIZE 0xEFFFFFFF
1460 #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29)
1461 #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1)
1462 #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF
1463 #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
1464 #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
1465 #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF
1466 #define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8)
1467 #define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1468 #define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12)
1469 #define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3)
1470 #define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16)
1471 #define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3)
1472 #define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20)
1473 #define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3)
1474 #define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1475 #define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3)
1476 #define DB_STENCIL_INFO 0x28044
1477 #define R_028044_DB_STENCIL_INFO 0x028044
1478 #define S_028044_FORMAT(x) (((x) & 0x1) << 0)
1479 #define G_028044_FORMAT(x) (((x) >> 0) & 0x1)
1480 #define C_028044_FORMAT 0xFFFFFFFE
1481 #define V_028044_STENCIL_INVALID 0
1482 #define V_028044_STENCIL_8 1
1483 #define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1484 #define DB_Z_READ_BASE 0x28048
1485 #define DB_STENCIL_READ_BASE 0x2804c
1486 #define DB_Z_WRITE_BASE 0x28050
1487 #define DB_STENCIL_WRITE_BASE 0x28054
1488 #define DB_DEPTH_SIZE 0x28058
1489 #define R_028058_DB_DEPTH_SIZE 0x028058
1490 #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0)
1491 #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF)
1492 #define C_028058_PITCH_TILE_MAX 0xFFFFF800
1493 #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11)
1494 #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF)
1495 #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF
1496 #define R_02805C_DB_DEPTH_SLICE 0x02805C
1497 #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
1498 #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
1499 #define C_02805C_SLICE_TILE_MAX 0xFFC00000
1501 #define SQ_PGM_START_PS 0x28840
1502 #define SQ_PGM_START_VS 0x2885c
1503 #define SQ_PGM_START_GS 0x28874
1504 #define SQ_PGM_START_ES 0x2888c
1505 #define SQ_PGM_START_FS 0x288a4
1506 #define SQ_PGM_START_HS 0x288b8
1507 #define SQ_PGM_START_LS 0x288d0
1509 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
1510 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
1511 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
1512 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
1513 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0
1514 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0
1515 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0
1516 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00
1517 #define VGT_STRMOUT_CONFIG 0x28b94
1518 #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98
1520 #define CB_TARGET_MASK 0x28238
1521 #define CB_SHADER_MASK 0x2823c
1523 #define GDS_ADDR_BASE 0x28720
1525 #define CB_IMMED0_BASE 0x28b9c
1526 #define CB_IMMED1_BASE 0x28ba0
1527 #define CB_IMMED2_BASE 0x28ba4
1528 #define CB_IMMED3_BASE 0x28ba8
1529 #define CB_IMMED4_BASE 0x28bac
1530 #define CB_IMMED5_BASE 0x28bb0
1531 #define CB_IMMED6_BASE 0x28bb4
1532 #define CB_IMMED7_BASE 0x28bb8
1533 #define CB_IMMED8_BASE 0x28bbc
1534 #define CB_IMMED9_BASE 0x28bc0
1535 #define CB_IMMED10_BASE 0x28bc4
1536 #define CB_IMMED11_BASE 0x28bc8
1538 /* all 12 CB blocks have these regs */
1539 #define CB_COLOR0_BASE 0x28c60
1540 #define CB_COLOR0_PITCH 0x28c64
1541 #define CB_COLOR0_SLICE 0x28c68
1542 #define CB_COLOR0_VIEW 0x28c6c
1543 #define R_028C6C_CB_COLOR0_VIEW 0x00028C6C
1544 #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0)
1545 #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF)
1546 #define C_028C6C_SLICE_START 0xFFFFF800
1547 #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1548 #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1549 #define C_028C6C_SLICE_MAX 0xFF001FFF
1550 #define R_028C70_CB_COLOR0_INFO 0x028C70
1551 #define S_028C70_ENDIAN(x) (((x) & 0x3) << 0)
1552 #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3)
1553 #define C_028C70_ENDIAN 0xFFFFFFFC
1554 #define S_028C70_FORMAT(x) (((x) & 0x3F) << 2)
1555 #define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F)
1556 #define C_028C70_FORMAT 0xFFFFFF03
1557 #define V_028C70_COLOR_INVALID 0x00000000
1558 #define V_028C70_COLOR_8 0x00000001
1559 #define V_028C70_COLOR_4_4 0x00000002
1560 #define V_028C70_COLOR_3_3_2 0x00000003
1561 #define V_028C70_COLOR_16 0x00000005
1562 #define V_028C70_COLOR_16_FLOAT 0x00000006
1563 #define V_028C70_COLOR_8_8 0x00000007
1564 #define V_028C70_COLOR_5_6_5 0x00000008
1565 #define V_028C70_COLOR_6_5_5 0x00000009
1566 #define V_028C70_COLOR_1_5_5_5 0x0000000A
1567 #define V_028C70_COLOR_4_4_4_4 0x0000000B
1568 #define V_028C70_COLOR_5_5_5_1 0x0000000C
1569 #define V_028C70_COLOR_32 0x0000000D
1570 #define V_028C70_COLOR_32_FLOAT 0x0000000E
1571 #define V_028C70_COLOR_16_16 0x0000000F
1572 #define V_028C70_COLOR_16_16_FLOAT 0x00000010
1573 #define V_028C70_COLOR_8_24 0x00000011
1574 #define V_028C70_COLOR_8_24_FLOAT 0x00000012
1575 #define V_028C70_COLOR_24_8 0x00000013
1576 #define V_028C70_COLOR_24_8_FLOAT 0x00000014
1577 #define V_028C70_COLOR_10_11_11 0x00000015
1578 #define V_028C70_COLOR_10_11_11_FLOAT 0x00000016
1579 #define V_028C70_COLOR_11_11_10 0x00000017
1580 #define V_028C70_COLOR_11_11_10_FLOAT 0x00000018
1581 #define V_028C70_COLOR_2_10_10_10 0x00000019
1582 #define V_028C70_COLOR_8_8_8_8 0x0000001A
1583 #define V_028C70_COLOR_10_10_10_2 0x0000001B
1584 #define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C
1585 #define V_028C70_COLOR_32_32 0x0000001D
1586 #define V_028C70_COLOR_32_32_FLOAT 0x0000001E
1587 #define V_028C70_COLOR_16_16_16_16 0x0000001F
1588 #define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020
1589 #define V_028C70_COLOR_32_32_32_32 0x00000022
1590 #define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023
1591 #define V_028C70_COLOR_32_32_32_FLOAT 0x00000030
1592 #define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8)
1593 #define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF)
1594 #define C_028C70_ARRAY_MODE 0xFFFFF0FF
1595 #define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000
1596 #define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001
1597 #define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002
1598 #define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004
1599 #define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12)
1600 #define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
1601 #define C_028C70_NUMBER_TYPE 0xFFFF8FFF
1602 #define V_028C70_NUMBER_UNORM 0x00000000
1603 #define V_028C70_NUMBER_SNORM 0x00000001
1604 #define V_028C70_NUMBER_USCALED 0x00000002
1605 #define V_028C70_NUMBER_SSCALED 0x00000003
1606 #define V_028C70_NUMBER_UINT 0x00000004
1607 #define V_028C70_NUMBER_SINT 0x00000005
1608 #define V_028C70_NUMBER_SRGB 0x00000006
1609 #define V_028C70_NUMBER_FLOAT 0x00000007
1610 #define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15)
1611 #define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3)
1612 #define C_028C70_COMP_SWAP 0xFFFE7FFF
1613 #define V_028C70_SWAP_STD 0x00000000
1614 #define V_028C70_SWAP_ALT 0x00000001
1615 #define V_028C70_SWAP_STD_REV 0x00000002
1616 #define V_028C70_SWAP_ALT_REV 0x00000003
1617 #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17)
1618 #define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1)
1619 #define C_028C70_FAST_CLEAR 0xFFFDFFFF
1620 #define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18)
1621 #define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3)
1622 #define C_028C70_COMPRESSION 0xFFF3FFFF
1623 #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19)
1624 #define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1)
1625 #define C_028C70_BLEND_CLAMP 0xFFF7FFFF
1626 #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20)
1627 #define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1)
1628 #define C_028C70_BLEND_BYPASS 0xFFEFFFFF
1629 #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21)
1630 #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1)
1631 #define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF
1632 #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22)
1633 #define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1)
1634 #define C_028C70_ROUND_MODE 0xFFBFFFFF
1635 #define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23)
1636 #define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1)
1637 #define C_028C70_TILE_COMPACT 0xFF7FFFFF
1638 #define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24)
1639 #define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3)
1640 #define C_028C70_SOURCE_FORMAT 0xFCFFFFFF
1641 #define V_028C70_EXPORT_4C_32BPC 0x0
1642 #define V_028C70_EXPORT_4C_16BPC 0x1
1643 #define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */
1644 #define S_028C70_RAT(x) (((x) & 0x1) << 26)
1645 #define G_028C70_RAT(x) (((x) >> 26) & 0x1)
1646 #define C_028C70_RAT 0xFBFFFFFF
1647 #define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27)
1648 #define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7)
1649 #define C_028C70_RESOURCE_TYPE 0xC7FFFFFF
1651 #define CB_COLOR0_INFO 0x28c70
1652 # define CB_FORMAT(x) ((x) << 2)
1653 # define CB_ARRAY_MODE(x) ((x) << 8)
1654 # define ARRAY_LINEAR_GENERAL 0
1655 # define ARRAY_LINEAR_ALIGNED 1
1656 # define ARRAY_1D_TILED_THIN1 2
1657 # define ARRAY_2D_TILED_THIN1 4
1658 # define CB_SOURCE_FORMAT(x) ((x) << 24)
1659 # define CB_SF_EXPORT_FULL 0
1660 # define CB_SF_EXPORT_NORM 1
1661 #define R_028C74_CB_COLOR0_ATTRIB 0x028C74
1662 #define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4)
1663 #define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1)
1664 #define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF
1665 #define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5)
1666 #define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf)
1667 #define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10)
1668 #define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3)
1669 #define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13)
1670 #define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3)
1671 #define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16)
1672 #define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3)
1673 #define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
1674 #define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3)
1675 #define CB_COLOR0_ATTRIB 0x28c74
1676 # define CB_TILE_SPLIT(x) (((x) & 0x7) << 5)
1677 # define ADDR_SURF_TILE_SPLIT_64B 0
1678 # define ADDR_SURF_TILE_SPLIT_128B 1
1679 # define ADDR_SURF_TILE_SPLIT_256B 2
1680 # define ADDR_SURF_TILE_SPLIT_512B 3
1681 # define ADDR_SURF_TILE_SPLIT_1KB 4
1682 # define ADDR_SURF_TILE_SPLIT_2KB 5
1683 # define ADDR_SURF_TILE_SPLIT_4KB 6
1684 # define CB_NUM_BANKS(x) (((x) & 0x3) << 10)
1685 # define ADDR_SURF_2_BANK 0
1686 # define ADDR_SURF_4_BANK 1
1687 # define ADDR_SURF_8_BANK 2
1688 # define ADDR_SURF_16_BANK 3
1689 # define CB_BANK_WIDTH(x) (((x) & 0x3) << 13)
1690 # define ADDR_SURF_BANK_WIDTH_1 0
1691 # define ADDR_SURF_BANK_WIDTH_2 1
1692 # define ADDR_SURF_BANK_WIDTH_4 2
1693 # define ADDR_SURF_BANK_WIDTH_8 3
1694 # define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16)
1695 # define ADDR_SURF_BANK_HEIGHT_1 0
1696 # define ADDR_SURF_BANK_HEIGHT_2 1
1697 # define ADDR_SURF_BANK_HEIGHT_4 2
1698 # define ADDR_SURF_BANK_HEIGHT_8 3
1699 # define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
1700 #define CB_COLOR0_DIM 0x28c78
1701 /* only CB0-7 blocks have these regs */
1702 #define CB_COLOR0_CMASK 0x28c7c
1703 #define CB_COLOR0_CMASK_SLICE 0x28c80
1704 #define CB_COLOR0_FMASK 0x28c84
1705 #define CB_COLOR0_FMASK_SLICE 0x28c88
1706 #define CB_COLOR0_CLEAR_WORD0 0x28c8c
1707 #define CB_COLOR0_CLEAR_WORD1 0x28c90
1708 #define CB_COLOR0_CLEAR_WORD2 0x28c94
1709 #define CB_COLOR0_CLEAR_WORD3 0x28c98
1711 #define CB_COLOR1_BASE 0x28c9c
1712 #define CB_COLOR2_BASE 0x28cd8
1713 #define CB_COLOR3_BASE 0x28d14
1714 #define CB_COLOR4_BASE 0x28d50
1715 #define CB_COLOR5_BASE 0x28d8c
1716 #define CB_COLOR6_BASE 0x28dc8
1717 #define CB_COLOR7_BASE 0x28e04
1718 #define CB_COLOR8_BASE 0x28e40
1719 #define CB_COLOR9_BASE 0x28e5c
1720 #define CB_COLOR10_BASE 0x28e78
1721 #define CB_COLOR11_BASE 0x28e94
1723 #define CB_COLOR1_PITCH 0x28ca0
1724 #define CB_COLOR2_PITCH 0x28cdc
1725 #define CB_COLOR3_PITCH 0x28d18
1726 #define CB_COLOR4_PITCH 0x28d54
1727 #define CB_COLOR5_PITCH 0x28d90
1728 #define CB_COLOR6_PITCH 0x28dcc
1729 #define CB_COLOR7_PITCH 0x28e08
1730 #define CB_COLOR8_PITCH 0x28e44
1731 #define CB_COLOR9_PITCH 0x28e60
1732 #define CB_COLOR10_PITCH 0x28e7c
1733 #define CB_COLOR11_PITCH 0x28e98
1735 #define CB_COLOR1_SLICE 0x28ca4
1736 #define CB_COLOR2_SLICE 0x28ce0
1737 #define CB_COLOR3_SLICE 0x28d1c
1738 #define CB_COLOR4_SLICE 0x28d58
1739 #define CB_COLOR5_SLICE 0x28d94
1740 #define CB_COLOR6_SLICE 0x28dd0
1741 #define CB_COLOR7_SLICE 0x28e0c
1742 #define CB_COLOR8_SLICE 0x28e48
1743 #define CB_COLOR9_SLICE 0x28e64
1744 #define CB_COLOR10_SLICE 0x28e80
1745 #define CB_COLOR11_SLICE 0x28e9c
1747 #define CB_COLOR1_VIEW 0x28ca8
1748 #define CB_COLOR2_VIEW 0x28ce4
1749 #define CB_COLOR3_VIEW 0x28d20
1750 #define CB_COLOR4_VIEW 0x28d5c
1751 #define CB_COLOR5_VIEW 0x28d98
1752 #define CB_COLOR6_VIEW 0x28dd4
1753 #define CB_COLOR7_VIEW 0x28e10
1754 #define CB_COLOR8_VIEW 0x28e4c
1755 #define CB_COLOR9_VIEW 0x28e68
1756 #define CB_COLOR10_VIEW 0x28e84
1757 #define CB_COLOR11_VIEW 0x28ea0
1759 #define CB_COLOR1_INFO 0x28cac
1760 #define CB_COLOR2_INFO 0x28ce8
1761 #define CB_COLOR3_INFO 0x28d24
1762 #define CB_COLOR4_INFO 0x28d60
1763 #define CB_COLOR5_INFO 0x28d9c
1764 #define CB_COLOR6_INFO 0x28dd8
1765 #define CB_COLOR7_INFO 0x28e14
1766 #define CB_COLOR8_INFO 0x28e50
1767 #define CB_COLOR9_INFO 0x28e6c
1768 #define CB_COLOR10_INFO 0x28e88
1769 #define CB_COLOR11_INFO 0x28ea4
1771 #define CB_COLOR1_ATTRIB 0x28cb0
1772 #define CB_COLOR2_ATTRIB 0x28cec
1773 #define CB_COLOR3_ATTRIB 0x28d28
1774 #define CB_COLOR4_ATTRIB 0x28d64
1775 #define CB_COLOR5_ATTRIB 0x28da0
1776 #define CB_COLOR6_ATTRIB 0x28ddc
1777 #define CB_COLOR7_ATTRIB 0x28e18
1778 #define CB_COLOR8_ATTRIB 0x28e54
1779 #define CB_COLOR9_ATTRIB 0x28e70
1780 #define CB_COLOR10_ATTRIB 0x28e8c
1781 #define CB_COLOR11_ATTRIB 0x28ea8
1783 #define CB_COLOR1_DIM 0x28cb4
1784 #define CB_COLOR2_DIM 0x28cf0
1785 #define CB_COLOR3_DIM 0x28d2c
1786 #define CB_COLOR4_DIM 0x28d68
1787 #define CB_COLOR5_DIM 0x28da4
1788 #define CB_COLOR6_DIM 0x28de0
1789 #define CB_COLOR7_DIM 0x28e1c
1790 #define CB_COLOR8_DIM 0x28e58
1791 #define CB_COLOR9_DIM 0x28e74
1792 #define CB_COLOR10_DIM 0x28e90
1793 #define CB_COLOR11_DIM 0x28eac
1795 #define CB_COLOR1_CMASK 0x28cb8
1796 #define CB_COLOR2_CMASK 0x28cf4
1797 #define CB_COLOR3_CMASK 0x28d30
1798 #define CB_COLOR4_CMASK 0x28d6c
1799 #define CB_COLOR5_CMASK 0x28da8
1800 #define CB_COLOR6_CMASK 0x28de4
1801 #define CB_COLOR7_CMASK 0x28e20
1803 #define CB_COLOR1_CMASK_SLICE 0x28cbc
1804 #define CB_COLOR2_CMASK_SLICE 0x28cf8
1805 #define CB_COLOR3_CMASK_SLICE 0x28d34
1806 #define CB_COLOR4_CMASK_SLICE 0x28d70
1807 #define CB_COLOR5_CMASK_SLICE 0x28dac
1808 #define CB_COLOR6_CMASK_SLICE 0x28de8
1809 #define CB_COLOR7_CMASK_SLICE 0x28e24
1811 #define CB_COLOR1_FMASK 0x28cc0
1812 #define CB_COLOR2_FMASK 0x28cfc
1813 #define CB_COLOR3_FMASK 0x28d38
1814 #define CB_COLOR4_FMASK 0x28d74
1815 #define CB_COLOR5_FMASK 0x28db0
1816 #define CB_COLOR6_FMASK 0x28dec
1817 #define CB_COLOR7_FMASK 0x28e28
1819 #define CB_COLOR1_FMASK_SLICE 0x28cc4
1820 #define CB_COLOR2_FMASK_SLICE 0x28d00
1821 #define CB_COLOR3_FMASK_SLICE 0x28d3c
1822 #define CB_COLOR4_FMASK_SLICE 0x28d78
1823 #define CB_COLOR5_FMASK_SLICE 0x28db4
1824 #define CB_COLOR6_FMASK_SLICE 0x28df0
1825 #define CB_COLOR7_FMASK_SLICE 0x28e2c
1827 #define CB_COLOR1_CLEAR_WORD0 0x28cc8
1828 #define CB_COLOR2_CLEAR_WORD0 0x28d04
1829 #define CB_COLOR3_CLEAR_WORD0 0x28d40
1830 #define CB_COLOR4_CLEAR_WORD0 0x28d7c
1831 #define CB_COLOR5_CLEAR_WORD0 0x28db8
1832 #define CB_COLOR6_CLEAR_WORD0 0x28df4
1833 #define CB_COLOR7_CLEAR_WORD0 0x28e30
1835 #define CB_COLOR1_CLEAR_WORD1 0x28ccc
1836 #define CB_COLOR2_CLEAR_WORD1 0x28d08
1837 #define CB_COLOR3_CLEAR_WORD1 0x28d44
1838 #define CB_COLOR4_CLEAR_WORD1 0x28d80
1839 #define CB_COLOR5_CLEAR_WORD1 0x28dbc
1840 #define CB_COLOR6_CLEAR_WORD1 0x28df8
1841 #define CB_COLOR7_CLEAR_WORD1 0x28e34
1843 #define CB_COLOR1_CLEAR_WORD2 0x28cd0
1844 #define CB_COLOR2_CLEAR_WORD2 0x28d0c
1845 #define CB_COLOR3_CLEAR_WORD2 0x28d48
1846 #define CB_COLOR4_CLEAR_WORD2 0x28d84
1847 #define CB_COLOR5_CLEAR_WORD2 0x28dc0
1848 #define CB_COLOR6_CLEAR_WORD2 0x28dfc
1849 #define CB_COLOR7_CLEAR_WORD2 0x28e38
1851 #define CB_COLOR1_CLEAR_WORD3 0x28cd4
1852 #define CB_COLOR2_CLEAR_WORD3 0x28d10
1853 #define CB_COLOR3_CLEAR_WORD3 0x28d4c
1854 #define CB_COLOR4_CLEAR_WORD3 0x28d88
1855 #define CB_COLOR5_CLEAR_WORD3 0x28dc4
1856 #define CB_COLOR6_CLEAR_WORD3 0x28e00
1857 #define CB_COLOR7_CLEAR_WORD3 0x28e3c
1859 #define SQ_TEX_RESOURCE_WORD0_0 0x30000
1860 # define TEX_DIM(x) ((x) << 0)
1861 # define SQ_TEX_DIM_1D 0
1862 # define SQ_TEX_DIM_2D 1
1863 # define SQ_TEX_DIM_3D 2
1864 # define SQ_TEX_DIM_CUBEMAP 3
1865 # define SQ_TEX_DIM_1D_ARRAY 4
1866 # define SQ_TEX_DIM_2D_ARRAY 5
1867 # define SQ_TEX_DIM_2D_MSAA 6
1868 # define SQ_TEX_DIM_2D_ARRAY_MSAA 7
1869 #define SQ_TEX_RESOURCE_WORD1_0 0x30004
1870 # define TEX_ARRAY_MODE(x) ((x) << 28)
1871 #define SQ_TEX_RESOURCE_WORD2_0 0x30008
1872 #define SQ_TEX_RESOURCE_WORD3_0 0x3000C
1873 #define SQ_TEX_RESOURCE_WORD4_0 0x30010
1874 # define TEX_DST_SEL_X(x) ((x) << 16)
1875 # define TEX_DST_SEL_Y(x) ((x) << 19)
1876 # define TEX_DST_SEL_Z(x) ((x) << 22)
1877 # define TEX_DST_SEL_W(x) ((x) << 25)
1884 #define SQ_TEX_RESOURCE_WORD5_0 0x30014
1885 #define SQ_TEX_RESOURCE_WORD6_0 0x30018
1886 # define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)
1887 #define SQ_TEX_RESOURCE_WORD7_0 0x3001c
1888 # define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
1889 # define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)
1890 # define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)
1891 # define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)
1892 #define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000
1893 #define S_030000_DIM(x) (((x) & 0x7) << 0)
1894 #define G_030000_DIM(x) (((x) >> 0) & 0x7)
1895 #define C_030000_DIM 0xFFFFFFF8
1896 #define V_030000_SQ_TEX_DIM_1D 0x00000000
1897 #define V_030000_SQ_TEX_DIM_2D 0x00000001
1898 #define V_030000_SQ_TEX_DIM_3D 0x00000002
1899 #define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003
1900 #define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004
1901 #define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005
1902 #define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006
1903 #define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
1904 #define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5)
1905 #define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1)
1906 #define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF
1907 #define S_030000_PITCH(x) (((x) & 0xFFF) << 6)
1908 #define G_030000_PITCH(x) (((x) >> 6) & 0xFFF)
1909 #define C_030000_PITCH 0xFFFC003F
1910 #define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18)
1911 #define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF)
1912 #define C_030000_TEX_WIDTH 0x0003FFFF
1913 #define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004
1914 #define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0)
1915 #define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF)
1916 #define C_030004_TEX_HEIGHT 0xFFFFC000
1917 #define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14)
1918 #define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF)
1919 #define C_030004_TEX_DEPTH 0xF8003FFF
1920 #define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28)
1921 #define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF)
1922 #define C_030004_ARRAY_MODE 0x0FFFFFFF
1923 #define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008
1924 #define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
1925 #define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
1926 #define C_030008_BASE_ADDRESS 0x00000000
1927 #define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C
1928 #define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
1929 #define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
1930 #define C_03000C_MIP_ADDRESS 0x00000000
1931 #define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010
1932 #define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
1933 #define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
1934 #define C_030010_FORMAT_COMP_X 0xFFFFFFFC
1935 #define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000
1936 #define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001
1937 #define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002
1938 #define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
1939 #define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
1940 #define C_030010_FORMAT_COMP_Y 0xFFFFFFF3
1941 #define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
1942 #define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
1943 #define C_030010_FORMAT_COMP_Z 0xFFFFFFCF
1944 #define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
1945 #define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
1946 #define C_030010_FORMAT_COMP_W 0xFFFFFF3F
1947 #define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
1948 #define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
1949 #define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF
1950 #define V_030010_SQ_NUM_FORMAT_NORM 0x00000000
1951 #define V_030010_SQ_NUM_FORMAT_INT 0x00000001
1952 #define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002
1953 #define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
1954 #define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
1955 #define C_030010_SRF_MODE_ALL 0xFFFFFBFF
1956 #define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000
1957 #define V_030010_SRF_MODE_NO_ZERO 0x00000001
1958 #define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
1959 #define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
1960 #define C_030010_FORCE_DEGAMMA 0xFFFFF7FF
1961 #define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
1962 #define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
1963 #define C_030010_ENDIAN_SWAP 0xFFFFCFFF
1964 #define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16)
1965 #define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7)
1966 #define C_030010_DST_SEL_X 0xFFF8FFFF
1967 #define V_030010_SQ_SEL_X 0x00000000
1968 #define V_030010_SQ_SEL_Y 0x00000001
1969 #define V_030010_SQ_SEL_Z 0x00000002
1970 #define V_030010_SQ_SEL_W 0x00000003
1971 #define V_030010_SQ_SEL_0 0x00000004
1972 #define V_030010_SQ_SEL_1 0x00000005
1973 #define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19)
1974 #define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
1975 #define C_030010_DST_SEL_Y 0xFFC7FFFF
1976 #define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22)
1977 #define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
1978 #define C_030010_DST_SEL_Z 0xFE3FFFFF
1979 #define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25)
1980 #define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7)
1981 #define C_030010_DST_SEL_W 0xF1FFFFFF
1982 #define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28)
1983 #define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
1984 #define C_030010_BASE_LEVEL 0x0FFFFFFF
1985 #define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014
1986 #define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0)
1987 #define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
1988 #define C_030014_LAST_LEVEL 0xFFFFFFF0
1989 #define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
1990 #define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
1991 #define C_030014_BASE_ARRAY 0xFFFE000F
1992 #define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
1993 #define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
1994 #define C_030014_LAST_ARRAY 0xC001FFFF
1995 #define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018
1996 #define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0)
1997 #define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7)
1998 #define C_030018_MAX_ANISO 0xFFFFFFF8
1999 #define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3)
2000 #define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7)
2001 #define C_030018_PERF_MODULATION 0xFFFFFFC7
2002 #define S_030018_INTERLACED(x) (((x) & 0x1) << 6)
2003 #define G_030018_INTERLACED(x) (((x) >> 6) & 0x1)
2004 #define C_030018_INTERLACED 0xFFFFFFBF
2005 #define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29)
2006 #define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7)
2007 #define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C
2008 #define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
2009 #define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3)
2010 #define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8)
2011 #define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3)
2012 #define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10)
2013 #define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3)
2014 #define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16)
2015 #define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3)
2016 #define S_03001C_TYPE(x) (((x) & 0x3) << 30)
2017 #define G_03001C_TYPE(x) (((x) >> 30) & 0x3)
2018 #define C_03001C_TYPE 0x3FFFFFFF
2019 #define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000
2020 #define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001
2021 #define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002
2022 #define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003
2023 #define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0)
2024 #define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F)
2025 #define C_03001C_DATA_FORMAT 0xFFFFFFC0
2027 #define SQ_VTX_CONSTANT_WORD0_0 0x30000
2028 #define SQ_VTX_CONSTANT_WORD1_0 0x30004
2029 #define SQ_VTX_CONSTANT_WORD2_0 0x30008
2030 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
2031 # define SQ_VTXC_STRIDE(x) ((x) << 8)
2032 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
2033 # define SQ_ENDIAN_NONE 0
2034 # define SQ_ENDIAN_8IN16 1
2035 # define SQ_ENDIAN_8IN32 2
2036 #define SQ_VTX_CONSTANT_WORD3_0 0x3000C
2037 # define SQ_VTCX_SEL_X(x) ((x) << 3)
2038 # define SQ_VTCX_SEL_Y(x) ((x) << 6)
2039 # define SQ_VTCX_SEL_Z(x) ((x) << 9)
2040 # define SQ_VTCX_SEL_W(x) ((x) << 12)
2041 #define SQ_VTX_CONSTANT_WORD4_0 0x30010
2042 #define SQ_VTX_CONSTANT_WORD5_0 0x30014
2043 #define SQ_VTX_CONSTANT_WORD6_0 0x30018
2044 #define SQ_VTX_CONSTANT_WORD7_0 0x3001c
2046 #define TD_PS_BORDER_COLOR_INDEX 0xA400
2047 #define TD_PS_BORDER_COLOR_RED 0xA404
2048 #define TD_PS_BORDER_COLOR_GREEN 0xA408
2049 #define TD_PS_BORDER_COLOR_BLUE 0xA40C
2050 #define TD_PS_BORDER_COLOR_ALPHA 0xA410
2051 #define TD_VS_BORDER_COLOR_INDEX 0xA414
2052 #define TD_VS_BORDER_COLOR_RED 0xA418
2053 #define TD_VS_BORDER_COLOR_GREEN 0xA41C
2054 #define TD_VS_BORDER_COLOR_BLUE 0xA420
2055 #define TD_VS_BORDER_COLOR_ALPHA 0xA424
2056 #define TD_GS_BORDER_COLOR_INDEX 0xA428
2057 #define TD_GS_BORDER_COLOR_RED 0xA42C
2058 #define TD_GS_BORDER_COLOR_GREEN 0xA430
2059 #define TD_GS_BORDER_COLOR_BLUE 0xA434
2060 #define TD_GS_BORDER_COLOR_ALPHA 0xA438
2061 #define TD_HS_BORDER_COLOR_INDEX 0xA43C
2062 #define TD_HS_BORDER_COLOR_RED 0xA440
2063 #define TD_HS_BORDER_COLOR_GREEN 0xA444
2064 #define TD_HS_BORDER_COLOR_BLUE 0xA448
2065 #define TD_HS_BORDER_COLOR_ALPHA 0xA44C
2066 #define TD_LS_BORDER_COLOR_INDEX 0xA450
2067 #define TD_LS_BORDER_COLOR_RED 0xA454
2068 #define TD_LS_BORDER_COLOR_GREEN 0xA458
2069 #define TD_LS_BORDER_COLOR_BLUE 0xA45C
2070 #define TD_LS_BORDER_COLOR_ALPHA 0xA460
2071 #define TD_CS_BORDER_COLOR_INDEX 0xA464
2072 #define TD_CS_BORDER_COLOR_RED 0xA468
2073 #define TD_CS_BORDER_COLOR_GREEN 0xA46C
2074 #define TD_CS_BORDER_COLOR_BLUE 0xA470
2075 #define TD_CS_BORDER_COLOR_ALPHA 0xA474
2077 /* cayman 3D regs */
2078 #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4
2079 #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48
2080 #define CAYMAN_DB_EQAA 0x28804
2081 #define CAYMAN_DB_DEPTH_INFO 0x2803C
2082 #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
2083 #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0
2084 #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7
2085 #define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358
2086 /* cayman packet3 addition */
2087 #define CAYMAN_PACKET3_DEALLOC_STATE 0x14
2089 /* DMA regs common on r6xx/r7xx/evergreen/ni */
2090 #define DMA_RB_CNTL 0xd000
2091 # define DMA_RB_ENABLE (1 << 0)
2092 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
2093 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
2094 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
2095 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
2096 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
2097 #define DMA_STATUS_REG 0xd034
2098 # define DMA_IDLE (1 << 0)
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