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UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / evergreen.c
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <drm/drmP.h>
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include <drm/radeon_drm.h>
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
42 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
43 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
44 int ring, u32 cp_int_cntl);
45
46 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
47 unsigned *bankh, unsigned *mtaspect,
48 unsigned *tile_split)
49 {
50 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
51 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
52 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
53 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
54 switch (*bankw) {
55 default:
56 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
57 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
58 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
59 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
60 }
61 switch (*bankh) {
62 default:
63 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
64 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
65 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
66 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
67 }
68 switch (*mtaspect) {
69 default:
70 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
71 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
72 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
73 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
74 }
75 }
76
77 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
78 {
79 u16 ctl, v;
80 int err;
81
82 err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
83 if (err)
84 return;
85
86 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
87
88 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
89 * to avoid hangs or perfomance issues
90 */
91 if ((v == 0) || (v == 6) || (v == 7)) {
92 ctl &= ~PCI_EXP_DEVCTL_READRQ;
93 ctl |= (2 << 12);
94 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
95 }
96 }
97
98 /**
99 * dce4_wait_for_vblank - vblank wait asic callback.
100 *
101 * @rdev: radeon_device pointer
102 * @crtc: crtc to wait for vblank on
103 *
104 * Wait for vblank on the requested crtc (evergreen+).
105 */
106 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
107 {
108 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
109 int i;
110
111 if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
112 for (i = 0; i < rdev->usec_timeout; i++) {
113 if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
114 break;
115 udelay(1);
116 }
117 for (i = 0; i < rdev->usec_timeout; i++) {
118 if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
119 break;
120 udelay(1);
121 }
122 }
123 }
124
125 /**
126 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
127 *
128 * @rdev: radeon_device pointer
129 * @crtc: crtc to prepare for pageflip on
130 *
131 * Pre-pageflip callback (evergreen+).
132 * Enables the pageflip irq (vblank irq).
133 */
134 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
135 {
136 /* enable the pflip int */
137 radeon_irq_kms_pflip_irq_get(rdev, crtc);
138 }
139
140 /**
141 * evergreen_post_page_flip - pos-pageflip callback.
142 *
143 * @rdev: radeon_device pointer
144 * @crtc: crtc to cleanup pageflip on
145 *
146 * Post-pageflip callback (evergreen+).
147 * Disables the pageflip irq (vblank irq).
148 */
149 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
150 {
151 /* disable the pflip int */
152 radeon_irq_kms_pflip_irq_put(rdev, crtc);
153 }
154
155 /**
156 * evergreen_page_flip - pageflip callback.
157 *
158 * @rdev: radeon_device pointer
159 * @crtc_id: crtc to cleanup pageflip on
160 * @crtc_base: new address of the crtc (GPU MC address)
161 *
162 * Does the actual pageflip (evergreen+).
163 * During vblank we take the crtc lock and wait for the update_pending
164 * bit to go high, when it does, we release the lock, and allow the
165 * double buffered update to take place.
166 * Returns the current update pending status.
167 */
168 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
169 {
170 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
171 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
172 int i;
173
174 /* Lock the graphics update lock */
175 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
176 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
177
178 /* update the scanout addresses */
179 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
180 upper_32_bits(crtc_base));
181 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
182 (u32)crtc_base);
183
184 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
185 upper_32_bits(crtc_base));
186 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
187 (u32)crtc_base);
188
189 /* Wait for update_pending to go high. */
190 for (i = 0; i < rdev->usec_timeout; i++) {
191 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
192 break;
193 udelay(1);
194 }
195 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
196
197 /* Unlock the lock, so double-buffering can take place inside vblank */
198 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
199 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
200
201 /* Return current update_pending status: */
202 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
203 }
204
205 /* get temperature in millidegrees */
206 int evergreen_get_temp(struct radeon_device *rdev)
207 {
208 u32 temp, toffset;
209 int actual_temp = 0;
210
211 if (rdev->family == CHIP_JUNIPER) {
212 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
213 TOFFSET_SHIFT;
214 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
215 TS0_ADC_DOUT_SHIFT;
216
217 if (toffset & 0x100)
218 actual_temp = temp / 2 - (0x200 - toffset);
219 else
220 actual_temp = temp / 2 + toffset;
221
222 actual_temp = actual_temp * 1000;
223
224 } else {
225 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
226 ASIC_T_SHIFT;
227
228 if (temp & 0x400)
229 actual_temp = -256;
230 else if (temp & 0x200)
231 actual_temp = 255;
232 else if (temp & 0x100) {
233 actual_temp = temp & 0x1ff;
234 actual_temp |= ~0x1ff;
235 } else
236 actual_temp = temp & 0xff;
237
238 actual_temp = (actual_temp * 1000) / 2;
239 }
240
241 return actual_temp;
242 }
243
244 int sumo_get_temp(struct radeon_device *rdev)
245 {
246 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
247 int actual_temp = temp - 49;
248
249 return actual_temp * 1000;
250 }
251
252 /**
253 * sumo_pm_init_profile - Initialize power profiles callback.
254 *
255 * @rdev: radeon_device pointer
256 *
257 * Initialize the power states used in profile mode
258 * (sumo, trinity, SI).
259 * Used for profile mode only.
260 */
261 void sumo_pm_init_profile(struct radeon_device *rdev)
262 {
263 int idx;
264
265 /* default */
266 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
267 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
268 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
269 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
270
271 /* low,mid sh/mh */
272 if (rdev->flags & RADEON_IS_MOBILITY)
273 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
274 else
275 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
276
277 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
278 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
279 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
280 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
281
282 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
283 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
284 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
285 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
286
287 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
288 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
289 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
290 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
291
292 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
293 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
294 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
295 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
296
297 /* high sh/mh */
298 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
299 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
300 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
301 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
303 rdev->pm.power_state[idx].num_clock_modes - 1;
304
305 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
306 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
307 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
309 rdev->pm.power_state[idx].num_clock_modes - 1;
310 }
311
312 /**
313 * evergreen_pm_misc - set additional pm hw parameters callback.
314 *
315 * @rdev: radeon_device pointer
316 *
317 * Set non-clock parameters associated with a power state
318 * (voltage, etc.) (evergreen+).
319 */
320 void evergreen_pm_misc(struct radeon_device *rdev)
321 {
322 int req_ps_idx = rdev->pm.requested_power_state_index;
323 int req_cm_idx = rdev->pm.requested_clock_mode_index;
324 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
325 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
326
327 if (voltage->type == VOLTAGE_SW) {
328 /* 0xff01 is a flag rather then an actual voltage */
329 if (voltage->voltage == 0xff01)
330 return;
331 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
332 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
333 rdev->pm.current_vddc = voltage->voltage;
334 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
335 }
336 /* 0xff01 is a flag rather then an actual voltage */
337 if (voltage->vddci == 0xff01)
338 return;
339 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
340 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
341 rdev->pm.current_vddci = voltage->vddci;
342 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
343 }
344 }
345 }
346
347 /**
348 * evergreen_pm_prepare - pre-power state change callback.
349 *
350 * @rdev: radeon_device pointer
351 *
352 * Prepare for a power state change (evergreen+).
353 */
354 void evergreen_pm_prepare(struct radeon_device *rdev)
355 {
356 struct drm_device *ddev = rdev->ddev;
357 struct drm_crtc *crtc;
358 struct radeon_crtc *radeon_crtc;
359 u32 tmp;
360
361 /* disable any active CRTCs */
362 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
363 radeon_crtc = to_radeon_crtc(crtc);
364 if (radeon_crtc->enabled) {
365 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
366 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
367 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
368 }
369 }
370 }
371
372 /**
373 * evergreen_pm_finish - post-power state change callback.
374 *
375 * @rdev: radeon_device pointer
376 *
377 * Clean up after a power state change (evergreen+).
378 */
379 void evergreen_pm_finish(struct radeon_device *rdev)
380 {
381 struct drm_device *ddev = rdev->ddev;
382 struct drm_crtc *crtc;
383 struct radeon_crtc *radeon_crtc;
384 u32 tmp;
385
386 /* enable any active CRTCs */
387 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
388 radeon_crtc = to_radeon_crtc(crtc);
389 if (radeon_crtc->enabled) {
390 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
391 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
392 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
393 }
394 }
395 }
396
397 /**
398 * evergreen_hpd_sense - hpd sense callback.
399 *
400 * @rdev: radeon_device pointer
401 * @hpd: hpd (hotplug detect) pin
402 *
403 * Checks if a digital monitor is connected (evergreen+).
404 * Returns true if connected, false if not connected.
405 */
406 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
407 {
408 bool connected = false;
409
410 switch (hpd) {
411 case RADEON_HPD_1:
412 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
413 connected = true;
414 break;
415 case RADEON_HPD_2:
416 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
417 connected = true;
418 break;
419 case RADEON_HPD_3:
420 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
421 connected = true;
422 break;
423 case RADEON_HPD_4:
424 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
425 connected = true;
426 break;
427 case RADEON_HPD_5:
428 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
429 connected = true;
430 break;
431 case RADEON_HPD_6:
432 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
433 connected = true;
434 break;
435 default:
436 break;
437 }
438
439 return connected;
440 }
441
442 /**
443 * evergreen_hpd_set_polarity - hpd set polarity callback.
444 *
445 * @rdev: radeon_device pointer
446 * @hpd: hpd (hotplug detect) pin
447 *
448 * Set the polarity of the hpd pin (evergreen+).
449 */
450 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
451 enum radeon_hpd_id hpd)
452 {
453 u32 tmp;
454 bool connected = evergreen_hpd_sense(rdev, hpd);
455
456 switch (hpd) {
457 case RADEON_HPD_1:
458 tmp = RREG32(DC_HPD1_INT_CONTROL);
459 if (connected)
460 tmp &= ~DC_HPDx_INT_POLARITY;
461 else
462 tmp |= DC_HPDx_INT_POLARITY;
463 WREG32(DC_HPD1_INT_CONTROL, tmp);
464 break;
465 case RADEON_HPD_2:
466 tmp = RREG32(DC_HPD2_INT_CONTROL);
467 if (connected)
468 tmp &= ~DC_HPDx_INT_POLARITY;
469 else
470 tmp |= DC_HPDx_INT_POLARITY;
471 WREG32(DC_HPD2_INT_CONTROL, tmp);
472 break;
473 case RADEON_HPD_3:
474 tmp = RREG32(DC_HPD3_INT_CONTROL);
475 if (connected)
476 tmp &= ~DC_HPDx_INT_POLARITY;
477 else
478 tmp |= DC_HPDx_INT_POLARITY;
479 WREG32(DC_HPD3_INT_CONTROL, tmp);
480 break;
481 case RADEON_HPD_4:
482 tmp = RREG32(DC_HPD4_INT_CONTROL);
483 if (connected)
484 tmp &= ~DC_HPDx_INT_POLARITY;
485 else
486 tmp |= DC_HPDx_INT_POLARITY;
487 WREG32(DC_HPD4_INT_CONTROL, tmp);
488 break;
489 case RADEON_HPD_5:
490 tmp = RREG32(DC_HPD5_INT_CONTROL);
491 if (connected)
492 tmp &= ~DC_HPDx_INT_POLARITY;
493 else
494 tmp |= DC_HPDx_INT_POLARITY;
495 WREG32(DC_HPD5_INT_CONTROL, tmp);
496 break;
497 case RADEON_HPD_6:
498 tmp = RREG32(DC_HPD6_INT_CONTROL);
499 if (connected)
500 tmp &= ~DC_HPDx_INT_POLARITY;
501 else
502 tmp |= DC_HPDx_INT_POLARITY;
503 WREG32(DC_HPD6_INT_CONTROL, tmp);
504 break;
505 default:
506 break;
507 }
508 }
509
510 /**
511 * evergreen_hpd_init - hpd setup callback.
512 *
513 * @rdev: radeon_device pointer
514 *
515 * Setup the hpd pins used by the card (evergreen+).
516 * Enable the pin, set the polarity, and enable the hpd interrupts.
517 */
518 void evergreen_hpd_init(struct radeon_device *rdev)
519 {
520 struct drm_device *dev = rdev->ddev;
521 struct drm_connector *connector;
522 unsigned enabled = 0;
523 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
524 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
525
526 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
527 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
528 switch (radeon_connector->hpd.hpd) {
529 case RADEON_HPD_1:
530 WREG32(DC_HPD1_CONTROL, tmp);
531 break;
532 case RADEON_HPD_2:
533 WREG32(DC_HPD2_CONTROL, tmp);
534 break;
535 case RADEON_HPD_3:
536 WREG32(DC_HPD3_CONTROL, tmp);
537 break;
538 case RADEON_HPD_4:
539 WREG32(DC_HPD4_CONTROL, tmp);
540 break;
541 case RADEON_HPD_5:
542 WREG32(DC_HPD5_CONTROL, tmp);
543 break;
544 case RADEON_HPD_6:
545 WREG32(DC_HPD6_CONTROL, tmp);
546 break;
547 default:
548 break;
549 }
550 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
551 enabled |= 1 << radeon_connector->hpd.hpd;
552 }
553 radeon_irq_kms_enable_hpd(rdev, enabled);
554 }
555
556 /**
557 * evergreen_hpd_fini - hpd tear down callback.
558 *
559 * @rdev: radeon_device pointer
560 *
561 * Tear down the hpd pins used by the card (evergreen+).
562 * Disable the hpd interrupts.
563 */
564 void evergreen_hpd_fini(struct radeon_device *rdev)
565 {
566 struct drm_device *dev = rdev->ddev;
567 struct drm_connector *connector;
568 unsigned disabled = 0;
569
570 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
571 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
572 switch (radeon_connector->hpd.hpd) {
573 case RADEON_HPD_1:
574 WREG32(DC_HPD1_CONTROL, 0);
575 break;
576 case RADEON_HPD_2:
577 WREG32(DC_HPD2_CONTROL, 0);
578 break;
579 case RADEON_HPD_3:
580 WREG32(DC_HPD3_CONTROL, 0);
581 break;
582 case RADEON_HPD_4:
583 WREG32(DC_HPD4_CONTROL, 0);
584 break;
585 case RADEON_HPD_5:
586 WREG32(DC_HPD5_CONTROL, 0);
587 break;
588 case RADEON_HPD_6:
589 WREG32(DC_HPD6_CONTROL, 0);
590 break;
591 default:
592 break;
593 }
594 disabled |= 1 << radeon_connector->hpd.hpd;
595 }
596 radeon_irq_kms_disable_hpd(rdev, disabled);
597 }
598
599 /* watermark setup */
600
601 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
602 struct radeon_crtc *radeon_crtc,
603 struct drm_display_mode *mode,
604 struct drm_display_mode *other_mode)
605 {
606 u32 tmp;
607 /*
608 * Line Buffer Setup
609 * There are 3 line buffers, each one shared by 2 display controllers.
610 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
611 * the display controllers. The paritioning is done via one of four
612 * preset allocations specified in bits 2:0:
613 * first display controller
614 * 0 - first half of lb (3840 * 2)
615 * 1 - first 3/4 of lb (5760 * 2)
616 * 2 - whole lb (7680 * 2), other crtc must be disabled
617 * 3 - first 1/4 of lb (1920 * 2)
618 * second display controller
619 * 4 - second half of lb (3840 * 2)
620 * 5 - second 3/4 of lb (5760 * 2)
621 * 6 - whole lb (7680 * 2), other crtc must be disabled
622 * 7 - last 1/4 of lb (1920 * 2)
623 */
624 /* this can get tricky if we have two large displays on a paired group
625 * of crtcs. Ideally for multiple large displays we'd assign them to
626 * non-linked crtcs for maximum line buffer allocation.
627 */
628 if (radeon_crtc->base.enabled && mode) {
629 if (other_mode)
630 tmp = 0; /* 1/2 */
631 else
632 tmp = 2; /* whole */
633 } else
634 tmp = 0;
635
636 /* second controller of the pair uses second half of the lb */
637 if (radeon_crtc->crtc_id % 2)
638 tmp += 4;
639 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
640
641 if (radeon_crtc->base.enabled && mode) {
642 switch (tmp) {
643 case 0:
644 case 4:
645 default:
646 if (ASIC_IS_DCE5(rdev))
647 return 4096 * 2;
648 else
649 return 3840 * 2;
650 case 1:
651 case 5:
652 if (ASIC_IS_DCE5(rdev))
653 return 6144 * 2;
654 else
655 return 5760 * 2;
656 case 2:
657 case 6:
658 if (ASIC_IS_DCE5(rdev))
659 return 8192 * 2;
660 else
661 return 7680 * 2;
662 case 3:
663 case 7:
664 if (ASIC_IS_DCE5(rdev))
665 return 2048 * 2;
666 else
667 return 1920 * 2;
668 }
669 }
670
671 /* controller not enabled, so no lb used */
672 return 0;
673 }
674
675 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
676 {
677 u32 tmp = RREG32(MC_SHARED_CHMAP);
678
679 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
680 case 0:
681 default:
682 return 1;
683 case 1:
684 return 2;
685 case 2:
686 return 4;
687 case 3:
688 return 8;
689 }
690 }
691
692 struct evergreen_wm_params {
693 u32 dram_channels; /* number of dram channels */
694 u32 yclk; /* bandwidth per dram data pin in kHz */
695 u32 sclk; /* engine clock in kHz */
696 u32 disp_clk; /* display clock in kHz */
697 u32 src_width; /* viewport width */
698 u32 active_time; /* active display time in ns */
699 u32 blank_time; /* blank time in ns */
700 bool interlaced; /* mode is interlaced */
701 fixed20_12 vsc; /* vertical scale ratio */
702 u32 num_heads; /* number of active crtcs */
703 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
704 u32 lb_size; /* line buffer allocated to pipe */
705 u32 vtaps; /* vertical scaler taps */
706 };
707
708 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
709 {
710 /* Calculate DRAM Bandwidth and the part allocated to display. */
711 fixed20_12 dram_efficiency; /* 0.7 */
712 fixed20_12 yclk, dram_channels, bandwidth;
713 fixed20_12 a;
714
715 a.full = dfixed_const(1000);
716 yclk.full = dfixed_const(wm->yclk);
717 yclk.full = dfixed_div(yclk, a);
718 dram_channels.full = dfixed_const(wm->dram_channels * 4);
719 a.full = dfixed_const(10);
720 dram_efficiency.full = dfixed_const(7);
721 dram_efficiency.full = dfixed_div(dram_efficiency, a);
722 bandwidth.full = dfixed_mul(dram_channels, yclk);
723 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
724
725 return dfixed_trunc(bandwidth);
726 }
727
728 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
729 {
730 /* Calculate DRAM Bandwidth and the part allocated to display. */
731 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
732 fixed20_12 yclk, dram_channels, bandwidth;
733 fixed20_12 a;
734
735 a.full = dfixed_const(1000);
736 yclk.full = dfixed_const(wm->yclk);
737 yclk.full = dfixed_div(yclk, a);
738 dram_channels.full = dfixed_const(wm->dram_channels * 4);
739 a.full = dfixed_const(10);
740 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
741 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
742 bandwidth.full = dfixed_mul(dram_channels, yclk);
743 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
744
745 return dfixed_trunc(bandwidth);
746 }
747
748 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
749 {
750 /* Calculate the display Data return Bandwidth */
751 fixed20_12 return_efficiency; /* 0.8 */
752 fixed20_12 sclk, bandwidth;
753 fixed20_12 a;
754
755 a.full = dfixed_const(1000);
756 sclk.full = dfixed_const(wm->sclk);
757 sclk.full = dfixed_div(sclk, a);
758 a.full = dfixed_const(10);
759 return_efficiency.full = dfixed_const(8);
760 return_efficiency.full = dfixed_div(return_efficiency, a);
761 a.full = dfixed_const(32);
762 bandwidth.full = dfixed_mul(a, sclk);
763 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
764
765 return dfixed_trunc(bandwidth);
766 }
767
768 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
769 {
770 /* Calculate the DMIF Request Bandwidth */
771 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
772 fixed20_12 disp_clk, bandwidth;
773 fixed20_12 a;
774
775 a.full = dfixed_const(1000);
776 disp_clk.full = dfixed_const(wm->disp_clk);
777 disp_clk.full = dfixed_div(disp_clk, a);
778 a.full = dfixed_const(10);
779 disp_clk_request_efficiency.full = dfixed_const(8);
780 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
781 a.full = dfixed_const(32);
782 bandwidth.full = dfixed_mul(a, disp_clk);
783 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
784
785 return dfixed_trunc(bandwidth);
786 }
787
788 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
789 {
790 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
791 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
792 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
793 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
794
795 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
796 }
797
798 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
799 {
800 /* Calculate the display mode Average Bandwidth
801 * DisplayMode should contain the source and destination dimensions,
802 * timing, etc.
803 */
804 fixed20_12 bpp;
805 fixed20_12 line_time;
806 fixed20_12 src_width;
807 fixed20_12 bandwidth;
808 fixed20_12 a;
809
810 a.full = dfixed_const(1000);
811 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
812 line_time.full = dfixed_div(line_time, a);
813 bpp.full = dfixed_const(wm->bytes_per_pixel);
814 src_width.full = dfixed_const(wm->src_width);
815 bandwidth.full = dfixed_mul(src_width, bpp);
816 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
817 bandwidth.full = dfixed_div(bandwidth, line_time);
818
819 return dfixed_trunc(bandwidth);
820 }
821
822 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
823 {
824 /* First calcualte the latency in ns */
825 u32 mc_latency = 2000; /* 2000 ns. */
826 u32 available_bandwidth = evergreen_available_bandwidth(wm);
827 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
828 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
829 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
830 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
831 (wm->num_heads * cursor_line_pair_return_time);
832 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
833 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
834 fixed20_12 a, b, c;
835
836 if (wm->num_heads == 0)
837 return 0;
838
839 a.full = dfixed_const(2);
840 b.full = dfixed_const(1);
841 if ((wm->vsc.full > a.full) ||
842 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
843 (wm->vtaps >= 5) ||
844 ((wm->vsc.full >= a.full) && wm->interlaced))
845 max_src_lines_per_dst_line = 4;
846 else
847 max_src_lines_per_dst_line = 2;
848
849 a.full = dfixed_const(available_bandwidth);
850 b.full = dfixed_const(wm->num_heads);
851 a.full = dfixed_div(a, b);
852
853 b.full = dfixed_const(1000);
854 c.full = dfixed_const(wm->disp_clk);
855 b.full = dfixed_div(c, b);
856 c.full = dfixed_const(wm->bytes_per_pixel);
857 b.full = dfixed_mul(b, c);
858
859 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
860
861 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
862 b.full = dfixed_const(1000);
863 c.full = dfixed_const(lb_fill_bw);
864 b.full = dfixed_div(c, b);
865 a.full = dfixed_div(a, b);
866 line_fill_time = dfixed_trunc(a);
867
868 if (line_fill_time < wm->active_time)
869 return latency;
870 else
871 return latency + (line_fill_time - wm->active_time);
872
873 }
874
875 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
876 {
877 if (evergreen_average_bandwidth(wm) <=
878 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
879 return true;
880 else
881 return false;
882 };
883
884 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
885 {
886 if (evergreen_average_bandwidth(wm) <=
887 (evergreen_available_bandwidth(wm) / wm->num_heads))
888 return true;
889 else
890 return false;
891 };
892
893 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
894 {
895 u32 lb_partitions = wm->lb_size / wm->src_width;
896 u32 line_time = wm->active_time + wm->blank_time;
897 u32 latency_tolerant_lines;
898 u32 latency_hiding;
899 fixed20_12 a;
900
901 a.full = dfixed_const(1);
902 if (wm->vsc.full > a.full)
903 latency_tolerant_lines = 1;
904 else {
905 if (lb_partitions <= (wm->vtaps + 1))
906 latency_tolerant_lines = 1;
907 else
908 latency_tolerant_lines = 2;
909 }
910
911 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
912
913 if (evergreen_latency_watermark(wm) <= latency_hiding)
914 return true;
915 else
916 return false;
917 }
918
919 static void evergreen_program_watermarks(struct radeon_device *rdev,
920 struct radeon_crtc *radeon_crtc,
921 u32 lb_size, u32 num_heads)
922 {
923 struct drm_display_mode *mode = &radeon_crtc->base.mode;
924 struct evergreen_wm_params wm;
925 u32 pixel_period;
926 u32 line_time = 0;
927 u32 latency_watermark_a = 0, latency_watermark_b = 0;
928 u32 priority_a_mark = 0, priority_b_mark = 0;
929 u32 priority_a_cnt = PRIORITY_OFF;
930 u32 priority_b_cnt = PRIORITY_OFF;
931 u32 pipe_offset = radeon_crtc->crtc_id * 16;
932 u32 tmp, arb_control3;
933 fixed20_12 a, b, c;
934
935 if (radeon_crtc->base.enabled && num_heads && mode) {
936 pixel_period = 1000000 / (u32)mode->clock;
937 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
938 priority_a_cnt = 0;
939 priority_b_cnt = 0;
940
941 wm.yclk = rdev->pm.current_mclk * 10;
942 wm.sclk = rdev->pm.current_sclk * 10;
943 wm.disp_clk = mode->clock;
944 wm.src_width = mode->crtc_hdisplay;
945 wm.active_time = mode->crtc_hdisplay * pixel_period;
946 wm.blank_time = line_time - wm.active_time;
947 wm.interlaced = false;
948 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
949 wm.interlaced = true;
950 wm.vsc = radeon_crtc->vsc;
951 wm.vtaps = 1;
952 if (radeon_crtc->rmx_type != RMX_OFF)
953 wm.vtaps = 2;
954 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
955 wm.lb_size = lb_size;
956 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
957 wm.num_heads = num_heads;
958
959 /* set for high clocks */
960 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
961 /* set for low clocks */
962 /* wm.yclk = low clk; wm.sclk = low clk */
963 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
964
965 /* possibly force display priority to high */
966 /* should really do this at mode validation time... */
967 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
968 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
969 !evergreen_check_latency_hiding(&wm) ||
970 (rdev->disp_priority == 2)) {
971 DRM_DEBUG_KMS("force priority to high\n");
972 priority_a_cnt |= PRIORITY_ALWAYS_ON;
973 priority_b_cnt |= PRIORITY_ALWAYS_ON;
974 }
975
976 a.full = dfixed_const(1000);
977 b.full = dfixed_const(mode->clock);
978 b.full = dfixed_div(b, a);
979 c.full = dfixed_const(latency_watermark_a);
980 c.full = dfixed_mul(c, b);
981 c.full = dfixed_mul(c, radeon_crtc->hsc);
982 c.full = dfixed_div(c, a);
983 a.full = dfixed_const(16);
984 c.full = dfixed_div(c, a);
985 priority_a_mark = dfixed_trunc(c);
986 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
987
988 a.full = dfixed_const(1000);
989 b.full = dfixed_const(mode->clock);
990 b.full = dfixed_div(b, a);
991 c.full = dfixed_const(latency_watermark_b);
992 c.full = dfixed_mul(c, b);
993 c.full = dfixed_mul(c, radeon_crtc->hsc);
994 c.full = dfixed_div(c, a);
995 a.full = dfixed_const(16);
996 c.full = dfixed_div(c, a);
997 priority_b_mark = dfixed_trunc(c);
998 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
999 }
1000
1001 /* select wm A */
1002 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1003 tmp = arb_control3;
1004 tmp &= ~LATENCY_WATERMARK_MASK(3);
1005 tmp |= LATENCY_WATERMARK_MASK(1);
1006 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1007 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1008 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1009 LATENCY_HIGH_WATERMARK(line_time)));
1010 /* select wm B */
1011 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1012 tmp &= ~LATENCY_WATERMARK_MASK(3);
1013 tmp |= LATENCY_WATERMARK_MASK(2);
1014 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1015 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1016 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1017 LATENCY_HIGH_WATERMARK(line_time)));
1018 /* restore original selection */
1019 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1020
1021 /* write the priority marks */
1022 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1023 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1024
1025 }
1026
1027 /**
1028 * evergreen_bandwidth_update - update display watermarks callback.
1029 *
1030 * @rdev: radeon_device pointer
1031 *
1032 * Update the display watermarks based on the requested mode(s)
1033 * (evergreen+).
1034 */
1035 void evergreen_bandwidth_update(struct radeon_device *rdev)
1036 {
1037 struct drm_display_mode *mode0 = NULL;
1038 struct drm_display_mode *mode1 = NULL;
1039 u32 num_heads = 0, lb_size;
1040 int i;
1041
1042 radeon_update_display_priority(rdev);
1043
1044 for (i = 0; i < rdev->num_crtc; i++) {
1045 if (rdev->mode_info.crtcs[i]->base.enabled)
1046 num_heads++;
1047 }
1048 for (i = 0; i < rdev->num_crtc; i += 2) {
1049 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1050 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1051 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1052 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1053 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1054 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1055 }
1056 }
1057
1058 /**
1059 * evergreen_mc_wait_for_idle - wait for MC idle callback.
1060 *
1061 * @rdev: radeon_device pointer
1062 *
1063 * Wait for the MC (memory controller) to be idle.
1064 * (evergreen+).
1065 * Returns 0 if the MC is idle, -1 if not.
1066 */
1067 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
1068 {
1069 unsigned i;
1070 u32 tmp;
1071
1072 for (i = 0; i < rdev->usec_timeout; i++) {
1073 /* read MC_STATUS */
1074 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1075 if (!tmp)
1076 return 0;
1077 udelay(1);
1078 }
1079 return -1;
1080 }
1081
1082 /*
1083 * GART
1084 */
1085 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1086 {
1087 unsigned i;
1088 u32 tmp;
1089
1090 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1091
1092 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1093 for (i = 0; i < rdev->usec_timeout; i++) {
1094 /* read MC_STATUS */
1095 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1096 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1097 if (tmp == 2) {
1098 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1099 return;
1100 }
1101 if (tmp) {
1102 return;
1103 }
1104 udelay(1);
1105 }
1106 }
1107
1108 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1109 {
1110 u32 tmp;
1111 int r;
1112
1113 if (rdev->gart.robj == NULL) {
1114 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1115 return -EINVAL;
1116 }
1117 r = radeon_gart_table_vram_pin(rdev);
1118 if (r)
1119 return r;
1120 radeon_gart_restore(rdev);
1121 /* Setup L2 cache */
1122 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1123 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1124 EFFECTIVE_L2_QUEUE_SIZE(7));
1125 WREG32(VM_L2_CNTL2, 0);
1126 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1127 /* Setup TLB control */
1128 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1129 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1130 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1131 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1132 if (rdev->flags & RADEON_IS_IGP) {
1133 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1134 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1135 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1136 } else {
1137 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1138 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1139 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1140 if ((rdev->family == CHIP_JUNIPER) ||
1141 (rdev->family == CHIP_CYPRESS) ||
1142 (rdev->family == CHIP_HEMLOCK) ||
1143 (rdev->family == CHIP_BARTS))
1144 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1145 }
1146 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1147 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1148 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1149 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1150 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1151 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1152 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1153 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1154 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1155 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1156 (u32)(rdev->dummy_page.addr >> 12));
1157 WREG32(VM_CONTEXT1_CNTL, 0);
1158
1159 evergreen_pcie_gart_tlb_flush(rdev);
1160 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1161 (unsigned)(rdev->mc.gtt_size >> 20),
1162 (unsigned long long)rdev->gart.table_addr);
1163 rdev->gart.ready = true;
1164 return 0;
1165 }
1166
1167 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1168 {
1169 u32 tmp;
1170
1171 /* Disable all tables */
1172 WREG32(VM_CONTEXT0_CNTL, 0);
1173 WREG32(VM_CONTEXT1_CNTL, 0);
1174
1175 /* Setup L2 cache */
1176 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1177 EFFECTIVE_L2_QUEUE_SIZE(7));
1178 WREG32(VM_L2_CNTL2, 0);
1179 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1180 /* Setup TLB control */
1181 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1182 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1183 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1184 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1185 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1186 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1187 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1188 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1189 radeon_gart_table_vram_unpin(rdev);
1190 }
1191
1192 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1193 {
1194 evergreen_pcie_gart_disable(rdev);
1195 radeon_gart_table_vram_free(rdev);
1196 radeon_gart_fini(rdev);
1197 }
1198
1199
1200 void evergreen_agp_enable(struct radeon_device *rdev)
1201 {
1202 u32 tmp;
1203
1204 /* Setup L2 cache */
1205 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1206 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1207 EFFECTIVE_L2_QUEUE_SIZE(7));
1208 WREG32(VM_L2_CNTL2, 0);
1209 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1210 /* Setup TLB control */
1211 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1212 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1213 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1214 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1215 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1216 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1217 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1218 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1219 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1220 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1221 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1222 WREG32(VM_CONTEXT0_CNTL, 0);
1223 WREG32(VM_CONTEXT1_CNTL, 0);
1224 }
1225
1226 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1227 {
1228 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1229 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1230
1231 /* Stop all video */
1232 WREG32(VGA_RENDER_CONTROL, 0);
1233 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1234 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1235 if (rdev->num_crtc >= 4) {
1236 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1237 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1238 }
1239 if (rdev->num_crtc >= 6) {
1240 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1241 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1242 }
1243 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1244 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1245 if (rdev->num_crtc >= 4) {
1246 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1247 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1248 }
1249 if (rdev->num_crtc >= 6) {
1250 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1251 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1252 }
1253 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1254 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1255 if (rdev->num_crtc >= 4) {
1256 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1257 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1258 }
1259 if (rdev->num_crtc >= 6) {
1260 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1261 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1262 }
1263
1264 WREG32(D1VGA_CONTROL, 0);
1265 WREG32(D2VGA_CONTROL, 0);
1266 if (rdev->num_crtc >= 4) {
1267 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1268 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1269 }
1270 if (rdev->num_crtc >= 6) {
1271 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1272 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1273 }
1274 }
1275
1276 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1277 {
1278 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1279 upper_32_bits(rdev->mc.vram_start));
1280 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1281 upper_32_bits(rdev->mc.vram_start));
1282 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1283 (u32)rdev->mc.vram_start);
1284 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1285 (u32)rdev->mc.vram_start);
1286
1287 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1288 upper_32_bits(rdev->mc.vram_start));
1289 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1290 upper_32_bits(rdev->mc.vram_start));
1291 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1292 (u32)rdev->mc.vram_start);
1293 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1294 (u32)rdev->mc.vram_start);
1295
1296 if (rdev->num_crtc >= 4) {
1297 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1298 upper_32_bits(rdev->mc.vram_start));
1299 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1300 upper_32_bits(rdev->mc.vram_start));
1301 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1302 (u32)rdev->mc.vram_start);
1303 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1304 (u32)rdev->mc.vram_start);
1305
1306 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1307 upper_32_bits(rdev->mc.vram_start));
1308 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1309 upper_32_bits(rdev->mc.vram_start));
1310 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1311 (u32)rdev->mc.vram_start);
1312 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1313 (u32)rdev->mc.vram_start);
1314 }
1315 if (rdev->num_crtc >= 6) {
1316 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1317 upper_32_bits(rdev->mc.vram_start));
1318 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1319 upper_32_bits(rdev->mc.vram_start));
1320 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1321 (u32)rdev->mc.vram_start);
1322 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1323 (u32)rdev->mc.vram_start);
1324
1325 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1326 upper_32_bits(rdev->mc.vram_start));
1327 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1328 upper_32_bits(rdev->mc.vram_start));
1329 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1330 (u32)rdev->mc.vram_start);
1331 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1332 (u32)rdev->mc.vram_start);
1333 }
1334
1335 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1336 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1337 /* Unlock host access */
1338 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1339 mdelay(1);
1340 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1341 }
1342
1343 void evergreen_mc_program(struct radeon_device *rdev)
1344 {
1345 struct evergreen_mc_save save;
1346 u32 tmp;
1347 int i, j;
1348
1349 /* Initialize HDP */
1350 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1351 WREG32((0x2c14 + j), 0x00000000);
1352 WREG32((0x2c18 + j), 0x00000000);
1353 WREG32((0x2c1c + j), 0x00000000);
1354 WREG32((0x2c20 + j), 0x00000000);
1355 WREG32((0x2c24 + j), 0x00000000);
1356 }
1357 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1358
1359 evergreen_mc_stop(rdev, &save);
1360 if (evergreen_mc_wait_for_idle(rdev)) {
1361 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1362 }
1363 /* Lockout access through VGA aperture*/
1364 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1365 /* Update configuration */
1366 if (rdev->flags & RADEON_IS_AGP) {
1367 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1368 /* VRAM before AGP */
1369 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1370 rdev->mc.vram_start >> 12);
1371 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1372 rdev->mc.gtt_end >> 12);
1373 } else {
1374 /* VRAM after AGP */
1375 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1376 rdev->mc.gtt_start >> 12);
1377 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1378 rdev->mc.vram_end >> 12);
1379 }
1380 } else {
1381 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1382 rdev->mc.vram_start >> 12);
1383 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1384 rdev->mc.vram_end >> 12);
1385 }
1386 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1387 /* llano/ontario only */
1388 if ((rdev->family == CHIP_PALM) ||
1389 (rdev->family == CHIP_SUMO) ||
1390 (rdev->family == CHIP_SUMO2)) {
1391 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1392 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1393 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1394 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1395 }
1396 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1397 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1398 WREG32(MC_VM_FB_LOCATION, tmp);
1399 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1400 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1401 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1402 if (rdev->flags & RADEON_IS_AGP) {
1403 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1404 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1405 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1406 } else {
1407 WREG32(MC_VM_AGP_BASE, 0);
1408 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1409 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1410 }
1411 if (evergreen_mc_wait_for_idle(rdev)) {
1412 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1413 }
1414 evergreen_mc_resume(rdev, &save);
1415 /* we need to own VRAM, so turn off the VGA renderer here
1416 * to stop it overwriting our objects */
1417 rv515_vga_render_disable(rdev);
1418 }
1419
1420 /*
1421 * CP.
1422 */
1423 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1424 {
1425 struct radeon_ring *ring = &rdev->ring[ib->ring];
1426 u32 next_rptr;
1427
1428 /* set to DX10/11 mode */
1429 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1430 radeon_ring_write(ring, 1);
1431
1432 if (ring->rptr_save_reg) {
1433 next_rptr = ring->wptr + 3 + 4;
1434 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1435 radeon_ring_write(ring, ((ring->rptr_save_reg -
1436 PACKET3_SET_CONFIG_REG_START) >> 2));
1437 radeon_ring_write(ring, next_rptr);
1438 } else if (rdev->wb.enabled) {
1439 next_rptr = ring->wptr + 5 + 4;
1440 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1441 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1442 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1443 radeon_ring_write(ring, next_rptr);
1444 radeon_ring_write(ring, 0);
1445 }
1446
1447 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1448 radeon_ring_write(ring,
1449 #ifdef __BIG_ENDIAN
1450 (2 << 0) |
1451 #endif
1452 (ib->gpu_addr & 0xFFFFFFFC));
1453 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1454 radeon_ring_write(ring, ib->length_dw);
1455 }
1456
1457
1458 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1459 {
1460 const __be32 *fw_data;
1461 int i;
1462
1463 if (!rdev->me_fw || !rdev->pfp_fw)
1464 return -EINVAL;
1465
1466 r700_cp_stop(rdev);
1467 WREG32(CP_RB_CNTL,
1468 #ifdef __BIG_ENDIAN
1469 BUF_SWAP_32BIT |
1470 #endif
1471 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1472
1473 fw_data = (const __be32 *)rdev->pfp_fw->data;
1474 WREG32(CP_PFP_UCODE_ADDR, 0);
1475 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1476 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1477 WREG32(CP_PFP_UCODE_ADDR, 0);
1478
1479 fw_data = (const __be32 *)rdev->me_fw->data;
1480 WREG32(CP_ME_RAM_WADDR, 0);
1481 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1482 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1483
1484 WREG32(CP_PFP_UCODE_ADDR, 0);
1485 WREG32(CP_ME_RAM_WADDR, 0);
1486 WREG32(CP_ME_RAM_RADDR, 0);
1487 return 0;
1488 }
1489
1490 static int evergreen_cp_start(struct radeon_device *rdev)
1491 {
1492 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1493 int r, i;
1494 uint32_t cp_me;
1495
1496 r = radeon_ring_lock(rdev, ring, 7);
1497 if (r) {
1498 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1499 return r;
1500 }
1501 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1502 radeon_ring_write(ring, 0x1);
1503 radeon_ring_write(ring, 0x0);
1504 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1505 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1506 radeon_ring_write(ring, 0);
1507 radeon_ring_write(ring, 0);
1508 radeon_ring_unlock_commit(rdev, ring);
1509
1510 cp_me = 0xff;
1511 WREG32(CP_ME_CNTL, cp_me);
1512
1513 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1514 if (r) {
1515 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1516 return r;
1517 }
1518
1519 /* setup clear context state */
1520 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1521 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1522
1523 for (i = 0; i < evergreen_default_size; i++)
1524 radeon_ring_write(ring, evergreen_default_state[i]);
1525
1526 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1527 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1528
1529 /* set clear context state */
1530 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1531 radeon_ring_write(ring, 0);
1532
1533 /* SQ_VTX_BASE_VTX_LOC */
1534 radeon_ring_write(ring, 0xc0026f00);
1535 radeon_ring_write(ring, 0x00000000);
1536 radeon_ring_write(ring, 0x00000000);
1537 radeon_ring_write(ring, 0x00000000);
1538
1539 /* Clear consts */
1540 radeon_ring_write(ring, 0xc0036f00);
1541 radeon_ring_write(ring, 0x00000bc4);
1542 radeon_ring_write(ring, 0xffffffff);
1543 radeon_ring_write(ring, 0xffffffff);
1544 radeon_ring_write(ring, 0xffffffff);
1545
1546 radeon_ring_write(ring, 0xc0026900);
1547 radeon_ring_write(ring, 0x00000316);
1548 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1549 radeon_ring_write(ring, 0x00000010); /* */
1550
1551 radeon_ring_unlock_commit(rdev, ring);
1552
1553 return 0;
1554 }
1555
1556 int evergreen_cp_resume(struct radeon_device *rdev)
1557 {
1558 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1559 u32 tmp;
1560 u32 rb_bufsz;
1561 int r;
1562
1563 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1564 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1565 SOFT_RESET_PA |
1566 SOFT_RESET_SH |
1567 SOFT_RESET_VGT |
1568 SOFT_RESET_SPI |
1569 SOFT_RESET_SX));
1570 RREG32(GRBM_SOFT_RESET);
1571 mdelay(15);
1572 WREG32(GRBM_SOFT_RESET, 0);
1573 RREG32(GRBM_SOFT_RESET);
1574
1575 /* Set ring buffer size */
1576 rb_bufsz = drm_order(ring->ring_size / 8);
1577 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1578 #ifdef __BIG_ENDIAN
1579 tmp |= BUF_SWAP_32BIT;
1580 #endif
1581 WREG32(CP_RB_CNTL, tmp);
1582 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1583 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1584
1585 /* Set the write pointer delay */
1586 WREG32(CP_RB_WPTR_DELAY, 0);
1587
1588 /* Initialize the ring buffer's read and write pointers */
1589 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1590 WREG32(CP_RB_RPTR_WR, 0);
1591 ring->wptr = 0;
1592 WREG32(CP_RB_WPTR, ring->wptr);
1593
1594 /* set the wb address wether it's enabled or not */
1595 WREG32(CP_RB_RPTR_ADDR,
1596 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1597 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1598 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1599
1600 if (rdev->wb.enabled)
1601 WREG32(SCRATCH_UMSK, 0xff);
1602 else {
1603 tmp |= RB_NO_UPDATE;
1604 WREG32(SCRATCH_UMSK, 0);
1605 }
1606
1607 mdelay(1);
1608 WREG32(CP_RB_CNTL, tmp);
1609
1610 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1611 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1612
1613 ring->rptr = RREG32(CP_RB_RPTR);
1614
1615 evergreen_cp_start(rdev);
1616 ring->ready = true;
1617 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1618 if (r) {
1619 ring->ready = false;
1620 return r;
1621 }
1622 return 0;
1623 }
1624
1625 /*
1626 * Core functions
1627 */
1628 static void evergreen_gpu_init(struct radeon_device *rdev)
1629 {
1630 u32 gb_addr_config;
1631 u32 mc_shared_chmap, mc_arb_ramcfg;
1632 u32 sx_debug_1;
1633 u32 smx_dc_ctl0;
1634 u32 sq_config;
1635 u32 sq_lds_resource_mgmt;
1636 u32 sq_gpr_resource_mgmt_1;
1637 u32 sq_gpr_resource_mgmt_2;
1638 u32 sq_gpr_resource_mgmt_3;
1639 u32 sq_thread_resource_mgmt;
1640 u32 sq_thread_resource_mgmt_2;
1641 u32 sq_stack_resource_mgmt_1;
1642 u32 sq_stack_resource_mgmt_2;
1643 u32 sq_stack_resource_mgmt_3;
1644 u32 vgt_cache_invalidation;
1645 u32 hdp_host_path_cntl, tmp;
1646 u32 disabled_rb_mask;
1647 int i, j, num_shader_engines, ps_thread_count;
1648
1649 switch (rdev->family) {
1650 case CHIP_CYPRESS:
1651 case CHIP_HEMLOCK:
1652 rdev->config.evergreen.num_ses = 2;
1653 rdev->config.evergreen.max_pipes = 4;
1654 rdev->config.evergreen.max_tile_pipes = 8;
1655 rdev->config.evergreen.max_simds = 10;
1656 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1657 rdev->config.evergreen.max_gprs = 256;
1658 rdev->config.evergreen.max_threads = 248;
1659 rdev->config.evergreen.max_gs_threads = 32;
1660 rdev->config.evergreen.max_stack_entries = 512;
1661 rdev->config.evergreen.sx_num_of_sets = 4;
1662 rdev->config.evergreen.sx_max_export_size = 256;
1663 rdev->config.evergreen.sx_max_export_pos_size = 64;
1664 rdev->config.evergreen.sx_max_export_smx_size = 192;
1665 rdev->config.evergreen.max_hw_contexts = 8;
1666 rdev->config.evergreen.sq_num_cf_insts = 2;
1667
1668 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1669 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1670 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1671 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
1672 break;
1673 case CHIP_JUNIPER:
1674 rdev->config.evergreen.num_ses = 1;
1675 rdev->config.evergreen.max_pipes = 4;
1676 rdev->config.evergreen.max_tile_pipes = 4;
1677 rdev->config.evergreen.max_simds = 10;
1678 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1679 rdev->config.evergreen.max_gprs = 256;
1680 rdev->config.evergreen.max_threads = 248;
1681 rdev->config.evergreen.max_gs_threads = 32;
1682 rdev->config.evergreen.max_stack_entries = 512;
1683 rdev->config.evergreen.sx_num_of_sets = 4;
1684 rdev->config.evergreen.sx_max_export_size = 256;
1685 rdev->config.evergreen.sx_max_export_pos_size = 64;
1686 rdev->config.evergreen.sx_max_export_smx_size = 192;
1687 rdev->config.evergreen.max_hw_contexts = 8;
1688 rdev->config.evergreen.sq_num_cf_insts = 2;
1689
1690 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1691 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1692 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1693 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
1694 break;
1695 case CHIP_REDWOOD:
1696 rdev->config.evergreen.num_ses = 1;
1697 rdev->config.evergreen.max_pipes = 4;
1698 rdev->config.evergreen.max_tile_pipes = 4;
1699 rdev->config.evergreen.max_simds = 5;
1700 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1701 rdev->config.evergreen.max_gprs = 256;
1702 rdev->config.evergreen.max_threads = 248;
1703 rdev->config.evergreen.max_gs_threads = 32;
1704 rdev->config.evergreen.max_stack_entries = 256;
1705 rdev->config.evergreen.sx_num_of_sets = 4;
1706 rdev->config.evergreen.sx_max_export_size = 256;
1707 rdev->config.evergreen.sx_max_export_pos_size = 64;
1708 rdev->config.evergreen.sx_max_export_smx_size = 192;
1709 rdev->config.evergreen.max_hw_contexts = 8;
1710 rdev->config.evergreen.sq_num_cf_insts = 2;
1711
1712 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1713 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1714 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1715 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1716 break;
1717 case CHIP_CEDAR:
1718 default:
1719 rdev->config.evergreen.num_ses = 1;
1720 rdev->config.evergreen.max_pipes = 2;
1721 rdev->config.evergreen.max_tile_pipes = 2;
1722 rdev->config.evergreen.max_simds = 2;
1723 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1724 rdev->config.evergreen.max_gprs = 256;
1725 rdev->config.evergreen.max_threads = 192;
1726 rdev->config.evergreen.max_gs_threads = 16;
1727 rdev->config.evergreen.max_stack_entries = 256;
1728 rdev->config.evergreen.sx_num_of_sets = 4;
1729 rdev->config.evergreen.sx_max_export_size = 128;
1730 rdev->config.evergreen.sx_max_export_pos_size = 32;
1731 rdev->config.evergreen.sx_max_export_smx_size = 96;
1732 rdev->config.evergreen.max_hw_contexts = 4;
1733 rdev->config.evergreen.sq_num_cf_insts = 1;
1734
1735 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1736 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1737 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1738 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1739 break;
1740 case CHIP_PALM:
1741 rdev->config.evergreen.num_ses = 1;
1742 rdev->config.evergreen.max_pipes = 2;
1743 rdev->config.evergreen.max_tile_pipes = 2;
1744 rdev->config.evergreen.max_simds = 2;
1745 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1746 rdev->config.evergreen.max_gprs = 256;
1747 rdev->config.evergreen.max_threads = 192;
1748 rdev->config.evergreen.max_gs_threads = 16;
1749 rdev->config.evergreen.max_stack_entries = 256;
1750 rdev->config.evergreen.sx_num_of_sets = 4;
1751 rdev->config.evergreen.sx_max_export_size = 128;
1752 rdev->config.evergreen.sx_max_export_pos_size = 32;
1753 rdev->config.evergreen.sx_max_export_smx_size = 96;
1754 rdev->config.evergreen.max_hw_contexts = 4;
1755 rdev->config.evergreen.sq_num_cf_insts = 1;
1756
1757 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1758 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1759 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1760 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1761 break;
1762 case CHIP_SUMO:
1763 rdev->config.evergreen.num_ses = 1;
1764 rdev->config.evergreen.max_pipes = 4;
1765 rdev->config.evergreen.max_tile_pipes = 2;
1766 if (rdev->pdev->device == 0x9648)
1767 rdev->config.evergreen.max_simds = 3;
1768 else if ((rdev->pdev->device == 0x9647) ||
1769 (rdev->pdev->device == 0x964a))
1770 rdev->config.evergreen.max_simds = 4;
1771 else
1772 rdev->config.evergreen.max_simds = 5;
1773 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1774 rdev->config.evergreen.max_gprs = 256;
1775 rdev->config.evergreen.max_threads = 248;
1776 rdev->config.evergreen.max_gs_threads = 32;
1777 rdev->config.evergreen.max_stack_entries = 256;
1778 rdev->config.evergreen.sx_num_of_sets = 4;
1779 rdev->config.evergreen.sx_max_export_size = 256;
1780 rdev->config.evergreen.sx_max_export_pos_size = 64;
1781 rdev->config.evergreen.sx_max_export_smx_size = 192;
1782 rdev->config.evergreen.max_hw_contexts = 8;
1783 rdev->config.evergreen.sq_num_cf_insts = 2;
1784
1785 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1786 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1787 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1788 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1789 break;
1790 case CHIP_SUMO2:
1791 rdev->config.evergreen.num_ses = 1;
1792 rdev->config.evergreen.max_pipes = 4;
1793 rdev->config.evergreen.max_tile_pipes = 4;
1794 rdev->config.evergreen.max_simds = 2;
1795 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1796 rdev->config.evergreen.max_gprs = 256;
1797 rdev->config.evergreen.max_threads = 248;
1798 rdev->config.evergreen.max_gs_threads = 32;
1799 rdev->config.evergreen.max_stack_entries = 512;
1800 rdev->config.evergreen.sx_num_of_sets = 4;
1801 rdev->config.evergreen.sx_max_export_size = 256;
1802 rdev->config.evergreen.sx_max_export_pos_size = 64;
1803 rdev->config.evergreen.sx_max_export_smx_size = 192;
1804 rdev->config.evergreen.max_hw_contexts = 8;
1805 rdev->config.evergreen.sq_num_cf_insts = 2;
1806
1807 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1808 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1809 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1810 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1811 break;
1812 case CHIP_BARTS:
1813 rdev->config.evergreen.num_ses = 2;
1814 rdev->config.evergreen.max_pipes = 4;
1815 rdev->config.evergreen.max_tile_pipes = 8;
1816 rdev->config.evergreen.max_simds = 7;
1817 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1818 rdev->config.evergreen.max_gprs = 256;
1819 rdev->config.evergreen.max_threads = 248;
1820 rdev->config.evergreen.max_gs_threads = 32;
1821 rdev->config.evergreen.max_stack_entries = 512;
1822 rdev->config.evergreen.sx_num_of_sets = 4;
1823 rdev->config.evergreen.sx_max_export_size = 256;
1824 rdev->config.evergreen.sx_max_export_pos_size = 64;
1825 rdev->config.evergreen.sx_max_export_smx_size = 192;
1826 rdev->config.evergreen.max_hw_contexts = 8;
1827 rdev->config.evergreen.sq_num_cf_insts = 2;
1828
1829 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1830 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1831 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1832 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
1833 break;
1834 case CHIP_TURKS:
1835 rdev->config.evergreen.num_ses = 1;
1836 rdev->config.evergreen.max_pipes = 4;
1837 rdev->config.evergreen.max_tile_pipes = 4;
1838 rdev->config.evergreen.max_simds = 6;
1839 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1840 rdev->config.evergreen.max_gprs = 256;
1841 rdev->config.evergreen.max_threads = 248;
1842 rdev->config.evergreen.max_gs_threads = 32;
1843 rdev->config.evergreen.max_stack_entries = 256;
1844 rdev->config.evergreen.sx_num_of_sets = 4;
1845 rdev->config.evergreen.sx_max_export_size = 256;
1846 rdev->config.evergreen.sx_max_export_pos_size = 64;
1847 rdev->config.evergreen.sx_max_export_smx_size = 192;
1848 rdev->config.evergreen.max_hw_contexts = 8;
1849 rdev->config.evergreen.sq_num_cf_insts = 2;
1850
1851 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1852 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1853 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1854 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
1855 break;
1856 case CHIP_CAICOS:
1857 rdev->config.evergreen.num_ses = 1;
1858 rdev->config.evergreen.max_pipes = 4;
1859 rdev->config.evergreen.max_tile_pipes = 2;
1860 rdev->config.evergreen.max_simds = 2;
1861 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1862 rdev->config.evergreen.max_gprs = 256;
1863 rdev->config.evergreen.max_threads = 192;
1864 rdev->config.evergreen.max_gs_threads = 16;
1865 rdev->config.evergreen.max_stack_entries = 256;
1866 rdev->config.evergreen.sx_num_of_sets = 4;
1867 rdev->config.evergreen.sx_max_export_size = 128;
1868 rdev->config.evergreen.sx_max_export_pos_size = 32;
1869 rdev->config.evergreen.sx_max_export_smx_size = 96;
1870 rdev->config.evergreen.max_hw_contexts = 4;
1871 rdev->config.evergreen.sq_num_cf_insts = 1;
1872
1873 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1874 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1875 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1876 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
1877 break;
1878 }
1879
1880 /* Initialize HDP */
1881 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1882 WREG32((0x2c14 + j), 0x00000000);
1883 WREG32((0x2c18 + j), 0x00000000);
1884 WREG32((0x2c1c + j), 0x00000000);
1885 WREG32((0x2c20 + j), 0x00000000);
1886 WREG32((0x2c24 + j), 0x00000000);
1887 }
1888
1889 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1890
1891 evergreen_fix_pci_max_read_req_size(rdev);
1892
1893 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1894 if ((rdev->family == CHIP_PALM) ||
1895 (rdev->family == CHIP_SUMO) ||
1896 (rdev->family == CHIP_SUMO2))
1897 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1898 else
1899 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1900
1901 /* setup tiling info dword. gb_addr_config is not adequate since it does
1902 * not have bank info, so create a custom tiling dword.
1903 * bits 3:0 num_pipes
1904 * bits 7:4 num_banks
1905 * bits 11:8 group_size
1906 * bits 15:12 row_size
1907 */
1908 rdev->config.evergreen.tile_config = 0;
1909 switch (rdev->config.evergreen.max_tile_pipes) {
1910 case 1:
1911 default:
1912 rdev->config.evergreen.tile_config |= (0 << 0);
1913 break;
1914 case 2:
1915 rdev->config.evergreen.tile_config |= (1 << 0);
1916 break;
1917 case 4:
1918 rdev->config.evergreen.tile_config |= (2 << 0);
1919 break;
1920 case 8:
1921 rdev->config.evergreen.tile_config |= (3 << 0);
1922 break;
1923 }
1924 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1925 if (rdev->flags & RADEON_IS_IGP)
1926 rdev->config.evergreen.tile_config |= 1 << 4;
1927 else {
1928 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1929 case 0: /* four banks */
1930 rdev->config.evergreen.tile_config |= 0 << 4;
1931 break;
1932 case 1: /* eight banks */
1933 rdev->config.evergreen.tile_config |= 1 << 4;
1934 break;
1935 case 2: /* sixteen banks */
1936 default:
1937 rdev->config.evergreen.tile_config |= 2 << 4;
1938 break;
1939 }
1940 }
1941 rdev->config.evergreen.tile_config |= 0 << 8;
1942 rdev->config.evergreen.tile_config |=
1943 ((gb_addr_config & 0x30000000) >> 28) << 12;
1944
1945 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
1946
1947 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
1948 u32 efuse_straps_4;
1949 u32 efuse_straps_3;
1950
1951 WREG32(RCU_IND_INDEX, 0x204);
1952 efuse_straps_4 = RREG32(RCU_IND_DATA);
1953 WREG32(RCU_IND_INDEX, 0x203);
1954 efuse_straps_3 = RREG32(RCU_IND_DATA);
1955 tmp = (((efuse_straps_4 & 0xf) << 4) |
1956 ((efuse_straps_3 & 0xf0000000) >> 28));
1957 } else {
1958 tmp = 0;
1959 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
1960 u32 rb_disable_bitmap;
1961
1962 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1963 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1964 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1965 tmp <<= 4;
1966 tmp |= rb_disable_bitmap;
1967 }
1968 }
1969 /* enabled rb are just the one not disabled :) */
1970 disabled_rb_mask = tmp;
1971
1972 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1973 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1974
1975 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1976 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1977 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1978
1979 tmp = gb_addr_config & NUM_PIPES_MASK;
1980 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
1981 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
1982 WREG32(GB_BACKEND_MAP, tmp);
1983
1984 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1985 WREG32(CGTS_TCC_DISABLE, 0);
1986 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1987 WREG32(CGTS_USER_TCC_DISABLE, 0);
1988
1989 /* set HW defaults for 3D engine */
1990 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1991 ROQ_IB2_START(0x2b)));
1992
1993 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1994
1995 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1996 SYNC_GRADIENT |
1997 SYNC_WALKER |
1998 SYNC_ALIGNER));
1999
2000 sx_debug_1 = RREG32(SX_DEBUG_1);
2001 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2002 WREG32(SX_DEBUG_1, sx_debug_1);
2003
2004
2005 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2006 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2007 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2008 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2009
2010 if (rdev->family <= CHIP_SUMO2)
2011 WREG32(SMX_SAR_CTL0, 0x00010000);
2012
2013 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2014 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2015 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2016
2017 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2018 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2019 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2020
2021 WREG32(VGT_NUM_INSTANCES, 1);
2022 WREG32(SPI_CONFIG_CNTL, 0);
2023 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2024 WREG32(CP_PERFMON_CNTL, 0);
2025
2026 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2027 FETCH_FIFO_HIWATER(0x4) |
2028 DONE_FIFO_HIWATER(0xe0) |
2029 ALU_UPDATE_FIFO_HIWATER(0x8)));
2030
2031 sq_config = RREG32(SQ_CONFIG);
2032 sq_config &= ~(PS_PRIO(3) |
2033 VS_PRIO(3) |
2034 GS_PRIO(3) |
2035 ES_PRIO(3));
2036 sq_config |= (VC_ENABLE |
2037 EXPORT_SRC_C |
2038 PS_PRIO(0) |
2039 VS_PRIO(1) |
2040 GS_PRIO(2) |
2041 ES_PRIO(3));
2042
2043 switch (rdev->family) {
2044 case CHIP_CEDAR:
2045 case CHIP_PALM:
2046 case CHIP_SUMO:
2047 case CHIP_SUMO2:
2048 case CHIP_CAICOS:
2049 /* no vertex cache */
2050 sq_config &= ~VC_ENABLE;
2051 break;
2052 default:
2053 break;
2054 }
2055
2056 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2057
2058 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2059 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2060 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2061 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2062 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2063 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2064 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2065
2066 switch (rdev->family) {
2067 case CHIP_CEDAR:
2068 case CHIP_PALM:
2069 case CHIP_SUMO:
2070 case CHIP_SUMO2:
2071 ps_thread_count = 96;
2072 break;
2073 default:
2074 ps_thread_count = 128;
2075 break;
2076 }
2077
2078 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2079 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2080 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2081 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2082 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2083 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2084
2085 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2086 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2087 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2088 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2089 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2090 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2091
2092 WREG32(SQ_CONFIG, sq_config);
2093 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2094 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2095 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2096 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2097 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2098 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2099 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2100 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2101 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2102 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2103
2104 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2105 FORCE_EOV_MAX_REZ_CNT(255)));
2106
2107 switch (rdev->family) {
2108 case CHIP_CEDAR:
2109 case CHIP_PALM:
2110 case CHIP_SUMO:
2111 case CHIP_SUMO2:
2112 case CHIP_CAICOS:
2113 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2114 break;
2115 default:
2116 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2117 break;
2118 }
2119 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2120 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2121
2122 WREG32(VGT_GS_VERTEX_REUSE, 16);
2123 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2124 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2125
2126 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2127 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2128
2129 WREG32(CB_PERF_CTR0_SEL_0, 0);
2130 WREG32(CB_PERF_CTR0_SEL_1, 0);
2131 WREG32(CB_PERF_CTR1_SEL_0, 0);
2132 WREG32(CB_PERF_CTR1_SEL_1, 0);
2133 WREG32(CB_PERF_CTR2_SEL_0, 0);
2134 WREG32(CB_PERF_CTR2_SEL_1, 0);
2135 WREG32(CB_PERF_CTR3_SEL_0, 0);
2136 WREG32(CB_PERF_CTR3_SEL_1, 0);
2137
2138 /* clear render buffer base addresses */
2139 WREG32(CB_COLOR0_BASE, 0);
2140 WREG32(CB_COLOR1_BASE, 0);
2141 WREG32(CB_COLOR2_BASE, 0);
2142 WREG32(CB_COLOR3_BASE, 0);
2143 WREG32(CB_COLOR4_BASE, 0);
2144 WREG32(CB_COLOR5_BASE, 0);
2145 WREG32(CB_COLOR6_BASE, 0);
2146 WREG32(CB_COLOR7_BASE, 0);
2147 WREG32(CB_COLOR8_BASE, 0);
2148 WREG32(CB_COLOR9_BASE, 0);
2149 WREG32(CB_COLOR10_BASE, 0);
2150 WREG32(CB_COLOR11_BASE, 0);
2151
2152 /* set the shader const cache sizes to 0 */
2153 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2154 WREG32(i, 0);
2155 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2156 WREG32(i, 0);
2157
2158 tmp = RREG32(HDP_MISC_CNTL);
2159 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2160 WREG32(HDP_MISC_CNTL, tmp);
2161
2162 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2163 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2164
2165 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2166
2167 udelay(50);
2168
2169 }
2170
2171 int evergreen_mc_init(struct radeon_device *rdev)
2172 {
2173 u32 tmp;
2174 int chansize, numchan;
2175
2176 /* Get VRAM informations */
2177 rdev->mc.vram_is_ddr = true;
2178 if ((rdev->family == CHIP_PALM) ||
2179 (rdev->family == CHIP_SUMO) ||
2180 (rdev->family == CHIP_SUMO2))
2181 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2182 else
2183 tmp = RREG32(MC_ARB_RAMCFG);
2184 if (tmp & CHANSIZE_OVERRIDE) {
2185 chansize = 16;
2186 } else if (tmp & CHANSIZE_MASK) {
2187 chansize = 64;
2188 } else {
2189 chansize = 32;
2190 }
2191 tmp = RREG32(MC_SHARED_CHMAP);
2192 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2193 case 0:
2194 default:
2195 numchan = 1;
2196 break;
2197 case 1:
2198 numchan = 2;
2199 break;
2200 case 2:
2201 numchan = 4;
2202 break;
2203 case 3:
2204 numchan = 8;
2205 break;
2206 }
2207 rdev->mc.vram_width = numchan * chansize;
2208 /* Could aper size report 0 ? */
2209 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2210 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2211 /* Setup GPU memory space */
2212 if ((rdev->family == CHIP_PALM) ||
2213 (rdev->family == CHIP_SUMO) ||
2214 (rdev->family == CHIP_SUMO2)) {
2215 /* size in bytes on fusion */
2216 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2217 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2218 } else {
2219 /* size in MB on evergreen/cayman/tn */
2220 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2221 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2222 }
2223 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2224 r700_vram_gtt_location(rdev, &rdev->mc);
2225 radeon_update_bandwidth_info(rdev);
2226
2227 return 0;
2228 }
2229
2230 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2231 {
2232 u32 srbm_status;
2233 u32 grbm_status;
2234 u32 grbm_status_se0, grbm_status_se1;
2235
2236 srbm_status = RREG32(SRBM_STATUS);
2237 grbm_status = RREG32(GRBM_STATUS);
2238 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2239 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2240 if (!(grbm_status & GUI_ACTIVE)) {
2241 radeon_ring_lockup_update(ring);
2242 return false;
2243 }
2244 /* force CP activities */
2245 radeon_ring_force_activity(rdev, ring);
2246 return radeon_ring_test_lockup(rdev, ring);
2247 }
2248
2249 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2250 {
2251 struct evergreen_mc_save save;
2252 u32 grbm_reset = 0;
2253
2254 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2255 return 0;
2256
2257 dev_info(rdev->dev, "GPU softreset \n");
2258 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2259 RREG32(GRBM_STATUS));
2260 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2261 RREG32(GRBM_STATUS_SE0));
2262 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2263 RREG32(GRBM_STATUS_SE1));
2264 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2265 RREG32(SRBM_STATUS));
2266 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2267 RREG32(CP_STALLED_STAT1));
2268 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2269 RREG32(CP_STALLED_STAT2));
2270 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2271 RREG32(CP_BUSY_STAT));
2272 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2273 RREG32(CP_STAT));
2274 evergreen_mc_stop(rdev, &save);
2275 if (evergreen_mc_wait_for_idle(rdev)) {
2276 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2277 }
2278 /* Disable CP parsing/prefetching */
2279 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2280
2281 /* reset all the gfx blocks */
2282 grbm_reset = (SOFT_RESET_CP |
2283 SOFT_RESET_CB |
2284 SOFT_RESET_DB |
2285 SOFT_RESET_PA |
2286 SOFT_RESET_SC |
2287 SOFT_RESET_SPI |
2288 SOFT_RESET_SH |
2289 SOFT_RESET_SX |
2290 SOFT_RESET_TC |
2291 SOFT_RESET_TA |
2292 SOFT_RESET_VC |
2293 SOFT_RESET_VGT);
2294
2295 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2296 WREG32(GRBM_SOFT_RESET, grbm_reset);
2297 (void)RREG32(GRBM_SOFT_RESET);
2298 udelay(50);
2299 WREG32(GRBM_SOFT_RESET, 0);
2300 (void)RREG32(GRBM_SOFT_RESET);
2301 /* Wait a little for things to settle down */
2302 udelay(50);
2303 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2304 RREG32(GRBM_STATUS));
2305 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2306 RREG32(GRBM_STATUS_SE0));
2307 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2308 RREG32(GRBM_STATUS_SE1));
2309 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2310 RREG32(SRBM_STATUS));
2311 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2312 RREG32(CP_STALLED_STAT1));
2313 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2314 RREG32(CP_STALLED_STAT2));
2315 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2316 RREG32(CP_BUSY_STAT));
2317 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2318 RREG32(CP_STAT));
2319 evergreen_mc_resume(rdev, &save);
2320 return 0;
2321 }
2322
2323 int evergreen_asic_reset(struct radeon_device *rdev)
2324 {
2325 return evergreen_gpu_soft_reset(rdev);
2326 }
2327
2328 /* Interrupts */
2329
2330 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2331 {
2332 switch (crtc) {
2333 case 0:
2334 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2335 case 1:
2336 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2337 case 2:
2338 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2339 case 3:
2340 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2341 case 4:
2342 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2343 case 5:
2344 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2345 default:
2346 return 0;
2347 }
2348 }
2349
2350 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2351 {
2352 u32 tmp;
2353
2354 if (rdev->family >= CHIP_CAYMAN) {
2355 cayman_cp_int_cntl_setup(rdev, 0,
2356 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2357 cayman_cp_int_cntl_setup(rdev, 1, 0);
2358 cayman_cp_int_cntl_setup(rdev, 2, 0);
2359 } else
2360 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2361 WREG32(GRBM_INT_CNTL, 0);
2362 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2363 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2364 if (rdev->num_crtc >= 4) {
2365 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2366 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2367 }
2368 if (rdev->num_crtc >= 6) {
2369 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2370 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2371 }
2372
2373 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2374 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2375 if (rdev->num_crtc >= 4) {
2376 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2377 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2378 }
2379 if (rdev->num_crtc >= 6) {
2380 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2381 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2382 }
2383
2384 /* only one DAC on DCE6 */
2385 if (!ASIC_IS_DCE6(rdev))
2386 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2387 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2388
2389 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2390 WREG32(DC_HPD1_INT_CONTROL, tmp);
2391 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2392 WREG32(DC_HPD2_INT_CONTROL, tmp);
2393 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2394 WREG32(DC_HPD3_INT_CONTROL, tmp);
2395 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2396 WREG32(DC_HPD4_INT_CONTROL, tmp);
2397 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2398 WREG32(DC_HPD5_INT_CONTROL, tmp);
2399 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2400 WREG32(DC_HPD6_INT_CONTROL, tmp);
2401
2402 }
2403
2404 int evergreen_irq_set(struct radeon_device *rdev)
2405 {
2406 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2407 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2408 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2409 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2410 u32 grbm_int_cntl = 0;
2411 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2412 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
2413
2414 if (!rdev->irq.installed) {
2415 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2416 return -EINVAL;
2417 }
2418 /* don't enable anything if the ih is disabled */
2419 if (!rdev->ih.enabled) {
2420 r600_disable_interrupts(rdev);
2421 /* force the active interrupt state to all disabled */
2422 evergreen_disable_interrupt_state(rdev);
2423 return 0;
2424 }
2425
2426 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2427 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2428 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2429 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2430 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2431 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2432
2433 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2434 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2435 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2436 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2437 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2438 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2439
2440 if (rdev->family >= CHIP_CAYMAN) {
2441 /* enable CP interrupts on all rings */
2442 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2443 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2444 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2445 }
2446 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
2447 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2448 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2449 }
2450 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
2451 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2452 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2453 }
2454 } else {
2455 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2456 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2457 cp_int_cntl |= RB_INT_ENABLE;
2458 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2459 }
2460 }
2461
2462 if (rdev->irq.crtc_vblank_int[0] ||
2463 atomic_read(&rdev->irq.pflip[0])) {
2464 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2465 crtc1 |= VBLANK_INT_MASK;
2466 }
2467 if (rdev->irq.crtc_vblank_int[1] ||
2468 atomic_read(&rdev->irq.pflip[1])) {
2469 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2470 crtc2 |= VBLANK_INT_MASK;
2471 }
2472 if (rdev->irq.crtc_vblank_int[2] ||
2473 atomic_read(&rdev->irq.pflip[2])) {
2474 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2475 crtc3 |= VBLANK_INT_MASK;
2476 }
2477 if (rdev->irq.crtc_vblank_int[3] ||
2478 atomic_read(&rdev->irq.pflip[3])) {
2479 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2480 crtc4 |= VBLANK_INT_MASK;
2481 }
2482 if (rdev->irq.crtc_vblank_int[4] ||
2483 atomic_read(&rdev->irq.pflip[4])) {
2484 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2485 crtc5 |= VBLANK_INT_MASK;
2486 }
2487 if (rdev->irq.crtc_vblank_int[5] ||
2488 atomic_read(&rdev->irq.pflip[5])) {
2489 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2490 crtc6 |= VBLANK_INT_MASK;
2491 }
2492 if (rdev->irq.hpd[0]) {
2493 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2494 hpd1 |= DC_HPDx_INT_EN;
2495 }
2496 if (rdev->irq.hpd[1]) {
2497 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2498 hpd2 |= DC_HPDx_INT_EN;
2499 }
2500 if (rdev->irq.hpd[2]) {
2501 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2502 hpd3 |= DC_HPDx_INT_EN;
2503 }
2504 if (rdev->irq.hpd[3]) {
2505 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2506 hpd4 |= DC_HPDx_INT_EN;
2507 }
2508 if (rdev->irq.hpd[4]) {
2509 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2510 hpd5 |= DC_HPDx_INT_EN;
2511 }
2512 if (rdev->irq.hpd[5]) {
2513 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2514 hpd6 |= DC_HPDx_INT_EN;
2515 }
2516 if (rdev->irq.afmt[0]) {
2517 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2518 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2519 }
2520 if (rdev->irq.afmt[1]) {
2521 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2522 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2523 }
2524 if (rdev->irq.afmt[2]) {
2525 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2526 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2527 }
2528 if (rdev->irq.afmt[3]) {
2529 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2530 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2531 }
2532 if (rdev->irq.afmt[4]) {
2533 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2534 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2535 }
2536 if (rdev->irq.afmt[5]) {
2537 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2538 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2539 }
2540 if (rdev->irq.gui_idle) {
2541 DRM_DEBUG("gui idle\n");
2542 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2543 }
2544
2545 if (rdev->family >= CHIP_CAYMAN) {
2546 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2547 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2548 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2549 } else
2550 WREG32(CP_INT_CNTL, cp_int_cntl);
2551 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2552
2553 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2554 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2555 if (rdev->num_crtc >= 4) {
2556 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2557 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2558 }
2559 if (rdev->num_crtc >= 6) {
2560 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2561 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2562 }
2563
2564 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2565 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2566 if (rdev->num_crtc >= 4) {
2567 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2568 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2569 }
2570 if (rdev->num_crtc >= 6) {
2571 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2572 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2573 }
2574
2575 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2576 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2577 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2578 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2579 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2580 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2581
2582 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2583 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2584 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2585 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2586 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2587 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2588
2589 return 0;
2590 }
2591
2592 static void evergreen_irq_ack(struct radeon_device *rdev)
2593 {
2594 u32 tmp;
2595
2596 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2597 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2598 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2599 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2600 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2601 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2602 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2603 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2604 if (rdev->num_crtc >= 4) {
2605 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2606 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2607 }
2608 if (rdev->num_crtc >= 6) {
2609 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2610 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2611 }
2612
2613 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2614 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2615 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2616 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2617 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2618 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2619
2620 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2621 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2622 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2623 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2624 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2625 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2626 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2627 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2628 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2629 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2630 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2631 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2632
2633 if (rdev->num_crtc >= 4) {
2634 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2635 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2636 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2637 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2638 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2639 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2640 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2641 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2642 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2643 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2644 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2645 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2646 }
2647
2648 if (rdev->num_crtc >= 6) {
2649 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2650 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2651 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2652 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2653 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2654 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2655 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2656 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2657 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2658 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2659 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2660 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2661 }
2662
2663 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2664 tmp = RREG32(DC_HPD1_INT_CONTROL);
2665 tmp |= DC_HPDx_INT_ACK;
2666 WREG32(DC_HPD1_INT_CONTROL, tmp);
2667 }
2668 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2669 tmp = RREG32(DC_HPD2_INT_CONTROL);
2670 tmp |= DC_HPDx_INT_ACK;
2671 WREG32(DC_HPD2_INT_CONTROL, tmp);
2672 }
2673 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2674 tmp = RREG32(DC_HPD3_INT_CONTROL);
2675 tmp |= DC_HPDx_INT_ACK;
2676 WREG32(DC_HPD3_INT_CONTROL, tmp);
2677 }
2678 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2679 tmp = RREG32(DC_HPD4_INT_CONTROL);
2680 tmp |= DC_HPDx_INT_ACK;
2681 WREG32(DC_HPD4_INT_CONTROL, tmp);
2682 }
2683 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2684 tmp = RREG32(DC_HPD5_INT_CONTROL);
2685 tmp |= DC_HPDx_INT_ACK;
2686 WREG32(DC_HPD5_INT_CONTROL, tmp);
2687 }
2688 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2689 tmp = RREG32(DC_HPD5_INT_CONTROL);
2690 tmp |= DC_HPDx_INT_ACK;
2691 WREG32(DC_HPD6_INT_CONTROL, tmp);
2692 }
2693 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2694 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2695 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2696 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2697 }
2698 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2699 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2700 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2701 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2702 }
2703 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2704 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2705 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2706 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2707 }
2708 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2709 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2710 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2711 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2712 }
2713 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2714 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2715 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2716 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2717 }
2718 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2719 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2720 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2721 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2722 }
2723 }
2724
2725 void evergreen_irq_disable(struct radeon_device *rdev)
2726 {
2727 r600_disable_interrupts(rdev);
2728 /* Wait and acknowledge irq */
2729 mdelay(1);
2730 evergreen_irq_ack(rdev);
2731 evergreen_disable_interrupt_state(rdev);
2732 }
2733
2734 void evergreen_irq_suspend(struct radeon_device *rdev)
2735 {
2736 evergreen_irq_disable(rdev);
2737 r600_rlc_stop(rdev);
2738 }
2739
2740 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2741 {
2742 u32 wptr, tmp;
2743
2744 if (rdev->wb.enabled)
2745 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2746 else
2747 wptr = RREG32(IH_RB_WPTR);
2748
2749 if (wptr & RB_OVERFLOW) {
2750 /* When a ring buffer overflow happen start parsing interrupt
2751 * from the last not overwritten vector (wptr + 16). Hopefully
2752 * this should allow us to catchup.
2753 */
2754 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2755 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2756 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2757 tmp = RREG32(IH_RB_CNTL);
2758 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2759 WREG32(IH_RB_CNTL, tmp);
2760 }
2761 return (wptr & rdev->ih.ptr_mask);
2762 }
2763
2764 int evergreen_irq_process(struct radeon_device *rdev)
2765 {
2766 u32 wptr;
2767 u32 rptr;
2768 u32 src_id, src_data;
2769 u32 ring_index;
2770 bool queue_hotplug = false;
2771 bool queue_hdmi = false;
2772
2773 if (!rdev->ih.enabled || rdev->shutdown)
2774 return IRQ_NONE;
2775
2776 wptr = evergreen_get_ih_wptr(rdev);
2777
2778 restart_ih:
2779 /* is somebody else already processing irqs? */
2780 if (atomic_xchg(&rdev->ih.lock, 1))
2781 return IRQ_NONE;
2782
2783 rptr = rdev->ih.rptr;
2784 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2785
2786 /* Order reading of wptr vs. reading of IH ring data */
2787 rmb();
2788
2789 /* display interrupts */
2790 evergreen_irq_ack(rdev);
2791
2792 while (rptr != wptr) {
2793 /* wptr/rptr are in bytes! */
2794 ring_index = rptr / 4;
2795 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2796 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2797
2798 switch (src_id) {
2799 case 1: /* D1 vblank/vline */
2800 switch (src_data) {
2801 case 0: /* D1 vblank */
2802 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2803 if (rdev->irq.crtc_vblank_int[0]) {
2804 drm_handle_vblank(rdev->ddev, 0);
2805 rdev->pm.vblank_sync = true;
2806 wake_up(&rdev->irq.vblank_queue);
2807 }
2808 if (atomic_read(&rdev->irq.pflip[0]))
2809 radeon_crtc_handle_flip(rdev, 0);
2810 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2811 DRM_DEBUG("IH: D1 vblank\n");
2812 }
2813 break;
2814 case 1: /* D1 vline */
2815 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2816 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2817 DRM_DEBUG("IH: D1 vline\n");
2818 }
2819 break;
2820 default:
2821 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2822 break;
2823 }
2824 break;
2825 case 2: /* D2 vblank/vline */
2826 switch (src_data) {
2827 case 0: /* D2 vblank */
2828 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2829 if (rdev->irq.crtc_vblank_int[1]) {
2830 drm_handle_vblank(rdev->ddev, 1);
2831 rdev->pm.vblank_sync = true;
2832 wake_up(&rdev->irq.vblank_queue);
2833 }
2834 if (atomic_read(&rdev->irq.pflip[1]))
2835 radeon_crtc_handle_flip(rdev, 1);
2836 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2837 DRM_DEBUG("IH: D2 vblank\n");
2838 }
2839 break;
2840 case 1: /* D2 vline */
2841 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2842 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2843 DRM_DEBUG("IH: D2 vline\n");
2844 }
2845 break;
2846 default:
2847 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2848 break;
2849 }
2850 break;
2851 case 3: /* D3 vblank/vline */
2852 switch (src_data) {
2853 case 0: /* D3 vblank */
2854 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2855 if (rdev->irq.crtc_vblank_int[2]) {
2856 drm_handle_vblank(rdev->ddev, 2);
2857 rdev->pm.vblank_sync = true;
2858 wake_up(&rdev->irq.vblank_queue);
2859 }
2860 if (atomic_read(&rdev->irq.pflip[2]))
2861 radeon_crtc_handle_flip(rdev, 2);
2862 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2863 DRM_DEBUG("IH: D3 vblank\n");
2864 }
2865 break;
2866 case 1: /* D3 vline */
2867 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2868 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2869 DRM_DEBUG("IH: D3 vline\n");
2870 }
2871 break;
2872 default:
2873 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2874 break;
2875 }
2876 break;
2877 case 4: /* D4 vblank/vline */
2878 switch (src_data) {
2879 case 0: /* D4 vblank */
2880 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2881 if (rdev->irq.crtc_vblank_int[3]) {
2882 drm_handle_vblank(rdev->ddev, 3);
2883 rdev->pm.vblank_sync = true;
2884 wake_up(&rdev->irq.vblank_queue);
2885 }
2886 if (atomic_read(&rdev->irq.pflip[3]))
2887 radeon_crtc_handle_flip(rdev, 3);
2888 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2889 DRM_DEBUG("IH: D4 vblank\n");
2890 }
2891 break;
2892 case 1: /* D4 vline */
2893 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2894 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2895 DRM_DEBUG("IH: D4 vline\n");
2896 }
2897 break;
2898 default:
2899 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2900 break;
2901 }
2902 break;
2903 case 5: /* D5 vblank/vline */
2904 switch (src_data) {
2905 case 0: /* D5 vblank */
2906 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2907 if (rdev->irq.crtc_vblank_int[4]) {
2908 drm_handle_vblank(rdev->ddev, 4);
2909 rdev->pm.vblank_sync = true;
2910 wake_up(&rdev->irq.vblank_queue);
2911 }
2912 if (atomic_read(&rdev->irq.pflip[4]))
2913 radeon_crtc_handle_flip(rdev, 4);
2914 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2915 DRM_DEBUG("IH: D5 vblank\n");
2916 }
2917 break;
2918 case 1: /* D5 vline */
2919 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2920 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2921 DRM_DEBUG("IH: D5 vline\n");
2922 }
2923 break;
2924 default:
2925 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2926 break;
2927 }
2928 break;
2929 case 6: /* D6 vblank/vline */
2930 switch (src_data) {
2931 case 0: /* D6 vblank */
2932 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2933 if (rdev->irq.crtc_vblank_int[5]) {
2934 drm_handle_vblank(rdev->ddev, 5);
2935 rdev->pm.vblank_sync = true;
2936 wake_up(&rdev->irq.vblank_queue);
2937 }
2938 if (atomic_read(&rdev->irq.pflip[5]))
2939 radeon_crtc_handle_flip(rdev, 5);
2940 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2941 DRM_DEBUG("IH: D6 vblank\n");
2942 }
2943 break;
2944 case 1: /* D6 vline */
2945 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2946 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2947 DRM_DEBUG("IH: D6 vline\n");
2948 }
2949 break;
2950 default:
2951 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2952 break;
2953 }
2954 break;
2955 case 42: /* HPD hotplug */
2956 switch (src_data) {
2957 case 0:
2958 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2959 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2960 queue_hotplug = true;
2961 DRM_DEBUG("IH: HPD1\n");
2962 }
2963 break;
2964 case 1:
2965 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2966 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2967 queue_hotplug = true;
2968 DRM_DEBUG("IH: HPD2\n");
2969 }
2970 break;
2971 case 2:
2972 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2973 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2974 queue_hotplug = true;
2975 DRM_DEBUG("IH: HPD3\n");
2976 }
2977 break;
2978 case 3:
2979 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2980 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2981 queue_hotplug = true;
2982 DRM_DEBUG("IH: HPD4\n");
2983 }
2984 break;
2985 case 4:
2986 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2987 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2988 queue_hotplug = true;
2989 DRM_DEBUG("IH: HPD5\n");
2990 }
2991 break;
2992 case 5:
2993 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2994 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2995 queue_hotplug = true;
2996 DRM_DEBUG("IH: HPD6\n");
2997 }
2998 break;
2999 default:
3000 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3001 break;
3002 }
3003 break;
3004 case 44: /* hdmi */
3005 switch (src_data) {
3006 case 0:
3007 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3008 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3009 queue_hdmi = true;
3010 DRM_DEBUG("IH: HDMI0\n");
3011 }
3012 break;
3013 case 1:
3014 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3015 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3016 queue_hdmi = true;
3017 DRM_DEBUG("IH: HDMI1\n");
3018 }
3019 break;
3020 case 2:
3021 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3022 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3023 queue_hdmi = true;
3024 DRM_DEBUG("IH: HDMI2\n");
3025 }
3026 break;
3027 case 3:
3028 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3029 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3030 queue_hdmi = true;
3031 DRM_DEBUG("IH: HDMI3\n");
3032 }
3033 break;
3034 case 4:
3035 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3036 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3037 queue_hdmi = true;
3038 DRM_DEBUG("IH: HDMI4\n");
3039 }
3040 break;
3041 case 5:
3042 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3043 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3044 queue_hdmi = true;
3045 DRM_DEBUG("IH: HDMI5\n");
3046 }
3047 break;
3048 default:
3049 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3050 break;
3051 }
3052 break;
3053 case 176: /* CP_INT in ring buffer */
3054 case 177: /* CP_INT in IB1 */
3055 case 178: /* CP_INT in IB2 */
3056 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3057 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3058 break;
3059 case 181: /* CP EOP event */
3060 DRM_DEBUG("IH: CP EOP\n");
3061 if (rdev->family >= CHIP_CAYMAN) {
3062 switch (src_data) {
3063 case 0:
3064 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3065 break;
3066 case 1:
3067 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3068 break;
3069 case 2:
3070 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3071 break;
3072 }
3073 } else
3074 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3075 break;
3076 case 233: /* GUI IDLE */
3077 DRM_DEBUG("IH: GUI idle\n");
3078 wake_up(&rdev->irq.idle_queue);
3079 break;
3080 default:
3081 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3082 break;
3083 }
3084
3085 /* wptr/rptr are in bytes! */
3086 rptr += 16;
3087 rptr &= rdev->ih.ptr_mask;
3088 }
3089 if (queue_hotplug)
3090 schedule_work(&rdev->hotplug_work);
3091 if (queue_hdmi)
3092 schedule_work(&rdev->audio_work);
3093 rdev->ih.rptr = rptr;
3094 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3095 atomic_set(&rdev->ih.lock, 0);
3096
3097 /* make sure wptr hasn't changed while processing */
3098 wptr = evergreen_get_ih_wptr(rdev);
3099 if (wptr != rptr)
3100 goto restart_ih;
3101
3102 return IRQ_HANDLED;
3103 }
3104
3105 static int evergreen_startup(struct radeon_device *rdev)
3106 {
3107 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3108 int r;
3109
3110 /* enable pcie gen2 link */
3111 evergreen_pcie_gen2_enable(rdev);
3112
3113 if (ASIC_IS_DCE5(rdev)) {
3114 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3115 r = ni_init_microcode(rdev);
3116 if (r) {
3117 DRM_ERROR("Failed to load firmware!\n");
3118 return r;
3119 }
3120 }
3121 r = ni_mc_load_microcode(rdev);
3122 if (r) {
3123 DRM_ERROR("Failed to load MC firmware!\n");
3124 return r;
3125 }
3126 } else {
3127 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3128 r = r600_init_microcode(rdev);
3129 if (r) {
3130 DRM_ERROR("Failed to load firmware!\n");
3131 return r;
3132 }
3133 }
3134 }
3135
3136 r = r600_vram_scratch_init(rdev);
3137 if (r)
3138 return r;
3139
3140 evergreen_mc_program(rdev);
3141 if (rdev->flags & RADEON_IS_AGP) {
3142 evergreen_agp_enable(rdev);
3143 } else {
3144 r = evergreen_pcie_gart_enable(rdev);
3145 if (r)
3146 return r;
3147 }
3148 evergreen_gpu_init(rdev);
3149
3150 r = evergreen_blit_init(rdev);
3151 if (r) {
3152 r600_blit_fini(rdev);
3153 rdev->asic->copy.copy = NULL;
3154 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3155 }
3156
3157 /* allocate wb buffer */
3158 r = radeon_wb_init(rdev);
3159 if (r)
3160 return r;
3161
3162 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3163 if (r) {
3164 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3165 return r;
3166 }
3167
3168 /* Enable IRQ */
3169 r = r600_irq_init(rdev);
3170 if (r) {
3171 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3172 radeon_irq_kms_fini(rdev);
3173 return r;
3174 }
3175 evergreen_irq_set(rdev);
3176
3177 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3178 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3179 0, 0xfffff, RADEON_CP_PACKET2);
3180 if (r)
3181 return r;
3182 r = evergreen_cp_load_microcode(rdev);
3183 if (r)
3184 return r;
3185 r = evergreen_cp_resume(rdev);
3186 if (r)
3187 return r;
3188
3189 r = radeon_ib_pool_init(rdev);
3190 if (r) {
3191 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3192 return r;
3193 }
3194
3195 r = r600_audio_init(rdev);
3196 if (r) {
3197 DRM_ERROR("radeon: audio init failed\n");
3198 return r;
3199 }
3200
3201 return 0;
3202 }
3203
3204 int evergreen_resume(struct radeon_device *rdev)
3205 {
3206 int r;
3207
3208 /* reset the asic, the gfx blocks are often in a bad state
3209 * after the driver is unloaded or after a resume
3210 */
3211 if (radeon_asic_reset(rdev))
3212 dev_warn(rdev->dev, "GPU reset failed !\n");
3213 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3214 * posting will perform necessary task to bring back GPU into good
3215 * shape.
3216 */
3217 /* post card */
3218 atom_asic_init(rdev->mode_info.atom_context);
3219
3220 rdev->accel_working = true;
3221 r = evergreen_startup(rdev);
3222 if (r) {
3223 DRM_ERROR("evergreen startup failed on resume\n");
3224 rdev->accel_working = false;
3225 return r;
3226 }
3227
3228 return r;
3229
3230 }
3231
3232 int evergreen_suspend(struct radeon_device *rdev)
3233 {
3234 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3235
3236 r600_audio_fini(rdev);
3237 r700_cp_stop(rdev);
3238 ring->ready = false;
3239 evergreen_irq_suspend(rdev);
3240 radeon_wb_disable(rdev);
3241 evergreen_pcie_gart_disable(rdev);
3242
3243 return 0;
3244 }
3245
3246 /* Plan is to move initialization in that function and use
3247 * helper function so that radeon_device_init pretty much
3248 * do nothing more than calling asic specific function. This
3249 * should also allow to remove a bunch of callback function
3250 * like vram_info.
3251 */
3252 int evergreen_init(struct radeon_device *rdev)
3253 {
3254 int r;
3255
3256 /* Read BIOS */
3257 if (!radeon_get_bios(rdev)) {
3258 if (ASIC_IS_AVIVO(rdev))
3259 return -EINVAL;
3260 }
3261 /* Must be an ATOMBIOS */
3262 if (!rdev->is_atom_bios) {
3263 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3264 return -EINVAL;
3265 }
3266 r = radeon_atombios_init(rdev);
3267 if (r)
3268 return r;
3269 /* reset the asic, the gfx blocks are often in a bad state
3270 * after the driver is unloaded or after a resume
3271 */
3272 if (radeon_asic_reset(rdev))
3273 dev_warn(rdev->dev, "GPU reset failed !\n");
3274 /* Post card if necessary */
3275 if (!radeon_card_posted(rdev)) {
3276 if (!rdev->bios) {
3277 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3278 return -EINVAL;
3279 }
3280 DRM_INFO("GPU not posted. posting now...\n");
3281 atom_asic_init(rdev->mode_info.atom_context);
3282 }
3283 /* Initialize scratch registers */
3284 r600_scratch_init(rdev);
3285 /* Initialize surface registers */
3286 radeon_surface_init(rdev);
3287 /* Initialize clocks */
3288 radeon_get_clock_info(rdev->ddev);
3289 /* Fence driver */
3290 r = radeon_fence_driver_init(rdev);
3291 if (r)
3292 return r;
3293 /* initialize AGP */
3294 if (rdev->flags & RADEON_IS_AGP) {
3295 r = radeon_agp_init(rdev);
3296 if (r)
3297 radeon_agp_disable(rdev);
3298 }
3299 /* initialize memory controller */
3300 r = evergreen_mc_init(rdev);
3301 if (r)
3302 return r;
3303 /* Memory manager */
3304 r = radeon_bo_init(rdev);
3305 if (r)
3306 return r;
3307
3308 r = radeon_irq_kms_init(rdev);
3309 if (r)
3310 return r;
3311
3312 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3313 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3314
3315 rdev->ih.ring_obj = NULL;
3316 r600_ih_ring_init(rdev, 64 * 1024);
3317
3318 r = r600_pcie_gart_init(rdev);
3319 if (r)
3320 return r;
3321
3322 rdev->accel_working = true;
3323 r = evergreen_startup(rdev);
3324 if (r) {
3325 dev_err(rdev->dev, "disabling GPU acceleration\n");
3326 r700_cp_fini(rdev);
3327 r600_irq_fini(rdev);
3328 radeon_wb_fini(rdev);
3329 radeon_ib_pool_fini(rdev);
3330 radeon_irq_kms_fini(rdev);
3331 evergreen_pcie_gart_fini(rdev);
3332 rdev->accel_working = false;
3333 }
3334
3335 /* Don't start up if the MC ucode is missing on BTC parts.
3336 * The default clocks and voltages before the MC ucode
3337 * is loaded are not suffient for advanced operations.
3338 */
3339 if (ASIC_IS_DCE5(rdev)) {
3340 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3341 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3342 return -EINVAL;
3343 }
3344 }
3345
3346 return 0;
3347 }
3348
3349 void evergreen_fini(struct radeon_device *rdev)
3350 {
3351 r600_audio_fini(rdev);
3352 r600_blit_fini(rdev);
3353 r700_cp_fini(rdev);
3354 r600_irq_fini(rdev);
3355 radeon_wb_fini(rdev);
3356 radeon_ib_pool_fini(rdev);
3357 radeon_irq_kms_fini(rdev);
3358 evergreen_pcie_gart_fini(rdev);
3359 r600_vram_scratch_fini(rdev);
3360 radeon_gem_fini(rdev);
3361 radeon_fence_driver_fini(rdev);
3362 radeon_agp_fini(rdev);
3363 radeon_bo_fini(rdev);
3364 radeon_atombios_fini(rdev);
3365 kfree(rdev->bios);
3366 rdev->bios = NULL;
3367 }
3368
3369 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3370 {
3371 u32 link_width_cntl, speed_cntl, mask;
3372 int ret;
3373
3374 if (radeon_pcie_gen2 == 0)
3375 return;
3376
3377 if (rdev->flags & RADEON_IS_IGP)
3378 return;
3379
3380 if (!(rdev->flags & RADEON_IS_PCIE))
3381 return;
3382
3383 /* x2 cards have a special sequence */
3384 if (ASIC_IS_X2(rdev))
3385 return;
3386
3387 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
3388 if (ret != 0)
3389 return;
3390
3391 if (!(mask & DRM_PCIE_SPEED_50))
3392 return;
3393
3394 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3395
3396 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3397 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3398 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3399
3400 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3401 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3402 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3403
3404 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3405 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3406 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3407
3408 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3409 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3410 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3411
3412 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3413 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3414 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3415
3416 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3417 speed_cntl |= LC_GEN2_EN_STRAP;
3418 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3419
3420 } else {
3421 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3422 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3423 if (1)
3424 link_width_cntl |= LC_UPCONFIGURE_DIS;
3425 else
3426 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3427 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3428 }
3429 }
kernel source for telekom puls (alcatel/mediatek)