drivers/gpu/drm/r128/r128_drv.h

   1 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
   2  * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
   3  */
   4 /*
   5  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   6  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   7  * All rights reserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Rickard E. (Rik) Faith <faith@valinux.com>
  30  *    Kevin E. Martin <martin@valinux.com>
  31  *    Gareth Hughes <gareth@valinux.com>
  32  *    Michel D�zer <daenzerm@student.ethz.ch>
  33  */
  34
  35 #ifndef __R128_DRV_H__
  36 #define __R128_DRV_H__
  37
  38 /* General customization:
  39  */
  40 #define DRIVER_AUTHOR           "Gareth Hughes, VA Linux Systems Inc."
  41
  42 #define DRIVER_NAME             "r128"
  43 #define DRIVER_DESC             "ATI Rage 128"
  44 #define DRIVER_DATE             "20030725"
  45
  46 /* Interface history:
  47  *
  48  * ??  - ??
  49  * 2.4 - Add support for ycbcr textures (no new ioctls)
  50  * 2.5 - Add FLIP ioctl, disable FULLSCREEN.
  51  */
  52 #define DRIVER_MAJOR            2
  53 #define DRIVER_MINOR            5
  54 #define DRIVER_PATCHLEVEL       0
  55
  56 #define GET_RING_HEAD(dev_priv)         R128_READ( R128_PM4_BUFFER_DL_RPTR )
  57
  58 typedef struct drm_r128_freelist {
  59         unsigned int age;
  60         struct drm_buf *buf;
  61         struct drm_r128_freelist *next;
  62         struct drm_r128_freelist *prev;
  63 } drm_r128_freelist_t;
  64
  65 typedef struct drm_r128_ring_buffer {
  66         u32 *start;
  67         u32 *end;
  68         int size;
  69         int size_l2qw;
  70
  71         u32 tail;
  72         u32 tail_mask;
  73         int space;
  74
  75         int high_mark;
  76 } drm_r128_ring_buffer_t;
  77
  78 typedef struct drm_r128_private {
  79         drm_r128_ring_buffer_t ring;
  80         drm_r128_sarea_t *sarea_priv;
  81
  82         int cce_mode;
  83         int cce_fifo_size;
  84         int cce_running;
  85
  86         drm_r128_freelist_t *head;
  87         drm_r128_freelist_t *tail;
  88
  89         int usec_timeout;
  90         int is_pci;
  91         unsigned long cce_buffers_offset;
  92
  93         atomic_t idle_count;
  94
  95         int page_flipping;
  96         int current_page;
  97         u32 crtc_offset;
  98         u32 crtc_offset_cntl;
  99
 100         atomic_t vbl_received;
 101
 102         u32 color_fmt;
 103         unsigned int front_offset;
 104         unsigned int front_pitch;
 105         unsigned int back_offset;
 106         unsigned int back_pitch;
 107
 108         u32 depth_fmt;
 109         unsigned int depth_offset;
 110         unsigned int depth_pitch;
 111         unsigned int span_offset;
 112
 113         u32 front_pitch_offset_c;
 114         u32 back_pitch_offset_c;
 115         u32 depth_pitch_offset_c;
 116         u32 span_pitch_offset_c;
 117
 118         drm_local_map_t *sarea;
 119         drm_local_map_t *mmio;
 120         drm_local_map_t *cce_ring;
 121         drm_local_map_t *ring_rptr;
 122         drm_local_map_t *agp_textures;
 123         struct drm_ati_pcigart_info gart_info;
 124 } drm_r128_private_t;
 125
 126 typedef struct drm_r128_buf_priv {
 127         u32 age;
 128         int prim;
 129         int discard;
 130         int dispatched;
 131         drm_r128_freelist_t *list_entry;
 132 } drm_r128_buf_priv_t;
 133
 134 extern struct drm_ioctl_desc r128_ioctls[];
 135 extern int r128_max_ioctl;
 136
 137                                 /* r128_cce.c */
 138 extern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
 139 extern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
 140 extern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
 141 extern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
 142 extern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
 143 extern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
 144 extern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
 145 extern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
 146
 147 extern void r128_freelist_reset(struct drm_device * dev);
 148
 149 extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n);
 150
 151 extern int r128_do_cce_idle(drm_r128_private_t * dev_priv);
 152 extern int r128_do_cleanup_cce(struct drm_device * dev);
 153
 154 extern int r128_enable_vblank(struct drm_device *dev, int crtc);
 155 extern void r128_disable_vblank(struct drm_device *dev, int crtc);
 156 extern u32 r128_get_vblank_counter(struct drm_device *dev, int crtc);
 157 extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS);
 158 extern void r128_driver_irq_preinstall(struct drm_device * dev);
 159 extern int r128_driver_irq_postinstall(struct drm_device *dev);
 160 extern void r128_driver_irq_uninstall(struct drm_device * dev);
 161 extern void r128_driver_lastclose(struct drm_device * dev);
 162 extern void r128_driver_preclose(struct drm_device * dev,
 163                                  struct drm_file *file_priv);
 164
 165 extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
 166                               unsigned long arg);
 167
 168 /* Register definitions, register access macros and drmAddMap constants
 169  * for Rage 128 kernel driver.
 170  */
 171
 172 #define R128_AUX_SC_CNTL                0x1660
 173 #       define R128_AUX1_SC_EN                  (1 << 0)
 174 #       define R128_AUX1_SC_MODE_OR             (0 << 1)
 175 #       define R128_AUX1_SC_MODE_NAND           (1 << 1)
 176 #       define R128_AUX2_SC_EN                  (1 << 2)
 177 #       define R128_AUX2_SC_MODE_OR             (0 << 3)
 178 #       define R128_AUX2_SC_MODE_NAND           (1 << 3)
 179 #       define R128_AUX3_SC_EN                  (1 << 4)
 180 #       define R128_AUX3_SC_MODE_OR             (0 << 5)
 181 #       define R128_AUX3_SC_MODE_NAND           (1 << 5)
 182 #define R128_AUX1_SC_LEFT               0x1664
 183 #define R128_AUX1_SC_RIGHT              0x1668
 184 #define R128_AUX1_SC_TOP                0x166c
 185 #define R128_AUX1_SC_BOTTOM             0x1670
 186 #define R128_AUX2_SC_LEFT               0x1674
 187 #define R128_AUX2_SC_RIGHT              0x1678
 188 #define R128_AUX2_SC_TOP                0x167c
 189 #define R128_AUX2_SC_BOTTOM             0x1680
 190 #define R128_AUX3_SC_LEFT               0x1684
 191 #define R128_AUX3_SC_RIGHT              0x1688
 192 #define R128_AUX3_SC_TOP                0x168c
 193 #define R128_AUX3_SC_BOTTOM             0x1690
 194
 195 #define R128_BRUSH_DATA0                0x1480
 196 #define R128_BUS_CNTL                   0x0030
 197 #       define R128_BUS_MASTER_DIS              (1 << 6)
 198
 199 #define R128_CLOCK_CNTL_INDEX           0x0008
 200 #define R128_CLOCK_CNTL_DATA            0x000c
 201 #       define R128_PLL_WR_EN                   (1 << 7)
 202 #define R128_CONSTANT_COLOR_C           0x1d34
 203 #define R128_CRTC_OFFSET                0x0224
 204 #define R128_CRTC_OFFSET_CNTL           0x0228
 205 #       define R128_CRTC_OFFSET_FLIP_CNTL       (1 << 16)
 206
 207 #define R128_DP_GUI_MASTER_CNTL         0x146c
 208 #       define R128_GMC_SRC_PITCH_OFFSET_CNTL   (1    <<  0)
 209 #       define R128_GMC_DST_PITCH_OFFSET_CNTL   (1    <<  1)
 210 #       define R128_GMC_BRUSH_SOLID_COLOR       (13   <<  4)
 211 #       define R128_GMC_BRUSH_NONE              (15   <<  4)
 212 #       define R128_GMC_DST_16BPP               (4    <<  8)
 213 #       define R128_GMC_DST_24BPP               (5    <<  8)
 214 #       define R128_GMC_DST_32BPP               (6    <<  8)
 215 #       define R128_GMC_DST_DATATYPE_SHIFT      8
 216 #       define R128_GMC_SRC_DATATYPE_COLOR      (3    << 12)
 217 #       define R128_DP_SRC_SOURCE_MEMORY        (2    << 24)
 218 #       define R128_DP_SRC_SOURCE_HOST_DATA     (3    << 24)
 219 #       define R128_GMC_CLR_CMP_CNTL_DIS        (1    << 28)
 220 #       define R128_GMC_AUX_CLIP_DIS            (1    << 29)
 221 #       define R128_GMC_WR_MSK_DIS              (1    << 30)
 222 #       define R128_ROP3_S                      0x00cc0000
 223 #       define R128_ROP3_P                      0x00f00000
 224 #define R128_DP_WRITE_MASK              0x16cc
 225 #define R128_DST_PITCH_OFFSET_C         0x1c80
 226 #       define R128_DST_TILE                    (1 << 31)
 227
 228 #define R128_GEN_INT_CNTL               0x0040
 229 #       define R128_CRTC_VBLANK_INT_EN          (1 <<  0)
 230 #define R128_GEN_INT_STATUS             0x0044
 231 #       define R128_CRTC_VBLANK_INT             (1 <<  0)
 232 #       define R128_CRTC_VBLANK_INT_AK          (1 <<  0)
 233 #define R128_GEN_RESET_CNTL             0x00f0
 234 #       define R128_SOFT_RESET_GUI              (1 <<  0)
 235
 236 #define R128_GUI_SCRATCH_REG0           0x15e0
 237 #define R128_GUI_SCRATCH_REG1           0x15e4
 238 #define R128_GUI_SCRATCH_REG2           0x15e8
 239 #define R128_GUI_SCRATCH_REG3           0x15ec
 240 #define R128_GUI_SCRATCH_REG4           0x15f0
 241 #define R128_GUI_SCRATCH_REG5           0x15f4
 242
 243 #define R128_GUI_STAT                   0x1740
 244 #       define R128_GUI_FIFOCNT_MASK            0x0fff
 245 #       define R128_GUI_ACTIVE                  (1 << 31)
 246
 247 #define R128_MCLK_CNTL                  0x000f
 248 #       define R128_FORCE_GCP                   (1 << 16)
 249 #       define R128_FORCE_PIPE3D_CP             (1 << 17)
 250 #       define R128_FORCE_RCP                   (1 << 18)
 251
 252 #define R128_PC_GUI_CTLSTAT             0x1748
 253 #define R128_PC_NGUI_CTLSTAT            0x0184
 254 #       define R128_PC_FLUSH_GUI                (3 << 0)
 255 #       define R128_PC_RI_GUI                   (1 << 2)
 256 #       define R128_PC_FLUSH_ALL                0x00ff
 257 #       define R128_PC_BUSY                     (1 << 31)
 258
 259 #define R128_PCI_GART_PAGE              0x017c
 260 #define R128_PRIM_TEX_CNTL_C            0x1cb0
 261
 262 #define R128_SCALE_3D_CNTL              0x1a00
 263 #define R128_SEC_TEX_CNTL_C             0x1d00
 264 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
 265 #define R128_SETUP_CNTL                 0x1bc4
 266 #define R128_STEN_REF_MASK_C            0x1d40
 267
 268 #define R128_TEX_CNTL_C                 0x1c9c
 269 #       define R128_TEX_CACHE_FLUSH             (1 << 23)
 270
 271 #define R128_WAIT_UNTIL                 0x1720
 272 #       define R128_EVENT_CRTC_OFFSET           (1 << 0)
 273 #define R128_WINDOW_XY_OFFSET           0x1bcc
 274
 275 /* CCE registers
 276  */
 277 #define R128_PM4_BUFFER_OFFSET          0x0700
 278 #define R128_PM4_BUFFER_CNTL            0x0704
 279 #       define R128_PM4_MASK                    (15 << 28)
 280 #       define R128_PM4_NONPM4                  (0  << 28)
 281 #       define R128_PM4_192PIO                  (1  << 28)
 282 #       define R128_PM4_192BM                   (2  << 28)
 283 #       define R128_PM4_128PIO_64INDBM          (3  << 28)
 284 #       define R128_PM4_128BM_64INDBM           (4  << 28)
 285 #       define R128_PM4_64PIO_128INDBM          (5  << 28)
 286 #       define R128_PM4_64BM_128INDBM           (6  << 28)
 287 #       define R128_PM4_64PIO_64VCBM_64INDBM    (7  << 28)
 288 #       define R128_PM4_64BM_64VCBM_64INDBM     (8  << 28)
 289 #       define R128_PM4_64PIO_64VCPIO_64INDPIO  (15 << 28)
 290 #       define R128_PM4_BUFFER_CNTL_NOUPDATE    (1  << 27)
 291
 292 #define R128_PM4_BUFFER_WM_CNTL         0x0708
 293 #       define R128_WMA_SHIFT                   0
 294 #       define R128_WMB_SHIFT                   8
 295 #       define R128_WMC_SHIFT                   16
 296 #       define R128_WB_WM_SHIFT                 24
 297
 298 #define R128_PM4_BUFFER_DL_RPTR_ADDR    0x070c
 299 #define R128_PM4_BUFFER_DL_RPTR         0x0710
 300 #define R128_PM4_BUFFER_DL_WPTR         0x0714
 301 #       define R128_PM4_BUFFER_DL_DONE          (1 << 31)
 302
 303 #define R128_PM4_VC_FPU_SETUP           0x071c
 304
 305 #define R128_PM4_IW_INDOFF              0x0738
 306 #define R128_PM4_IW_INDSIZE             0x073c
 307
 308 #define R128_PM4_STAT                   0x07b8
 309 #       define R128_PM4_FIFOCNT_MASK            0x0fff
 310 #       define R128_PM4_BUSY                    (1 << 16)
 311 #       define R128_PM4_GUI_ACTIVE              (1 << 31)
 312
 313 #define R128_PM4_MICROCODE_ADDR         0x07d4
 314 #define R128_PM4_MICROCODE_RADDR        0x07d8
 315 #define R128_PM4_MICROCODE_DATAH        0x07dc
 316 #define R128_PM4_MICROCODE_DATAL        0x07e0
 317
 318 #define R128_PM4_BUFFER_ADDR            0x07f0
 319 #define R128_PM4_MICRO_CNTL             0x07fc
 320 #       define R128_PM4_MICRO_FREERUN           (1 << 30)
 321
 322 #define R128_PM4_FIFO_DATA_EVEN         0x1000
 323 #define R128_PM4_FIFO_DATA_ODD          0x1004
 324
 325 /* CCE command packets
 326  */
 327 #define R128_CCE_PACKET0                0x00000000
 328 #define R128_CCE_PACKET1                0x40000000
 329 #define R128_CCE_PACKET2                0x80000000
 330 #define R128_CCE_PACKET3                0xC0000000
 331 #       define R128_CNTL_HOSTDATA_BLT           0x00009400
 332 #       define R128_CNTL_PAINT_MULTI            0x00009A00
 333 #       define R128_CNTL_BITBLT_MULTI           0x00009B00
 334 #       define R128_3D_RNDR_GEN_INDX_PRIM       0x00002300
 335
 336 #define R128_CCE_PACKET_MASK            0xC0000000
 337 #define R128_CCE_PACKET_COUNT_MASK      0x3fff0000
 338 #define R128_CCE_PACKET0_REG_MASK       0x000007ff
 339 #define R128_CCE_PACKET1_REG0_MASK      0x000007ff
 340 #define R128_CCE_PACKET1_REG1_MASK      0x003ff800
 341
 342 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE         0x00000000
 343 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT        0x00000001
 344 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE         0x00000002
 345 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE    0x00000003
 346 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST     0x00000004
 347 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN      0x00000005
 348 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP    0x00000006
 349 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2    0x00000007
 350 #define R128_CCE_VC_CNTL_PRIM_WALK_IND          0x00000010
 351 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST         0x00000020
 352 #define R128_CCE_VC_CNTL_PRIM_WALK_RING         0x00000030
 353 #define R128_CCE_VC_CNTL_NUM_SHIFT              16
 354
 355 #define R128_DATATYPE_VQ                0
 356 #define R128_DATATYPE_CI4               1
 357 #define R128_DATATYPE_CI8               2
 358 #define R128_DATATYPE_ARGB1555          3
 359 #define R128_DATATYPE_RGB565            4
 360 #define R128_DATATYPE_RGB888            5
 361 #define R128_DATATYPE_ARGB8888          6
 362 #define R128_DATATYPE_RGB332            7
 363 #define R128_DATATYPE_Y8                8
 364 #define R128_DATATYPE_RGB8              9
 365 #define R128_DATATYPE_CI16              10
 366 #define R128_DATATYPE_YVYU422           11
 367 #define R128_DATATYPE_VYUY422           12
 368 #define R128_DATATYPE_AYUV444           14
 369 #define R128_DATATYPE_ARGB4444          15
 370
 371 /* Constants */
 372 #define R128_AGP_OFFSET                 0x02000000
 373
 374 #define R128_WATERMARK_L                16
 375 #define R128_WATERMARK_M                8
 376 #define R128_WATERMARK_N                8
 377 #define R128_WATERMARK_K                128
 378
 379 #define R128_MAX_USEC_TIMEOUT           100000  /* 100 ms */
 380
 381 #define R128_LAST_FRAME_REG             R128_GUI_SCRATCH_REG0
 382 #define R128_LAST_DISPATCH_REG          R128_GUI_SCRATCH_REG1
 383 #define R128_MAX_VB_AGE                 0x7fffffff
 384 #define R128_MAX_VB_VERTS               (0xffff)
 385
 386 #define R128_RING_HIGH_MARK             128
 387
 388 #define R128_PERFORMANCE_BOXES          0
 389
 390 #define R128_PCIGART_TABLE_SIZE         32768
 391
 392 #define R128_READ(reg)          DRM_READ32(  dev_priv->mmio, (reg) )
 393 #define R128_WRITE(reg,val)     DRM_WRITE32( dev_priv->mmio, (reg), (val) )
 394 #define R128_READ8(reg)         DRM_READ8(   dev_priv->mmio, (reg) )
 395 #define R128_WRITE8(reg,val)    DRM_WRITE8(  dev_priv->mmio, (reg), (val) )
 396
 397 #define R128_WRITE_PLL(addr,val)                                        \
 398 do {                                                                    \
 399         R128_WRITE8(R128_CLOCK_CNTL_INDEX,                              \
 400                     ((addr) & 0x1f) | R128_PLL_WR_EN);                  \
 401         R128_WRITE(R128_CLOCK_CNTL_DATA, (val));                        \
 402 } while (0)
 403
 404 #define CCE_PACKET0( reg, n )           (R128_CCE_PACKET0 |             \
 405                                          ((n) << 16) | ((reg) >> 2))
 406 #define CCE_PACKET1( reg0, reg1 )       (R128_CCE_PACKET1 |             \
 407                                          (((reg1) >> 2) << 11) | ((reg0) >> 2))
 408 #define CCE_PACKET2()                   (R128_CCE_PACKET2)
 409 #define CCE_PACKET3( pkt, n )           (R128_CCE_PACKET3 |             \
 410                                          (pkt) | ((n) << 16))
 411
 412 static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv)
 413 {
 414         drm_r128_ring_buffer_t *ring = &dev_priv->ring;
 415         ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32);
 416         if (ring->space <= 0)
 417                 ring->space += ring->size;
 418 }
 419
 420 /* ================================================================
 421  * Misc helper macros
 422  */
 423
 424 #define RING_SPACE_TEST_WITH_RETURN( dev_priv )                         \
 425 do {                                                                    \
 426         drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i;          \
 427         if ( ring->space < ring->high_mark ) {                          \
 428                 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {      \
 429                         r128_update_ring_snapshot( dev_priv );          \
 430                         if ( ring->space >= ring->high_mark )           \
 431                                 goto __ring_space_done;                 \
 432                         DRM_UDELAY(1);                          \
 433                 }                                                       \
 434                 DRM_ERROR( "ring space check failed!\n" );              \
 435                 return -EBUSY;                          \
 436         }                                                               \
 437  __ring_space_done:                                                     \
 438         ;                                                               \
 439 } while (0)
 440
 441 #define VB_AGE_TEST_WITH_RETURN( dev_priv )                             \
 442 do {                                                                    \
 443         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;            \
 444         if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) {           \
 445                 int __ret = r128_do_cce_idle( dev_priv );               \
 446                 if ( __ret ) return __ret;                              \
 447                 sarea_priv->last_dispatch = 0;                          \
 448                 r128_freelist_reset( dev );                             \
 449         }                                                               \
 450 } while (0)
 451
 452 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do {                             \
 453         OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) );                  \
 454         OUT_RING( R128_EVENT_CRTC_OFFSET );                             \
 455 } while (0)
 456
 457 /* ================================================================
 458  * Ring control
 459  */
 460
 461 #define R128_VERBOSE    0
 462
 463 #define RING_LOCALS                                                     \
 464         int write, _nr; unsigned int tail_mask; volatile u32 *ring;
 465
 466 #define BEGIN_RING( n ) do {                                            \
 467         if ( R128_VERBOSE ) {                                           \
 468                 DRM_INFO( "BEGIN_RING( %d )\n", (n));                   \
 469         }                                                               \
 470         if ( dev_priv->ring.space <= (n) * sizeof(u32) ) {              \
 471                 COMMIT_RING();                                          \
 472                 r128_wait_ring( dev_priv, (n) * sizeof(u32) );          \
 473         }                                                               \
 474         _nr = n; dev_priv->ring.space -= (n) * sizeof(u32);             \
 475         ring = dev_priv->ring.start;                                    \
 476         write = dev_priv->ring.tail;                                    \
 477         tail_mask = dev_priv->ring.tail_mask;                           \
 478 } while (0)
 479
 480 /* You can set this to zero if you want.  If the card locks up, you'll
 481  * need to keep this set.  It works around a bug in early revs of the
 482  * Rage 128 chipset, where the CCE would read 32 dwords past the end of
 483  * the ring buffer before wrapping around.
 484  */
 485 #define R128_BROKEN_CCE 1
 486
 487 #define ADVANCE_RING() do {                                             \
 488         if ( R128_VERBOSE ) {                                           \
 489                 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n",     \
 490                           write, dev_priv->ring.tail );                 \
 491         }                                                               \
 492         if ( R128_BROKEN_CCE && write < 32 ) {                          \
 493                 memcpy( dev_priv->ring.end,                             \
 494                         dev_priv->ring.start,                           \
 495                         write * sizeof(u32) );                          \
 496         }                                                               \
 497         if (((dev_priv->ring.tail + _nr) & tail_mask) != write) {       \
 498                 DRM_ERROR(                                              \
 499                         "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n",        \
 500                         ((dev_priv->ring.tail + _nr) & tail_mask),      \
 501                         write, __LINE__);                               \
 502         } else                                                          \
 503                 dev_priv->ring.tail = write;                            \
 504 } while (0)
 505
 506 #define COMMIT_RING() do {                                              \
 507         if ( R128_VERBOSE ) {                                           \
 508                 DRM_INFO( "COMMIT_RING() tail=0x%06x\n",                \
 509                         dev_priv->ring.tail );                          \
 510         }                                                               \
 511         DRM_MEMORYBARRIER();                                            \
 512         R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail );     \
 513         R128_READ( R128_PM4_BUFFER_DL_WPTR );                           \
 514 } while (0)
 515
 516 #define OUT_RING( x ) do {                                              \
 517         if ( R128_VERBOSE ) {                                           \
 518                 DRM_INFO( "   OUT_RING( 0x%08x ) at 0x%x\n",            \
 519                            (unsigned int)(x), write );                  \
 520         }                                                               \
 521         ring[write++] = cpu_to_le32( x );                               \
 522         write &= tail_mask;                                             \
 523 } while (0)
 524
 525 #endif                          /* __R128_DRV_H__ */