drm/nouveau: port all engines to new engine module format
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / gpu / drm / nouveau / nvc0_fence.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <core/object.h>
26 #include <core/client.h>
27 #include <core/class.h>
28
29 #include <engine/fifo.h>
30
31 #include "nouveau_drm.h"
32 #include "nouveau_dma.h"
33 #include "nouveau_fence.h"
34
35 struct nvc0_fence_priv {
36 struct nouveau_fence_priv base;
37 struct nouveau_bo *bo;
38 u32 *suspend;
39 };
40
41 struct nvc0_fence_chan {
42 struct nouveau_fence_chan base;
43 struct nouveau_vma vma;
44 struct nouveau_vma dispc_vma[4];
45 };
46
47 u64
48 nvc0_fence_crtc(struct nouveau_channel *chan, int crtc)
49 {
50 struct nvc0_fence_chan *fctx = chan->fence;
51 return fctx->dispc_vma[crtc].offset;
52 }
53
54 static int
55 nvc0_fence_emit(struct nouveau_fence *fence)
56 {
57 struct nouveau_channel *chan = fence->channel;
58 struct nvc0_fence_chan *fctx = chan->fence;
59 struct nouveau_fifo_chan *fifo = (void *)chan->object;
60 u64 addr = fctx->vma.offset + fifo->chid * 16;
61 int ret;
62
63 ret = RING_SPACE(chan, 5);
64 if (ret == 0) {
65 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
66 OUT_RING (chan, upper_32_bits(addr));
67 OUT_RING (chan, lower_32_bits(addr));
68 OUT_RING (chan, fence->sequence);
69 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
70 FIRE_RING (chan);
71 }
72
73 return ret;
74 }
75
76 static int
77 nvc0_fence_sync(struct nouveau_fence *fence,
78 struct nouveau_channel *prev, struct nouveau_channel *chan)
79 {
80 struct nvc0_fence_chan *fctx = chan->fence;
81 struct nouveau_fifo_chan *fifo = (void *)prev->object;
82 u64 addr = fctx->vma.offset + fifo->chid * 16;
83 int ret;
84
85 ret = RING_SPACE(chan, 5);
86 if (ret == 0) {
87 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
88 OUT_RING (chan, upper_32_bits(addr));
89 OUT_RING (chan, lower_32_bits(addr));
90 OUT_RING (chan, fence->sequence);
91 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
92 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
93 FIRE_RING (chan);
94 }
95
96 return ret;
97 }
98
99 static u32
100 nvc0_fence_read(struct nouveau_channel *chan)
101 {
102 struct nouveau_fifo_chan *fifo = (void *)chan->object;
103 struct nvc0_fence_priv *priv = chan->drm->fence;
104 return nouveau_bo_rd32(priv->bo, fifo->chid * 16/4);
105 }
106
107 static void
108 nvc0_fence_context_del(struct nouveau_channel *chan)
109 {
110 struct drm_device *dev = chan->drm->dev;
111 struct nvc0_fence_priv *priv = chan->drm->fence;
112 struct nvc0_fence_chan *fctx = chan->fence;
113 int i;
114
115 if (nv_device(chan->drm->device)->card_type >= NV_D0) {
116 for (i = 0; i < dev->mode_config.num_crtc; i++) {
117 struct nouveau_bo *bo = nvd0sema(dev, i);
118 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
119 }
120 } else
121 if (nv_device(chan->drm->device)->card_type >= NV_50) {
122 for (i = 0; i < dev->mode_config.num_crtc; i++) {
123 struct nouveau_bo *bo = nv50sema(dev, i);
124 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
125 }
126 }
127
128 nouveau_bo_vma_del(priv->bo, &fctx->vma);
129 nouveau_fence_context_del(&fctx->base);
130 chan->fence = NULL;
131 kfree(fctx);
132 }
133
134 static int
135 nvc0_fence_context_new(struct nouveau_channel *chan)
136 {
137 struct nouveau_fifo_chan *fifo = (void *)chan->object;
138 struct nouveau_client *client = nouveau_client(fifo);
139 struct nvc0_fence_priv *priv = chan->drm->fence;
140 struct nvc0_fence_chan *fctx;
141 int ret, i;
142
143 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
144 if (!fctx)
145 return -ENOMEM;
146
147 nouveau_fence_context_new(&fctx->base);
148
149 ret = nouveau_bo_vma_add(priv->bo, client->vm, &fctx->vma);
150 if (ret)
151 nvc0_fence_context_del(chan);
152
153 /* map display semaphore buffers into channel's vm */
154 for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
155 struct nouveau_bo *bo;
156 if (nv_device(chan->drm->device)->card_type >= NV_D0)
157 bo = nvd0sema(chan->drm->dev, i);
158 else
159 bo = nv50sema(chan->drm->dev, i);
160
161 ret = nouveau_bo_vma_add(bo, client->vm, &fctx->dispc_vma[i]);
162 }
163
164 nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, 0x00000000);
165 return ret;
166 }
167
168 static bool
169 nvc0_fence_suspend(struct nouveau_drm *drm)
170 {
171 struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
172 struct nvc0_fence_priv *priv = drm->fence;
173 int i;
174
175 priv->suspend = vmalloc((pfifo->max + 1) * sizeof(u32));
176 if (priv->suspend) {
177 for (i = 0; i <= pfifo->max; i++)
178 priv->suspend[i] = nouveau_bo_rd32(priv->bo, i);
179 }
180
181 return priv->suspend != NULL;
182 }
183
184 static void
185 nvc0_fence_resume(struct nouveau_drm *drm)
186 {
187 struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
188 struct nvc0_fence_priv *priv = drm->fence;
189 int i;
190
191 if (priv->suspend) {
192 for (i = 0; i <= pfifo->max; i++)
193 nouveau_bo_wr32(priv->bo, i, priv->suspend[i]);
194 vfree(priv->suspend);
195 priv->suspend = NULL;
196 }
197 }
198
199 static void
200 nvc0_fence_destroy(struct nouveau_drm *drm)
201 {
202 struct nvc0_fence_priv *priv = drm->fence;
203 nouveau_bo_unmap(priv->bo);
204 nouveau_bo_ref(NULL, &priv->bo);
205 drm->fence = NULL;
206 kfree(priv);
207 }
208
209 int
210 nvc0_fence_create(struct nouveau_drm *drm)
211 {
212 struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
213 struct nvc0_fence_priv *priv;
214 int ret;
215
216 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
217 if (!priv)
218 return -ENOMEM;
219
220 priv->base.dtor = nvc0_fence_destroy;
221 priv->base.suspend = nvc0_fence_suspend;
222 priv->base.resume = nvc0_fence_resume;
223 priv->base.context_new = nvc0_fence_context_new;
224 priv->base.context_del = nvc0_fence_context_del;
225 priv->base.emit = nvc0_fence_emit;
226 priv->base.sync = nvc0_fence_sync;
227 priv->base.read = nvc0_fence_read;
228
229 ret = nouveau_bo_new(drm->dev, 16 * (pfifo->max + 1), 0,
230 TTM_PL_FLAG_VRAM, 0, 0, NULL, &priv->bo);
231 if (ret == 0) {
232 ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
233 if (ret == 0)
234 ret = nouveau_bo_map(priv->bo);
235 if (ret)
236 nouveau_bo_ref(NULL, &priv->bo);
237 }
238
239 if (ret)
240 nvc0_fence_destroy(drm);
241 return ret;
242 }