drivers/gpu/drm/nouveau/nv40_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include <drm/drmP.h>
  28 #include "nouveau_drv.h"
  29 #include "nouveau_fifo.h"
  30 #include "nouveau_ramht.h"
  31
  32 struct nv40_graph_engine {
  33         struct nouveau_exec_engine base;
  34         u32 grctx_size;
  35 };
  36
  37 static int
  38 nv40_graph_context_new(struct nouveau_channel *chan, int engine)
  39 {
  40         struct nv40_graph_engine *pgraph = nv_engine(chan->dev, engine);
  41         struct drm_device *dev = chan->dev;
  42         struct drm_nouveau_private *dev_priv = dev->dev_private;
  43         struct nouveau_gpuobj *grctx = NULL;
  44         unsigned long flags;
  45         int ret;
  46
  47         ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
  48                                  NVOBJ_FLAG_ZERO_ALLOC, &grctx);
  49         if (ret)
  50                 return ret;
  51
  52         /* Initialise default context values */
  53         nv40_grctx_fill(dev, grctx);
  54         nv_wo32(grctx, 0, grctx->vinst);
  55
  56         /* init grctx pointer in ramfc, and on PFIFO if channel is
  57          * already active there
  58          */
  59         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
  60         nv_wo32(chan->ramfc, 0x38, grctx->vinst >> 4);
  61         nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
  62         if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
  63                 nv_wr32(dev, 0x0032e0, grctx->vinst >> 4);
  64         nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
  65         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
  66
  67         chan->engctx[engine] = grctx;
  68         return 0;
  69 }
  70
  71 static void
  72 nv40_graph_context_del(struct nouveau_channel *chan, int engine)
  73 {
  74         struct nouveau_gpuobj *grctx = chan->engctx[engine];
  75         struct drm_device *dev = chan->dev;
  76         struct drm_nouveau_private *dev_priv = dev->dev_private;
  77         u32 inst = 0x01000000 | (grctx->pinst >> 4);
  78         unsigned long flags;
  79
  80         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
  81         nv_mask(dev, 0x400720, 0x00000000, 0x00000001);
  82         if (nv_rd32(dev, 0x40032c) == inst)
  83                 nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
  84         if (nv_rd32(dev, 0x400330) == inst)
  85                 nv_mask(dev, 0x400330, 0x01000000, 0x00000000);
  86         nv_mask(dev, 0x400720, 0x00000001, 0x00000001);
  87         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
  88
  89         /* Free the context resources */
  90         nouveau_gpuobj_ref(NULL, &grctx);
  91         chan->engctx[engine] = NULL;
  92 }
  93
  94 int
  95 nv40_graph_object_new(struct nouveau_channel *chan, int engine,
  96                       u32 handle, u16 class)
  97 {
  98         struct drm_device *dev = chan->dev;
  99         struct nouveau_gpuobj *obj = NULL;
 100         int ret;
 101
 102         ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
 103         if (ret)
 104                 return ret;
 105         obj->engine = 1;
 106         obj->class  = class;
 107
 108         nv_wo32(obj, 0x00, class);
 109         nv_wo32(obj, 0x04, 0x00000000);
 110 #ifndef __BIG_ENDIAN
 111         nv_wo32(obj, 0x08, 0x00000000);
 112 #else
 113         nv_wo32(obj, 0x08, 0x01000000);
 114 #endif
 115         nv_wo32(obj, 0x0c, 0x00000000);
 116         nv_wo32(obj, 0x10, 0x00000000);
 117
 118         ret = nouveau_ramht_insert(chan, handle, obj);
 119         nouveau_gpuobj_ref(NULL, &obj);
 120         return ret;
 121 }
 122
 123 static void
 124 nv40_graph_set_tile_region(struct drm_device *dev, int i)
 125 {
 126         struct drm_nouveau_private *dev_priv = dev->dev_private;
 127         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
 128
 129         switch (dev_priv->chipset) {
 130         case 0x40:
 131         case 0x41: /* guess */
 132         case 0x42:
 133         case 0x43:
 134         case 0x45: /* guess */
 135         case 0x4e:
 136                 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
 137                 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
 138                 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
 139                 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 140                 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 141                 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
 142                 break;
 143         case 0x44:
 144         case 0x4a:
 145                 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
 146                 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
 147                 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
 148                 break;
 149         case 0x46:
 150         case 0x47:
 151         case 0x49:
 152         case 0x4b:
 153         case 0x4c:
 154         case 0x67:
 155         default:
 156                 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
 157                 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
 158                 nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
 159                 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 160                 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 161                 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
 162                 break;
 163         }
 164 }
 165
 166 /*
 167  * G70          0x47
 168  * G71          0x49
 169  * NV45         0x48
 170  * G72[M]       0x46
 171  * G73          0x4b
 172  * C51_G7X      0x4c
 173  * C51          0x4e
 174  */
 175 int
 176 nv40_graph_init(struct drm_device *dev, int engine)
 177 {
 178         struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
 179         struct drm_nouveau_private *dev_priv = dev->dev_private;
 180         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 181         uint32_t vramsz;
 182         int i, j;
 183
 184         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
 185                         ~NV_PMC_ENABLE_PGRAPH);
 186         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 187                          NV_PMC_ENABLE_PGRAPH);
 188
 189         /* generate and upload context program */
 190         nv40_grctx_init(dev, &pgraph->grctx_size);
 191
 192         /* No context present currently */
 193         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
 194
 195         nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 196         nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
 197
 198         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 199         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
 200         nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
 201         nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
 202         nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
 203         nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
 204
 205         nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 206         nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 207
 208         j = nv_rd32(dev, 0x1540) & 0xff;
 209         if (j) {
 210                 for (i = 0; !(j & 1); j >>= 1, i++)
 211                         ;
 212                 nv_wr32(dev, 0x405000, i);
 213         }
 214
 215         if (dev_priv->chipset == 0x40) {
 216                 nv_wr32(dev, 0x4009b0, 0x83280fff);
 217                 nv_wr32(dev, 0x4009b4, 0x000000a0);
 218         } else {
 219                 nv_wr32(dev, 0x400820, 0x83280eff);
 220                 nv_wr32(dev, 0x400824, 0x000000a0);
 221         }
 222
 223         switch (dev_priv->chipset) {
 224         case 0x40:
 225         case 0x45:
 226                 nv_wr32(dev, 0x4009b8, 0x0078e366);
 227                 nv_wr32(dev, 0x4009bc, 0x0000014c);
 228                 break;
 229         case 0x41:
 230         case 0x42: /* pciid also 0x00Cx */
 231         /* case 0x0120: XXX (pciid) */
 232                 nv_wr32(dev, 0x400828, 0x007596ff);
 233                 nv_wr32(dev, 0x40082c, 0x00000108);
 234                 break;
 235         case 0x43:
 236                 nv_wr32(dev, 0x400828, 0x0072cb77);
 237                 nv_wr32(dev, 0x40082c, 0x00000108);
 238                 break;
 239         case 0x44:
 240         case 0x46: /* G72 */
 241         case 0x4a:
 242         case 0x4c: /* G7x-based C51 */
 243         case 0x4e:
 244                 nv_wr32(dev, 0x400860, 0);
 245                 nv_wr32(dev, 0x400864, 0);
 246                 break;
 247         case 0x47: /* G70 */
 248         case 0x49: /* G71 */
 249         case 0x4b: /* G73 */
 250                 nv_wr32(dev, 0x400828, 0x07830610);
 251                 nv_wr32(dev, 0x40082c, 0x0000016A);
 252                 break;
 253         default:
 254                 break;
 255         }
 256
 257         nv_wr32(dev, 0x400b38, 0x2ffff800);
 258         nv_wr32(dev, 0x400b3c, 0x00006000);
 259
 260         /* Tiling related stuff. */
 261         switch (dev_priv->chipset) {
 262         case 0x44:
 263         case 0x4a:
 264                 nv_wr32(dev, 0x400bc4, 0x1003d888);
 265                 nv_wr32(dev, 0x400bbc, 0xb7a7b500);
 266                 break;
 267         case 0x46:
 268                 nv_wr32(dev, 0x400bc4, 0x0000e024);
 269                 nv_wr32(dev, 0x400bbc, 0xb7a7b520);
 270                 break;
 271         case 0x4c:
 272         case 0x4e:
 273         case 0x67:
 274                 nv_wr32(dev, 0x400bc4, 0x1003d888);
 275                 nv_wr32(dev, 0x400bbc, 0xb7a7b540);
 276                 break;
 277         default:
 278                 break;
 279         }
 280
 281         /* Turn all the tiling regions off. */
 282         for (i = 0; i < pfb->num_tiles; i++)
 283                 nv40_graph_set_tile_region(dev, i);
 284
 285         /* begin RAM config */
 286         vramsz = pci_resource_len(dev->pdev, 0) - 1;
 287         switch (dev_priv->chipset) {
 288         case 0x40:
 289                 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
 290                 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
 291                 nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
 292                 nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
 293                 nv_wr32(dev, 0x400820, 0);
 294                 nv_wr32(dev, 0x400824, 0);
 295                 nv_wr32(dev, 0x400864, vramsz);
 296                 nv_wr32(dev, 0x400868, vramsz);
 297                 break;
 298         default:
 299                 switch (dev_priv->chipset) {
 300                 case 0x41:
 301                 case 0x42:
 302                 case 0x43:
 303                 case 0x45:
 304                 case 0x4e:
 305                 case 0x44:
 306                 case 0x4a:
 307                         nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
 308                         nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
 309                         break;
 310                 default:
 311                         nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
 312                         nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
 313                         break;
 314                 }
 315                 nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
 316                 nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
 317                 nv_wr32(dev, 0x400840, 0);
 318                 nv_wr32(dev, 0x400844, 0);
 319                 nv_wr32(dev, 0x4008A0, vramsz);
 320                 nv_wr32(dev, 0x4008A4, vramsz);
 321                 break;
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int
 328 nv40_graph_fini(struct drm_device *dev, int engine, bool suspend)
 329 {
 330         u32 inst = nv_rd32(dev, 0x40032c);
 331         if (inst & 0x01000000) {
 332                 nv_wr32(dev, 0x400720, 0x00000000);
 333                 nv_wr32(dev, 0x400784, inst);
 334                 nv_mask(dev, 0x400310, 0x00000020, 0x00000020);
 335                 nv_mask(dev, 0x400304, 0x00000001, 0x00000001);
 336                 if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000)) {
 337                         u32 insn = nv_rd32(dev, 0x400308);
 338                         NV_ERROR(dev, "PGRAPH: ctxprog timeout 0x%08x\n", insn);
 339                 }
 340                 nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
 341         }
 342         return 0;
 343 }
 344
 345 static int
 346 nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
 347 {
 348         struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 349         struct drm_nouveau_private *dev_priv = dev->dev_private;
 350         struct nouveau_gpuobj *grctx;
 351         unsigned long flags;
 352         int i;
 353
 354         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 355         for (i = 0; i < pfifo->channels; i++) {
 356                 if (!dev_priv->channels.ptr[i])
 357                         continue;
 358                 grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
 359
 360                 if (grctx && grctx->pinst == inst)
 361                         break;
 362         }
 363         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 364         return i;
 365 }
 366
 367 static void
 368 nv40_graph_isr(struct drm_device *dev)
 369 {
 370         u32 stat;
 371
 372         while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
 373                 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
 374                 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
 375                 u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
 376                 u32 chid = nv40_graph_isr_chid(dev, inst);
 377                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
 378                 u32 subc = (addr & 0x00070000) >> 16;
 379                 u32 mthd = (addr & 0x00001ffc);
 380                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
 381                 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
 382                 u32 show = stat;
 383
 384                 if (stat & NV_PGRAPH_INTR_ERROR) {
 385                         if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 386                                 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
 387                                         show &= ~NV_PGRAPH_INTR_ERROR;
 388                         } else
 389                         if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
 390                                 nv_mask(dev, 0x402000, 0, 0);
 391                         }
 392                 }
 393
 394                 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
 395                 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
 396
 397                 if (show && nouveau_ratelimit()) {
 398                         NV_INFO(dev, "PGRAPH -");
 399                         nouveau_bitfield_print(nv10_graph_intr, show);
 400                         printk(" nsource:");
 401                         nouveau_bitfield_print(nv04_graph_nsource, nsource);
 402                         printk(" nstatus:");
 403                         nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
 404                         printk("\n");
 405                         NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
 406                                      "class 0x%04x mthd 0x%04x data 0x%08x\n",
 407                                 chid, inst, subc, class, mthd, data);
 408                 }
 409         }
 410 }
 411
 412 static void
 413 nv40_graph_destroy(struct drm_device *dev, int engine)
 414 {
 415         struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
 416
 417         nouveau_irq_unregister(dev, 12);
 418
 419         NVOBJ_ENGINE_DEL(dev, GR);
 420         kfree(pgraph);
 421 }
 422
 423 int
 424 nv40_graph_create(struct drm_device *dev)
 425 {
 426         struct nv40_graph_engine *pgraph;
 427
 428         pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
 429         if (!pgraph)
 430                 return -ENOMEM;
 431
 432         pgraph->base.destroy = nv40_graph_destroy;
 433         pgraph->base.init = nv40_graph_init;
 434         pgraph->base.fini = nv40_graph_fini;
 435         pgraph->base.context_new = nv40_graph_context_new;
 436         pgraph->base.context_del = nv40_graph_context_del;
 437         pgraph->base.object_new = nv40_graph_object_new;
 438         pgraph->base.set_tile_region = nv40_graph_set_tile_region;
 439
 440         NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
 441         nouveau_irq_register(dev, 12, nv40_graph_isr);
 442
 443         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 444         NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
 445         NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
 446         NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
 447         NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
 448         NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
 449         NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
 450         NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
 451         NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
 452         NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
 453         NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
 454         NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
 455         NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
 456         NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
 457         NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
 458
 459         /* curie */
 460         if (nv44_graph_class(dev))
 461                 NVOBJ_CLASS(dev, 0x4497, GR);
 462         else
 463                 NVOBJ_CLASS(dev, 0x4097, GR);
 464
 465         return 0;
 466 }