3 #include "nouveau_drv.h"
4 #include "nouveau_drm.h"
9 * There are 3 families :
10 * NV20 is 0x10de:0x020*
11 * NV25/28 is 0x10de:0x025* / 0x10de:0x028*
12 * NV2A is 0x10de:0x02A0
16 * There are 3 families :
17 * NV30/31 is 0x10de:0x030* / 0x10de:0x031*
18 * NV34 is 0x10de:0x032*
19 * NV35/36 is 0x10de:0x033* / 0x10de:0x034*
21 * Not seen in the wild, no dumps (probably NV35) :
22 * NV37 is 0x10de:0x00fc, 0x10de:0x00fd
23 * NV38 is 0x10de:0x0333, 0x10de:0x00fe
27 struct nv20_graph_engine
{
28 struct nouveau_exec_engine base
;
29 struct nouveau_gpuobj
*ctxtab
;
30 void (*grctx_init
)(struct nouveau_gpuobj
*);
35 #define NV20_GRCTX_SIZE (3580*4)
36 #define NV25_GRCTX_SIZE (3529*4)
37 #define NV2A_GRCTX_SIZE (3500*4)
39 #define NV30_31_GRCTX_SIZE (24392)
40 #define NV34_GRCTX_SIZE (18140)
41 #define NV35_36_GRCTX_SIZE (22396)
44 nv20_graph_unload_context(struct drm_device
*dev
)
46 struct nouveau_channel
*chan
;
47 struct nouveau_gpuobj
*grctx
;
50 chan
= nv10_graph_channel(dev
);
53 grctx
= chan
->engctx
[NVOBJ_ENGINE_GR
];
55 nv_wr32(dev
, NV20_PGRAPH_CHANNEL_CTX_POINTER
, grctx
->pinst
>> 4);
56 nv_wr32(dev
, NV20_PGRAPH_CHANNEL_CTX_XFER
,
57 NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE
);
59 nouveau_wait_for_idle(dev
);
61 nv_wr32(dev
, NV10_PGRAPH_CTX_CONTROL
, 0x10000000);
62 tmp
= nv_rd32(dev
, NV10_PGRAPH_CTX_USER
) & 0x00ffffff;
64 nv_wr32(dev
, NV10_PGRAPH_CTX_USER
, tmp
);
69 nv20_graph_rdi(struct drm_device
*dev
)
71 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
72 int i
, writecount
= 32;
73 uint32_t rdi_index
= 0x2c80000;
75 if (dev_priv
->chipset
== 0x20) {
80 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, rdi_index
);
81 for (i
= 0; i
< writecount
; i
++)
82 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, 0);
84 nouveau_wait_for_idle(dev
);
88 nv20_graph_context_init(struct nouveau_gpuobj
*ctx
)
92 nv_wo32(ctx
, 0x033c, 0xffff0000);
93 nv_wo32(ctx
, 0x03a0, 0x0fff0000);
94 nv_wo32(ctx
, 0x03a4, 0x0fff0000);
95 nv_wo32(ctx
, 0x047c, 0x00000101);
96 nv_wo32(ctx
, 0x0490, 0x00000111);
97 nv_wo32(ctx
, 0x04a8, 0x44400000);
98 for (i
= 0x04d4; i
<= 0x04e0; i
+= 4)
99 nv_wo32(ctx
, i
, 0x00030303);
100 for (i
= 0x04f4; i
<= 0x0500; i
+= 4)
101 nv_wo32(ctx
, i
, 0x00080000);
102 for (i
= 0x050c; i
<= 0x0518; i
+= 4)
103 nv_wo32(ctx
, i
, 0x01012000);
104 for (i
= 0x051c; i
<= 0x0528; i
+= 4)
105 nv_wo32(ctx
, i
, 0x000105b8);
106 for (i
= 0x052c; i
<= 0x0538; i
+= 4)
107 nv_wo32(ctx
, i
, 0x00080008);
108 for (i
= 0x055c; i
<= 0x0598; i
+= 4)
109 nv_wo32(ctx
, i
, 0x07ff0000);
110 nv_wo32(ctx
, 0x05a4, 0x4b7fffff);
111 nv_wo32(ctx
, 0x05fc, 0x00000001);
112 nv_wo32(ctx
, 0x0604, 0x00004000);
113 nv_wo32(ctx
, 0x0610, 0x00000001);
114 nv_wo32(ctx
, 0x0618, 0x00040000);
115 nv_wo32(ctx
, 0x061c, 0x00010000);
116 for (i
= 0x1c1c; i
<= 0x248c; i
+= 16) {
117 nv_wo32(ctx
, (i
+ 0), 0x10700ff9);
118 nv_wo32(ctx
, (i
+ 4), 0x0436086c);
119 nv_wo32(ctx
, (i
+ 8), 0x000c001b);
121 nv_wo32(ctx
, 0x281c, 0x3f800000);
122 nv_wo32(ctx
, 0x2830, 0x3f800000);
123 nv_wo32(ctx
, 0x285c, 0x40000000);
124 nv_wo32(ctx
, 0x2860, 0x3f800000);
125 nv_wo32(ctx
, 0x2864, 0x3f000000);
126 nv_wo32(ctx
, 0x286c, 0x40000000);
127 nv_wo32(ctx
, 0x2870, 0x3f800000);
128 nv_wo32(ctx
, 0x2878, 0xbf800000);
129 nv_wo32(ctx
, 0x2880, 0xbf800000);
130 nv_wo32(ctx
, 0x34a4, 0x000fe000);
131 nv_wo32(ctx
, 0x3530, 0x000003f8);
132 nv_wo32(ctx
, 0x3540, 0x002fe000);
133 for (i
= 0x355c; i
<= 0x3578; i
+= 4)
134 nv_wo32(ctx
, i
, 0x001c527c);
138 nv25_graph_context_init(struct nouveau_gpuobj
*ctx
)
142 nv_wo32(ctx
, 0x035c, 0xffff0000);
143 nv_wo32(ctx
, 0x03c0, 0x0fff0000);
144 nv_wo32(ctx
, 0x03c4, 0x0fff0000);
145 nv_wo32(ctx
, 0x049c, 0x00000101);
146 nv_wo32(ctx
, 0x04b0, 0x00000111);
147 nv_wo32(ctx
, 0x04c8, 0x00000080);
148 nv_wo32(ctx
, 0x04cc, 0xffff0000);
149 nv_wo32(ctx
, 0x04d0, 0x00000001);
150 nv_wo32(ctx
, 0x04e4, 0x44400000);
151 nv_wo32(ctx
, 0x04fc, 0x4b800000);
152 for (i
= 0x0510; i
<= 0x051c; i
+= 4)
153 nv_wo32(ctx
, i
, 0x00030303);
154 for (i
= 0x0530; i
<= 0x053c; i
+= 4)
155 nv_wo32(ctx
, i
, 0x00080000);
156 for (i
= 0x0548; i
<= 0x0554; i
+= 4)
157 nv_wo32(ctx
, i
, 0x01012000);
158 for (i
= 0x0558; i
<= 0x0564; i
+= 4)
159 nv_wo32(ctx
, i
, 0x000105b8);
160 for (i
= 0x0568; i
<= 0x0574; i
+= 4)
161 nv_wo32(ctx
, i
, 0x00080008);
162 for (i
= 0x0598; i
<= 0x05d4; i
+= 4)
163 nv_wo32(ctx
, i
, 0x07ff0000);
164 nv_wo32(ctx
, 0x05e0, 0x4b7fffff);
165 nv_wo32(ctx
, 0x0620, 0x00000080);
166 nv_wo32(ctx
, 0x0624, 0x30201000);
167 nv_wo32(ctx
, 0x0628, 0x70605040);
168 nv_wo32(ctx
, 0x062c, 0xb0a09080);
169 nv_wo32(ctx
, 0x0630, 0xf0e0d0c0);
170 nv_wo32(ctx
, 0x0664, 0x00000001);
171 nv_wo32(ctx
, 0x066c, 0x00004000);
172 nv_wo32(ctx
, 0x0678, 0x00000001);
173 nv_wo32(ctx
, 0x0680, 0x00040000);
174 nv_wo32(ctx
, 0x0684, 0x00010000);
175 for (i
= 0x1b04; i
<= 0x2374; i
+= 16) {
176 nv_wo32(ctx
, (i
+ 0), 0x10700ff9);
177 nv_wo32(ctx
, (i
+ 4), 0x0436086c);
178 nv_wo32(ctx
, (i
+ 8), 0x000c001b);
180 nv_wo32(ctx
, 0x2704, 0x3f800000);
181 nv_wo32(ctx
, 0x2718, 0x3f800000);
182 nv_wo32(ctx
, 0x2744, 0x40000000);
183 nv_wo32(ctx
, 0x2748, 0x3f800000);
184 nv_wo32(ctx
, 0x274c, 0x3f000000);
185 nv_wo32(ctx
, 0x2754, 0x40000000);
186 nv_wo32(ctx
, 0x2758, 0x3f800000);
187 nv_wo32(ctx
, 0x2760, 0xbf800000);
188 nv_wo32(ctx
, 0x2768, 0xbf800000);
189 nv_wo32(ctx
, 0x308c, 0x000fe000);
190 nv_wo32(ctx
, 0x3108, 0x000003f8);
191 nv_wo32(ctx
, 0x3468, 0x002fe000);
192 for (i
= 0x3484; i
<= 0x34a0; i
+= 4)
193 nv_wo32(ctx
, i
, 0x001c527c);
197 nv2a_graph_context_init(struct nouveau_gpuobj
*ctx
)
201 nv_wo32(ctx
, 0x033c, 0xffff0000);
202 nv_wo32(ctx
, 0x03a0, 0x0fff0000);
203 nv_wo32(ctx
, 0x03a4, 0x0fff0000);
204 nv_wo32(ctx
, 0x047c, 0x00000101);
205 nv_wo32(ctx
, 0x0490, 0x00000111);
206 nv_wo32(ctx
, 0x04a8, 0x44400000);
207 for (i
= 0x04d4; i
<= 0x04e0; i
+= 4)
208 nv_wo32(ctx
, i
, 0x00030303);
209 for (i
= 0x04f4; i
<= 0x0500; i
+= 4)
210 nv_wo32(ctx
, i
, 0x00080000);
211 for (i
= 0x050c; i
<= 0x0518; i
+= 4)
212 nv_wo32(ctx
, i
, 0x01012000);
213 for (i
= 0x051c; i
<= 0x0528; i
+= 4)
214 nv_wo32(ctx
, i
, 0x000105b8);
215 for (i
= 0x052c; i
<= 0x0538; i
+= 4)
216 nv_wo32(ctx
, i
, 0x00080008);
217 for (i
= 0x055c; i
<= 0x0598; i
+= 4)
218 nv_wo32(ctx
, i
, 0x07ff0000);
219 nv_wo32(ctx
, 0x05a4, 0x4b7fffff);
220 nv_wo32(ctx
, 0x05fc, 0x00000001);
221 nv_wo32(ctx
, 0x0604, 0x00004000);
222 nv_wo32(ctx
, 0x0610, 0x00000001);
223 nv_wo32(ctx
, 0x0618, 0x00040000);
224 nv_wo32(ctx
, 0x061c, 0x00010000);
225 for (i
= 0x1a9c; i
<= 0x22fc; i
+= 16) { /*XXX: check!! */
226 nv_wo32(ctx
, (i
+ 0), 0x10700ff9);
227 nv_wo32(ctx
, (i
+ 4), 0x0436086c);
228 nv_wo32(ctx
, (i
+ 8), 0x000c001b);
230 nv_wo32(ctx
, 0x269c, 0x3f800000);
231 nv_wo32(ctx
, 0x26b0, 0x3f800000);
232 nv_wo32(ctx
, 0x26dc, 0x40000000);
233 nv_wo32(ctx
, 0x26e0, 0x3f800000);
234 nv_wo32(ctx
, 0x26e4, 0x3f000000);
235 nv_wo32(ctx
, 0x26ec, 0x40000000);
236 nv_wo32(ctx
, 0x26f0, 0x3f800000);
237 nv_wo32(ctx
, 0x26f8, 0xbf800000);
238 nv_wo32(ctx
, 0x2700, 0xbf800000);
239 nv_wo32(ctx
, 0x3024, 0x000fe000);
240 nv_wo32(ctx
, 0x30a0, 0x000003f8);
241 nv_wo32(ctx
, 0x33fc, 0x002fe000);
242 for (i
= 0x341c; i
<= 0x3438; i
+= 4)
243 nv_wo32(ctx
, i
, 0x001c527c);
247 nv30_31_graph_context_init(struct nouveau_gpuobj
*ctx
)
251 nv_wo32(ctx
, 0x0410, 0x00000101);
252 nv_wo32(ctx
, 0x0424, 0x00000111);
253 nv_wo32(ctx
, 0x0428, 0x00000060);
254 nv_wo32(ctx
, 0x0444, 0x00000080);
255 nv_wo32(ctx
, 0x0448, 0xffff0000);
256 nv_wo32(ctx
, 0x044c, 0x00000001);
257 nv_wo32(ctx
, 0x0460, 0x44400000);
258 nv_wo32(ctx
, 0x048c, 0xffff0000);
259 for (i
= 0x04e0; i
< 0x04e8; i
+= 4)
260 nv_wo32(ctx
, i
, 0x0fff0000);
261 nv_wo32(ctx
, 0x04ec, 0x00011100);
262 for (i
= 0x0508; i
< 0x0548; i
+= 4)
263 nv_wo32(ctx
, i
, 0x07ff0000);
264 nv_wo32(ctx
, 0x0550, 0x4b7fffff);
265 nv_wo32(ctx
, 0x058c, 0x00000080);
266 nv_wo32(ctx
, 0x0590, 0x30201000);
267 nv_wo32(ctx
, 0x0594, 0x70605040);
268 nv_wo32(ctx
, 0x0598, 0xb8a89888);
269 nv_wo32(ctx
, 0x059c, 0xf8e8d8c8);
270 nv_wo32(ctx
, 0x05b0, 0xb0000000);
271 for (i
= 0x0600; i
< 0x0640; i
+= 4)
272 nv_wo32(ctx
, i
, 0x00010588);
273 for (i
= 0x0640; i
< 0x0680; i
+= 4)
274 nv_wo32(ctx
, i
, 0x00030303);
275 for (i
= 0x06c0; i
< 0x0700; i
+= 4)
276 nv_wo32(ctx
, i
, 0x0008aae4);
277 for (i
= 0x0700; i
< 0x0740; i
+= 4)
278 nv_wo32(ctx
, i
, 0x01012000);
279 for (i
= 0x0740; i
< 0x0780; i
+= 4)
280 nv_wo32(ctx
, i
, 0x00080008);
281 nv_wo32(ctx
, 0x085c, 0x00040000);
282 nv_wo32(ctx
, 0x0860, 0x00010000);
283 for (i
= 0x0864; i
< 0x0874; i
+= 4)
284 nv_wo32(ctx
, i
, 0x00040004);
285 for (i
= 0x1f18; i
<= 0x3088 ; i
+= 16) {
286 nv_wo32(ctx
, i
+ 0, 0x10700ff9);
287 nv_wo32(ctx
, i
+ 1, 0x0436086c);
288 nv_wo32(ctx
, i
+ 2, 0x000c001b);
290 for (i
= 0x30b8; i
< 0x30c8; i
+= 4)
291 nv_wo32(ctx
, i
, 0x0000ffff);
292 nv_wo32(ctx
, 0x344c, 0x3f800000);
293 nv_wo32(ctx
, 0x3808, 0x3f800000);
294 nv_wo32(ctx
, 0x381c, 0x3f800000);
295 nv_wo32(ctx
, 0x3848, 0x40000000);
296 nv_wo32(ctx
, 0x384c, 0x3f800000);
297 nv_wo32(ctx
, 0x3850, 0x3f000000);
298 nv_wo32(ctx
, 0x3858, 0x40000000);
299 nv_wo32(ctx
, 0x385c, 0x3f800000);
300 nv_wo32(ctx
, 0x3864, 0xbf800000);
301 nv_wo32(ctx
, 0x386c, 0xbf800000);
305 nv34_graph_context_init(struct nouveau_gpuobj
*ctx
)
309 nv_wo32(ctx
, 0x040c, 0x01000101);
310 nv_wo32(ctx
, 0x0420, 0x00000111);
311 nv_wo32(ctx
, 0x0424, 0x00000060);
312 nv_wo32(ctx
, 0x0440, 0x00000080);
313 nv_wo32(ctx
, 0x0444, 0xffff0000);
314 nv_wo32(ctx
, 0x0448, 0x00000001);
315 nv_wo32(ctx
, 0x045c, 0x44400000);
316 nv_wo32(ctx
, 0x0480, 0xffff0000);
317 for (i
= 0x04d4; i
< 0x04dc; i
+= 4)
318 nv_wo32(ctx
, i
, 0x0fff0000);
319 nv_wo32(ctx
, 0x04e0, 0x00011100);
320 for (i
= 0x04fc; i
< 0x053c; i
+= 4)
321 nv_wo32(ctx
, i
, 0x07ff0000);
322 nv_wo32(ctx
, 0x0544, 0x4b7fffff);
323 nv_wo32(ctx
, 0x057c, 0x00000080);
324 nv_wo32(ctx
, 0x0580, 0x30201000);
325 nv_wo32(ctx
, 0x0584, 0x70605040);
326 nv_wo32(ctx
, 0x0588, 0xb8a89888);
327 nv_wo32(ctx
, 0x058c, 0xf8e8d8c8);
328 nv_wo32(ctx
, 0x05a0, 0xb0000000);
329 for (i
= 0x05f0; i
< 0x0630; i
+= 4)
330 nv_wo32(ctx
, i
, 0x00010588);
331 for (i
= 0x0630; i
< 0x0670; i
+= 4)
332 nv_wo32(ctx
, i
, 0x00030303);
333 for (i
= 0x06b0; i
< 0x06f0; i
+= 4)
334 nv_wo32(ctx
, i
, 0x0008aae4);
335 for (i
= 0x06f0; i
< 0x0730; i
+= 4)
336 nv_wo32(ctx
, i
, 0x01012000);
337 for (i
= 0x0730; i
< 0x0770; i
+= 4)
338 nv_wo32(ctx
, i
, 0x00080008);
339 nv_wo32(ctx
, 0x0850, 0x00040000);
340 nv_wo32(ctx
, 0x0854, 0x00010000);
341 for (i
= 0x0858; i
< 0x0868; i
+= 4)
342 nv_wo32(ctx
, i
, 0x00040004);
343 for (i
= 0x15ac; i
<= 0x271c ; i
+= 16) {
344 nv_wo32(ctx
, i
+ 0, 0x10700ff9);
345 nv_wo32(ctx
, i
+ 1, 0x0436086c);
346 nv_wo32(ctx
, i
+ 2, 0x000c001b);
348 for (i
= 0x274c; i
< 0x275c; i
+= 4)
349 nv_wo32(ctx
, i
, 0x0000ffff);
350 nv_wo32(ctx
, 0x2ae0, 0x3f800000);
351 nv_wo32(ctx
, 0x2e9c, 0x3f800000);
352 nv_wo32(ctx
, 0x2eb0, 0x3f800000);
353 nv_wo32(ctx
, 0x2edc, 0x40000000);
354 nv_wo32(ctx
, 0x2ee0, 0x3f800000);
355 nv_wo32(ctx
, 0x2ee4, 0x3f000000);
356 nv_wo32(ctx
, 0x2eec, 0x40000000);
357 nv_wo32(ctx
, 0x2ef0, 0x3f800000);
358 nv_wo32(ctx
, 0x2ef8, 0xbf800000);
359 nv_wo32(ctx
, 0x2f00, 0xbf800000);
363 nv35_36_graph_context_init(struct nouveau_gpuobj
*ctx
)
367 nv_wo32(ctx
, 0x040c, 0x00000101);
368 nv_wo32(ctx
, 0x0420, 0x00000111);
369 nv_wo32(ctx
, 0x0424, 0x00000060);
370 nv_wo32(ctx
, 0x0440, 0x00000080);
371 nv_wo32(ctx
, 0x0444, 0xffff0000);
372 nv_wo32(ctx
, 0x0448, 0x00000001);
373 nv_wo32(ctx
, 0x045c, 0x44400000);
374 nv_wo32(ctx
, 0x0488, 0xffff0000);
375 for (i
= 0x04dc; i
< 0x04e4; i
+= 4)
376 nv_wo32(ctx
, i
, 0x0fff0000);
377 nv_wo32(ctx
, 0x04e8, 0x00011100);
378 for (i
= 0x0504; i
< 0x0544; i
+= 4)
379 nv_wo32(ctx
, i
, 0x07ff0000);
380 nv_wo32(ctx
, 0x054c, 0x4b7fffff);
381 nv_wo32(ctx
, 0x0588, 0x00000080);
382 nv_wo32(ctx
, 0x058c, 0x30201000);
383 nv_wo32(ctx
, 0x0590, 0x70605040);
384 nv_wo32(ctx
, 0x0594, 0xb8a89888);
385 nv_wo32(ctx
, 0x0598, 0xf8e8d8c8);
386 nv_wo32(ctx
, 0x05ac, 0xb0000000);
387 for (i
= 0x0604; i
< 0x0644; i
+= 4)
388 nv_wo32(ctx
, i
, 0x00010588);
389 for (i
= 0x0644; i
< 0x0684; i
+= 4)
390 nv_wo32(ctx
, i
, 0x00030303);
391 for (i
= 0x06c4; i
< 0x0704; i
+= 4)
392 nv_wo32(ctx
, i
, 0x0008aae4);
393 for (i
= 0x0704; i
< 0x0744; i
+= 4)
394 nv_wo32(ctx
, i
, 0x01012000);
395 for (i
= 0x0744; i
< 0x0784; i
+= 4)
396 nv_wo32(ctx
, i
, 0x00080008);
397 nv_wo32(ctx
, 0x0860, 0x00040000);
398 nv_wo32(ctx
, 0x0864, 0x00010000);
399 for (i
= 0x0868; i
< 0x0878; i
+= 4)
400 nv_wo32(ctx
, i
, 0x00040004);
401 for (i
= 0x1f1c; i
<= 0x308c ; i
+= 16) {
402 nv_wo32(ctx
, i
+ 0, 0x10700ff9);
403 nv_wo32(ctx
, i
+ 4, 0x0436086c);
404 nv_wo32(ctx
, i
+ 8, 0x000c001b);
406 for (i
= 0x30bc; i
< 0x30cc; i
+= 4)
407 nv_wo32(ctx
, i
, 0x0000ffff);
408 nv_wo32(ctx
, 0x3450, 0x3f800000);
409 nv_wo32(ctx
, 0x380c, 0x3f800000);
410 nv_wo32(ctx
, 0x3820, 0x3f800000);
411 nv_wo32(ctx
, 0x384c, 0x40000000);
412 nv_wo32(ctx
, 0x3850, 0x3f800000);
413 nv_wo32(ctx
, 0x3854, 0x3f000000);
414 nv_wo32(ctx
, 0x385c, 0x40000000);
415 nv_wo32(ctx
, 0x3860, 0x3f800000);
416 nv_wo32(ctx
, 0x3868, 0xbf800000);
417 nv_wo32(ctx
, 0x3870, 0xbf800000);
421 nv20_graph_context_new(struct nouveau_channel
*chan
, int engine
)
423 struct nv20_graph_engine
*pgraph
= nv_engine(chan
->dev
, engine
);
424 struct nouveau_gpuobj
*grctx
= NULL
;
425 struct drm_device
*dev
= chan
->dev
;
428 ret
= nouveau_gpuobj_new(dev
, NULL
, pgraph
->grctx_size
, 16,
429 NVOBJ_FLAG_ZERO_ALLOC
, &grctx
);
433 /* Initialise default context values */
434 pgraph
->grctx_init(grctx
);
436 /* nv20: nv_wo32(dev, chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
438 nv_wo32(grctx
, pgraph
->grctx_user
, (chan
->id
<< 24) | 0x1);
440 nv_wo32(pgraph
->ctxtab
, chan
->id
* 4, grctx
->pinst
>> 4);
441 chan
->engctx
[engine
] = grctx
;
446 nv20_graph_context_del(struct nouveau_channel
*chan
, int engine
)
448 struct nv20_graph_engine
*pgraph
= nv_engine(chan
->dev
, engine
);
449 struct nouveau_gpuobj
*grctx
= chan
->engctx
[engine
];
450 struct drm_device
*dev
= chan
->dev
;
451 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
454 spin_lock_irqsave(&dev_priv
->context_switch_lock
, flags
);
455 nv_mask(dev
, NV04_PGRAPH_FIFO
, 0x00000001, 0x00000000);
457 /* Unload the context if it's the currently active one */
458 if (nv10_graph_channel(dev
) == chan
)
459 nv20_graph_unload_context(dev
);
461 nv_mask(dev
, NV04_PGRAPH_FIFO
, 0x00000001, 0x00000001);
462 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, flags
);
464 /* Free the context resources */
465 nv_wo32(pgraph
->ctxtab
, chan
->id
* 4, 0);
467 nouveau_gpuobj_ref(NULL
, &grctx
);
468 chan
->engctx
[engine
] = NULL
;
472 nv20_graph_set_tile_region(struct drm_device
*dev
, int i
)
474 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
475 struct nouveau_tile_reg
*tile
= &dev_priv
->tile
.reg
[i
];
477 nv_wr32(dev
, NV20_PGRAPH_TLIMIT(i
), tile
->limit
);
478 nv_wr32(dev
, NV20_PGRAPH_TSIZE(i
), tile
->pitch
);
479 nv_wr32(dev
, NV20_PGRAPH_TILE(i
), tile
->addr
);
481 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0030 + 4 * i
);
482 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, tile
->limit
);
483 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0050 + 4 * i
);
484 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, tile
->pitch
);
485 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0010 + 4 * i
);
486 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, tile
->addr
);
488 if (dev_priv
->card_type
== NV_20
) {
489 nv_wr32(dev
, NV20_PGRAPH_ZCOMP(i
), tile
->zcomp
);
490 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00ea0090 + 4 * i
);
491 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, tile
->zcomp
);
496 nv20_graph_init(struct drm_device
*dev
, int engine
)
498 struct nv20_graph_engine
*pgraph
= nv_engine(dev
, engine
);
499 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
500 uint32_t tmp
, vramsz
;
503 nv_wr32(dev
, NV03_PMC_ENABLE
,
504 nv_rd32(dev
, NV03_PMC_ENABLE
) & ~NV_PMC_ENABLE_PGRAPH
);
505 nv_wr32(dev
, NV03_PMC_ENABLE
,
506 nv_rd32(dev
, NV03_PMC_ENABLE
) | NV_PMC_ENABLE_PGRAPH
);
508 nv_wr32(dev
, NV20_PGRAPH_CHANNEL_CTX_TABLE
, pgraph
->ctxtab
->pinst
>> 4);
512 nv_wr32(dev
, NV03_PGRAPH_INTR
, 0xFFFFFFFF);
513 nv_wr32(dev
, NV03_PGRAPH_INTR_EN
, 0xFFFFFFFF);
515 nv_wr32(dev
, NV04_PGRAPH_DEBUG_0
, 0xFFFFFFFF);
516 nv_wr32(dev
, NV04_PGRAPH_DEBUG_0
, 0x00000000);
517 nv_wr32(dev
, NV04_PGRAPH_DEBUG_1
, 0x00118700);
518 nv_wr32(dev
, NV04_PGRAPH_DEBUG_3
, 0xF3CE0475); /* 0x4 = auto ctx switch */
519 nv_wr32(dev
, NV10_PGRAPH_DEBUG_4
, 0x00000000);
520 nv_wr32(dev
, 0x40009C , 0x00000040);
522 if (dev_priv
->chipset
>= 0x25) {
523 nv_wr32(dev
, 0x400890, 0x00a8cfff);
524 nv_wr32(dev
, 0x400610, 0x304B1FB6);
525 nv_wr32(dev
, 0x400B80, 0x1cbd3883);
526 nv_wr32(dev
, 0x400B84, 0x44000000);
527 nv_wr32(dev
, 0x400098, 0x40000080);
528 nv_wr32(dev
, 0x400B88, 0x000000ff);
531 nv_wr32(dev
, 0x400880, 0x0008c7df);
532 nv_wr32(dev
, 0x400094, 0x00000005);
533 nv_wr32(dev
, 0x400B80, 0x45eae20e);
534 nv_wr32(dev
, 0x400B84, 0x24000000);
535 nv_wr32(dev
, 0x400098, 0x00000040);
536 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00E00038);
537 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, 0x00000030);
538 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00E10038);
539 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, 0x00000030);
542 /* Turn all the tiling regions off. */
543 for (i
= 0; i
< NV10_PFB_TILE__SIZE
; i
++)
544 nv20_graph_set_tile_region(dev
, i
);
546 nv_wr32(dev
, 0x4009a0, nv_rd32(dev
, 0x100324));
547 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00EA000C);
548 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, nv_rd32(dev
, 0x100324));
550 nv_wr32(dev
, NV10_PGRAPH_CTX_CONTROL
, 0x10000100);
551 nv_wr32(dev
, NV10_PGRAPH_STATE
, 0xFFFFFFFF);
553 tmp
= nv_rd32(dev
, NV10_PGRAPH_SURFACE
) & 0x0007ff00;
554 nv_wr32(dev
, NV10_PGRAPH_SURFACE
, tmp
);
555 tmp
= nv_rd32(dev
, NV10_PGRAPH_SURFACE
) | 0x00020100;
556 nv_wr32(dev
, NV10_PGRAPH_SURFACE
, tmp
);
558 /* begin RAM config */
559 vramsz
= pci_resource_len(dev
->pdev
, 0) - 1;
560 nv_wr32(dev
, 0x4009A4, nv_rd32(dev
, NV04_PFB_CFG0
));
561 nv_wr32(dev
, 0x4009A8, nv_rd32(dev
, NV04_PFB_CFG1
));
562 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0000);
563 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, nv_rd32(dev
, NV04_PFB_CFG0
));
564 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0004);
565 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, nv_rd32(dev
, NV04_PFB_CFG1
));
566 nv_wr32(dev
, 0x400820, 0);
567 nv_wr32(dev
, 0x400824, 0);
568 nv_wr32(dev
, 0x400864, vramsz
- 1);
569 nv_wr32(dev
, 0x400868, vramsz
- 1);
571 /* interesting.. the below overwrites some of the tile setup above.. */
572 nv_wr32(dev
, 0x400B20, 0x00000000);
573 nv_wr32(dev
, 0x400B04, 0xFFFFFFFF);
575 nv_wr32(dev
, NV03_PGRAPH_ABS_UCLIP_XMIN
, 0);
576 nv_wr32(dev
, NV03_PGRAPH_ABS_UCLIP_YMIN
, 0);
577 nv_wr32(dev
, NV03_PGRAPH_ABS_UCLIP_XMAX
, 0x7fff);
578 nv_wr32(dev
, NV03_PGRAPH_ABS_UCLIP_YMAX
, 0x7fff);
584 nv30_graph_init(struct drm_device
*dev
, int engine
)
586 struct nv20_graph_engine
*pgraph
= nv_engine(dev
, engine
);
587 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
590 nv_wr32(dev
, NV03_PMC_ENABLE
,
591 nv_rd32(dev
, NV03_PMC_ENABLE
) & ~NV_PMC_ENABLE_PGRAPH
);
592 nv_wr32(dev
, NV03_PMC_ENABLE
,
593 nv_rd32(dev
, NV03_PMC_ENABLE
) | NV_PMC_ENABLE_PGRAPH
);
595 nv_wr32(dev
, NV20_PGRAPH_CHANNEL_CTX_TABLE
, pgraph
->ctxtab
->pinst
>> 4);
597 nv_wr32(dev
, NV03_PGRAPH_INTR
, 0xFFFFFFFF);
598 nv_wr32(dev
, NV03_PGRAPH_INTR_EN
, 0xFFFFFFFF);
600 nv_wr32(dev
, NV04_PGRAPH_DEBUG_0
, 0xFFFFFFFF);
601 nv_wr32(dev
, NV04_PGRAPH_DEBUG_0
, 0x00000000);
602 nv_wr32(dev
, NV04_PGRAPH_DEBUG_1
, 0x401287c0);
603 nv_wr32(dev
, 0x400890, 0x01b463ff);
604 nv_wr32(dev
, NV04_PGRAPH_DEBUG_3
, 0xf2de0475);
605 nv_wr32(dev
, NV10_PGRAPH_DEBUG_4
, 0x00008000);
606 nv_wr32(dev
, NV04_PGRAPH_LIMIT_VIOL_PIX
, 0xf04bdff6);
607 nv_wr32(dev
, 0x400B80, 0x1003d888);
608 nv_wr32(dev
, 0x400B84, 0x0c000000);
609 nv_wr32(dev
, 0x400098, 0x00000000);
610 nv_wr32(dev
, 0x40009C, 0x0005ad00);
611 nv_wr32(dev
, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
612 nv_wr32(dev
, 0x4000a0, 0x00000000);
613 nv_wr32(dev
, 0x4000a4, 0x00000008);
614 nv_wr32(dev
, 0x4008a8, 0xb784a400);
615 nv_wr32(dev
, 0x400ba0, 0x002f8685);
616 nv_wr32(dev
, 0x400ba4, 0x00231f3f);
617 nv_wr32(dev
, 0x4008a4, 0x40000020);
619 if (dev_priv
->chipset
== 0x34) {
620 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0004);
621 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, 0x00200201);
622 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0008);
623 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, 0x00000008);
624 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0000);
625 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, 0x00000032);
626 nv_wr32(dev
, NV10_PGRAPH_RDI_INDEX
, 0x00E00004);
627 nv_wr32(dev
, NV10_PGRAPH_RDI_DATA
, 0x00000002);
630 nv_wr32(dev
, 0x4000c0, 0x00000016);
632 /* Turn all the tiling regions off. */
633 for (i
= 0; i
< NV10_PFB_TILE__SIZE
; i
++)
634 nv20_graph_set_tile_region(dev
, i
);
636 nv_wr32(dev
, NV10_PGRAPH_CTX_CONTROL
, 0x10000100);
637 nv_wr32(dev
, NV10_PGRAPH_STATE
, 0xFFFFFFFF);
638 nv_wr32(dev
, 0x0040075c , 0x00000001);
640 /* begin RAM config */
641 /* vramsz = pci_resource_len(dev->pdev, 0) - 1; */
642 nv_wr32(dev
, 0x4009A4, nv_rd32(dev
, NV04_PFB_CFG0
));
643 nv_wr32(dev
, 0x4009A8, nv_rd32(dev
, NV04_PFB_CFG1
));
644 if (dev_priv
->chipset
!= 0x34) {
645 nv_wr32(dev
, 0x400750, 0x00EA0000);
646 nv_wr32(dev
, 0x400754, nv_rd32(dev
, NV04_PFB_CFG0
));
647 nv_wr32(dev
, 0x400750, 0x00EA0004);
648 nv_wr32(dev
, 0x400754, nv_rd32(dev
, NV04_PFB_CFG1
));
655 nv20_graph_fini(struct drm_device
*dev
, int engine
, bool suspend
)
657 nv_mask(dev
, NV04_PGRAPH_FIFO
, 0x00000001, 0x00000000);
658 if (!nv_wait(dev
, NV04_PGRAPH_STATUS
, ~0, 0) && suspend
) {
659 nv_mask(dev
, NV04_PGRAPH_FIFO
, 0x00000001, 0x00000001);
662 nv20_graph_unload_context(dev
);
663 nv_wr32(dev
, NV03_PGRAPH_INTR_EN
, 0x00000000);
668 nv20_graph_isr(struct drm_device
*dev
)
672 while ((stat
= nv_rd32(dev
, NV03_PGRAPH_INTR
))) {
673 u32 nsource
= nv_rd32(dev
, NV03_PGRAPH_NSOURCE
);
674 u32 nstatus
= nv_rd32(dev
, NV03_PGRAPH_NSTATUS
);
675 u32 addr
= nv_rd32(dev
, NV04_PGRAPH_TRAPPED_ADDR
);
676 u32 chid
= (addr
& 0x01f00000) >> 20;
677 u32 subc
= (addr
& 0x00070000) >> 16;
678 u32 mthd
= (addr
& 0x00001ffc);
679 u32 data
= nv_rd32(dev
, NV04_PGRAPH_TRAPPED_DATA
);
680 u32
class = nv_rd32(dev
, 0x400160 + subc
* 4) & 0xfff;
683 if (stat
& NV_PGRAPH_INTR_ERROR
) {
684 if (nsource
& NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD
) {
685 if (!nouveau_gpuobj_mthd_call2(dev
, chid
, class, mthd
, data
))
686 show
&= ~NV_PGRAPH_INTR_ERROR
;
690 nv_wr32(dev
, NV03_PGRAPH_INTR
, stat
);
691 nv_wr32(dev
, NV04_PGRAPH_FIFO
, 0x00000001);
693 if (show
&& nouveau_ratelimit()) {
694 NV_INFO(dev
, "PGRAPH -");
695 nouveau_bitfield_print(nv10_graph_intr
, show
);
697 nouveau_bitfield_print(nv04_graph_nsource
, nsource
);
699 nouveau_bitfield_print(nv10_graph_nstatus
, nstatus
);
701 NV_INFO(dev
, "PGRAPH - ch %d/%d class 0x%04x "
702 "mthd 0x%04x data 0x%08x\n",
703 chid
, subc
, class, mthd
, data
);
709 nv20_graph_destroy(struct drm_device
*dev
, int engine
)
711 struct nv20_graph_engine
*pgraph
= nv_engine(dev
, engine
);
713 nouveau_irq_unregister(dev
, 12);
714 nouveau_gpuobj_ref(NULL
, &pgraph
->ctxtab
);
716 NVOBJ_ENGINE_DEL(dev
, GR
);
721 nv20_graph_create(struct drm_device
*dev
)
723 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
724 struct nv20_graph_engine
*pgraph
;
727 pgraph
= kzalloc(sizeof(*pgraph
), GFP_KERNEL
);
731 pgraph
->base
.destroy
= nv20_graph_destroy
;
732 pgraph
->base
.fini
= nv20_graph_fini
;
733 pgraph
->base
.context_new
= nv20_graph_context_new
;
734 pgraph
->base
.context_del
= nv20_graph_context_del
;
735 pgraph
->base
.object_new
= nv04_graph_object_new
;
736 pgraph
->base
.set_tile_region
= nv20_graph_set_tile_region
;
738 pgraph
->grctx_user
= 0x0028;
739 if (dev_priv
->card_type
== NV_20
) {
740 pgraph
->base
.init
= nv20_graph_init
;
741 switch (dev_priv
->chipset
) {
743 pgraph
->grctx_init
= nv20_graph_context_init
;
744 pgraph
->grctx_size
= NV20_GRCTX_SIZE
;
745 pgraph
->grctx_user
= 0x0000;
749 pgraph
->grctx_init
= nv25_graph_context_init
;
750 pgraph
->grctx_size
= NV25_GRCTX_SIZE
;
753 pgraph
->grctx_init
= nv2a_graph_context_init
;
754 pgraph
->grctx_size
= NV2A_GRCTX_SIZE
;
755 pgraph
->grctx_user
= 0x0000;
758 NV_ERROR(dev
, "PGRAPH: unknown chipset\n");
763 pgraph
->base
.init
= nv30_graph_init
;
764 switch (dev_priv
->chipset
) {
767 pgraph
->grctx_init
= nv30_31_graph_context_init
;
768 pgraph
->grctx_size
= NV30_31_GRCTX_SIZE
;
771 pgraph
->grctx_init
= nv34_graph_context_init
;
772 pgraph
->grctx_size
= NV34_GRCTX_SIZE
;
776 pgraph
->grctx_init
= nv35_36_graph_context_init
;
777 pgraph
->grctx_size
= NV35_36_GRCTX_SIZE
;
780 NV_ERROR(dev
, "PGRAPH: unknown chipset\n");
786 /* Create Context Pointer Table */
787 ret
= nouveau_gpuobj_new(dev
, NULL
, 32 * 4, 16, NVOBJ_FLAG_ZERO_ALLOC
,
794 NVOBJ_ENGINE_ADD(dev
, GR
, &pgraph
->base
);
795 nouveau_irq_register(dev
, 12, nv20_graph_isr
);
797 NVOBJ_CLASS(dev
, 0x0030, GR
); /* null */
798 NVOBJ_CLASS(dev
, 0x0039, GR
); /* m2mf */
799 NVOBJ_CLASS(dev
, 0x004a, GR
); /* gdirect */
800 NVOBJ_CLASS(dev
, 0x009f, GR
); /* imageblit (nv12) */
801 NVOBJ_CLASS(dev
, 0x008a, GR
); /* ifc */
802 NVOBJ_CLASS(dev
, 0x0089, GR
); /* sifm */
803 NVOBJ_CLASS(dev
, 0x0062, GR
); /* surf2d */
804 NVOBJ_CLASS(dev
, 0x0043, GR
); /* rop */
805 NVOBJ_CLASS(dev
, 0x0012, GR
); /* beta1 */
806 NVOBJ_CLASS(dev
, 0x0072, GR
); /* beta4 */
807 NVOBJ_CLASS(dev
, 0x0019, GR
); /* cliprect */
808 NVOBJ_CLASS(dev
, 0x0044, GR
); /* pattern */
809 if (dev_priv
->card_type
== NV_20
) {
810 NVOBJ_CLASS(dev
, 0x009e, GR
); /* swzsurf */
811 NVOBJ_CLASS(dev
, 0x0096, GR
); /* celcius */
814 if (dev_priv
->chipset
< 0x25)
815 NVOBJ_CLASS(dev
, 0x0097, GR
);
817 NVOBJ_CLASS(dev
, 0x0597, GR
);
819 NVOBJ_CLASS(dev
, 0x038a, GR
); /* ifc (nv30) */
820 NVOBJ_CLASS(dev
, 0x0389, GR
); /* sifm (nv30) */
821 NVOBJ_CLASS(dev
, 0x0362, GR
); /* surf2d (nv30) */
822 NVOBJ_CLASS(dev
, 0x039e, GR
); /* swzsurf */
825 if (0x00000003 & (1 << (dev_priv
->chipset
& 0x0f)))
826 NVOBJ_CLASS(dev
, 0x0397, GR
);
828 if (0x00000010 & (1 << (dev_priv
->chipset
& 0x0f)))
829 NVOBJ_CLASS(dev
, 0x0697, GR
);
831 if (0x000001e0 & (1 << (dev_priv
->chipset
& 0x0f)))
832 NVOBJ_CLASS(dev
, 0x0497, GR
);