drivers/gpu/drm/nouveau/nv20_graph.c

   1 #include <drm/drmP.h>
   2 #include "nouveau_drv.h"
   3 #include <drm/nouveau_drm.h>
   4
   5 /*
   6  * NV20
   7  * -----
   8  * There are 3 families :
   9  * NV20 is 0x10de:0x020*
  10  * NV25/28 is 0x10de:0x025* / 0x10de:0x028*
  11  * NV2A is 0x10de:0x02A0
  12  *
  13  * NV30
  14  * -----
  15  * There are 3 families :
  16  * NV30/31 is 0x10de:0x030* / 0x10de:0x031*
  17  * NV34 is 0x10de:0x032*
  18  * NV35/36 is 0x10de:0x033* / 0x10de:0x034*
  19  *
  20  * Not seen in the wild, no dumps (probably NV35) :
  21  * NV37 is 0x10de:0x00fc, 0x10de:0x00fd
  22  * NV38 is 0x10de:0x0333, 0x10de:0x00fe
  23  *
  24  */
  25
  26 struct nv20_graph_engine {
  27         struct nouveau_exec_engine base;
  28         struct nouveau_gpuobj *ctxtab;
  29         void (*grctx_init)(struct nouveau_gpuobj *);
  30         u32 grctx_size;
  31         u32 grctx_user;
  32 };
  33
  34 #define NV20_GRCTX_SIZE (3580*4)
  35 #define NV25_GRCTX_SIZE (3529*4)
  36 #define NV2A_GRCTX_SIZE (3500*4)
  37
  38 #define NV30_31_GRCTX_SIZE (24392)
  39 #define NV34_GRCTX_SIZE    (18140)
  40 #define NV35_36_GRCTX_SIZE (22396)
  41
  42 int
  43 nv20_graph_unload_context(struct drm_device *dev)
  44 {
  45         struct nouveau_channel *chan;
  46         struct nouveau_gpuobj *grctx;
  47         u32 tmp;
  48
  49         chan = nv10_graph_channel(dev);
  50         if (!chan)
  51                 return 0;
  52         grctx = chan->engctx[NVOBJ_ENGINE_GR];
  53
  54         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, grctx->pinst >> 4);
  55         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
  56                      NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
  57
  58         nouveau_wait_for_idle(dev);
  59
  60         nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
  61         tmp  = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
  62         tmp |= 31 << 24;
  63         nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
  64         return 0;
  65 }
  66
  67 static void
  68 nv20_graph_rdi(struct drm_device *dev)
  69 {
  70         struct drm_nouveau_private *dev_priv = dev->dev_private;
  71         int i, writecount = 32;
  72         uint32_t rdi_index = 0x2c80000;
  73
  74         if (dev_priv->chipset == 0x20) {
  75                 rdi_index = 0x3d0000;
  76                 writecount = 15;
  77         }
  78
  79         nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, rdi_index);
  80         for (i = 0; i < writecount; i++)
  81                 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, 0);
  82
  83         nouveau_wait_for_idle(dev);
  84 }
  85
  86 static void
  87 nv20_graph_context_init(struct nouveau_gpuobj *ctx)
  88 {
  89         int i;
  90
  91         nv_wo32(ctx, 0x033c, 0xffff0000);
  92         nv_wo32(ctx, 0x03a0, 0x0fff0000);
  93         nv_wo32(ctx, 0x03a4, 0x0fff0000);
  94         nv_wo32(ctx, 0x047c, 0x00000101);
  95         nv_wo32(ctx, 0x0490, 0x00000111);
  96         nv_wo32(ctx, 0x04a8, 0x44400000);
  97         for (i = 0x04d4; i <= 0x04e0; i += 4)
  98                 nv_wo32(ctx, i, 0x00030303);
  99         for (i = 0x04f4; i <= 0x0500; i += 4)
 100                 nv_wo32(ctx, i, 0x00080000);
 101         for (i = 0x050c; i <= 0x0518; i += 4)
 102                 nv_wo32(ctx, i, 0x01012000);
 103         for (i = 0x051c; i <= 0x0528; i += 4)
 104                 nv_wo32(ctx, i, 0x000105b8);
 105         for (i = 0x052c; i <= 0x0538; i += 4)
 106                 nv_wo32(ctx, i, 0x00080008);
 107         for (i = 0x055c; i <= 0x0598; i += 4)
 108                 nv_wo32(ctx, i, 0x07ff0000);
 109         nv_wo32(ctx, 0x05a4, 0x4b7fffff);
 110         nv_wo32(ctx, 0x05fc, 0x00000001);
 111         nv_wo32(ctx, 0x0604, 0x00004000);
 112         nv_wo32(ctx, 0x0610, 0x00000001);
 113         nv_wo32(ctx, 0x0618, 0x00040000);
 114         nv_wo32(ctx, 0x061c, 0x00010000);
 115         for (i = 0x1c1c; i <= 0x248c; i += 16) {
 116                 nv_wo32(ctx, (i + 0), 0x10700ff9);
 117                 nv_wo32(ctx, (i + 4), 0x0436086c);
 118                 nv_wo32(ctx, (i + 8), 0x000c001b);
 119         }
 120         nv_wo32(ctx, 0x281c, 0x3f800000);
 121         nv_wo32(ctx, 0x2830, 0x3f800000);
 122         nv_wo32(ctx, 0x285c, 0x40000000);
 123         nv_wo32(ctx, 0x2860, 0x3f800000);
 124         nv_wo32(ctx, 0x2864, 0x3f000000);
 125         nv_wo32(ctx, 0x286c, 0x40000000);
 126         nv_wo32(ctx, 0x2870, 0x3f800000);
 127         nv_wo32(ctx, 0x2878, 0xbf800000);
 128         nv_wo32(ctx, 0x2880, 0xbf800000);
 129         nv_wo32(ctx, 0x34a4, 0x000fe000);
 130         nv_wo32(ctx, 0x3530, 0x000003f8);
 131         nv_wo32(ctx, 0x3540, 0x002fe000);
 132         for (i = 0x355c; i <= 0x3578; i += 4)
 133                 nv_wo32(ctx, i, 0x001c527c);
 134 }
 135
 136 static void
 137 nv25_graph_context_init(struct nouveau_gpuobj *ctx)
 138 {
 139         int i;
 140
 141         nv_wo32(ctx, 0x035c, 0xffff0000);
 142         nv_wo32(ctx, 0x03c0, 0x0fff0000);
 143         nv_wo32(ctx, 0x03c4, 0x0fff0000);
 144         nv_wo32(ctx, 0x049c, 0x00000101);
 145         nv_wo32(ctx, 0x04b0, 0x00000111);
 146         nv_wo32(ctx, 0x04c8, 0x00000080);
 147         nv_wo32(ctx, 0x04cc, 0xffff0000);
 148         nv_wo32(ctx, 0x04d0, 0x00000001);
 149         nv_wo32(ctx, 0x04e4, 0x44400000);
 150         nv_wo32(ctx, 0x04fc, 0x4b800000);
 151         for (i = 0x0510; i <= 0x051c; i += 4)
 152                 nv_wo32(ctx, i, 0x00030303);
 153         for (i = 0x0530; i <= 0x053c; i += 4)
 154                 nv_wo32(ctx, i, 0x00080000);
 155         for (i = 0x0548; i <= 0x0554; i += 4)
 156                 nv_wo32(ctx, i, 0x01012000);
 157         for (i = 0x0558; i <= 0x0564; i += 4)
 158                 nv_wo32(ctx, i, 0x000105b8);
 159         for (i = 0x0568; i <= 0x0574; i += 4)
 160                 nv_wo32(ctx, i, 0x00080008);
 161         for (i = 0x0598; i <= 0x05d4; i += 4)
 162                 nv_wo32(ctx, i, 0x07ff0000);
 163         nv_wo32(ctx, 0x05e0, 0x4b7fffff);
 164         nv_wo32(ctx, 0x0620, 0x00000080);
 165         nv_wo32(ctx, 0x0624, 0x30201000);
 166         nv_wo32(ctx, 0x0628, 0x70605040);
 167         nv_wo32(ctx, 0x062c, 0xb0a09080);
 168         nv_wo32(ctx, 0x0630, 0xf0e0d0c0);
 169         nv_wo32(ctx, 0x0664, 0x00000001);
 170         nv_wo32(ctx, 0x066c, 0x00004000);
 171         nv_wo32(ctx, 0x0678, 0x00000001);
 172         nv_wo32(ctx, 0x0680, 0x00040000);
 173         nv_wo32(ctx, 0x0684, 0x00010000);
 174         for (i = 0x1b04; i <= 0x2374; i += 16) {
 175                 nv_wo32(ctx, (i + 0), 0x10700ff9);
 176                 nv_wo32(ctx, (i + 4), 0x0436086c);
 177                 nv_wo32(ctx, (i + 8), 0x000c001b);
 178         }
 179         nv_wo32(ctx, 0x2704, 0x3f800000);
 180         nv_wo32(ctx, 0x2718, 0x3f800000);
 181         nv_wo32(ctx, 0x2744, 0x40000000);
 182         nv_wo32(ctx, 0x2748, 0x3f800000);
 183         nv_wo32(ctx, 0x274c, 0x3f000000);
 184         nv_wo32(ctx, 0x2754, 0x40000000);
 185         nv_wo32(ctx, 0x2758, 0x3f800000);
 186         nv_wo32(ctx, 0x2760, 0xbf800000);
 187         nv_wo32(ctx, 0x2768, 0xbf800000);
 188         nv_wo32(ctx, 0x308c, 0x000fe000);
 189         nv_wo32(ctx, 0x3108, 0x000003f8);
 190         nv_wo32(ctx, 0x3468, 0x002fe000);
 191         for (i = 0x3484; i <= 0x34a0; i += 4)
 192                 nv_wo32(ctx, i, 0x001c527c);
 193 }
 194
 195 static void
 196 nv2a_graph_context_init(struct nouveau_gpuobj *ctx)
 197 {
 198         int i;
 199
 200         nv_wo32(ctx, 0x033c, 0xffff0000);
 201         nv_wo32(ctx, 0x03a0, 0x0fff0000);
 202         nv_wo32(ctx, 0x03a4, 0x0fff0000);
 203         nv_wo32(ctx, 0x047c, 0x00000101);
 204         nv_wo32(ctx, 0x0490, 0x00000111);
 205         nv_wo32(ctx, 0x04a8, 0x44400000);
 206         for (i = 0x04d4; i <= 0x04e0; i += 4)
 207                 nv_wo32(ctx, i, 0x00030303);
 208         for (i = 0x04f4; i <= 0x0500; i += 4)
 209                 nv_wo32(ctx, i, 0x00080000);
 210         for (i = 0x050c; i <= 0x0518; i += 4)
 211                 nv_wo32(ctx, i, 0x01012000);
 212         for (i = 0x051c; i <= 0x0528; i += 4)
 213                 nv_wo32(ctx, i, 0x000105b8);
 214         for (i = 0x052c; i <= 0x0538; i += 4)
 215                 nv_wo32(ctx, i, 0x00080008);
 216         for (i = 0x055c; i <= 0x0598; i += 4)
 217                 nv_wo32(ctx, i, 0x07ff0000);
 218         nv_wo32(ctx, 0x05a4, 0x4b7fffff);
 219         nv_wo32(ctx, 0x05fc, 0x00000001);
 220         nv_wo32(ctx, 0x0604, 0x00004000);
 221         nv_wo32(ctx, 0x0610, 0x00000001);
 222         nv_wo32(ctx, 0x0618, 0x00040000);
 223         nv_wo32(ctx, 0x061c, 0x00010000);
 224         for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */
 225                 nv_wo32(ctx, (i + 0), 0x10700ff9);
 226                 nv_wo32(ctx, (i + 4), 0x0436086c);
 227                 nv_wo32(ctx, (i + 8), 0x000c001b);
 228         }
 229         nv_wo32(ctx, 0x269c, 0x3f800000);
 230         nv_wo32(ctx, 0x26b0, 0x3f800000);
 231         nv_wo32(ctx, 0x26dc, 0x40000000);
 232         nv_wo32(ctx, 0x26e0, 0x3f800000);
 233         nv_wo32(ctx, 0x26e4, 0x3f000000);
 234         nv_wo32(ctx, 0x26ec, 0x40000000);
 235         nv_wo32(ctx, 0x26f0, 0x3f800000);
 236         nv_wo32(ctx, 0x26f8, 0xbf800000);
 237         nv_wo32(ctx, 0x2700, 0xbf800000);
 238         nv_wo32(ctx, 0x3024, 0x000fe000);
 239         nv_wo32(ctx, 0x30a0, 0x000003f8);
 240         nv_wo32(ctx, 0x33fc, 0x002fe000);
 241         for (i = 0x341c; i <= 0x3438; i += 4)
 242                 nv_wo32(ctx, i, 0x001c527c);
 243 }
 244
 245 static void
 246 nv30_31_graph_context_init(struct nouveau_gpuobj *ctx)
 247 {
 248         int i;
 249
 250         nv_wo32(ctx, 0x0410, 0x00000101);
 251         nv_wo32(ctx, 0x0424, 0x00000111);
 252         nv_wo32(ctx, 0x0428, 0x00000060);
 253         nv_wo32(ctx, 0x0444, 0x00000080);
 254         nv_wo32(ctx, 0x0448, 0xffff0000);
 255         nv_wo32(ctx, 0x044c, 0x00000001);
 256         nv_wo32(ctx, 0x0460, 0x44400000);
 257         nv_wo32(ctx, 0x048c, 0xffff0000);
 258         for (i = 0x04e0; i < 0x04e8; i += 4)
 259                 nv_wo32(ctx, i, 0x0fff0000);
 260         nv_wo32(ctx, 0x04ec, 0x00011100);
 261         for (i = 0x0508; i < 0x0548; i += 4)
 262                 nv_wo32(ctx, i, 0x07ff0000);
 263         nv_wo32(ctx, 0x0550, 0x4b7fffff);
 264         nv_wo32(ctx, 0x058c, 0x00000080);
 265         nv_wo32(ctx, 0x0590, 0x30201000);
 266         nv_wo32(ctx, 0x0594, 0x70605040);
 267         nv_wo32(ctx, 0x0598, 0xb8a89888);
 268         nv_wo32(ctx, 0x059c, 0xf8e8d8c8);
 269         nv_wo32(ctx, 0x05b0, 0xb0000000);
 270         for (i = 0x0600; i < 0x0640; i += 4)
 271                 nv_wo32(ctx, i, 0x00010588);
 272         for (i = 0x0640; i < 0x0680; i += 4)
 273                 nv_wo32(ctx, i, 0x00030303);
 274         for (i = 0x06c0; i < 0x0700; i += 4)
 275                 nv_wo32(ctx, i, 0x0008aae4);
 276         for (i = 0x0700; i < 0x0740; i += 4)
 277                 nv_wo32(ctx, i, 0x01012000);
 278         for (i = 0x0740; i < 0x0780; i += 4)
 279                 nv_wo32(ctx, i, 0x00080008);
 280         nv_wo32(ctx, 0x085c, 0x00040000);
 281         nv_wo32(ctx, 0x0860, 0x00010000);
 282         for (i = 0x0864; i < 0x0874; i += 4)
 283                 nv_wo32(ctx, i, 0x00040004);
 284         for (i = 0x1f18; i <= 0x3088 ; i += 16) {
 285                 nv_wo32(ctx, i + 0, 0x10700ff9);
 286                 nv_wo32(ctx, i + 1, 0x0436086c);
 287                 nv_wo32(ctx, i + 2, 0x000c001b);
 288         }
 289         for (i = 0x30b8; i < 0x30c8; i += 4)
 290                 nv_wo32(ctx, i, 0x0000ffff);
 291         nv_wo32(ctx, 0x344c, 0x3f800000);
 292         nv_wo32(ctx, 0x3808, 0x3f800000);
 293         nv_wo32(ctx, 0x381c, 0x3f800000);
 294         nv_wo32(ctx, 0x3848, 0x40000000);
 295         nv_wo32(ctx, 0x384c, 0x3f800000);
 296         nv_wo32(ctx, 0x3850, 0x3f000000);
 297         nv_wo32(ctx, 0x3858, 0x40000000);
 298         nv_wo32(ctx, 0x385c, 0x3f800000);
 299         nv_wo32(ctx, 0x3864, 0xbf800000);
 300         nv_wo32(ctx, 0x386c, 0xbf800000);
 301 }
 302
 303 static void
 304 nv34_graph_context_init(struct nouveau_gpuobj *ctx)
 305 {
 306         int i;
 307
 308         nv_wo32(ctx, 0x040c, 0x01000101);
 309         nv_wo32(ctx, 0x0420, 0x00000111);
 310         nv_wo32(ctx, 0x0424, 0x00000060);
 311         nv_wo32(ctx, 0x0440, 0x00000080);
 312         nv_wo32(ctx, 0x0444, 0xffff0000);
 313         nv_wo32(ctx, 0x0448, 0x00000001);
 314         nv_wo32(ctx, 0x045c, 0x44400000);
 315         nv_wo32(ctx, 0x0480, 0xffff0000);
 316         for (i = 0x04d4; i < 0x04dc; i += 4)
 317                 nv_wo32(ctx, i, 0x0fff0000);
 318         nv_wo32(ctx, 0x04e0, 0x00011100);
 319         for (i = 0x04fc; i < 0x053c; i += 4)
 320                 nv_wo32(ctx, i, 0x07ff0000);
 321         nv_wo32(ctx, 0x0544, 0x4b7fffff);
 322         nv_wo32(ctx, 0x057c, 0x00000080);
 323         nv_wo32(ctx, 0x0580, 0x30201000);
 324         nv_wo32(ctx, 0x0584, 0x70605040);
 325         nv_wo32(ctx, 0x0588, 0xb8a89888);
 326         nv_wo32(ctx, 0x058c, 0xf8e8d8c8);
 327         nv_wo32(ctx, 0x05a0, 0xb0000000);
 328         for (i = 0x05f0; i < 0x0630; i += 4)
 329                 nv_wo32(ctx, i, 0x00010588);
 330         for (i = 0x0630; i < 0x0670; i += 4)
 331                 nv_wo32(ctx, i, 0x00030303);
 332         for (i = 0x06b0; i < 0x06f0; i += 4)
 333                 nv_wo32(ctx, i, 0x0008aae4);
 334         for (i = 0x06f0; i < 0x0730; i += 4)
 335                 nv_wo32(ctx, i, 0x01012000);
 336         for (i = 0x0730; i < 0x0770; i += 4)
 337                 nv_wo32(ctx, i, 0x00080008);
 338         nv_wo32(ctx, 0x0850, 0x00040000);
 339         nv_wo32(ctx, 0x0854, 0x00010000);
 340         for (i = 0x0858; i < 0x0868; i += 4)
 341                 nv_wo32(ctx, i, 0x00040004);
 342         for (i = 0x15ac; i <= 0x271c ; i += 16) {
 343                 nv_wo32(ctx, i + 0, 0x10700ff9);
 344                 nv_wo32(ctx, i + 1, 0x0436086c);
 345                 nv_wo32(ctx, i + 2, 0x000c001b);
 346         }
 347         for (i = 0x274c; i < 0x275c; i += 4)
 348                 nv_wo32(ctx, i, 0x0000ffff);
 349         nv_wo32(ctx, 0x2ae0, 0x3f800000);
 350         nv_wo32(ctx, 0x2e9c, 0x3f800000);
 351         nv_wo32(ctx, 0x2eb0, 0x3f800000);
 352         nv_wo32(ctx, 0x2edc, 0x40000000);
 353         nv_wo32(ctx, 0x2ee0, 0x3f800000);
 354         nv_wo32(ctx, 0x2ee4, 0x3f000000);
 355         nv_wo32(ctx, 0x2eec, 0x40000000);
 356         nv_wo32(ctx, 0x2ef0, 0x3f800000);
 357         nv_wo32(ctx, 0x2ef8, 0xbf800000);
 358         nv_wo32(ctx, 0x2f00, 0xbf800000);
 359 }
 360
 361 static void
 362 nv35_36_graph_context_init(struct nouveau_gpuobj *ctx)
 363 {
 364         int i;
 365
 366         nv_wo32(ctx, 0x040c, 0x00000101);
 367         nv_wo32(ctx, 0x0420, 0x00000111);
 368         nv_wo32(ctx, 0x0424, 0x00000060);
 369         nv_wo32(ctx, 0x0440, 0x00000080);
 370         nv_wo32(ctx, 0x0444, 0xffff0000);
 371         nv_wo32(ctx, 0x0448, 0x00000001);
 372         nv_wo32(ctx, 0x045c, 0x44400000);
 373         nv_wo32(ctx, 0x0488, 0xffff0000);
 374         for (i = 0x04dc; i < 0x04e4; i += 4)
 375                 nv_wo32(ctx, i, 0x0fff0000);
 376         nv_wo32(ctx, 0x04e8, 0x00011100);
 377         for (i = 0x0504; i < 0x0544; i += 4)
 378                 nv_wo32(ctx, i, 0x07ff0000);
 379         nv_wo32(ctx, 0x054c, 0x4b7fffff);
 380         nv_wo32(ctx, 0x0588, 0x00000080);
 381         nv_wo32(ctx, 0x058c, 0x30201000);
 382         nv_wo32(ctx, 0x0590, 0x70605040);
 383         nv_wo32(ctx, 0x0594, 0xb8a89888);
 384         nv_wo32(ctx, 0x0598, 0xf8e8d8c8);
 385         nv_wo32(ctx, 0x05ac, 0xb0000000);
 386         for (i = 0x0604; i < 0x0644; i += 4)
 387                 nv_wo32(ctx, i, 0x00010588);
 388         for (i = 0x0644; i < 0x0684; i += 4)
 389                 nv_wo32(ctx, i, 0x00030303);
 390         for (i = 0x06c4; i < 0x0704; i += 4)
 391                 nv_wo32(ctx, i, 0x0008aae4);
 392         for (i = 0x0704; i < 0x0744; i += 4)
 393                 nv_wo32(ctx, i, 0x01012000);
 394         for (i = 0x0744; i < 0x0784; i += 4)
 395                 nv_wo32(ctx, i, 0x00080008);
 396         nv_wo32(ctx, 0x0860, 0x00040000);
 397         nv_wo32(ctx, 0x0864, 0x00010000);
 398         for (i = 0x0868; i < 0x0878; i += 4)
 399                 nv_wo32(ctx, i, 0x00040004);
 400         for (i = 0x1f1c; i <= 0x308c ; i += 16) {
 401                 nv_wo32(ctx, i + 0, 0x10700ff9);
 402                 nv_wo32(ctx, i + 4, 0x0436086c);
 403                 nv_wo32(ctx, i + 8, 0x000c001b);
 404         }
 405         for (i = 0x30bc; i < 0x30cc; i += 4)
 406                 nv_wo32(ctx, i, 0x0000ffff);
 407         nv_wo32(ctx, 0x3450, 0x3f800000);
 408         nv_wo32(ctx, 0x380c, 0x3f800000);
 409         nv_wo32(ctx, 0x3820, 0x3f800000);
 410         nv_wo32(ctx, 0x384c, 0x40000000);
 411         nv_wo32(ctx, 0x3850, 0x3f800000);
 412         nv_wo32(ctx, 0x3854, 0x3f000000);
 413         nv_wo32(ctx, 0x385c, 0x40000000);
 414         nv_wo32(ctx, 0x3860, 0x3f800000);
 415         nv_wo32(ctx, 0x3868, 0xbf800000);
 416         nv_wo32(ctx, 0x3870, 0xbf800000);
 417 }
 418
 419 int
 420 nv20_graph_context_new(struct nouveau_channel *chan, int engine)
 421 {
 422         struct nv20_graph_engine *pgraph = nv_engine(chan->dev, engine);
 423         struct nouveau_gpuobj *grctx = NULL;
 424         struct drm_device *dev = chan->dev;
 425         int ret;
 426
 427         ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
 428                                  NVOBJ_FLAG_ZERO_ALLOC, &grctx);
 429         if (ret)
 430                 return ret;
 431
 432         /* Initialise default context values */
 433         pgraph->grctx_init(grctx);
 434
 435         /* nv20: nv_wo32(dev, chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
 436         /* CTX_USER */
 437         nv_wo32(grctx, pgraph->grctx_user, (chan->id << 24) | 0x1);
 438
 439         nv_wo32(pgraph->ctxtab, chan->id * 4, grctx->pinst >> 4);
 440         chan->engctx[engine] = grctx;
 441         return 0;
 442 }
 443
 444 void
 445 nv20_graph_context_del(struct nouveau_channel *chan, int engine)
 446 {
 447         struct nv20_graph_engine *pgraph = nv_engine(chan->dev, engine);
 448         struct nouveau_gpuobj *grctx = chan->engctx[engine];
 449         struct drm_device *dev = chan->dev;
 450         struct drm_nouveau_private *dev_priv = dev->dev_private;
 451         unsigned long flags;
 452
 453         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 454         nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
 455
 456         /* Unload the context if it's the currently active one */
 457         if (nv10_graph_channel(dev) == chan)
 458                 nv20_graph_unload_context(dev);
 459
 460         nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
 461         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 462
 463         /* Free the context resources */
 464         nv_wo32(pgraph->ctxtab, chan->id * 4, 0);
 465
 466         nouveau_gpuobj_ref(NULL, &grctx);
 467         chan->engctx[engine] = NULL;
 468 }
 469
 470 static void
 471 nv20_graph_set_tile_region(struct drm_device *dev, int i)
 472 {
 473         struct drm_nouveau_private *dev_priv = dev->dev_private;
 474         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
 475
 476         nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
 477         nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
 478         nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
 479
 480         nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
 481         nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->limit);
 482         nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
 483         nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->pitch);
 484         nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
 485         nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->addr);
 486
 487         if (dev_priv->card_type == NV_20) {
 488                 nv_wr32(dev, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
 489                 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
 490                 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->zcomp);
 491         }
 492 }
 493
 494 int
 495 nv20_graph_init(struct drm_device *dev, int engine)
 496 {
 497         struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
 498         struct drm_nouveau_private *dev_priv = dev->dev_private;
 499         uint32_t tmp, vramsz;
 500         int i;
 501
 502         nv_wr32(dev, NV03_PMC_ENABLE,
 503                 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
 504         nv_wr32(dev, NV03_PMC_ENABLE,
 505                 nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PGRAPH);
 506
 507         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->pinst >> 4);
 508
 509         nv20_graph_rdi(dev);
 510
 511         nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 512         nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 513
 514         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 515         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
 516         nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x00118700);
 517         nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
 518         nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000);
 519         nv_wr32(dev, 0x40009C           , 0x00000040);
 520
 521         if (dev_priv->chipset >= 0x25) {
 522                 nv_wr32(dev, 0x400890, 0x00a8cfff);
 523                 nv_wr32(dev, 0x400610, 0x304B1FB6);
 524                 nv_wr32(dev, 0x400B80, 0x1cbd3883);
 525                 nv_wr32(dev, 0x400B84, 0x44000000);
 526                 nv_wr32(dev, 0x400098, 0x40000080);
 527                 nv_wr32(dev, 0x400B88, 0x000000ff);
 528
 529         } else {
 530                 nv_wr32(dev, 0x400880, 0x0008c7df);
 531                 nv_wr32(dev, 0x400094, 0x00000005);
 532                 nv_wr32(dev, 0x400B80, 0x45eae20e);
 533                 nv_wr32(dev, 0x400B84, 0x24000000);
 534                 nv_wr32(dev, 0x400098, 0x00000040);
 535                 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
 536                 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030);
 537                 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
 538                 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030);
 539         }
 540
 541         /* Turn all the tiling regions off. */
 542         for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
 543                 nv20_graph_set_tile_region(dev, i);
 544
 545         nv_wr32(dev, 0x4009a0, nv_rd32(dev, 0x100324));
 546         nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
 547         nv_wr32(dev, NV10_PGRAPH_RDI_DATA, nv_rd32(dev, 0x100324));
 548
 549         nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
 550         nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 551
 552         tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) & 0x0007ff00;
 553         nv_wr32(dev, NV10_PGRAPH_SURFACE, tmp);
 554         tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) | 0x00020100;
 555         nv_wr32(dev, NV10_PGRAPH_SURFACE, tmp);
 556
 557         /* begin RAM config */
 558         vramsz = pci_resource_len(dev->pdev, 0) - 1;
 559         nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
 560         nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
 561         nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
 562         nv_wr32(dev, NV10_PGRAPH_RDI_DATA , nv_rd32(dev, NV04_PFB_CFG0));
 563         nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
 564         nv_wr32(dev, NV10_PGRAPH_RDI_DATA , nv_rd32(dev, NV04_PFB_CFG1));
 565         nv_wr32(dev, 0x400820, 0);
 566         nv_wr32(dev, 0x400824, 0);
 567         nv_wr32(dev, 0x400864, vramsz - 1);
 568         nv_wr32(dev, 0x400868, vramsz - 1);
 569
 570         /* interesting.. the below overwrites some of the tile setup above.. */
 571         nv_wr32(dev, 0x400B20, 0x00000000);
 572         nv_wr32(dev, 0x400B04, 0xFFFFFFFF);
 573
 574         nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
 575         nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
 576         nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
 577         nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
 578
 579         return 0;
 580 }
 581
 582 int
 583 nv30_graph_init(struct drm_device *dev, int engine)
 584 {
 585         struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
 586         struct drm_nouveau_private *dev_priv = dev->dev_private;
 587         int i;
 588
 589         nv_wr32(dev, NV03_PMC_ENABLE,
 590                 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
 591         nv_wr32(dev, NV03_PMC_ENABLE,
 592                 nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PGRAPH);
 593
 594         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->pinst >> 4);
 595
 596         nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 597         nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 598
 599         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 600         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
 601         nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
 602         nv_wr32(dev, 0x400890, 0x01b463ff);
 603         nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
 604         nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
 605         nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
 606         nv_wr32(dev, 0x400B80, 0x1003d888);
 607         nv_wr32(dev, 0x400B84, 0x0c000000);
 608         nv_wr32(dev, 0x400098, 0x00000000);
 609         nv_wr32(dev, 0x40009C, 0x0005ad00);
 610         nv_wr32(dev, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
 611         nv_wr32(dev, 0x4000a0, 0x00000000);
 612         nv_wr32(dev, 0x4000a4, 0x00000008);
 613         nv_wr32(dev, 0x4008a8, 0xb784a400);
 614         nv_wr32(dev, 0x400ba0, 0x002f8685);
 615         nv_wr32(dev, 0x400ba4, 0x00231f3f);
 616         nv_wr32(dev, 0x4008a4, 0x40000020);
 617
 618         if (dev_priv->chipset == 0x34) {
 619                 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
 620                 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00200201);
 621                 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
 622                 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000008);
 623                 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
 624                 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000032);
 625                 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
 626                 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000002);
 627         }
 628
 629         nv_wr32(dev, 0x4000c0, 0x00000016);
 630
 631         /* Turn all the tiling regions off. */
 632         for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
 633                 nv20_graph_set_tile_region(dev, i);
 634
 635         nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
 636         nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 637         nv_wr32(dev, 0x0040075c             , 0x00000001);
 638
 639         /* begin RAM config */
 640         /* vramsz = pci_resource_len(dev->pdev, 0) - 1; */
 641         nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
 642         nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
 643         if (dev_priv->chipset != 0x34) {
 644                 nv_wr32(dev, 0x400750, 0x00EA0000);
 645                 nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG0));
 646                 nv_wr32(dev, 0x400750, 0x00EA0004);
 647                 nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG1));
 648         }
 649
 650         return 0;
 651 }
 652
 653 int
 654 nv20_graph_fini(struct drm_device *dev, int engine, bool suspend)
 655 {
 656         nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
 657         if (!nv_wait(dev, NV04_PGRAPH_STATUS, ~0, 0) && suspend) {
 658                 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
 659                 return -EBUSY;
 660         }
 661         nv20_graph_unload_context(dev);
 662         nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
 663         return 0;
 664 }
 665
 666 static void
 667 nv20_graph_isr(struct drm_device *dev)
 668 {
 669         u32 stat;
 670
 671         while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
 672                 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
 673                 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
 674                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
 675                 u32 chid = (addr & 0x01f00000) >> 20;
 676                 u32 subc = (addr & 0x00070000) >> 16;
 677                 u32 mthd = (addr & 0x00001ffc);
 678                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
 679                 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xfff;
 680                 u32 show = stat;
 681
 682                 if (stat & NV_PGRAPH_INTR_ERROR) {
 683                         if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 684                                 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
 685                                         show &= ~NV_PGRAPH_INTR_ERROR;
 686                         }
 687                 }
 688
 689                 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
 690                 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
 691
 692                 if (show && nouveau_ratelimit()) {
 693                         NV_INFO(dev, "PGRAPH -");
 694                         nouveau_bitfield_print(nv10_graph_intr, show);
 695                         printk(" nsource:");
 696                         nouveau_bitfield_print(nv04_graph_nsource, nsource);
 697                         printk(" nstatus:");
 698                         nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
 699                         printk("\n");
 700                         NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
 701                                      "mthd 0x%04x data 0x%08x\n",
 702                                 chid, subc, class, mthd, data);
 703                 }
 704         }
 705 }
 706
 707 static void
 708 nv20_graph_destroy(struct drm_device *dev, int engine)
 709 {
 710         struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
 711
 712         nouveau_irq_unregister(dev, 12);
 713         nouveau_gpuobj_ref(NULL, &pgraph->ctxtab);
 714
 715         NVOBJ_ENGINE_DEL(dev, GR);
 716         kfree(pgraph);
 717 }
 718
 719 int
 720 nv20_graph_create(struct drm_device *dev)
 721 {
 722         struct drm_nouveau_private *dev_priv = dev->dev_private;
 723         struct nv20_graph_engine *pgraph;
 724         int ret;
 725
 726         pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
 727         if (!pgraph)
 728                 return -ENOMEM;
 729
 730         pgraph->base.destroy = nv20_graph_destroy;
 731         pgraph->base.fini = nv20_graph_fini;
 732         pgraph->base.context_new = nv20_graph_context_new;
 733         pgraph->base.context_del = nv20_graph_context_del;
 734         pgraph->base.object_new = nv04_graph_object_new;
 735         pgraph->base.set_tile_region = nv20_graph_set_tile_region;
 736
 737         pgraph->grctx_user = 0x0028;
 738         if (dev_priv->card_type == NV_20) {
 739                 pgraph->base.init = nv20_graph_init;
 740                 switch (dev_priv->chipset) {
 741                 case 0x20:
 742                         pgraph->grctx_init = nv20_graph_context_init;
 743                         pgraph->grctx_size = NV20_GRCTX_SIZE;
 744                         pgraph->grctx_user = 0x0000;
 745                         break;
 746                 case 0x25:
 747                 case 0x28:
 748                         pgraph->grctx_init = nv25_graph_context_init;
 749                         pgraph->grctx_size = NV25_GRCTX_SIZE;
 750                         break;
 751                 case 0x2a:
 752                         pgraph->grctx_init = nv2a_graph_context_init;
 753                         pgraph->grctx_size = NV2A_GRCTX_SIZE;
 754                         pgraph->grctx_user = 0x0000;
 755                         break;
 756                 default:
 757                         NV_ERROR(dev, "PGRAPH: unknown chipset\n");
 758                         kfree(pgraph);
 759                         return 0;
 760                 }
 761         } else {
 762                 pgraph->base.init = nv30_graph_init;
 763                 switch (dev_priv->chipset) {
 764                 case 0x30:
 765                 case 0x31:
 766                         pgraph->grctx_init = nv30_31_graph_context_init;
 767                         pgraph->grctx_size = NV30_31_GRCTX_SIZE;
 768                         break;
 769                 case 0x34:
 770                         pgraph->grctx_init = nv34_graph_context_init;
 771                         pgraph->grctx_size = NV34_GRCTX_SIZE;
 772                         break;
 773                 case 0x35:
 774                 case 0x36:
 775                         pgraph->grctx_init = nv35_36_graph_context_init;
 776                         pgraph->grctx_size = NV35_36_GRCTX_SIZE;
 777                         break;
 778                 default:
 779                         NV_ERROR(dev, "PGRAPH: unknown chipset\n");
 780                         kfree(pgraph);
 781                         return 0;
 782                 }
 783         }
 784
 785         /* Create Context Pointer Table */
 786         ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16, NVOBJ_FLAG_ZERO_ALLOC,
 787                                  &pgraph->ctxtab);
 788         if (ret) {
 789                 kfree(pgraph);
 790                 return ret;
 791         }
 792
 793         NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
 794         nouveau_irq_register(dev, 12, nv20_graph_isr);
 795
 796         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 797         NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
 798         NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
 799         NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
 800         NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
 801         NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
 802         NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
 803         NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
 804         NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
 805         NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
 806         NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
 807         NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
 808         if (dev_priv->card_type == NV_20) {
 809                 NVOBJ_CLASS(dev, 0x009e, GR); /* swzsurf */
 810                 NVOBJ_CLASS(dev, 0x0096, GR); /* celcius */
 811
 812                 /* kelvin */
 813                 if (dev_priv->chipset < 0x25)
 814                         NVOBJ_CLASS(dev, 0x0097, GR);
 815                 else
 816                         NVOBJ_CLASS(dev, 0x0597, GR);
 817         } else {
 818                 NVOBJ_CLASS(dev, 0x038a, GR); /* ifc (nv30) */
 819                 NVOBJ_CLASS(dev, 0x0389, GR); /* sifm (nv30) */
 820                 NVOBJ_CLASS(dev, 0x0362, GR); /* surf2d (nv30) */
 821                 NVOBJ_CLASS(dev, 0x039e, GR); /* swzsurf */
 822
 823                 /* rankine */
 824                 if (0x00000003 & (1 << (dev_priv->chipset & 0x0f)))
 825                         NVOBJ_CLASS(dev, 0x0397, GR);
 826                 else
 827                 if (0x00000010 & (1 << (dev_priv->chipset & 0x0f)))
 828                         NVOBJ_CLASS(dev, 0x0697, GR);
 829                 else
 830                 if (0x000001e0 & (1 << (dev_priv->chipset & 0x0f)))
 831                         NVOBJ_CLASS(dev, 0x0497, GR);
 832         }
 833
 834         return 0;
 835 }