2 * Copyright (C) 2012 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "nouveau_drv.h"
29 #include "nouveau_fifo.h"
30 #include "nouveau_util.h"
31 #include "nouveau_ramht.h"
33 static struct ramfc_desc
{
40 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT
},
41 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET
},
42 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT
},
43 { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE
},
44 { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT
},
45 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE
},
46 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH
},
47 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE
},
48 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1
},
49 { 32, 0, 0x20, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE
},
50 { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP
},
51 { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT
},
52 { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_SEMAPHORE
},
53 { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE
},
57 struct nv17_fifo_priv
{
58 struct nouveau_fifo_priv base
;
59 struct ramfc_desc
*ramfc_desc
;
62 struct nv17_fifo_chan
{
63 struct nouveau_fifo_chan base
;
64 struct nouveau_gpuobj
*ramfc
;
68 nv17_fifo_context_new(struct nouveau_channel
*chan
, int engine
)
70 struct drm_device
*dev
= chan
->dev
;
71 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
72 struct nv17_fifo_priv
*priv
= nv_engine(dev
, engine
);
73 struct nv17_fifo_chan
*fctx
;
77 fctx
= chan
->engctx
[engine
] = kzalloc(sizeof(*fctx
), GFP_KERNEL
);
81 /* map channel control registers */
82 chan
->user
= ioremap(pci_resource_start(dev
->pdev
, 0) +
83 NV03_USER(chan
->id
), PAGE_SIZE
);
89 /* initialise default fifo context */
90 ret
= nouveau_gpuobj_new_fake(dev
, dev_priv
->ramfc
->pinst
+
91 chan
->id
* 64, ~0, 64,
92 NVOBJ_FLAG_ZERO_ALLOC
|
93 NVOBJ_FLAG_ZERO_FREE
, &fctx
->ramfc
);
97 nv_wo32(fctx
->ramfc
, 0x00, chan
->pushbuf_base
);
98 nv_wo32(fctx
->ramfc
, 0x04, chan
->pushbuf_base
);
99 nv_wo32(fctx
->ramfc
, 0x0c, chan
->pushbuf
->pinst
>> 4);
100 nv_wo32(fctx
->ramfc
, 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES
|
101 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES
|
103 NV_PFIFO_CACHE1_BIG_ENDIAN
|
105 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8
);
107 /* enable dma mode on the channel */
108 spin_lock_irqsave(&dev_priv
->context_switch_lock
, flags
);
109 nv_mask(dev
, NV04_PFIFO_MODE
, (1 << chan
->id
), (1 << chan
->id
));
110 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, flags
);
114 priv
->base
.base
.context_del(chan
, engine
);
119 nv17_fifo_init(struct drm_device
*dev
, int engine
)
121 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
122 struct nv17_fifo_priv
*priv
= nv_engine(dev
, engine
);
125 nv_mask(dev
, NV03_PMC_ENABLE
, NV_PMC_ENABLE_PFIFO
, 0);
126 nv_mask(dev
, NV03_PMC_ENABLE
, NV_PMC_ENABLE_PFIFO
, NV_PMC_ENABLE_PFIFO
);
128 nv_wr32(dev
, NV04_PFIFO_DELAY_0
, 0x000000ff);
129 nv_wr32(dev
, NV04_PFIFO_DMA_TIMESLICE
, 0x0101ffff);
131 nv_wr32(dev
, NV03_PFIFO_RAMHT
, (0x03 << 24) /* search 128 */ |
132 ((dev_priv
->ramht
->bits
- 9) << 16) |
133 (dev_priv
->ramht
->gpuobj
->pinst
>> 8));
134 nv_wr32(dev
, NV03_PFIFO_RAMRO
, dev_priv
->ramro
->pinst
>> 8);
135 nv_wr32(dev
, NV03_PFIFO_RAMFC
, 0x00010000 |
136 dev_priv
->ramfc
->pinst
>> 8);
138 nv_wr32(dev
, NV03_PFIFO_CACHE1_PUSH1
, priv
->base
.channels
);
140 nv_wr32(dev
, NV03_PFIFO_INTR_0
, 0xffffffff);
141 nv_wr32(dev
, NV03_PFIFO_INTR_EN_0
, 0xffffffff);
143 nv_wr32(dev
, NV03_PFIFO_CACHE1_PUSH0
, 1);
144 nv_wr32(dev
, NV04_PFIFO_CACHE1_PULL0
, 1);
145 nv_wr32(dev
, NV03_PFIFO_CACHES
, 1);
147 for (i
= 0; i
< priv
->base
.channels
; i
++) {
148 if (dev_priv
->channels
.ptr
[i
])
149 nv_mask(dev
, NV04_PFIFO_MODE
, (1 << i
), (1 << i
));
156 nv17_fifo_create(struct drm_device
*dev
)
158 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
159 struct nv17_fifo_priv
*priv
;
161 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
165 priv
->base
.base
.destroy
= nv04_fifo_destroy
;
166 priv
->base
.base
.init
= nv17_fifo_init
;
167 priv
->base
.base
.fini
= nv04_fifo_fini
;
168 priv
->base
.base
.context_new
= nv17_fifo_context_new
;
169 priv
->base
.base
.context_del
= nv04_fifo_context_del
;
170 priv
->base
.channels
= 31;
171 priv
->ramfc_desc
= nv17_ramfc
;
172 dev_priv
->eng
[NVOBJ_ENGINE_FIFO
] = &priv
->base
.base
;
174 nouveau_irq_register(dev
, 8, nv04_fifo_isr
);