drivers/gpu/drm/nouveau/nv10_gpio.c

   1 /*
   2  * Copyright (C) 2009 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include <drm/drmP.h>
  28 #include "nouveau_drv.h"
  29 #include "nouveau_hw.h"
  30 #include "nouveau_gpio.h"
  31
  32 int
  33 nv10_gpio_sense(struct drm_device *dev, int line)
  34 {
  35         if (line < 2) {
  36                 line = line * 16;
  37                 line = NVReadCRTC(dev, 0, NV_PCRTC_GPIO) >> line;
  38                 return !!(line & 0x0100);
  39         } else
  40         if (line < 10) {
  41                 line = (line - 2) * 4;
  42                 line = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT) >> line;
  43                 return !!(line & 0x04);
  44         } else
  45         if (line < 14) {
  46                 line = (line - 10) * 4;
  47                 line = NVReadCRTC(dev, 0, NV_PCRTC_850) >> line;
  48                 return !!(line & 0x04);
  49         }
  50
  51         return -EINVAL;
  52 }
  53
  54 int
  55 nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out)
  56 {
  57         u32 reg, mask, data;
  58
  59         if (line < 2) {
  60                 line = line * 16;
  61                 reg  = NV_PCRTC_GPIO;
  62                 mask = 0x00000011;
  63                 data = (dir << 4) | out;
  64         } else
  65         if (line < 10) {
  66                 line = (line - 2) * 4;
  67                 reg  = NV_PCRTC_GPIO_EXT;
  68                 mask = 0x00000003;
  69                 data = (dir << 1) | out;
  70         } else
  71         if (line < 14) {
  72                 line = (line - 10) * 4;
  73                 reg  = NV_PCRTC_850;
  74                 mask = 0x00000003;
  75                 data = (dir << 1) | out;
  76         } else {
  77                 return -EINVAL;
  78         }
  79
  80         mask = NVReadCRTC(dev, 0, reg) & ~(mask << line);
  81         NVWriteCRTC(dev, 0, reg, mask | (data << line));
  82         return 0;
  83 }
  84
  85 void
  86 nv10_gpio_irq_enable(struct drm_device *dev, int line, bool on)
  87 {
  88         u32 mask = 0x00010001 << line;
  89
  90         nv_wr32(dev, 0x001104, mask);
  91         nv_mask(dev, 0x001144, mask, on ? mask : 0);
  92 }
  93
  94 static void
  95 nv10_gpio_isr(struct drm_device *dev)
  96 {
  97         u32 intr = nv_rd32(dev, 0x1104);
  98         u32 hi = (intr & 0x0000ffff) >> 0;
  99         u32 lo = (intr & 0xffff0000) >> 16;
 100
 101         nouveau_gpio_isr(dev, 0, hi | lo);
 102
 103         nv_wr32(dev, 0x001104, intr);
 104 }
 105
 106 int
 107 nv10_gpio_init(struct drm_device *dev)
 108 {
 109         nv_wr32(dev, 0x001140, 0x00000000);
 110         nv_wr32(dev, 0x001100, 0xffffffff);
 111         nv_wr32(dev, 0x001144, 0x00000000);
 112         nv_wr32(dev, 0x001104, 0xffffffff);
 113         nouveau_irq_register(dev, 28, nv10_gpio_isr); /* PBUS */
 114         return 0;
 115 }
 116
 117 void
 118 nv10_gpio_fini(struct drm_device *dev)
 119 {
 120         nv_wr32(dev, 0x001140, 0x00000000);
 121         nv_wr32(dev, 0x001144, 0x00000000);
 122         nouveau_irq_unregister(dev, 28);
 123 }