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UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nv04_graph.c
1 /*
2 * Copyright 2007 Stephane Marchesin
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <drm/drmP.h>
26 #include <drm/nouveau_drm.h>
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
29 #include "nouveau_util.h"
30 #include "nouveau_ramht.h"
31
32 struct nv04_graph_engine {
33 struct nouveau_exec_engine base;
34 };
35
36 static uint32_t nv04_graph_ctx_regs[] = {
37 0x0040053c,
38 0x00400544,
39 0x00400540,
40 0x00400548,
41 NV04_PGRAPH_CTX_SWITCH1,
42 NV04_PGRAPH_CTX_SWITCH2,
43 NV04_PGRAPH_CTX_SWITCH3,
44 NV04_PGRAPH_CTX_SWITCH4,
45 NV04_PGRAPH_CTX_CACHE1,
46 NV04_PGRAPH_CTX_CACHE2,
47 NV04_PGRAPH_CTX_CACHE3,
48 NV04_PGRAPH_CTX_CACHE4,
49 0x00400184,
50 0x004001a4,
51 0x004001c4,
52 0x004001e4,
53 0x00400188,
54 0x004001a8,
55 0x004001c8,
56 0x004001e8,
57 0x0040018c,
58 0x004001ac,
59 0x004001cc,
60 0x004001ec,
61 0x00400190,
62 0x004001b0,
63 0x004001d0,
64 0x004001f0,
65 0x00400194,
66 0x004001b4,
67 0x004001d4,
68 0x004001f4,
69 0x00400198,
70 0x004001b8,
71 0x004001d8,
72 0x004001f8,
73 0x0040019c,
74 0x004001bc,
75 0x004001dc,
76 0x004001fc,
77 0x00400174,
78 NV04_PGRAPH_DMA_START_0,
79 NV04_PGRAPH_DMA_START_1,
80 NV04_PGRAPH_DMA_LENGTH,
81 NV04_PGRAPH_DMA_MISC,
82 NV04_PGRAPH_DMA_PITCH,
83 NV04_PGRAPH_BOFFSET0,
84 NV04_PGRAPH_BBASE0,
85 NV04_PGRAPH_BLIMIT0,
86 NV04_PGRAPH_BOFFSET1,
87 NV04_PGRAPH_BBASE1,
88 NV04_PGRAPH_BLIMIT1,
89 NV04_PGRAPH_BOFFSET2,
90 NV04_PGRAPH_BBASE2,
91 NV04_PGRAPH_BLIMIT2,
92 NV04_PGRAPH_BOFFSET3,
93 NV04_PGRAPH_BBASE3,
94 NV04_PGRAPH_BLIMIT3,
95 NV04_PGRAPH_BOFFSET4,
96 NV04_PGRAPH_BBASE4,
97 NV04_PGRAPH_BLIMIT4,
98 NV04_PGRAPH_BOFFSET5,
99 NV04_PGRAPH_BBASE5,
100 NV04_PGRAPH_BLIMIT5,
101 NV04_PGRAPH_BPITCH0,
102 NV04_PGRAPH_BPITCH1,
103 NV04_PGRAPH_BPITCH2,
104 NV04_PGRAPH_BPITCH3,
105 NV04_PGRAPH_BPITCH4,
106 NV04_PGRAPH_SURFACE,
107 NV04_PGRAPH_STATE,
108 NV04_PGRAPH_BSWIZZLE2,
109 NV04_PGRAPH_BSWIZZLE5,
110 NV04_PGRAPH_BPIXEL,
111 NV04_PGRAPH_NOTIFY,
112 NV04_PGRAPH_PATT_COLOR0,
113 NV04_PGRAPH_PATT_COLOR1,
114 NV04_PGRAPH_PATT_COLORRAM+0x00,
115 NV04_PGRAPH_PATT_COLORRAM+0x04,
116 NV04_PGRAPH_PATT_COLORRAM+0x08,
117 NV04_PGRAPH_PATT_COLORRAM+0x0c,
118 NV04_PGRAPH_PATT_COLORRAM+0x10,
119 NV04_PGRAPH_PATT_COLORRAM+0x14,
120 NV04_PGRAPH_PATT_COLORRAM+0x18,
121 NV04_PGRAPH_PATT_COLORRAM+0x1c,
122 NV04_PGRAPH_PATT_COLORRAM+0x20,
123 NV04_PGRAPH_PATT_COLORRAM+0x24,
124 NV04_PGRAPH_PATT_COLORRAM+0x28,
125 NV04_PGRAPH_PATT_COLORRAM+0x2c,
126 NV04_PGRAPH_PATT_COLORRAM+0x30,
127 NV04_PGRAPH_PATT_COLORRAM+0x34,
128 NV04_PGRAPH_PATT_COLORRAM+0x38,
129 NV04_PGRAPH_PATT_COLORRAM+0x3c,
130 NV04_PGRAPH_PATT_COLORRAM+0x40,
131 NV04_PGRAPH_PATT_COLORRAM+0x44,
132 NV04_PGRAPH_PATT_COLORRAM+0x48,
133 NV04_PGRAPH_PATT_COLORRAM+0x4c,
134 NV04_PGRAPH_PATT_COLORRAM+0x50,
135 NV04_PGRAPH_PATT_COLORRAM+0x54,
136 NV04_PGRAPH_PATT_COLORRAM+0x58,
137 NV04_PGRAPH_PATT_COLORRAM+0x5c,
138 NV04_PGRAPH_PATT_COLORRAM+0x60,
139 NV04_PGRAPH_PATT_COLORRAM+0x64,
140 NV04_PGRAPH_PATT_COLORRAM+0x68,
141 NV04_PGRAPH_PATT_COLORRAM+0x6c,
142 NV04_PGRAPH_PATT_COLORRAM+0x70,
143 NV04_PGRAPH_PATT_COLORRAM+0x74,
144 NV04_PGRAPH_PATT_COLORRAM+0x78,
145 NV04_PGRAPH_PATT_COLORRAM+0x7c,
146 NV04_PGRAPH_PATT_COLORRAM+0x80,
147 NV04_PGRAPH_PATT_COLORRAM+0x84,
148 NV04_PGRAPH_PATT_COLORRAM+0x88,
149 NV04_PGRAPH_PATT_COLORRAM+0x8c,
150 NV04_PGRAPH_PATT_COLORRAM+0x90,
151 NV04_PGRAPH_PATT_COLORRAM+0x94,
152 NV04_PGRAPH_PATT_COLORRAM+0x98,
153 NV04_PGRAPH_PATT_COLORRAM+0x9c,
154 NV04_PGRAPH_PATT_COLORRAM+0xa0,
155 NV04_PGRAPH_PATT_COLORRAM+0xa4,
156 NV04_PGRAPH_PATT_COLORRAM+0xa8,
157 NV04_PGRAPH_PATT_COLORRAM+0xac,
158 NV04_PGRAPH_PATT_COLORRAM+0xb0,
159 NV04_PGRAPH_PATT_COLORRAM+0xb4,
160 NV04_PGRAPH_PATT_COLORRAM+0xb8,
161 NV04_PGRAPH_PATT_COLORRAM+0xbc,
162 NV04_PGRAPH_PATT_COLORRAM+0xc0,
163 NV04_PGRAPH_PATT_COLORRAM+0xc4,
164 NV04_PGRAPH_PATT_COLORRAM+0xc8,
165 NV04_PGRAPH_PATT_COLORRAM+0xcc,
166 NV04_PGRAPH_PATT_COLORRAM+0xd0,
167 NV04_PGRAPH_PATT_COLORRAM+0xd4,
168 NV04_PGRAPH_PATT_COLORRAM+0xd8,
169 NV04_PGRAPH_PATT_COLORRAM+0xdc,
170 NV04_PGRAPH_PATT_COLORRAM+0xe0,
171 NV04_PGRAPH_PATT_COLORRAM+0xe4,
172 NV04_PGRAPH_PATT_COLORRAM+0xe8,
173 NV04_PGRAPH_PATT_COLORRAM+0xec,
174 NV04_PGRAPH_PATT_COLORRAM+0xf0,
175 NV04_PGRAPH_PATT_COLORRAM+0xf4,
176 NV04_PGRAPH_PATT_COLORRAM+0xf8,
177 NV04_PGRAPH_PATT_COLORRAM+0xfc,
178 NV04_PGRAPH_PATTERN,
179 0x0040080c,
180 NV04_PGRAPH_PATTERN_SHAPE,
181 0x00400600,
182 NV04_PGRAPH_ROP3,
183 NV04_PGRAPH_CHROMA,
184 NV04_PGRAPH_BETA_AND,
185 NV04_PGRAPH_BETA_PREMULT,
186 NV04_PGRAPH_CONTROL0,
187 NV04_PGRAPH_CONTROL1,
188 NV04_PGRAPH_CONTROL2,
189 NV04_PGRAPH_BLEND,
190 NV04_PGRAPH_STORED_FMT,
191 NV04_PGRAPH_SOURCE_COLOR,
192 0x00400560,
193 0x00400568,
194 0x00400564,
195 0x0040056c,
196 0x00400400,
197 0x00400480,
198 0x00400404,
199 0x00400484,
200 0x00400408,
201 0x00400488,
202 0x0040040c,
203 0x0040048c,
204 0x00400410,
205 0x00400490,
206 0x00400414,
207 0x00400494,
208 0x00400418,
209 0x00400498,
210 0x0040041c,
211 0x0040049c,
212 0x00400420,
213 0x004004a0,
214 0x00400424,
215 0x004004a4,
216 0x00400428,
217 0x004004a8,
218 0x0040042c,
219 0x004004ac,
220 0x00400430,
221 0x004004b0,
222 0x00400434,
223 0x004004b4,
224 0x00400438,
225 0x004004b8,
226 0x0040043c,
227 0x004004bc,
228 0x00400440,
229 0x004004c0,
230 0x00400444,
231 0x004004c4,
232 0x00400448,
233 0x004004c8,
234 0x0040044c,
235 0x004004cc,
236 0x00400450,
237 0x004004d0,
238 0x00400454,
239 0x004004d4,
240 0x00400458,
241 0x004004d8,
242 0x0040045c,
243 0x004004dc,
244 0x00400460,
245 0x004004e0,
246 0x00400464,
247 0x004004e4,
248 0x00400468,
249 0x004004e8,
250 0x0040046c,
251 0x004004ec,
252 0x00400470,
253 0x004004f0,
254 0x00400474,
255 0x004004f4,
256 0x00400478,
257 0x004004f8,
258 0x0040047c,
259 0x004004fc,
260 0x00400534,
261 0x00400538,
262 0x00400514,
263 0x00400518,
264 0x0040051c,
265 0x00400520,
266 0x00400524,
267 0x00400528,
268 0x0040052c,
269 0x00400530,
270 0x00400d00,
271 0x00400d40,
272 0x00400d80,
273 0x00400d04,
274 0x00400d44,
275 0x00400d84,
276 0x00400d08,
277 0x00400d48,
278 0x00400d88,
279 0x00400d0c,
280 0x00400d4c,
281 0x00400d8c,
282 0x00400d10,
283 0x00400d50,
284 0x00400d90,
285 0x00400d14,
286 0x00400d54,
287 0x00400d94,
288 0x00400d18,
289 0x00400d58,
290 0x00400d98,
291 0x00400d1c,
292 0x00400d5c,
293 0x00400d9c,
294 0x00400d20,
295 0x00400d60,
296 0x00400da0,
297 0x00400d24,
298 0x00400d64,
299 0x00400da4,
300 0x00400d28,
301 0x00400d68,
302 0x00400da8,
303 0x00400d2c,
304 0x00400d6c,
305 0x00400dac,
306 0x00400d30,
307 0x00400d70,
308 0x00400db0,
309 0x00400d34,
310 0x00400d74,
311 0x00400db4,
312 0x00400d38,
313 0x00400d78,
314 0x00400db8,
315 0x00400d3c,
316 0x00400d7c,
317 0x00400dbc,
318 0x00400590,
319 0x00400594,
320 0x00400598,
321 0x0040059c,
322 0x004005a8,
323 0x004005ac,
324 0x004005b0,
325 0x004005b4,
326 0x004005c0,
327 0x004005c4,
328 0x004005c8,
329 0x004005cc,
330 0x004005d0,
331 0x004005d4,
332 0x004005d8,
333 0x004005dc,
334 0x004005e0,
335 NV04_PGRAPH_PASSTHRU_0,
336 NV04_PGRAPH_PASSTHRU_1,
337 NV04_PGRAPH_PASSTHRU_2,
338 NV04_PGRAPH_DVD_COLORFMT,
339 NV04_PGRAPH_SCALED_FORMAT,
340 NV04_PGRAPH_MISC24_0,
341 NV04_PGRAPH_MISC24_1,
342 NV04_PGRAPH_MISC24_2,
343 0x00400500,
344 0x00400504,
345 NV04_PGRAPH_VALID1,
346 NV04_PGRAPH_VALID2,
347 NV04_PGRAPH_DEBUG_3
348 };
349
350 struct graph_state {
351 uint32_t nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
352 };
353
354 static struct nouveau_channel *
355 nv04_graph_channel(struct drm_device *dev)
356 {
357 struct drm_nouveau_private *dev_priv = dev->dev_private;
358 int chid = 15;
359
360 if (nv_rd32(dev, NV04_PGRAPH_CTX_CONTROL) & 0x00010000)
361 chid = nv_rd32(dev, NV04_PGRAPH_CTX_USER) >> 24;
362
363 if (chid > 15)
364 return NULL;
365
366 return dev_priv->channels.ptr[chid];
367 }
368
369 static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
370 {
371 int i;
372
373 for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
374 if (nv04_graph_ctx_regs[i] == reg)
375 return &ctx->nv04[i];
376 }
377
378 return NULL;
379 }
380
381 static int
382 nv04_graph_load_context(struct nouveau_channel *chan)
383 {
384 struct graph_state *pgraph_ctx = chan->engctx[NVOBJ_ENGINE_GR];
385 struct drm_device *dev = chan->dev;
386 uint32_t tmp;
387 int i;
388
389 for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
390 nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
391
392 nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
393
394 tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
395 nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp | chan->id << 24);
396
397 tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2);
398 nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff);
399
400 return 0;
401 }
402
403 static int
404 nv04_graph_unload_context(struct drm_device *dev)
405 {
406 struct nouveau_channel *chan = NULL;
407 struct graph_state *ctx;
408 uint32_t tmp;
409 int i;
410
411 chan = nv04_graph_channel(dev);
412 if (!chan)
413 return 0;
414 ctx = chan->engctx[NVOBJ_ENGINE_GR];
415
416 for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
417 ctx->nv04[i] = nv_rd32(dev, nv04_graph_ctx_regs[i]);
418
419 nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
420 tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
421 tmp |= 15 << 24;
422 nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
423 return 0;
424 }
425
426 static int
427 nv04_graph_context_new(struct nouveau_channel *chan, int engine)
428 {
429 struct graph_state *pgraph_ctx;
430 NV_DEBUG(chan->dev, "nv04_graph_context_create %d\n", chan->id);
431
432 pgraph_ctx = kzalloc(sizeof(*pgraph_ctx), GFP_KERNEL);
433 if (pgraph_ctx == NULL)
434 return -ENOMEM;
435
436 *ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
437
438 chan->engctx[engine] = pgraph_ctx;
439 return 0;
440 }
441
442 static void
443 nv04_graph_context_del(struct nouveau_channel *chan, int engine)
444 {
445 struct drm_device *dev = chan->dev;
446 struct drm_nouveau_private *dev_priv = dev->dev_private;
447 struct graph_state *pgraph_ctx = chan->engctx[engine];
448 unsigned long flags;
449
450 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
451 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
452
453 /* Unload the context if it's the currently active one */
454 if (nv04_graph_channel(dev) == chan)
455 nv04_graph_unload_context(dev);
456
457 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
458 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
459
460 /* Free the context resources */
461 kfree(pgraph_ctx);
462 chan->engctx[engine] = NULL;
463 }
464
465 int
466 nv04_graph_object_new(struct nouveau_channel *chan, int engine,
467 u32 handle, u16 class)
468 {
469 struct drm_device *dev = chan->dev;
470 struct nouveau_gpuobj *obj = NULL;
471 int ret;
472
473 ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
474 if (ret)
475 return ret;
476 obj->engine = 1;
477 obj->class = class;
478
479 #ifdef __BIG_ENDIAN
480 nv_wo32(obj, 0x00, 0x00080000 | class);
481 #else
482 nv_wo32(obj, 0x00, class);
483 #endif
484 nv_wo32(obj, 0x04, 0x00000000);
485 nv_wo32(obj, 0x08, 0x00000000);
486 nv_wo32(obj, 0x0c, 0x00000000);
487
488 ret = nouveau_ramht_insert(chan, handle, obj);
489 nouveau_gpuobj_ref(NULL, &obj);
490 return ret;
491 }
492
493 static int
494 nv04_graph_init(struct drm_device *dev, int engine)
495 {
496 uint32_t tmp;
497
498 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
499 ~NV_PMC_ENABLE_PGRAPH);
500 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
501 NV_PMC_ENABLE_PGRAPH);
502
503 /* Enable PGRAPH interrupts */
504 nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF);
505 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
506
507 nv_wr32(dev, NV04_PGRAPH_VALID1, 0);
508 nv_wr32(dev, NV04_PGRAPH_VALID2, 0);
509 /*nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x000001FF);
510 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
511 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x1231c000);
512 /*1231C000 blob, 001 haiku*/
513 /*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
514 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x72111100);
515 /*0x72111100 blob , 01 haiku*/
516 /*nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
517 nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
518 /*haiku same*/
519
520 /*nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
521 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
522 /*haiku and blob 10d4*/
523
524 nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF);
525 nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
526 tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
527 tmp |= 15 << 24;
528 nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
529
530 /* These don't belong here, they're part of a per-channel context */
531 nv_wr32(dev, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
532 nv_wr32(dev, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
533
534 return 0;
535 }
536
537 static int
538 nv04_graph_fini(struct drm_device *dev, int engine, bool suspend)
539 {
540 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
541 if (!nv_wait(dev, NV04_PGRAPH_STATUS, ~0, 0) && suspend) {
542 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
543 return -EBUSY;
544 }
545 nv04_graph_unload_context(dev);
546 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
547 return 0;
548 }
549
550 /*
551 * Software methods, why they are needed, and how they all work:
552 *
553 * NV04 and NV05 keep most of the state in PGRAPH context itself, but some
554 * 2d engine settings are kept inside the grobjs themselves. The grobjs are
555 * 3 words long on both. grobj format on NV04 is:
556 *
557 * word 0:
558 * - bits 0-7: class
559 * - bit 12: color key active
560 * - bit 13: clip rect active
561 * - bit 14: if set, destination surface is swizzled and taken from buffer 5
562 * [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
563 * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
564 * NV03_CONTEXT_SURFACE_DST].
565 * - bits 15-17: 2d operation [aka patch config]
566 * - bit 24: patch valid [enables rendering using this object]
567 * - bit 25: surf3d valid [for tex_tri and multitex_tri only]
568 * word 1:
569 * - bits 0-1: mono format
570 * - bits 8-13: color format
571 * - bits 16-31: DMA_NOTIFY instance
572 * word 2:
573 * - bits 0-15: DMA_A instance
574 * - bits 16-31: DMA_B instance
575 *
576 * On NV05 it's:
577 *
578 * word 0:
579 * - bits 0-7: class
580 * - bit 12: color key active
581 * - bit 13: clip rect active
582 * - bit 14: if set, destination surface is swizzled and taken from buffer 5
583 * [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
584 * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
585 * NV03_CONTEXT_SURFACE_DST].
586 * - bits 15-17: 2d operation [aka patch config]
587 * - bits 20-22: dither mode
588 * - bit 24: patch valid [enables rendering using this object]
589 * - bit 25: surface_dst/surface_color/surf2d/surf3d valid
590 * - bit 26: surface_src/surface_zeta valid
591 * - bit 27: pattern valid
592 * - bit 28: rop valid
593 * - bit 29: beta1 valid
594 * - bit 30: beta4 valid
595 * word 1:
596 * - bits 0-1: mono format
597 * - bits 8-13: color format
598 * - bits 16-31: DMA_NOTIFY instance
599 * word 2:
600 * - bits 0-15: DMA_A instance
601 * - bits 16-31: DMA_B instance
602 *
603 * NV05 will set/unset the relevant valid bits when you poke the relevant
604 * object-binding methods with object of the proper type, or with the NULL
605 * type. It'll only allow rendering using the grobj if all needed objects
606 * are bound. The needed set of objects depends on selected operation: for
607 * example rop object is needed by ROP_AND, but not by SRCCOPY_AND.
608 *
609 * NV04 doesn't have these methods implemented at all, and doesn't have the
610 * relevant bits in grobj. Instead, it'll allow rendering whenever bit 24
611 * is set. So we have to emulate them in software, internally keeping the
612 * same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04,
613 * but the last word isn't actually used for anything, we abuse it for this
614 * purpose.
615 *
616 * Actually, NV05 can optionally check bit 24 too, but we disable this since
617 * there's no use for it.
618 *
619 * For unknown reasons, NV04 implements surf3d binding in hardware as an
620 * exception. Also for unknown reasons, NV04 doesn't implement the clipping
621 * methods on the surf3d object, so we have to emulate them too.
622 */
623
624 static void
625 nv04_graph_set_ctx1(struct nouveau_channel *chan, u32 mask, u32 value)
626 {
627 struct drm_device *dev = chan->dev;
628 u32 instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
629 int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
630 u32 tmp;
631
632 tmp = nv_ri32(dev, instance);
633 tmp &= ~mask;
634 tmp |= value;
635
636 nv_wi32(dev, instance, tmp);
637 nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp);
638 nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
639 }
640
641 static void
642 nv04_graph_set_ctx_val(struct nouveau_channel *chan, u32 mask, u32 value)
643 {
644 struct drm_device *dev = chan->dev;
645 u32 instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
646 u32 tmp, ctx1;
647 int class, op, valid = 1;
648
649 ctx1 = nv_ri32(dev, instance);
650 class = ctx1 & 0xff;
651 op = (ctx1 >> 15) & 7;
652 tmp = nv_ri32(dev, instance + 0xc);
653 tmp &= ~mask;
654 tmp |= value;
655 nv_wi32(dev, instance + 0xc, tmp);
656
657 /* check for valid surf2d/surf_dst/surf_color */
658 if (!(tmp & 0x02000000))
659 valid = 0;
660 /* check for valid surf_src/surf_zeta */
661 if ((class == 0x1f || class == 0x48) && !(tmp & 0x04000000))
662 valid = 0;
663
664 switch (op) {
665 /* SRCCOPY_AND, SRCCOPY: no extra objects required */
666 case 0:
667 case 3:
668 break;
669 /* ROP_AND: requires pattern and rop */
670 case 1:
671 if (!(tmp & 0x18000000))
672 valid = 0;
673 break;
674 /* BLEND_AND: requires beta1 */
675 case 2:
676 if (!(tmp & 0x20000000))
677 valid = 0;
678 break;
679 /* SRCCOPY_PREMULT, BLEND_PREMULT: beta4 required */
680 case 4:
681 case 5:
682 if (!(tmp & 0x40000000))
683 valid = 0;
684 break;
685 }
686
687 nv04_graph_set_ctx1(chan, 0x01000000, valid << 24);
688 }
689
690 static int
691 nv04_graph_mthd_set_operation(struct nouveau_channel *chan,
692 u32 class, u32 mthd, u32 data)
693 {
694 if (data > 5)
695 return 1;
696 /* Old versions of the objects only accept first three operations. */
697 if (data > 2 && class < 0x40)
698 return 1;
699 nv04_graph_set_ctx1(chan, 0x00038000, data << 15);
700 /* changing operation changes set of objects needed for validation */
701 nv04_graph_set_ctx_val(chan, 0, 0);
702 return 0;
703 }
704
705 static int
706 nv04_graph_mthd_surf3d_clip_h(struct nouveau_channel *chan,
707 u32 class, u32 mthd, u32 data)
708 {
709 uint32_t min = data & 0xffff, max;
710 uint32_t w = data >> 16;
711 if (min & 0x8000)
712 /* too large */
713 return 1;
714 if (w & 0x8000)
715 /* yes, it accepts negative for some reason. */
716 w |= 0xffff0000;
717 max = min + w;
718 max &= 0x3ffff;
719 nv_wr32(chan->dev, 0x40053c, min);
720 nv_wr32(chan->dev, 0x400544, max);
721 return 0;
722 }
723
724 static int
725 nv04_graph_mthd_surf3d_clip_v(struct nouveau_channel *chan,
726 u32 class, u32 mthd, u32 data)
727 {
728 uint32_t min = data & 0xffff, max;
729 uint32_t w = data >> 16;
730 if (min & 0x8000)
731 /* too large */
732 return 1;
733 if (w & 0x8000)
734 /* yes, it accepts negative for some reason. */
735 w |= 0xffff0000;
736 max = min + w;
737 max &= 0x3ffff;
738 nv_wr32(chan->dev, 0x400540, min);
739 nv_wr32(chan->dev, 0x400548, max);
740 return 0;
741 }
742
743 static int
744 nv04_graph_mthd_bind_surf2d(struct nouveau_channel *chan,
745 u32 class, u32 mthd, u32 data)
746 {
747 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
748 case 0x30:
749 nv04_graph_set_ctx1(chan, 0x00004000, 0);
750 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
751 return 0;
752 case 0x42:
753 nv04_graph_set_ctx1(chan, 0x00004000, 0);
754 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
755 return 0;
756 }
757 return 1;
758 }
759
760 static int
761 nv04_graph_mthd_bind_surf2d_swzsurf(struct nouveau_channel *chan,
762 u32 class, u32 mthd, u32 data)
763 {
764 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
765 case 0x30:
766 nv04_graph_set_ctx1(chan, 0x00004000, 0);
767 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
768 return 0;
769 case 0x42:
770 nv04_graph_set_ctx1(chan, 0x00004000, 0);
771 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
772 return 0;
773 case 0x52:
774 nv04_graph_set_ctx1(chan, 0x00004000, 0x00004000);
775 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
776 return 0;
777 }
778 return 1;
779 }
780
781 static int
782 nv04_graph_mthd_bind_nv01_patt(struct nouveau_channel *chan,
783 u32 class, u32 mthd, u32 data)
784 {
785 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
786 case 0x30:
787 nv04_graph_set_ctx_val(chan, 0x08000000, 0);
788 return 0;
789 case 0x18:
790 nv04_graph_set_ctx_val(chan, 0x08000000, 0x08000000);
791 return 0;
792 }
793 return 1;
794 }
795
796 static int
797 nv04_graph_mthd_bind_nv04_patt(struct nouveau_channel *chan,
798 u32 class, u32 mthd, u32 data)
799 {
800 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
801 case 0x30:
802 nv04_graph_set_ctx_val(chan, 0x08000000, 0);
803 return 0;
804 case 0x44:
805 nv04_graph_set_ctx_val(chan, 0x08000000, 0x08000000);
806 return 0;
807 }
808 return 1;
809 }
810
811 static int
812 nv04_graph_mthd_bind_rop(struct nouveau_channel *chan,
813 u32 class, u32 mthd, u32 data)
814 {
815 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
816 case 0x30:
817 nv04_graph_set_ctx_val(chan, 0x10000000, 0);
818 return 0;
819 case 0x43:
820 nv04_graph_set_ctx_val(chan, 0x10000000, 0x10000000);
821 return 0;
822 }
823 return 1;
824 }
825
826 static int
827 nv04_graph_mthd_bind_beta1(struct nouveau_channel *chan,
828 u32 class, u32 mthd, u32 data)
829 {
830 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
831 case 0x30:
832 nv04_graph_set_ctx_val(chan, 0x20000000, 0);
833 return 0;
834 case 0x12:
835 nv04_graph_set_ctx_val(chan, 0x20000000, 0x20000000);
836 return 0;
837 }
838 return 1;
839 }
840
841 static int
842 nv04_graph_mthd_bind_beta4(struct nouveau_channel *chan,
843 u32 class, u32 mthd, u32 data)
844 {
845 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
846 case 0x30:
847 nv04_graph_set_ctx_val(chan, 0x40000000, 0);
848 return 0;
849 case 0x72:
850 nv04_graph_set_ctx_val(chan, 0x40000000, 0x40000000);
851 return 0;
852 }
853 return 1;
854 }
855
856 static int
857 nv04_graph_mthd_bind_surf_dst(struct nouveau_channel *chan,
858 u32 class, u32 mthd, u32 data)
859 {
860 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
861 case 0x30:
862 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
863 return 0;
864 case 0x58:
865 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
866 return 0;
867 }
868 return 1;
869 }
870
871 static int
872 nv04_graph_mthd_bind_surf_src(struct nouveau_channel *chan,
873 u32 class, u32 mthd, u32 data)
874 {
875 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
876 case 0x30:
877 nv04_graph_set_ctx_val(chan, 0x04000000, 0);
878 return 0;
879 case 0x59:
880 nv04_graph_set_ctx_val(chan, 0x04000000, 0x04000000);
881 return 0;
882 }
883 return 1;
884 }
885
886 static int
887 nv04_graph_mthd_bind_surf_color(struct nouveau_channel *chan,
888 u32 class, u32 mthd, u32 data)
889 {
890 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
891 case 0x30:
892 nv04_graph_set_ctx_val(chan, 0x02000000, 0);
893 return 0;
894 case 0x5a:
895 nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
896 return 0;
897 }
898 return 1;
899 }
900
901 static int
902 nv04_graph_mthd_bind_surf_zeta(struct nouveau_channel *chan,
903 u32 class, u32 mthd, u32 data)
904 {
905 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
906 case 0x30:
907 nv04_graph_set_ctx_val(chan, 0x04000000, 0);
908 return 0;
909 case 0x5b:
910 nv04_graph_set_ctx_val(chan, 0x04000000, 0x04000000);
911 return 0;
912 }
913 return 1;
914 }
915
916 static int
917 nv04_graph_mthd_bind_clip(struct nouveau_channel *chan,
918 u32 class, u32 mthd, u32 data)
919 {
920 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
921 case 0x30:
922 nv04_graph_set_ctx1(chan, 0x2000, 0);
923 return 0;
924 case 0x19:
925 nv04_graph_set_ctx1(chan, 0x2000, 0x2000);
926 return 0;
927 }
928 return 1;
929 }
930
931 static int
932 nv04_graph_mthd_bind_chroma(struct nouveau_channel *chan,
933 u32 class, u32 mthd, u32 data)
934 {
935 switch (nv_ri32(chan->dev, data << 4) & 0xff) {
936 case 0x30:
937 nv04_graph_set_ctx1(chan, 0x1000, 0);
938 return 0;
939 /* Yes, for some reason even the old versions of objects
940 * accept 0x57 and not 0x17. Consistency be damned.
941 */
942 case 0x57:
943 nv04_graph_set_ctx1(chan, 0x1000, 0x1000);
944 return 0;
945 }
946 return 1;
947 }
948
949 static struct nouveau_bitfield nv04_graph_intr[] = {
950 { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
951 {}
952 };
953
954 static struct nouveau_bitfield nv04_graph_nstatus[] = {
955 { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
956 { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
957 { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
958 { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
959 {}
960 };
961
962 struct nouveau_bitfield nv04_graph_nsource[] = {
963 { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
964 { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
965 { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
966 { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
967 { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
968 { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
969 { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
970 { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
971 { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
972 { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
973 { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
974 { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
975 { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
976 { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
977 { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
978 { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
979 { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
980 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
981 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
982 {}
983 };
984
985 static void
986 nv04_graph_context_switch(struct drm_device *dev)
987 {
988 struct drm_nouveau_private *dev_priv = dev->dev_private;
989 struct nouveau_channel *chan = NULL;
990 int chid;
991
992 nouveau_wait_for_idle(dev);
993
994 /* If previous context is valid, we need to save it */
995 nv04_graph_unload_context(dev);
996
997 /* Load context for next channel */
998 chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
999 NV03_PFIFO_CACHE1_PUSH1_CHID_MASK;
1000 chan = dev_priv->channels.ptr[chid];
1001 if (chan)
1002 nv04_graph_load_context(chan);
1003 }
1004
1005 static void
1006 nv04_graph_isr(struct drm_device *dev)
1007 {
1008 u32 stat;
1009
1010 while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
1011 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
1012 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
1013 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
1014 u32 chid = (addr & 0x0f000000) >> 24;
1015 u32 subc = (addr & 0x0000e000) >> 13;
1016 u32 mthd = (addr & 0x00001ffc);
1017 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
1018 u32 class = nv_rd32(dev, 0x400180 + subc * 4) & 0xff;
1019 u32 show = stat;
1020
1021 if (stat & NV_PGRAPH_INTR_NOTIFY) {
1022 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
1023 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
1024 show &= ~NV_PGRAPH_INTR_NOTIFY;
1025 }
1026 }
1027
1028 if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
1029 nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
1030 stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1031 show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1032 nv04_graph_context_switch(dev);
1033 }
1034
1035 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
1036 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
1037
1038 if (show && nouveau_ratelimit()) {
1039 NV_INFO(dev, "PGRAPH -");
1040 nouveau_bitfield_print(nv04_graph_intr, show);
1041 printk(" nsource:");
1042 nouveau_bitfield_print(nv04_graph_nsource, nsource);
1043 printk(" nstatus:");
1044 nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
1045 printk("\n");
1046 NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
1047 "mthd 0x%04x data 0x%08x\n",
1048 chid, subc, class, mthd, data);
1049 }
1050 }
1051 }
1052
1053 static void
1054 nv04_graph_destroy(struct drm_device *dev, int engine)
1055 {
1056 struct nv04_graph_engine *pgraph = nv_engine(dev, engine);
1057
1058 nouveau_irq_unregister(dev, 12);
1059
1060 NVOBJ_ENGINE_DEL(dev, GR);
1061 kfree(pgraph);
1062 }
1063
1064 int
1065 nv04_graph_create(struct drm_device *dev)
1066 {
1067 struct nv04_graph_engine *pgraph;
1068
1069 pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
1070 if (!pgraph)
1071 return -ENOMEM;
1072
1073 pgraph->base.destroy = nv04_graph_destroy;
1074 pgraph->base.init = nv04_graph_init;
1075 pgraph->base.fini = nv04_graph_fini;
1076 pgraph->base.context_new = nv04_graph_context_new;
1077 pgraph->base.context_del = nv04_graph_context_del;
1078 pgraph->base.object_new = nv04_graph_object_new;
1079
1080 NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
1081 nouveau_irq_register(dev, 12, nv04_graph_isr);
1082
1083 /* dvd subpicture */
1084 NVOBJ_CLASS(dev, 0x0038, GR);
1085
1086 /* m2mf */
1087 NVOBJ_CLASS(dev, 0x0039, GR);
1088
1089 /* nv03 gdirect */
1090 NVOBJ_CLASS(dev, 0x004b, GR);
1091 NVOBJ_MTHD (dev, 0x004b, 0x0184, nv04_graph_mthd_bind_nv01_patt);
1092 NVOBJ_MTHD (dev, 0x004b, 0x0188, nv04_graph_mthd_bind_rop);
1093 NVOBJ_MTHD (dev, 0x004b, 0x018c, nv04_graph_mthd_bind_beta1);
1094 NVOBJ_MTHD (dev, 0x004b, 0x0190, nv04_graph_mthd_bind_surf_dst);
1095 NVOBJ_MTHD (dev, 0x004b, 0x02fc, nv04_graph_mthd_set_operation);
1096
1097 /* nv04 gdirect */
1098 NVOBJ_CLASS(dev, 0x004a, GR);
1099 NVOBJ_MTHD (dev, 0x004a, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1100 NVOBJ_MTHD (dev, 0x004a, 0x018c, nv04_graph_mthd_bind_rop);
1101 NVOBJ_MTHD (dev, 0x004a, 0x0190, nv04_graph_mthd_bind_beta1);
1102 NVOBJ_MTHD (dev, 0x004a, 0x0194, nv04_graph_mthd_bind_beta4);
1103 NVOBJ_MTHD (dev, 0x004a, 0x0198, nv04_graph_mthd_bind_surf2d);
1104 NVOBJ_MTHD (dev, 0x004a, 0x02fc, nv04_graph_mthd_set_operation);
1105
1106 /* nv01 imageblit */
1107 NVOBJ_CLASS(dev, 0x001f, GR);
1108 NVOBJ_MTHD (dev, 0x001f, 0x0184, nv04_graph_mthd_bind_chroma);
1109 NVOBJ_MTHD (dev, 0x001f, 0x0188, nv04_graph_mthd_bind_clip);
1110 NVOBJ_MTHD (dev, 0x001f, 0x018c, nv04_graph_mthd_bind_nv01_patt);
1111 NVOBJ_MTHD (dev, 0x001f, 0x0190, nv04_graph_mthd_bind_rop);
1112 NVOBJ_MTHD (dev, 0x001f, 0x0194, nv04_graph_mthd_bind_beta1);
1113 NVOBJ_MTHD (dev, 0x001f, 0x0198, nv04_graph_mthd_bind_surf_dst);
1114 NVOBJ_MTHD (dev, 0x001f, 0x019c, nv04_graph_mthd_bind_surf_src);
1115 NVOBJ_MTHD (dev, 0x001f, 0x02fc, nv04_graph_mthd_set_operation);
1116
1117 /* nv04 imageblit */
1118 NVOBJ_CLASS(dev, 0x005f, GR);
1119 NVOBJ_MTHD (dev, 0x005f, 0x0184, nv04_graph_mthd_bind_chroma);
1120 NVOBJ_MTHD (dev, 0x005f, 0x0188, nv04_graph_mthd_bind_clip);
1121 NVOBJ_MTHD (dev, 0x005f, 0x018c, nv04_graph_mthd_bind_nv04_patt);
1122 NVOBJ_MTHD (dev, 0x005f, 0x0190, nv04_graph_mthd_bind_rop);
1123 NVOBJ_MTHD (dev, 0x005f, 0x0194, nv04_graph_mthd_bind_beta1);
1124 NVOBJ_MTHD (dev, 0x005f, 0x0198, nv04_graph_mthd_bind_beta4);
1125 NVOBJ_MTHD (dev, 0x005f, 0x019c, nv04_graph_mthd_bind_surf2d);
1126 NVOBJ_MTHD (dev, 0x005f, 0x02fc, nv04_graph_mthd_set_operation);
1127
1128 /* nv04 iifc */
1129 NVOBJ_CLASS(dev, 0x0060, GR);
1130 NVOBJ_MTHD (dev, 0x0060, 0x0188, nv04_graph_mthd_bind_chroma);
1131 NVOBJ_MTHD (dev, 0x0060, 0x018c, nv04_graph_mthd_bind_clip);
1132 NVOBJ_MTHD (dev, 0x0060, 0x0190, nv04_graph_mthd_bind_nv04_patt);
1133 NVOBJ_MTHD (dev, 0x0060, 0x0194, nv04_graph_mthd_bind_rop);
1134 NVOBJ_MTHD (dev, 0x0060, 0x0198, nv04_graph_mthd_bind_beta1);
1135 NVOBJ_MTHD (dev, 0x0060, 0x019c, nv04_graph_mthd_bind_beta4);
1136 NVOBJ_MTHD (dev, 0x0060, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf);
1137 NVOBJ_MTHD (dev, 0x0060, 0x03e4, nv04_graph_mthd_set_operation);
1138
1139 /* nv05 iifc */
1140 NVOBJ_CLASS(dev, 0x0064, GR);
1141
1142 /* nv01 ifc */
1143 NVOBJ_CLASS(dev, 0x0021, GR);
1144 NVOBJ_MTHD (dev, 0x0021, 0x0184, nv04_graph_mthd_bind_chroma);
1145 NVOBJ_MTHD (dev, 0x0021, 0x0188, nv04_graph_mthd_bind_clip);
1146 NVOBJ_MTHD (dev, 0x0021, 0x018c, nv04_graph_mthd_bind_nv01_patt);
1147 NVOBJ_MTHD (dev, 0x0021, 0x0190, nv04_graph_mthd_bind_rop);
1148 NVOBJ_MTHD (dev, 0x0021, 0x0194, nv04_graph_mthd_bind_beta1);
1149 NVOBJ_MTHD (dev, 0x0021, 0x0198, nv04_graph_mthd_bind_surf_dst);
1150 NVOBJ_MTHD (dev, 0x0021, 0x02fc, nv04_graph_mthd_set_operation);
1151
1152 /* nv04 ifc */
1153 NVOBJ_CLASS(dev, 0x0061, GR);
1154 NVOBJ_MTHD (dev, 0x0061, 0x0184, nv04_graph_mthd_bind_chroma);
1155 NVOBJ_MTHD (dev, 0x0061, 0x0188, nv04_graph_mthd_bind_clip);
1156 NVOBJ_MTHD (dev, 0x0061, 0x018c, nv04_graph_mthd_bind_nv04_patt);
1157 NVOBJ_MTHD (dev, 0x0061, 0x0190, nv04_graph_mthd_bind_rop);
1158 NVOBJ_MTHD (dev, 0x0061, 0x0194, nv04_graph_mthd_bind_beta1);
1159 NVOBJ_MTHD (dev, 0x0061, 0x0198, nv04_graph_mthd_bind_beta4);
1160 NVOBJ_MTHD (dev, 0x0061, 0x019c, nv04_graph_mthd_bind_surf2d);
1161 NVOBJ_MTHD (dev, 0x0061, 0x02fc, nv04_graph_mthd_set_operation);
1162
1163 /* nv05 ifc */
1164 NVOBJ_CLASS(dev, 0x0065, GR);
1165
1166 /* nv03 sifc */
1167 NVOBJ_CLASS(dev, 0x0036, GR);
1168 NVOBJ_MTHD (dev, 0x0036, 0x0184, nv04_graph_mthd_bind_chroma);
1169 NVOBJ_MTHD (dev, 0x0036, 0x0188, nv04_graph_mthd_bind_nv01_patt);
1170 NVOBJ_MTHD (dev, 0x0036, 0x018c, nv04_graph_mthd_bind_rop);
1171 NVOBJ_MTHD (dev, 0x0036, 0x0190, nv04_graph_mthd_bind_beta1);
1172 NVOBJ_MTHD (dev, 0x0036, 0x0194, nv04_graph_mthd_bind_surf_dst);
1173 NVOBJ_MTHD (dev, 0x0036, 0x02fc, nv04_graph_mthd_set_operation);
1174
1175 /* nv04 sifc */
1176 NVOBJ_CLASS(dev, 0x0076, GR);
1177 NVOBJ_MTHD (dev, 0x0076, 0x0184, nv04_graph_mthd_bind_chroma);
1178 NVOBJ_MTHD (dev, 0x0076, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1179 NVOBJ_MTHD (dev, 0x0076, 0x018c, nv04_graph_mthd_bind_rop);
1180 NVOBJ_MTHD (dev, 0x0076, 0x0190, nv04_graph_mthd_bind_beta1);
1181 NVOBJ_MTHD (dev, 0x0076, 0x0194, nv04_graph_mthd_bind_beta4);
1182 NVOBJ_MTHD (dev, 0x0076, 0x0198, nv04_graph_mthd_bind_surf2d);
1183 NVOBJ_MTHD (dev, 0x0076, 0x02fc, nv04_graph_mthd_set_operation);
1184
1185 /* nv05 sifc */
1186 NVOBJ_CLASS(dev, 0x0066, GR);
1187
1188 /* nv03 sifm */
1189 NVOBJ_CLASS(dev, 0x0037, GR);
1190 NVOBJ_MTHD (dev, 0x0037, 0x0188, nv04_graph_mthd_bind_nv01_patt);
1191 NVOBJ_MTHD (dev, 0x0037, 0x018c, nv04_graph_mthd_bind_rop);
1192 NVOBJ_MTHD (dev, 0x0037, 0x0190, nv04_graph_mthd_bind_beta1);
1193 NVOBJ_MTHD (dev, 0x0037, 0x0194, nv04_graph_mthd_bind_surf_dst);
1194 NVOBJ_MTHD (dev, 0x0037, 0x0304, nv04_graph_mthd_set_operation);
1195
1196 /* nv04 sifm */
1197 NVOBJ_CLASS(dev, 0x0077, GR);
1198 NVOBJ_MTHD (dev, 0x0077, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1199 NVOBJ_MTHD (dev, 0x0077, 0x018c, nv04_graph_mthd_bind_rop);
1200 NVOBJ_MTHD (dev, 0x0077, 0x0190, nv04_graph_mthd_bind_beta1);
1201 NVOBJ_MTHD (dev, 0x0077, 0x0194, nv04_graph_mthd_bind_beta4);
1202 NVOBJ_MTHD (dev, 0x0077, 0x0198, nv04_graph_mthd_bind_surf2d_swzsurf);
1203 NVOBJ_MTHD (dev, 0x0077, 0x0304, nv04_graph_mthd_set_operation);
1204
1205 /* null */
1206 NVOBJ_CLASS(dev, 0x0030, GR);
1207
1208 /* surf2d */
1209 NVOBJ_CLASS(dev, 0x0042, GR);
1210
1211 /* rop */
1212 NVOBJ_CLASS(dev, 0x0043, GR);
1213
1214 /* beta1 */
1215 NVOBJ_CLASS(dev, 0x0012, GR);
1216
1217 /* beta4 */
1218 NVOBJ_CLASS(dev, 0x0072, GR);
1219
1220 /* cliprect */
1221 NVOBJ_CLASS(dev, 0x0019, GR);
1222
1223 /* nv01 pattern */
1224 NVOBJ_CLASS(dev, 0x0018, GR);
1225
1226 /* nv04 pattern */
1227 NVOBJ_CLASS(dev, 0x0044, GR);
1228
1229 /* swzsurf */
1230 NVOBJ_CLASS(dev, 0x0052, GR);
1231
1232 /* surf3d */
1233 NVOBJ_CLASS(dev, 0x0053, GR);
1234 NVOBJ_MTHD (dev, 0x0053, 0x02f8, nv04_graph_mthd_surf3d_clip_h);
1235 NVOBJ_MTHD (dev, 0x0053, 0x02fc, nv04_graph_mthd_surf3d_clip_v);
1236
1237 /* nv03 tex_tri */
1238 NVOBJ_CLASS(dev, 0x0048, GR);
1239 NVOBJ_MTHD (dev, 0x0048, 0x0188, nv04_graph_mthd_bind_clip);
1240 NVOBJ_MTHD (dev, 0x0048, 0x018c, nv04_graph_mthd_bind_surf_color);
1241 NVOBJ_MTHD (dev, 0x0048, 0x0190, nv04_graph_mthd_bind_surf_zeta);
1242
1243 /* tex_tri */
1244 NVOBJ_CLASS(dev, 0x0054, GR);
1245
1246 /* multitex_tri */
1247 NVOBJ_CLASS(dev, 0x0055, GR);
1248
1249 /* nv01 chroma */
1250 NVOBJ_CLASS(dev, 0x0017, GR);
1251
1252 /* nv04 chroma */
1253 NVOBJ_CLASS(dev, 0x0057, GR);
1254
1255 /* surf_dst */
1256 NVOBJ_CLASS(dev, 0x0058, GR);
1257
1258 /* surf_src */
1259 NVOBJ_CLASS(dev, 0x0059, GR);
1260
1261 /* surf_color */
1262 NVOBJ_CLASS(dev, 0x005a, GR);
1263
1264 /* surf_zeta */
1265 NVOBJ_CLASS(dev, 0x005b, GR);
1266
1267 /* nv01 line */
1268 NVOBJ_CLASS(dev, 0x001c, GR);
1269 NVOBJ_MTHD (dev, 0x001c, 0x0184, nv04_graph_mthd_bind_clip);
1270 NVOBJ_MTHD (dev, 0x001c, 0x0188, nv04_graph_mthd_bind_nv01_patt);
1271 NVOBJ_MTHD (dev, 0x001c, 0x018c, nv04_graph_mthd_bind_rop);
1272 NVOBJ_MTHD (dev, 0x001c, 0x0190, nv04_graph_mthd_bind_beta1);
1273 NVOBJ_MTHD (dev, 0x001c, 0x0194, nv04_graph_mthd_bind_surf_dst);
1274 NVOBJ_MTHD (dev, 0x001c, 0x02fc, nv04_graph_mthd_set_operation);
1275
1276 /* nv04 line */
1277 NVOBJ_CLASS(dev, 0x005c, GR);
1278 NVOBJ_MTHD (dev, 0x005c, 0x0184, nv04_graph_mthd_bind_clip);
1279 NVOBJ_MTHD (dev, 0x005c, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1280 NVOBJ_MTHD (dev, 0x005c, 0x018c, nv04_graph_mthd_bind_rop);
1281 NVOBJ_MTHD (dev, 0x005c, 0x0190, nv04_graph_mthd_bind_beta1);
1282 NVOBJ_MTHD (dev, 0x005c, 0x0194, nv04_graph_mthd_bind_beta4);
1283 NVOBJ_MTHD (dev, 0x005c, 0x0198, nv04_graph_mthd_bind_surf2d);
1284 NVOBJ_MTHD (dev, 0x005c, 0x02fc, nv04_graph_mthd_set_operation);
1285
1286 /* nv01 tri */
1287 NVOBJ_CLASS(dev, 0x001d, GR);
1288 NVOBJ_MTHD (dev, 0x001d, 0x0184, nv04_graph_mthd_bind_clip);
1289 NVOBJ_MTHD (dev, 0x001d, 0x0188, nv04_graph_mthd_bind_nv01_patt);
1290 NVOBJ_MTHD (dev, 0x001d, 0x018c, nv04_graph_mthd_bind_rop);
1291 NVOBJ_MTHD (dev, 0x001d, 0x0190, nv04_graph_mthd_bind_beta1);
1292 NVOBJ_MTHD (dev, 0x001d, 0x0194, nv04_graph_mthd_bind_surf_dst);
1293 NVOBJ_MTHD (dev, 0x001d, 0x02fc, nv04_graph_mthd_set_operation);
1294
1295 /* nv04 tri */
1296 NVOBJ_CLASS(dev, 0x005d, GR);
1297 NVOBJ_MTHD (dev, 0x005d, 0x0184, nv04_graph_mthd_bind_clip);
1298 NVOBJ_MTHD (dev, 0x005d, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1299 NVOBJ_MTHD (dev, 0x005d, 0x018c, nv04_graph_mthd_bind_rop);
1300 NVOBJ_MTHD (dev, 0x005d, 0x0190, nv04_graph_mthd_bind_beta1);
1301 NVOBJ_MTHD (dev, 0x005d, 0x0194, nv04_graph_mthd_bind_beta4);
1302 NVOBJ_MTHD (dev, 0x005d, 0x0198, nv04_graph_mthd_bind_surf2d);
1303 NVOBJ_MTHD (dev, 0x005d, 0x02fc, nv04_graph_mthd_set_operation);
1304
1305 /* nv01 rect */
1306 NVOBJ_CLASS(dev, 0x001e, GR);
1307 NVOBJ_MTHD (dev, 0x001e, 0x0184, nv04_graph_mthd_bind_clip);
1308 NVOBJ_MTHD (dev, 0x001e, 0x0188, nv04_graph_mthd_bind_nv01_patt);
1309 NVOBJ_MTHD (dev, 0x001e, 0x018c, nv04_graph_mthd_bind_rop);
1310 NVOBJ_MTHD (dev, 0x001e, 0x0190, nv04_graph_mthd_bind_beta1);
1311 NVOBJ_MTHD (dev, 0x001e, 0x0194, nv04_graph_mthd_bind_surf_dst);
1312 NVOBJ_MTHD (dev, 0x001e, 0x02fc, nv04_graph_mthd_set_operation);
1313
1314 /* nv04 rect */
1315 NVOBJ_CLASS(dev, 0x005e, GR);
1316 NVOBJ_MTHD (dev, 0x005e, 0x0184, nv04_graph_mthd_bind_clip);
1317 NVOBJ_MTHD (dev, 0x005e, 0x0188, nv04_graph_mthd_bind_nv04_patt);
1318 NVOBJ_MTHD (dev, 0x005e, 0x018c, nv04_graph_mthd_bind_rop);
1319 NVOBJ_MTHD (dev, 0x005e, 0x0190, nv04_graph_mthd_bind_beta1);
1320 NVOBJ_MTHD (dev, 0x005e, 0x0194, nv04_graph_mthd_bind_beta4);
1321 NVOBJ_MTHD (dev, 0x005e, 0x0198, nv04_graph_mthd_bind_surf2d);
1322 NVOBJ_MTHD (dev, 0x005e, 0x02fc, nv04_graph_mthd_set_operation);
1323
1324 return 0;
1325 }
kernel source for telekom puls (alcatel/mediatek)