2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
27 #include "drm_crtc_helper.h"
29 #include "nouveau_drv.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_connector.h"
32 #include "nouveau_crtc.h"
33 #include "nouveau_fb.h"
34 #include "nouveau_hw.h"
36 #include "nouveau_fbcon.h"
39 nv04_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
40 struct drm_framebuffer
*old_fb
);
43 crtc_wr_cio_state(struct drm_crtc
*crtc
, struct nv04_crtc_reg
*crtcstate
, int index
)
45 NVWriteVgaCrtc(crtc
->dev
, nouveau_crtc(crtc
)->index
, index
,
46 crtcstate
->CRTC
[index
]);
49 static void nv_crtc_set_digital_vibrance(struct drm_crtc
*crtc
, int level
)
51 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
52 struct drm_nouveau_private
*dev_priv
= crtc
->dev
->dev_private
;
53 struct nv04_crtc_reg
*regp
= &dev_priv
->mode_reg
.crtc_reg
[nv_crtc
->index
];
55 regp
->CRTC
[NV_CIO_CRE_CSB
] = nv_crtc
->saturation
= level
;
56 if (nv_crtc
->saturation
&& nv_gf4_disp_arch(crtc
->dev
)) {
57 regp
->CRTC
[NV_CIO_CRE_CSB
] = 0x80;
58 regp
->CRTC
[NV_CIO_CRE_5B
] = nv_crtc
->saturation
<< 2;
59 crtc_wr_cio_state(crtc
, regp
, NV_CIO_CRE_5B
);
61 crtc_wr_cio_state(crtc
, regp
, NV_CIO_CRE_CSB
);
64 static void nv_crtc_set_image_sharpening(struct drm_crtc
*crtc
, int level
)
66 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
67 struct drm_nouveau_private
*dev_priv
= crtc
->dev
->dev_private
;
68 struct nv04_crtc_reg
*regp
= &dev_priv
->mode_reg
.crtc_reg
[nv_crtc
->index
];
70 nv_crtc
->sharpness
= level
;
71 if (level
< 0) /* blur is in hw range 0x3f -> 0x20 */
73 regp
->ramdac_634
= level
;
74 NVWriteRAMDAC(crtc
->dev
, nv_crtc
->index
, NV_PRAMDAC_634
, regp
->ramdac_634
);
77 #define PLLSEL_VPLL1_MASK \
78 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
79 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
80 #define PLLSEL_VPLL2_MASK \
81 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
82 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
83 #define PLLSEL_TV_MASK \
84 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
85 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
86 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
87 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
89 /* NV4x 0x40.. pll notes:
90 * gpu pll: 0x4000 + 0x4004
91 * ?gpu? pll: 0x4008 + 0x400c
92 * vpll1: 0x4010 + 0x4014
93 * vpll2: 0x4018 + 0x401c
94 * mpll: 0x4020 + 0x4024
95 * mpll: 0x4038 + 0x403c
97 * the first register of each pair has some unknown details:
98 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
99 * bits 20-23: (mpll) something to do with post divider?
100 * bits 28-31: related to single stage mode? (bit 8/12)
103 static void nv_crtc_calc_state_ext(struct drm_crtc
*crtc
, struct drm_display_mode
* mode
, int dot_clock
)
105 struct drm_device
*dev
= crtc
->dev
;
106 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
107 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
108 struct nv04_mode_state
*state
= &dev_priv
->mode_reg
;
109 struct nv04_crtc_reg
*regp
= &state
->crtc_reg
[nv_crtc
->index
];
110 struct nouveau_pll_vals
*pv
= ®p
->pllvals
;
111 struct pll_lims pll_lim
;
113 if (get_pll_limits(dev
, nv_crtc
->index
? VPLL2
: VPLL1
, &pll_lim
))
116 /* NM2 == 0 is used to determine single stage mode on two stage plls */
119 /* for newer nv4x the blob uses only the first stage of the vpll below a
120 * certain clock. for a certain nv4b this is 150MHz. since the max
121 * output frequency of the first stage for this card is 300MHz, it is
122 * assumed the threshold is given by vco1 maxfreq/2
124 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
125 * not 8, others unknown), the blob always uses both plls. no problem
126 * has yet been observed in allowing the use a single stage pll on all
127 * nv43 however. the behaviour of single stage use is untested on nv40
129 if (dev_priv
->chipset
> 0x40 && dot_clock
<= (pll_lim
.vco1
.maxfreq
/ 2))
130 memset(&pll_lim
.vco2
, 0, sizeof(pll_lim
.vco2
));
132 if (!nouveau_calc_pll_mnp(dev
, &pll_lim
, dot_clock
, pv
))
135 state
->pllsel
&= PLLSEL_VPLL1_MASK
| PLLSEL_VPLL2_MASK
| PLLSEL_TV_MASK
;
137 /* The blob uses this always, so let's do the same */
138 if (dev_priv
->card_type
== NV_40
)
139 state
->pllsel
|= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE
;
140 /* again nv40 and some nv43 act more like nv3x as described above */
141 if (dev_priv
->chipset
< 0x41)
142 state
->pllsel
|= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL
|
143 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL
;
144 state
->pllsel
|= nv_crtc
->index
? PLLSEL_VPLL2_MASK
: PLLSEL_VPLL1_MASK
;
147 NV_DEBUG_KMS(dev
, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
148 pv
->N1
, pv
->N2
, pv
->M1
, pv
->M2
, pv
->log2P
);
150 NV_DEBUG_KMS(dev
, "vpll: n %d m %d log2p %d\n",
151 pv
->N1
, pv
->M1
, pv
->log2P
);
153 nv_crtc
->cursor
.set_offset(nv_crtc
, nv_crtc
->cursor
.offset
);
157 nv_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
159 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
160 struct drm_device
*dev
= crtc
->dev
;
161 struct drm_connector
*connector
;
162 unsigned char seq1
= 0, crtc17
= 0;
163 unsigned char crtc1A
;
165 NV_DEBUG_KMS(dev
, "Setting dpms mode %d on CRTC %d\n", mode
,
168 if (nv_crtc
->last_dpms
== mode
) /* Don't do unnecesary mode changes. */
171 nv_crtc
->last_dpms
= mode
;
173 if (nv_two_heads(dev
))
174 NVSetOwner(dev
, nv_crtc
->index
);
176 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */
177 crtc1A
= NVReadVgaCrtc(dev
, nv_crtc
->index
,
178 NV_CIO_CRE_RPC1_INDEX
) & ~0xC0;
180 case DRM_MODE_DPMS_STANDBY
:
181 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
186 case DRM_MODE_DPMS_SUSPEND
:
187 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
192 case DRM_MODE_DPMS_OFF
:
193 /* Screen: Off; HSync: Off, VSync: Off */
198 case DRM_MODE_DPMS_ON
:
200 /* Screen: On; HSync: On, VSync: On */
206 NVVgaSeqReset(dev
, nv_crtc
->index
, true);
207 /* Each head has it's own sequencer, so we can turn it off when we want */
208 seq1
|= (NVReadVgaSeq(dev
, nv_crtc
->index
, NV_VIO_SR_CLOCK_INDEX
) & ~0x20);
209 NVWriteVgaSeq(dev
, nv_crtc
->index
, NV_VIO_SR_CLOCK_INDEX
, seq1
);
210 crtc17
|= (NVReadVgaCrtc(dev
, nv_crtc
->index
, NV_CIO_CR_MODE_INDEX
) & ~0x80);
212 NVWriteVgaCrtc(dev
, nv_crtc
->index
, NV_CIO_CR_MODE_INDEX
, crtc17
);
213 NVVgaSeqReset(dev
, nv_crtc
->index
, false);
215 NVWriteVgaCrtc(dev
, nv_crtc
->index
, NV_CIO_CRE_RPC1_INDEX
, crtc1A
);
217 /* Update connector polling modes */
218 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
)
219 nouveau_connector_set_polling(connector
);
223 nv_crtc_mode_fixup(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
224 struct drm_display_mode
*adjusted_mode
)
230 nv_crtc_mode_set_vga(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
)
232 struct drm_device
*dev
= crtc
->dev
;
233 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
234 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
235 struct nv04_crtc_reg
*regp
= &dev_priv
->mode_reg
.crtc_reg
[nv_crtc
->index
];
236 struct drm_framebuffer
*fb
= crtc
->fb
;
238 /* Calculate our timings */
239 int horizDisplay
= (mode
->crtc_hdisplay
>> 3) - 1;
240 int horizStart
= (mode
->crtc_hsync_start
>> 3) + 1;
241 int horizEnd
= (mode
->crtc_hsync_end
>> 3) + 1;
242 int horizTotal
= (mode
->crtc_htotal
>> 3) - 5;
243 int horizBlankStart
= (mode
->crtc_hdisplay
>> 3) - 1;
244 int horizBlankEnd
= (mode
->crtc_htotal
>> 3) - 1;
245 int vertDisplay
= mode
->crtc_vdisplay
- 1;
246 int vertStart
= mode
->crtc_vsync_start
- 1;
247 int vertEnd
= mode
->crtc_vsync_end
- 1;
248 int vertTotal
= mode
->crtc_vtotal
- 2;
249 int vertBlankStart
= mode
->crtc_vdisplay
- 1;
250 int vertBlankEnd
= mode
->crtc_vtotal
- 1;
252 struct drm_encoder
*encoder
;
253 bool fp_output
= false;
255 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
256 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
258 if (encoder
->crtc
== crtc
&&
259 (nv_encoder
->dcb
->type
== OUTPUT_LVDS
||
260 nv_encoder
->dcb
->type
== OUTPUT_TMDS
))
265 vertStart
= vertTotal
- 3;
266 vertEnd
= vertTotal
- 2;
267 vertBlankStart
= vertStart
;
268 horizStart
= horizTotal
- 5;
269 horizEnd
= horizTotal
- 2;
270 horizBlankEnd
= horizTotal
+ 4;
272 if (dev
->overlayAdaptor
&& dev_priv
->card_type
>= NV_10
)
273 /* This reportedly works around some video overlay bandwidth problems */
278 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
282 ErrorF("horizDisplay: 0x%X \n", horizDisplay
);
283 ErrorF("horizStart: 0x%X \n", horizStart
);
284 ErrorF("horizEnd: 0x%X \n", horizEnd
);
285 ErrorF("horizTotal: 0x%X \n", horizTotal
);
286 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart
);
287 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd
);
288 ErrorF("vertDisplay: 0x%X \n", vertDisplay
);
289 ErrorF("vertStart: 0x%X \n", vertStart
);
290 ErrorF("vertEnd: 0x%X \n", vertEnd
);
291 ErrorF("vertTotal: 0x%X \n", vertTotal
);
292 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart
);
293 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd
);
297 * compute correct Hsync & Vsync polarity
299 if ((mode
->flags
& (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
))
300 && (mode
->flags
& (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
))) {
302 regp
->MiscOutReg
= 0x23;
303 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
304 regp
->MiscOutReg
|= 0x40;
305 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
306 regp
->MiscOutReg
|= 0x80;
308 int vdisplay
= mode
->vdisplay
;
309 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
312 vdisplay
*= mode
->vscan
;
314 regp
->MiscOutReg
= 0xA3; /* +hsync -vsync */
315 else if (vdisplay
< 480)
316 regp
->MiscOutReg
= 0x63; /* -hsync +vsync */
317 else if (vdisplay
< 768)
318 regp
->MiscOutReg
= 0xE3; /* -hsync -vsync */
320 regp
->MiscOutReg
= 0x23; /* +hsync +vsync */
323 regp
->MiscOutReg
|= (mode
->clock_index
& 0x03) << 2;
328 regp
->Sequencer
[NV_VIO_SR_RESET_INDEX
] = 0x00;
329 /* 0x20 disables the sequencer */
330 if (mode
->flags
& DRM_MODE_FLAG_CLKDIV2
)
331 regp
->Sequencer
[NV_VIO_SR_CLOCK_INDEX
] = 0x29;
333 regp
->Sequencer
[NV_VIO_SR_CLOCK_INDEX
] = 0x21;
334 regp
->Sequencer
[NV_VIO_SR_PLANE_MASK_INDEX
] = 0x0F;
335 regp
->Sequencer
[NV_VIO_SR_CHAR_MAP_INDEX
] = 0x00;
336 regp
->Sequencer
[NV_VIO_SR_MEM_MODE_INDEX
] = 0x0E;
341 regp
->CRTC
[NV_CIO_CR_HDT_INDEX
] = horizTotal
;
342 regp
->CRTC
[NV_CIO_CR_HDE_INDEX
] = horizDisplay
;
343 regp
->CRTC
[NV_CIO_CR_HBS_INDEX
] = horizBlankStart
;
344 regp
->CRTC
[NV_CIO_CR_HBE_INDEX
] = (1 << 7) |
345 XLATE(horizBlankEnd
, 0, NV_CIO_CR_HBE_4_0
);
346 regp
->CRTC
[NV_CIO_CR_HRS_INDEX
] = horizStart
;
347 regp
->CRTC
[NV_CIO_CR_HRE_INDEX
] = XLATE(horizBlankEnd
, 5, NV_CIO_CR_HRE_HBE_5
) |
348 XLATE(horizEnd
, 0, NV_CIO_CR_HRE_4_0
);
349 regp
->CRTC
[NV_CIO_CR_VDT_INDEX
] = vertTotal
;
350 regp
->CRTC
[NV_CIO_CR_OVL_INDEX
] = XLATE(vertStart
, 9, NV_CIO_CR_OVL_VRS_9
) |
351 XLATE(vertDisplay
, 9, NV_CIO_CR_OVL_VDE_9
) |
352 XLATE(vertTotal
, 9, NV_CIO_CR_OVL_VDT_9
) |
354 XLATE(vertBlankStart
, 8, NV_CIO_CR_OVL_VBS_8
) |
355 XLATE(vertStart
, 8, NV_CIO_CR_OVL_VRS_8
) |
356 XLATE(vertDisplay
, 8, NV_CIO_CR_OVL_VDE_8
) |
357 XLATE(vertTotal
, 8, NV_CIO_CR_OVL_VDT_8
);
358 regp
->CRTC
[NV_CIO_CR_RSAL_INDEX
] = 0x00;
359 regp
->CRTC
[NV_CIO_CR_CELL_HT_INDEX
] = ((mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL
) : 0) |
361 XLATE(vertBlankStart
, 9, NV_CIO_CR_CELL_HT_VBS_9
);
362 regp
->CRTC
[NV_CIO_CR_CURS_ST_INDEX
] = 0x00;
363 regp
->CRTC
[NV_CIO_CR_CURS_END_INDEX
] = 0x00;
364 regp
->CRTC
[NV_CIO_CR_SA_HI_INDEX
] = 0x00;
365 regp
->CRTC
[NV_CIO_CR_SA_LO_INDEX
] = 0x00;
366 regp
->CRTC
[NV_CIO_CR_TCOFF_HI_INDEX
] = 0x00;
367 regp
->CRTC
[NV_CIO_CR_TCOFF_LO_INDEX
] = 0x00;
368 regp
->CRTC
[NV_CIO_CR_VRS_INDEX
] = vertStart
;
369 regp
->CRTC
[NV_CIO_CR_VRE_INDEX
] = 1 << 5 | XLATE(vertEnd
, 0, NV_CIO_CR_VRE_3_0
);
370 regp
->CRTC
[NV_CIO_CR_VDE_INDEX
] = vertDisplay
;
371 /* framebuffer can be larger than crtc scanout area. */
372 regp
->CRTC
[NV_CIO_CR_OFFSET_INDEX
] = fb
->pitch
/ 8;
373 regp
->CRTC
[NV_CIO_CR_ULINE_INDEX
] = 0x00;
374 regp
->CRTC
[NV_CIO_CR_VBS_INDEX
] = vertBlankStart
;
375 regp
->CRTC
[NV_CIO_CR_VBE_INDEX
] = vertBlankEnd
;
376 regp
->CRTC
[NV_CIO_CR_MODE_INDEX
] = 0x43;
377 regp
->CRTC
[NV_CIO_CR_LCOMP_INDEX
] = 0xff;
380 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
383 /* framebuffer can be larger than crtc scanout area. */
384 regp
->CRTC
[NV_CIO_CRE_RPC0_INDEX
] = XLATE(fb
->pitch
/ 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8
);
385 regp
->CRTC
[NV_CIO_CRE_RPC1_INDEX
] = mode
->crtc_hdisplay
< 1280 ?
386 MASK(NV_CIO_CRE_RPC1_LARGE
) : 0x00;
387 regp
->CRTC
[NV_CIO_CRE_LSR_INDEX
] = XLATE(horizBlankEnd
, 6, NV_CIO_CRE_LSR_HBE_6
) |
388 XLATE(vertBlankStart
, 10, NV_CIO_CRE_LSR_VBS_10
) |
389 XLATE(vertStart
, 10, NV_CIO_CRE_LSR_VRS_10
) |
390 XLATE(vertDisplay
, 10, NV_CIO_CRE_LSR_VDE_10
) |
391 XLATE(vertTotal
, 10, NV_CIO_CRE_LSR_VDT_10
);
392 regp
->CRTC
[NV_CIO_CRE_HEB__INDEX
] = XLATE(horizStart
, 8, NV_CIO_CRE_HEB_HRS_8
) |
393 XLATE(horizBlankStart
, 8, NV_CIO_CRE_HEB_HBS_8
) |
394 XLATE(horizDisplay
, 8, NV_CIO_CRE_HEB_HDE_8
) |
395 XLATE(horizTotal
, 8, NV_CIO_CRE_HEB_HDT_8
);
396 regp
->CRTC
[NV_CIO_CRE_EBR_INDEX
] = XLATE(vertBlankStart
, 11, NV_CIO_CRE_EBR_VBS_11
) |
397 XLATE(vertStart
, 11, NV_CIO_CRE_EBR_VRS_11
) |
398 XLATE(vertDisplay
, 11, NV_CIO_CRE_EBR_VDE_11
) |
399 XLATE(vertTotal
, 11, NV_CIO_CRE_EBR_VDT_11
);
401 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
402 horizTotal
= (horizTotal
>> 1) & ~1;
403 regp
->CRTC
[NV_CIO_CRE_ILACE__INDEX
] = horizTotal
;
404 regp
->CRTC
[NV_CIO_CRE_HEB__INDEX
] |= XLATE(horizTotal
, 8, NV_CIO_CRE_HEB_ILC_8
);
406 regp
->CRTC
[NV_CIO_CRE_ILACE__INDEX
] = 0xff; /* interlace off */
409 * Graphics Display Controller
411 regp
->Graphics
[NV_VIO_GX_SR_INDEX
] = 0x00;
412 regp
->Graphics
[NV_VIO_GX_SREN_INDEX
] = 0x00;
413 regp
->Graphics
[NV_VIO_GX_CCOMP_INDEX
] = 0x00;
414 regp
->Graphics
[NV_VIO_GX_ROP_INDEX
] = 0x00;
415 regp
->Graphics
[NV_VIO_GX_READ_MAP_INDEX
] = 0x00;
416 regp
->Graphics
[NV_VIO_GX_MODE_INDEX
] = 0x40; /* 256 color mode */
417 regp
->Graphics
[NV_VIO_GX_MISC_INDEX
] = 0x05; /* map 64k mem + graphic mode */
418 regp
->Graphics
[NV_VIO_GX_DONT_CARE_INDEX
] = 0x0F;
419 regp
->Graphics
[NV_VIO_GX_BIT_MASK_INDEX
] = 0xFF;
421 regp
->Attribute
[0] = 0x00; /* standard colormap translation */
422 regp
->Attribute
[1] = 0x01;
423 regp
->Attribute
[2] = 0x02;
424 regp
->Attribute
[3] = 0x03;
425 regp
->Attribute
[4] = 0x04;
426 regp
->Attribute
[5] = 0x05;
427 regp
->Attribute
[6] = 0x06;
428 regp
->Attribute
[7] = 0x07;
429 regp
->Attribute
[8] = 0x08;
430 regp
->Attribute
[9] = 0x09;
431 regp
->Attribute
[10] = 0x0A;
432 regp
->Attribute
[11] = 0x0B;
433 regp
->Attribute
[12] = 0x0C;
434 regp
->Attribute
[13] = 0x0D;
435 regp
->Attribute
[14] = 0x0E;
436 regp
->Attribute
[15] = 0x0F;
437 regp
->Attribute
[NV_CIO_AR_MODE_INDEX
] = 0x01; /* Enable graphic mode */
439 regp
->Attribute
[NV_CIO_AR_OSCAN_INDEX
] = 0x00;
440 regp
->Attribute
[NV_CIO_AR_PLANE_INDEX
] = 0x0F; /* enable all color planes */
441 regp
->Attribute
[NV_CIO_AR_HPP_INDEX
] = 0x00;
442 regp
->Attribute
[NV_CIO_AR_CSEL_INDEX
] = 0x00;
446 * Sets up registers for the given mode/adjusted_mode pair.
448 * The clocks, CRTCs and outputs attached to this CRTC must be off.
450 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
451 * be easily turned on/off after this.
454 nv_crtc_mode_set_regs(struct drm_crtc
*crtc
, struct drm_display_mode
* mode
)
456 struct drm_device
*dev
= crtc
->dev
;
457 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
458 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
459 struct nv04_crtc_reg
*regp
= &dev_priv
->mode_reg
.crtc_reg
[nv_crtc
->index
];
460 struct nv04_crtc_reg
*savep
= &dev_priv
->saved_reg
.crtc_reg
[nv_crtc
->index
];
461 struct drm_encoder
*encoder
;
462 bool lvds_output
= false, tmds_output
= false, tv_output
= false,
463 off_chip_digital
= false;
465 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
466 struct nouveau_encoder
*nv_encoder
= nouveau_encoder(encoder
);
467 bool digital
= false;
469 if (encoder
->crtc
!= crtc
)
472 if (nv_encoder
->dcb
->type
== OUTPUT_LVDS
)
473 digital
= lvds_output
= true;
474 if (nv_encoder
->dcb
->type
== OUTPUT_TV
)
476 if (nv_encoder
->dcb
->type
== OUTPUT_TMDS
)
477 digital
= tmds_output
= true;
478 if (nv_encoder
->dcb
->location
!= DCB_LOC_ON_CHIP
&& digital
)
479 off_chip_digital
= true;
482 /* Registers not directly related to the (s)vga mode */
484 /* What is the meaning of this register? */
485 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
486 regp
->CRTC
[NV_CIO_CRE_ENH_INDEX
] = savep
->CRTC
[NV_CIO_CRE_ENH_INDEX
] & ~(1<<5);
488 regp
->crtc_eng_ctrl
= 0;
489 /* Except for rare conditions I2C is enabled on the primary crtc */
490 if (nv_crtc
->index
== 0)
491 regp
->crtc_eng_ctrl
|= NV_CRTC_FSEL_I2C
;
493 /* Set overlay to desired crtc. */
494 if (dev
->overlayAdaptor
) {
495 NVPortPrivPtr pPriv
= GET_OVERLAY_PRIVATE(dev
);
496 if (pPriv
->overlayCRTC
== nv_crtc
->index
)
497 regp
->crtc_eng_ctrl
|= NV_CRTC_FSEL_OVERLAY
;
501 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
502 regp
->cursor_cfg
= NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64
|
503 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64
|
504 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM
;
505 if (dev_priv
->chipset
>= 0x11)
506 regp
->cursor_cfg
|= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32
;
507 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
508 regp
->cursor_cfg
|= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE
;
510 /* Unblock some timings */
511 regp
->CRTC
[NV_CIO_CRE_53
] = 0;
512 regp
->CRTC
[NV_CIO_CRE_54
] = 0;
514 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
516 regp
->CRTC
[NV_CIO_CRE_SCRATCH3__INDEX
] = 0x11;
517 else if (tmds_output
)
518 regp
->CRTC
[NV_CIO_CRE_SCRATCH3__INDEX
] = 0x88;
520 regp
->CRTC
[NV_CIO_CRE_SCRATCH3__INDEX
] = 0x22;
522 /* These values seem to vary */
523 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
524 regp
->CRTC
[NV_CIO_CRE_SCRATCH4__INDEX
] = savep
->CRTC
[NV_CIO_CRE_SCRATCH4__INDEX
];
526 nv_crtc_set_digital_vibrance(crtc
, nv_crtc
->saturation
);
528 /* probably a scratch reg, but kept for cargo-cult purposes:
529 * bit0: crtc0?, head A
531 * bit7: (only in X), head A
533 if (nv_crtc
->index
== 0)
534 regp
->CRTC
[NV_CIO_CRE_4B
] = savep
->CRTC
[NV_CIO_CRE_4B
] | 0x80;
536 /* The blob seems to take the current value from crtc 0, add 4 to that
537 * and reuse the old value for crtc 1 */
538 regp
->CRTC
[NV_CIO_CRE_TVOUT_LATENCY
] = dev_priv
->saved_reg
.crtc_reg
[0].CRTC
[NV_CIO_CRE_TVOUT_LATENCY
];
540 regp
->CRTC
[NV_CIO_CRE_TVOUT_LATENCY
] += 4;
542 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
543 * 1 << 30 on 0x60.830), for no apparent reason */
544 regp
->CRTC
[NV_CIO_CRE_59
] = off_chip_digital
;
546 if (dev_priv
->card_type
>= NV_30
)
547 regp
->CRTC
[0x9f] = off_chip_digital
? 0x11 : 0x1;
549 regp
->crtc_830
= mode
->crtc_vdisplay
- 3;
550 regp
->crtc_834
= mode
->crtc_vdisplay
- 1;
552 if (dev_priv
->card_type
== NV_40
)
553 /* This is what the blob does */
554 regp
->crtc_850
= NVReadCRTC(dev
, 0, NV_PCRTC_850
);
556 if (dev_priv
->card_type
>= NV_30
)
557 regp
->gpio_ext
= NVReadCRTC(dev
, 0, NV_PCRTC_GPIO_EXT
);
559 regp
->crtc_cfg
= NV_PCRTC_CONFIG_START_ADDRESS_HSYNC
;
562 if (dev_priv
->card_type
== NV_40
) {
563 regp
->CRTC
[NV_CIO_CRE_85
] = 0xFF;
564 regp
->CRTC
[NV_CIO_CRE_86
] = 0x1;
567 regp
->CRTC
[NV_CIO_CRE_PIXEL_INDEX
] = (crtc
->fb
->depth
+ 1) / 8;
568 /* Enable slaved mode (called MODE_TV in nv4ref.h) */
569 if (lvds_output
|| tmds_output
|| tv_output
)
570 regp
->CRTC
[NV_CIO_CRE_PIXEL_INDEX
] |= (1 << 7);
572 /* Generic PRAMDAC regs */
574 if (dev_priv
->card_type
>= NV_10
)
575 /* Only bit that bios and blob set. */
576 regp
->nv10_cursync
= (1 << 25);
578 regp
->ramdac_gen_ctrl
= NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS
|
579 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL
|
580 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON
;
581 if (crtc
->fb
->depth
== 16)
582 regp
->ramdac_gen_ctrl
|= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL
;
583 if (dev_priv
->chipset
>= 0x11)
584 regp
->ramdac_gen_ctrl
|= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG
;
586 regp
->ramdac_630
= 0; /* turn off green mode (tv test pattern?) */
589 nv_crtc_set_image_sharpening(crtc
, nv_crtc
->sharpness
);
591 /* Some values the blob sets */
592 regp
->ramdac_8c0
= 0x100;
593 regp
->ramdac_a20
= 0x0;
594 regp
->ramdac_a24
= 0xfffff;
595 regp
->ramdac_a34
= 0x1;
599 * Sets up registers for the given mode/adjusted_mode pair.
601 * The clocks, CRTCs and outputs attached to this CRTC must be off.
603 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
604 * be easily turned on/off after this.
607 nv_crtc_mode_set(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
608 struct drm_display_mode
*adjusted_mode
,
609 int x
, int y
, struct drm_framebuffer
*old_fb
)
611 struct drm_device
*dev
= crtc
->dev
;
612 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
613 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
615 NV_DEBUG_KMS(dev
, "CTRC mode on CRTC %d:\n", nv_crtc
->index
);
616 drm_mode_debug_printmodeline(adjusted_mode
);
618 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
619 nv_lock_vga_crtc_shadow(dev
, nv_crtc
->index
, -1);
621 nv_crtc_mode_set_vga(crtc
, adjusted_mode
);
622 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
623 if (dev_priv
->card_type
== NV_40
)
624 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
, dev_priv
->mode_reg
.sel_clk
);
625 nv_crtc_mode_set_regs(crtc
, adjusted_mode
);
626 nv_crtc_calc_state_ext(crtc
, mode
, adjusted_mode
->clock
);
630 static void nv_crtc_save(struct drm_crtc
*crtc
)
632 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
633 struct drm_nouveau_private
*dev_priv
= crtc
->dev
->dev_private
;
634 struct nv04_mode_state
*state
= &dev_priv
->mode_reg
;
635 struct nv04_crtc_reg
*crtc_state
= &state
->crtc_reg
[nv_crtc
->index
];
636 struct nv04_mode_state
*saved
= &dev_priv
->saved_reg
;
637 struct nv04_crtc_reg
*crtc_saved
= &saved
->crtc_reg
[nv_crtc
->index
];
639 if (nv_two_heads(crtc
->dev
))
640 NVSetOwner(crtc
->dev
, nv_crtc
->index
);
642 nouveau_hw_save_state(crtc
->dev
, nv_crtc
->index
, saved
);
644 /* init some state to saved value */
645 state
->sel_clk
= saved
->sel_clk
& ~(0x5 << 16);
646 crtc_state
->CRTC
[NV_CIO_CRE_LCD__INDEX
] = crtc_saved
->CRTC
[NV_CIO_CRE_LCD__INDEX
];
647 state
->pllsel
= saved
->pllsel
& ~(PLLSEL_VPLL1_MASK
| PLLSEL_VPLL2_MASK
| PLLSEL_TV_MASK
);
648 crtc_state
->gpio_ext
= crtc_saved
->gpio_ext
;
651 static void nv_crtc_restore(struct drm_crtc
*crtc
)
653 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
654 struct drm_nouveau_private
*dev_priv
= crtc
->dev
->dev_private
;
655 int head
= nv_crtc
->index
;
656 uint8_t saved_cr21
= dev_priv
->saved_reg
.crtc_reg
[head
].CRTC
[NV_CIO_CRE_21
];
658 if (nv_two_heads(crtc
->dev
))
659 NVSetOwner(crtc
->dev
, head
);
661 nouveau_hw_load_state(crtc
->dev
, head
, &dev_priv
->saved_reg
);
662 nv_lock_vga_crtc_shadow(crtc
->dev
, head
, saved_cr21
);
664 nv_crtc
->last_dpms
= NV_DPMS_CLEARED
;
667 static void nv_crtc_prepare(struct drm_crtc
*crtc
)
669 struct drm_device
*dev
= crtc
->dev
;
670 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
671 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
672 struct drm_crtc_helper_funcs
*funcs
= crtc
->helper_private
;
674 if (nv_two_heads(dev
))
675 NVSetOwner(dev
, nv_crtc
->index
);
677 funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
679 NVBlankScreen(dev
, nv_crtc
->index
, true);
681 /* Some more preperation. */
682 NVWriteCRTC(dev
, nv_crtc
->index
, NV_PCRTC_CONFIG
, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA
);
683 if (dev_priv
->card_type
== NV_40
) {
684 uint32_t reg900
= NVReadRAMDAC(dev
, nv_crtc
->index
, NV_PRAMDAC_900
);
685 NVWriteRAMDAC(dev
, nv_crtc
->index
, NV_PRAMDAC_900
, reg900
& ~0x10000);
689 static void nv_crtc_commit(struct drm_crtc
*crtc
)
691 struct drm_device
*dev
= crtc
->dev
;
692 struct drm_crtc_helper_funcs
*funcs
= crtc
->helper_private
;
693 struct drm_nouveau_private
*dev_priv
= crtc
->dev
->dev_private
;
694 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
696 nouveau_hw_load_state(dev
, nv_crtc
->index
, &dev_priv
->mode_reg
);
697 nv04_crtc_mode_set_base(crtc
, crtc
->x
, crtc
->y
, NULL
);
700 /* turn on LFB swapping */
702 uint8_t tmp
= NVReadVgaCrtc(dev
, nv_crtc
->index
, NV_CIO_CRE_RCR
);
703 tmp
|= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG
);
704 NVWriteVgaCrtc(dev
, nv_crtc
->index
, NV_CIO_CRE_RCR
, tmp
);
708 funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
711 static void nv_crtc_destroy(struct drm_crtc
*crtc
)
713 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
715 NV_DEBUG_KMS(crtc
->dev
, "\n");
720 drm_crtc_cleanup(crtc
);
722 nouveau_bo_ref(NULL
, &nv_crtc
->cursor
.nvbo
);
727 nv_crtc_gamma_load(struct drm_crtc
*crtc
)
729 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
730 struct drm_device
*dev
= nv_crtc
->base
.dev
;
731 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
732 struct rgb
{ uint8_t r
, g
, b
; } __attribute__((packed
)) *rgbs
;
735 rgbs
= (struct rgb
*)dev_priv
->mode_reg
.crtc_reg
[nv_crtc
->index
].DAC
;
736 for (i
= 0; i
< 256; i
++) {
737 rgbs
[i
].r
= nv_crtc
->lut
.r
[i
] >> 8;
738 rgbs
[i
].g
= nv_crtc
->lut
.g
[i
] >> 8;
739 rgbs
[i
].b
= nv_crtc
->lut
.b
[i
] >> 8;
742 nouveau_hw_load_state_palette(dev
, nv_crtc
->index
, &dev_priv
->mode_reg
);
746 nv_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*r
, u16
*g
, u16
*b
, uint32_t start
,
749 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
750 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
752 for (i
= start
; i
< end
; i
++) {
753 nv_crtc
->lut
.r
[i
] = r
[i
];
754 nv_crtc
->lut
.g
[i
] = g
[i
];
755 nv_crtc
->lut
.b
[i
] = b
[i
];
758 /* We need to know the depth before we upload, but it's possible to
759 * get called before a framebuffer is bound. If this is the case,
760 * mark the lut values as dirty by setting depth==0, and it'll be
761 * uploaded on the first mode_set_base()
763 if (!nv_crtc
->base
.fb
) {
764 nv_crtc
->lut
.depth
= 0;
768 nv_crtc_gamma_load(crtc
);
772 nv04_crtc_do_mode_set_base(struct drm_crtc
*crtc
,
773 struct drm_framebuffer
*passed_fb
,
774 int x
, int y
, bool atomic
)
776 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
777 struct drm_device
*dev
= crtc
->dev
;
778 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
779 struct nv04_crtc_reg
*regp
= &dev_priv
->mode_reg
.crtc_reg
[nv_crtc
->index
];
780 struct drm_framebuffer
*drm_fb
= nv_crtc
->base
.fb
;
781 struct nouveau_framebuffer
*fb
= nouveau_framebuffer(drm_fb
);
782 int arb_burst
, arb_lwm
;
785 /* If atomic, we want to switch to the fb we were passed, so
786 * now we update pointers to do that. (We don't pin; just
787 * assume we're already pinned and update the base address.)
791 fb
= nouveau_framebuffer(passed_fb
);
794 /* If not atomic, we can go ahead and pin, and unpin the
795 * old fb we were passed.
797 ret
= nouveau_bo_pin(fb
->nvbo
, TTM_PL_FLAG_VRAM
);
802 struct nouveau_framebuffer
*ofb
= nouveau_framebuffer(passed_fb
);
803 nouveau_bo_unpin(ofb
->nvbo
);
807 nv_crtc
->fb
.offset
= fb
->nvbo
->bo
.offset
;
809 if (nv_crtc
->lut
.depth
!= drm_fb
->depth
) {
810 nv_crtc
->lut
.depth
= drm_fb
->depth
;
811 nv_crtc_gamma_load(crtc
);
814 /* Update the framebuffer format. */
815 regp
->CRTC
[NV_CIO_CRE_PIXEL_INDEX
] &= ~3;
816 regp
->CRTC
[NV_CIO_CRE_PIXEL_INDEX
] |= (crtc
->fb
->depth
+ 1) / 8;
817 regp
->ramdac_gen_ctrl
&= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL
;
818 if (crtc
->fb
->depth
== 16)
819 regp
->ramdac_gen_ctrl
|= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL
;
820 crtc_wr_cio_state(crtc
, regp
, NV_CIO_CRE_PIXEL_INDEX
);
821 NVWriteRAMDAC(dev
, nv_crtc
->index
, NV_PRAMDAC_GENERAL_CONTROL
,
822 regp
->ramdac_gen_ctrl
);
824 regp
->CRTC
[NV_CIO_CR_OFFSET_INDEX
] = drm_fb
->pitch
>> 3;
825 regp
->CRTC
[NV_CIO_CRE_RPC0_INDEX
] =
826 XLATE(drm_fb
->pitch
>> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8
);
827 crtc_wr_cio_state(crtc
, regp
, NV_CIO_CRE_RPC0_INDEX
);
828 crtc_wr_cio_state(crtc
, regp
, NV_CIO_CR_OFFSET_INDEX
);
830 /* Update the framebuffer location. */
831 regp
->fb_start
= nv_crtc
->fb
.offset
& ~3;
832 regp
->fb_start
+= (y
* drm_fb
->pitch
) + (x
* drm_fb
->bits_per_pixel
/ 8);
833 NVWriteCRTC(dev
, nv_crtc
->index
, NV_PCRTC_START
, regp
->fb_start
);
835 /* Update the arbitration parameters. */
836 nouveau_calc_arb(dev
, crtc
->mode
.clock
, drm_fb
->bits_per_pixel
,
837 &arb_burst
, &arb_lwm
);
839 regp
->CRTC
[NV_CIO_CRE_FF_INDEX
] = arb_burst
;
840 regp
->CRTC
[NV_CIO_CRE_FFLWM__INDEX
] = arb_lwm
& 0xff;
841 crtc_wr_cio_state(crtc
, regp
, NV_CIO_CRE_FF_INDEX
);
842 crtc_wr_cio_state(crtc
, regp
, NV_CIO_CRE_FFLWM__INDEX
);
844 if (dev_priv
->card_type
>= NV_30
) {
845 regp
->CRTC
[NV_CIO_CRE_47
] = arb_lwm
>> 8;
846 crtc_wr_cio_state(crtc
, regp
, NV_CIO_CRE_47
);
853 nv04_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
854 struct drm_framebuffer
*old_fb
)
856 return nv04_crtc_do_mode_set_base(crtc
, old_fb
, x
, y
, false);
860 nv04_crtc_mode_set_base_atomic(struct drm_crtc
*crtc
,
861 struct drm_framebuffer
*fb
,
862 int x
, int y
, int enter
)
864 struct drm_nouveau_private
*dev_priv
= crtc
->dev
->dev_private
;
865 struct drm_device
*dev
= dev_priv
->dev
;
868 nouveau_fbcon_save_disable_accel(dev
);
870 nouveau_fbcon_restore_accel(dev
);
872 return nv04_crtc_do_mode_set_base(crtc
, fb
, x
, y
, true);
875 static void nv04_cursor_upload(struct drm_device
*dev
, struct nouveau_bo
*src
,
876 struct nouveau_bo
*dst
)
878 int width
= nv_cursor_width(dev
);
882 for (i
= 0; i
< width
; i
++) {
883 for (j
= 0; j
< width
; j
++) {
884 pixel
= nouveau_bo_rd32(src
, i
*64 + j
);
886 nouveau_bo_wr16(dst
, i
*width
+ j
, (pixel
& 0x80000000) >> 16
887 | (pixel
& 0xf80000) >> 9
888 | (pixel
& 0xf800) >> 6
889 | (pixel
& 0xf8) >> 3);
894 static void nv11_cursor_upload(struct drm_device
*dev
, struct nouveau_bo
*src
,
895 struct nouveau_bo
*dst
)
900 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha
901 * cursors (though NPM in combination with fp dithering may not work on
902 * nv11, from "nv" driver history)
903 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
904 * blob uses, however we get given PM cursors so we use PM mode
906 for (i
= 0; i
< 64 * 64; i
++) {
907 pixel
= nouveau_bo_rd32(src
, i
);
909 /* hw gets unhappy if alpha <= rgb values. for a PM image "less
910 * than" shouldn't happen; fix "equal to" case by adding one to
911 * alpha channel (slightly inaccurate, but so is attempting to
912 * get back to NPM images, due to limits of integer precision)
915 if (alpha
> 0 && alpha
< 255)
916 pixel
= (pixel
& 0x00ffffff) | ((alpha
+ 1) << 24);
920 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
922 if (dev_priv
->chipset
== 0x11) {
923 pixel
= ((pixel
& 0x000000ff) << 24) |
924 ((pixel
& 0x0000ff00) << 8) |
925 ((pixel
& 0x00ff0000) >> 8) |
926 ((pixel
& 0xff000000) >> 24);
931 nouveau_bo_wr32(dst
, i
, pixel
);
936 nv04_crtc_cursor_set(struct drm_crtc
*crtc
, struct drm_file
*file_priv
,
937 uint32_t buffer_handle
, uint32_t width
, uint32_t height
)
939 struct drm_nouveau_private
*dev_priv
= crtc
->dev
->dev_private
;
940 struct drm_device
*dev
= dev_priv
->dev
;
941 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
942 struct nouveau_bo
*cursor
= NULL
;
943 struct drm_gem_object
*gem
;
946 if (width
!= 64 || height
!= 64)
949 if (!buffer_handle
) {
950 nv_crtc
->cursor
.hide(nv_crtc
, true);
954 gem
= drm_gem_object_lookup(dev
, file_priv
, buffer_handle
);
957 cursor
= nouveau_gem_object(gem
);
959 ret
= nouveau_bo_map(cursor
);
963 if (dev_priv
->chipset
>= 0x11)
964 nv11_cursor_upload(dev
, cursor
, nv_crtc
->cursor
.nvbo
);
966 nv04_cursor_upload(dev
, cursor
, nv_crtc
->cursor
.nvbo
);
968 nouveau_bo_unmap(cursor
);
969 nv_crtc
->cursor
.offset
= nv_crtc
->cursor
.nvbo
->bo
.offset
;
970 nv_crtc
->cursor
.set_offset(nv_crtc
, nv_crtc
->cursor
.offset
);
971 nv_crtc
->cursor
.show(nv_crtc
, true);
973 drm_gem_object_unreference_unlocked(gem
);
978 nv04_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
980 struct nouveau_crtc
*nv_crtc
= nouveau_crtc(crtc
);
982 nv_crtc
->cursor
.set_pos(nv_crtc
, x
, y
);
986 static const struct drm_crtc_funcs nv04_crtc_funcs
= {
987 .save
= nv_crtc_save
,
988 .restore
= nv_crtc_restore
,
989 .cursor_set
= nv04_crtc_cursor_set
,
990 .cursor_move
= nv04_crtc_cursor_move
,
991 .gamma_set
= nv_crtc_gamma_set
,
992 .set_config
= drm_crtc_helper_set_config
,
993 .destroy
= nv_crtc_destroy
,
996 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs
= {
997 .dpms
= nv_crtc_dpms
,
998 .prepare
= nv_crtc_prepare
,
999 .commit
= nv_crtc_commit
,
1000 .mode_fixup
= nv_crtc_mode_fixup
,
1001 .mode_set
= nv_crtc_mode_set
,
1002 .mode_set_base
= nv04_crtc_mode_set_base
,
1003 .mode_set_base_atomic
= nv04_crtc_mode_set_base_atomic
,
1004 .load_lut
= nv_crtc_gamma_load
,
1008 nv04_crtc_create(struct drm_device
*dev
, int crtc_num
)
1010 struct nouveau_crtc
*nv_crtc
;
1013 nv_crtc
= kzalloc(sizeof(*nv_crtc
), GFP_KERNEL
);
1017 for (i
= 0; i
< 256; i
++) {
1018 nv_crtc
->lut
.r
[i
] = i
<< 8;
1019 nv_crtc
->lut
.g
[i
] = i
<< 8;
1020 nv_crtc
->lut
.b
[i
] = i
<< 8;
1022 nv_crtc
->lut
.depth
= 0;
1024 nv_crtc
->index
= crtc_num
;
1025 nv_crtc
->last_dpms
= NV_DPMS_CLEARED
;
1027 drm_crtc_init(dev
, &nv_crtc
->base
, &nv04_crtc_funcs
);
1028 drm_crtc_helper_add(&nv_crtc
->base
, &nv04_crtc_helper_funcs
);
1029 drm_mode_crtc_set_gamma_size(&nv_crtc
->base
, 256);
1031 ret
= nouveau_bo_new(dev
, NULL
, 64*64*4, 0x100, TTM_PL_FLAG_VRAM
,
1032 0, 0x0000, false, true, &nv_crtc
->cursor
.nvbo
);
1034 ret
= nouveau_bo_pin(nv_crtc
->cursor
.nvbo
, TTM_PL_FLAG_VRAM
);
1036 ret
= nouveau_bo_map(nv_crtc
->cursor
.nvbo
);
1038 nouveau_bo_ref(NULL
, &nv_crtc
->cursor
.nvbo
);
1041 nv04_cursor_init(nv_crtc
);