2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #include <linux/swab.h>
27 #include <linux/slab.h>
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_gpio.h"
40 #include "nouveau_pm.h"
41 #include "nv50_display.h"
42 #include "nouveau_fifo.h"
43 #include "nouveau_fence.h"
44 #include "nouveau_software.h"
46 static void nouveau_stub_takedown(struct drm_device
*dev
) {}
47 static int nouveau_stub_init(struct drm_device
*dev
) { return 0; }
49 static int nouveau_init_engine_ptrs(struct drm_device
*dev
)
51 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
52 struct nouveau_engine
*engine
= &dev_priv
->engine
;
54 switch (dev_priv
->chipset
& 0xf0) {
56 engine
->instmem
.init
= nv04_instmem_init
;
57 engine
->instmem
.takedown
= nv04_instmem_takedown
;
58 engine
->instmem
.suspend
= nv04_instmem_suspend
;
59 engine
->instmem
.resume
= nv04_instmem_resume
;
60 engine
->instmem
.get
= nv04_instmem_get
;
61 engine
->instmem
.put
= nv04_instmem_put
;
62 engine
->instmem
.map
= nv04_instmem_map
;
63 engine
->instmem
.unmap
= nv04_instmem_unmap
;
64 engine
->instmem
.flush
= nv04_instmem_flush
;
65 engine
->mc
.init
= nv04_mc_init
;
66 engine
->mc
.takedown
= nv04_mc_takedown
;
67 engine
->timer
.init
= nv04_timer_init
;
68 engine
->timer
.read
= nv04_timer_read
;
69 engine
->timer
.takedown
= nv04_timer_takedown
;
70 engine
->fb
.init
= nv04_fb_init
;
71 engine
->fb
.takedown
= nv04_fb_takedown
;
72 engine
->display
.early_init
= nv04_display_early_init
;
73 engine
->display
.late_takedown
= nv04_display_late_takedown
;
74 engine
->display
.create
= nv04_display_create
;
75 engine
->display
.destroy
= nv04_display_destroy
;
76 engine
->display
.init
= nv04_display_init
;
77 engine
->display
.fini
= nv04_display_fini
;
78 engine
->pm
.clocks_get
= nv04_pm_clocks_get
;
79 engine
->pm
.clocks_pre
= nv04_pm_clocks_pre
;
80 engine
->pm
.clocks_set
= nv04_pm_clocks_set
;
81 engine
->vram
.init
= nv04_fb_vram_init
;
82 engine
->vram
.takedown
= nouveau_stub_takedown
;
83 engine
->vram
.flags_valid
= nouveau_mem_flags_valid
;
86 engine
->instmem
.init
= nv04_instmem_init
;
87 engine
->instmem
.takedown
= nv04_instmem_takedown
;
88 engine
->instmem
.suspend
= nv04_instmem_suspend
;
89 engine
->instmem
.resume
= nv04_instmem_resume
;
90 engine
->instmem
.get
= nv04_instmem_get
;
91 engine
->instmem
.put
= nv04_instmem_put
;
92 engine
->instmem
.map
= nv04_instmem_map
;
93 engine
->instmem
.unmap
= nv04_instmem_unmap
;
94 engine
->instmem
.flush
= nv04_instmem_flush
;
95 engine
->mc
.init
= nv04_mc_init
;
96 engine
->mc
.takedown
= nv04_mc_takedown
;
97 engine
->timer
.init
= nv04_timer_init
;
98 engine
->timer
.read
= nv04_timer_read
;
99 engine
->timer
.takedown
= nv04_timer_takedown
;
100 engine
->fb
.init
= nv10_fb_init
;
101 engine
->fb
.takedown
= nv10_fb_takedown
;
102 engine
->fb
.init_tile_region
= nv10_fb_init_tile_region
;
103 engine
->fb
.set_tile_region
= nv10_fb_set_tile_region
;
104 engine
->fb
.free_tile_region
= nv10_fb_free_tile_region
;
105 engine
->display
.early_init
= nv04_display_early_init
;
106 engine
->display
.late_takedown
= nv04_display_late_takedown
;
107 engine
->display
.create
= nv04_display_create
;
108 engine
->display
.destroy
= nv04_display_destroy
;
109 engine
->display
.init
= nv04_display_init
;
110 engine
->display
.fini
= nv04_display_fini
;
111 engine
->gpio
.drive
= nv10_gpio_drive
;
112 engine
->gpio
.sense
= nv10_gpio_sense
;
113 engine
->pm
.clocks_get
= nv04_pm_clocks_get
;
114 engine
->pm
.clocks_pre
= nv04_pm_clocks_pre
;
115 engine
->pm
.clocks_set
= nv04_pm_clocks_set
;
116 if (dev_priv
->chipset
== 0x1a ||
117 dev_priv
->chipset
== 0x1f)
118 engine
->vram
.init
= nv1a_fb_vram_init
;
120 engine
->vram
.init
= nv10_fb_vram_init
;
121 engine
->vram
.takedown
= nouveau_stub_takedown
;
122 engine
->vram
.flags_valid
= nouveau_mem_flags_valid
;
125 engine
->instmem
.init
= nv04_instmem_init
;
126 engine
->instmem
.takedown
= nv04_instmem_takedown
;
127 engine
->instmem
.suspend
= nv04_instmem_suspend
;
128 engine
->instmem
.resume
= nv04_instmem_resume
;
129 engine
->instmem
.get
= nv04_instmem_get
;
130 engine
->instmem
.put
= nv04_instmem_put
;
131 engine
->instmem
.map
= nv04_instmem_map
;
132 engine
->instmem
.unmap
= nv04_instmem_unmap
;
133 engine
->instmem
.flush
= nv04_instmem_flush
;
134 engine
->mc
.init
= nv04_mc_init
;
135 engine
->mc
.takedown
= nv04_mc_takedown
;
136 engine
->timer
.init
= nv04_timer_init
;
137 engine
->timer
.read
= nv04_timer_read
;
138 engine
->timer
.takedown
= nv04_timer_takedown
;
139 engine
->fb
.init
= nv20_fb_init
;
140 engine
->fb
.takedown
= nv20_fb_takedown
;
141 engine
->fb
.init_tile_region
= nv20_fb_init_tile_region
;
142 engine
->fb
.set_tile_region
= nv20_fb_set_tile_region
;
143 engine
->fb
.free_tile_region
= nv20_fb_free_tile_region
;
144 engine
->display
.early_init
= nv04_display_early_init
;
145 engine
->display
.late_takedown
= nv04_display_late_takedown
;
146 engine
->display
.create
= nv04_display_create
;
147 engine
->display
.destroy
= nv04_display_destroy
;
148 engine
->display
.init
= nv04_display_init
;
149 engine
->display
.fini
= nv04_display_fini
;
150 engine
->gpio
.drive
= nv10_gpio_drive
;
151 engine
->gpio
.sense
= nv10_gpio_sense
;
152 engine
->pm
.clocks_get
= nv04_pm_clocks_get
;
153 engine
->pm
.clocks_pre
= nv04_pm_clocks_pre
;
154 engine
->pm
.clocks_set
= nv04_pm_clocks_set
;
155 engine
->vram
.init
= nv20_fb_vram_init
;
156 engine
->vram
.takedown
= nouveau_stub_takedown
;
157 engine
->vram
.flags_valid
= nouveau_mem_flags_valid
;
160 engine
->instmem
.init
= nv04_instmem_init
;
161 engine
->instmem
.takedown
= nv04_instmem_takedown
;
162 engine
->instmem
.suspend
= nv04_instmem_suspend
;
163 engine
->instmem
.resume
= nv04_instmem_resume
;
164 engine
->instmem
.get
= nv04_instmem_get
;
165 engine
->instmem
.put
= nv04_instmem_put
;
166 engine
->instmem
.map
= nv04_instmem_map
;
167 engine
->instmem
.unmap
= nv04_instmem_unmap
;
168 engine
->instmem
.flush
= nv04_instmem_flush
;
169 engine
->mc
.init
= nv04_mc_init
;
170 engine
->mc
.takedown
= nv04_mc_takedown
;
171 engine
->timer
.init
= nv04_timer_init
;
172 engine
->timer
.read
= nv04_timer_read
;
173 engine
->timer
.takedown
= nv04_timer_takedown
;
174 engine
->fb
.init
= nv30_fb_init
;
175 engine
->fb
.takedown
= nv30_fb_takedown
;
176 engine
->fb
.init_tile_region
= nv30_fb_init_tile_region
;
177 engine
->fb
.set_tile_region
= nv10_fb_set_tile_region
;
178 engine
->fb
.free_tile_region
= nv30_fb_free_tile_region
;
179 engine
->display
.early_init
= nv04_display_early_init
;
180 engine
->display
.late_takedown
= nv04_display_late_takedown
;
181 engine
->display
.create
= nv04_display_create
;
182 engine
->display
.destroy
= nv04_display_destroy
;
183 engine
->display
.init
= nv04_display_init
;
184 engine
->display
.fini
= nv04_display_fini
;
185 engine
->gpio
.drive
= nv10_gpio_drive
;
186 engine
->gpio
.sense
= nv10_gpio_sense
;
187 engine
->pm
.clocks_get
= nv04_pm_clocks_get
;
188 engine
->pm
.clocks_pre
= nv04_pm_clocks_pre
;
189 engine
->pm
.clocks_set
= nv04_pm_clocks_set
;
190 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
191 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
192 engine
->vram
.init
= nv20_fb_vram_init
;
193 engine
->vram
.takedown
= nouveau_stub_takedown
;
194 engine
->vram
.flags_valid
= nouveau_mem_flags_valid
;
198 engine
->instmem
.init
= nv04_instmem_init
;
199 engine
->instmem
.takedown
= nv04_instmem_takedown
;
200 engine
->instmem
.suspend
= nv04_instmem_suspend
;
201 engine
->instmem
.resume
= nv04_instmem_resume
;
202 engine
->instmem
.get
= nv04_instmem_get
;
203 engine
->instmem
.put
= nv04_instmem_put
;
204 engine
->instmem
.map
= nv04_instmem_map
;
205 engine
->instmem
.unmap
= nv04_instmem_unmap
;
206 engine
->instmem
.flush
= nv04_instmem_flush
;
207 engine
->mc
.init
= nv40_mc_init
;
208 engine
->mc
.takedown
= nv40_mc_takedown
;
209 engine
->timer
.init
= nv04_timer_init
;
210 engine
->timer
.read
= nv04_timer_read
;
211 engine
->timer
.takedown
= nv04_timer_takedown
;
212 engine
->fb
.init
= nv40_fb_init
;
213 engine
->fb
.takedown
= nv40_fb_takedown
;
214 engine
->fb
.init_tile_region
= nv30_fb_init_tile_region
;
215 engine
->fb
.set_tile_region
= nv40_fb_set_tile_region
;
216 engine
->fb
.free_tile_region
= nv30_fb_free_tile_region
;
217 engine
->display
.early_init
= nv04_display_early_init
;
218 engine
->display
.late_takedown
= nv04_display_late_takedown
;
219 engine
->display
.create
= nv04_display_create
;
220 engine
->display
.destroy
= nv04_display_destroy
;
221 engine
->display
.init
= nv04_display_init
;
222 engine
->display
.fini
= nv04_display_fini
;
223 engine
->gpio
.init
= nv10_gpio_init
;
224 engine
->gpio
.fini
= nv10_gpio_fini
;
225 engine
->gpio
.drive
= nv10_gpio_drive
;
226 engine
->gpio
.sense
= nv10_gpio_sense
;
227 engine
->gpio
.irq_enable
= nv10_gpio_irq_enable
;
228 engine
->pm
.clocks_get
= nv40_pm_clocks_get
;
229 engine
->pm
.clocks_pre
= nv40_pm_clocks_pre
;
230 engine
->pm
.clocks_set
= nv40_pm_clocks_set
;
231 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
232 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
233 engine
->pm
.temp_get
= nv40_temp_get
;
234 engine
->pm
.pwm_get
= nv40_pm_pwm_get
;
235 engine
->pm
.pwm_set
= nv40_pm_pwm_set
;
236 engine
->vram
.init
= nv40_fb_vram_init
;
237 engine
->vram
.takedown
= nouveau_stub_takedown
;
238 engine
->vram
.flags_valid
= nouveau_mem_flags_valid
;
241 case 0x80: /* gotta love NVIDIA's consistency.. */
244 engine
->instmem
.init
= nv50_instmem_init
;
245 engine
->instmem
.takedown
= nv50_instmem_takedown
;
246 engine
->instmem
.suspend
= nv50_instmem_suspend
;
247 engine
->instmem
.resume
= nv50_instmem_resume
;
248 engine
->instmem
.get
= nv50_instmem_get
;
249 engine
->instmem
.put
= nv50_instmem_put
;
250 engine
->instmem
.map
= nv50_instmem_map
;
251 engine
->instmem
.unmap
= nv50_instmem_unmap
;
252 if (dev_priv
->chipset
== 0x50)
253 engine
->instmem
.flush
= nv50_instmem_flush
;
255 engine
->instmem
.flush
= nv84_instmem_flush
;
256 engine
->mc
.init
= nv50_mc_init
;
257 engine
->mc
.takedown
= nv50_mc_takedown
;
258 engine
->timer
.init
= nv04_timer_init
;
259 engine
->timer
.read
= nv04_timer_read
;
260 engine
->timer
.takedown
= nv04_timer_takedown
;
261 engine
->fb
.init
= nv50_fb_init
;
262 engine
->fb
.takedown
= nv50_fb_takedown
;
263 engine
->display
.early_init
= nv50_display_early_init
;
264 engine
->display
.late_takedown
= nv50_display_late_takedown
;
265 engine
->display
.create
= nv50_display_create
;
266 engine
->display
.destroy
= nv50_display_destroy
;
267 engine
->display
.init
= nv50_display_init
;
268 engine
->display
.fini
= nv50_display_fini
;
269 engine
->gpio
.init
= nv50_gpio_init
;
270 engine
->gpio
.fini
= nv50_gpio_fini
;
271 engine
->gpio
.drive
= nv50_gpio_drive
;
272 engine
->gpio
.sense
= nv50_gpio_sense
;
273 engine
->gpio
.irq_enable
= nv50_gpio_irq_enable
;
274 switch (dev_priv
->chipset
) {
285 engine
->pm
.clocks_get
= nv50_pm_clocks_get
;
286 engine
->pm
.clocks_pre
= nv50_pm_clocks_pre
;
287 engine
->pm
.clocks_set
= nv50_pm_clocks_set
;
290 engine
->pm
.clocks_get
= nva3_pm_clocks_get
;
291 engine
->pm
.clocks_pre
= nva3_pm_clocks_pre
;
292 engine
->pm
.clocks_set
= nva3_pm_clocks_set
;
295 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
296 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
297 if (dev_priv
->chipset
>= 0x84)
298 engine
->pm
.temp_get
= nv84_temp_get
;
300 engine
->pm
.temp_get
= nv40_temp_get
;
301 engine
->pm
.pwm_get
= nv50_pm_pwm_get
;
302 engine
->pm
.pwm_set
= nv50_pm_pwm_set
;
303 engine
->vram
.init
= nv50_vram_init
;
304 engine
->vram
.takedown
= nv50_vram_fini
;
305 engine
->vram
.get
= nv50_vram_new
;
306 engine
->vram
.put
= nv50_vram_del
;
307 engine
->vram
.flags_valid
= nv50_vram_flags_valid
;
310 engine
->instmem
.init
= nvc0_instmem_init
;
311 engine
->instmem
.takedown
= nvc0_instmem_takedown
;
312 engine
->instmem
.suspend
= nvc0_instmem_suspend
;
313 engine
->instmem
.resume
= nvc0_instmem_resume
;
314 engine
->instmem
.get
= nv50_instmem_get
;
315 engine
->instmem
.put
= nv50_instmem_put
;
316 engine
->instmem
.map
= nv50_instmem_map
;
317 engine
->instmem
.unmap
= nv50_instmem_unmap
;
318 engine
->instmem
.flush
= nv84_instmem_flush
;
319 engine
->mc
.init
= nv50_mc_init
;
320 engine
->mc
.takedown
= nv50_mc_takedown
;
321 engine
->timer
.init
= nv04_timer_init
;
322 engine
->timer
.read
= nv04_timer_read
;
323 engine
->timer
.takedown
= nv04_timer_takedown
;
324 engine
->fb
.init
= nvc0_fb_init
;
325 engine
->fb
.takedown
= nvc0_fb_takedown
;
326 engine
->display
.early_init
= nv50_display_early_init
;
327 engine
->display
.late_takedown
= nv50_display_late_takedown
;
328 engine
->display
.create
= nv50_display_create
;
329 engine
->display
.destroy
= nv50_display_destroy
;
330 engine
->display
.init
= nv50_display_init
;
331 engine
->display
.fini
= nv50_display_fini
;
332 engine
->gpio
.init
= nv50_gpio_init
;
333 engine
->gpio
.fini
= nv50_gpio_fini
;
334 engine
->gpio
.drive
= nv50_gpio_drive
;
335 engine
->gpio
.sense
= nv50_gpio_sense
;
336 engine
->gpio
.irq_enable
= nv50_gpio_irq_enable
;
337 engine
->vram
.init
= nvc0_vram_init
;
338 engine
->vram
.takedown
= nv50_vram_fini
;
339 engine
->vram
.get
= nvc0_vram_new
;
340 engine
->vram
.put
= nv50_vram_del
;
341 engine
->vram
.flags_valid
= nvc0_vram_flags_valid
;
342 engine
->pm
.temp_get
= nv84_temp_get
;
343 engine
->pm
.clocks_get
= nvc0_pm_clocks_get
;
344 engine
->pm
.clocks_pre
= nvc0_pm_clocks_pre
;
345 engine
->pm
.clocks_set
= nvc0_pm_clocks_set
;
346 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
347 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
348 engine
->pm
.pwm_get
= nv50_pm_pwm_get
;
349 engine
->pm
.pwm_set
= nv50_pm_pwm_set
;
352 engine
->instmem
.init
= nvc0_instmem_init
;
353 engine
->instmem
.takedown
= nvc0_instmem_takedown
;
354 engine
->instmem
.suspend
= nvc0_instmem_suspend
;
355 engine
->instmem
.resume
= nvc0_instmem_resume
;
356 engine
->instmem
.get
= nv50_instmem_get
;
357 engine
->instmem
.put
= nv50_instmem_put
;
358 engine
->instmem
.map
= nv50_instmem_map
;
359 engine
->instmem
.unmap
= nv50_instmem_unmap
;
360 engine
->instmem
.flush
= nv84_instmem_flush
;
361 engine
->mc
.init
= nv50_mc_init
;
362 engine
->mc
.takedown
= nv50_mc_takedown
;
363 engine
->timer
.init
= nv04_timer_init
;
364 engine
->timer
.read
= nv04_timer_read
;
365 engine
->timer
.takedown
= nv04_timer_takedown
;
366 engine
->fb
.init
= nvc0_fb_init
;
367 engine
->fb
.takedown
= nvc0_fb_takedown
;
368 engine
->display
.early_init
= nouveau_stub_init
;
369 engine
->display
.late_takedown
= nouveau_stub_takedown
;
370 engine
->display
.create
= nvd0_display_create
;
371 engine
->display
.destroy
= nvd0_display_destroy
;
372 engine
->display
.init
= nvd0_display_init
;
373 engine
->display
.fini
= nvd0_display_fini
;
374 engine
->gpio
.init
= nv50_gpio_init
;
375 engine
->gpio
.fini
= nv50_gpio_fini
;
376 engine
->gpio
.drive
= nvd0_gpio_drive
;
377 engine
->gpio
.sense
= nvd0_gpio_sense
;
378 engine
->gpio
.irq_enable
= nv50_gpio_irq_enable
;
379 engine
->vram
.init
= nvc0_vram_init
;
380 engine
->vram
.takedown
= nv50_vram_fini
;
381 engine
->vram
.get
= nvc0_vram_new
;
382 engine
->vram
.put
= nv50_vram_del
;
383 engine
->vram
.flags_valid
= nvc0_vram_flags_valid
;
384 engine
->pm
.temp_get
= nv84_temp_get
;
385 engine
->pm
.clocks_get
= nvc0_pm_clocks_get
;
386 engine
->pm
.clocks_pre
= nvc0_pm_clocks_pre
;
387 engine
->pm
.clocks_set
= nvc0_pm_clocks_set
;
388 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
389 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
392 engine
->instmem
.init
= nvc0_instmem_init
;
393 engine
->instmem
.takedown
= nvc0_instmem_takedown
;
394 engine
->instmem
.suspend
= nvc0_instmem_suspend
;
395 engine
->instmem
.resume
= nvc0_instmem_resume
;
396 engine
->instmem
.get
= nv50_instmem_get
;
397 engine
->instmem
.put
= nv50_instmem_put
;
398 engine
->instmem
.map
= nv50_instmem_map
;
399 engine
->instmem
.unmap
= nv50_instmem_unmap
;
400 engine
->instmem
.flush
= nv84_instmem_flush
;
401 engine
->mc
.init
= nv50_mc_init
;
402 engine
->mc
.takedown
= nv50_mc_takedown
;
403 engine
->timer
.init
= nv04_timer_init
;
404 engine
->timer
.read
= nv04_timer_read
;
405 engine
->timer
.takedown
= nv04_timer_takedown
;
406 engine
->fb
.init
= nvc0_fb_init
;
407 engine
->fb
.takedown
= nvc0_fb_takedown
;
408 engine
->display
.early_init
= nouveau_stub_init
;
409 engine
->display
.late_takedown
= nouveau_stub_takedown
;
410 engine
->display
.create
= nvd0_display_create
;
411 engine
->display
.destroy
= nvd0_display_destroy
;
412 engine
->display
.init
= nvd0_display_init
;
413 engine
->display
.fini
= nvd0_display_fini
;
414 engine
->gpio
.init
= nv50_gpio_init
;
415 engine
->gpio
.fini
= nv50_gpio_fini
;
416 engine
->gpio
.drive
= nvd0_gpio_drive
;
417 engine
->gpio
.sense
= nvd0_gpio_sense
;
418 engine
->gpio
.irq_enable
= nv50_gpio_irq_enable
;
419 engine
->vram
.init
= nvc0_vram_init
;
420 engine
->vram
.takedown
= nv50_vram_fini
;
421 engine
->vram
.get
= nvc0_vram_new
;
422 engine
->vram
.put
= nv50_vram_del
;
423 engine
->vram
.flags_valid
= nvc0_vram_flags_valid
;
426 NV_ERROR(dev
, "NV%02x unsupported\n", dev_priv
->chipset
);
431 if (nouveau_modeset
== 2) {
432 engine
->display
.early_init
= nouveau_stub_init
;
433 engine
->display
.late_takedown
= nouveau_stub_takedown
;
434 engine
->display
.create
= nouveau_stub_init
;
435 engine
->display
.init
= nouveau_stub_init
;
436 engine
->display
.destroy
= nouveau_stub_takedown
;
443 nouveau_vga_set_decode(void *priv
, bool state
)
445 struct drm_device
*dev
= priv
;
446 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
448 if (dev_priv
->chipset
>= 0x40)
449 nv_wr32(dev
, 0x88054, state
);
451 nv_wr32(dev
, 0x1854, state
);
454 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
455 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
457 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
460 static void nouveau_switcheroo_set_state(struct pci_dev
*pdev
,
461 enum vga_switcheroo_state state
)
463 struct drm_device
*dev
= pci_get_drvdata(pdev
);
464 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
465 if (state
== VGA_SWITCHEROO_ON
) {
466 printk(KERN_ERR
"VGA switcheroo: switched nouveau on\n");
467 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
468 nouveau_pci_resume(pdev
);
469 drm_kms_helper_poll_enable(dev
);
470 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
472 printk(KERN_ERR
"VGA switcheroo: switched nouveau off\n");
473 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
474 drm_kms_helper_poll_disable(dev
);
475 nouveau_switcheroo_optimus_dsm();
476 nouveau_pci_suspend(pdev
, pmm
);
477 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
481 static void nouveau_switcheroo_reprobe(struct pci_dev
*pdev
)
483 struct drm_device
*dev
= pci_get_drvdata(pdev
);
484 nouveau_fbcon_output_poll_changed(dev
);
487 static bool nouveau_switcheroo_can_switch(struct pci_dev
*pdev
)
489 struct drm_device
*dev
= pci_get_drvdata(pdev
);
492 spin_lock(&dev
->count_lock
);
493 can_switch
= (dev
->open_count
== 0);
494 spin_unlock(&dev
->count_lock
);
499 nouveau_card_channel_fini(struct drm_device
*dev
)
501 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
503 if (dev_priv
->channel
)
504 nouveau_channel_put_unlocked(&dev_priv
->channel
);
508 nouveau_card_channel_init(struct drm_device
*dev
)
510 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
511 struct nouveau_channel
*chan
;
514 ret
= nouveau_channel_alloc(dev
, &chan
, NULL
, NvDmaFB
, NvDmaTT
);
515 dev_priv
->channel
= chan
;
518 mutex_unlock(&dev_priv
->channel
->mutex
);
520 nouveau_bo_move_init(chan
);
524 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops
= {
525 .set_gpu_state
= nouveau_switcheroo_set_state
,
526 .reprobe
= nouveau_switcheroo_reprobe
,
527 .can_switch
= nouveau_switcheroo_can_switch
,
531 nouveau_card_init(struct drm_device
*dev
)
533 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
534 struct nouveau_engine
*engine
;
537 vga_client_register(dev
->pdev
, dev
, NULL
, nouveau_vga_set_decode
);
538 vga_switcheroo_register_client(dev
->pdev
, &nouveau_switcheroo_ops
);
540 /* Initialise internal driver API hooks */
541 ret
= nouveau_init_engine_ptrs(dev
);
544 engine
= &dev_priv
->engine
;
545 spin_lock_init(&dev_priv
->channels
.lock
);
546 spin_lock_init(&dev_priv
->tile
.lock
);
547 spin_lock_init(&dev_priv
->context_switch_lock
);
548 spin_lock_init(&dev_priv
->vm_lock
);
550 /* Make the CRTCs and I2C buses accessible */
551 ret
= engine
->display
.early_init(dev
);
555 /* Parse BIOS tables / Run init tables if card not POSTed */
556 ret
= nouveau_bios_init(dev
);
558 goto out_display_early
;
560 /* workaround an odd issue on nvc1 by disabling the device's
561 * nosnoop capability. hopefully won't cause issues until a
562 * better fix is found - assuming there is one...
564 if (dev_priv
->chipset
== 0xc1) {
565 nv_mask(dev
, 0x00088080, 0x00000800, 0x00000000);
569 ret
= engine
->mc
.init(dev
);
574 ret
= engine
->timer
.init(dev
);
579 ret
= engine
->fb
.init(dev
);
583 ret
= engine
->vram
.init(dev
);
588 ret
= nouveau_gpio_create(dev
);
592 ret
= nouveau_gpuobj_init(dev
);
596 ret
= engine
->instmem
.init(dev
);
600 ret
= nouveau_mem_vram_init(dev
);
604 ret
= nouveau_mem_gart_init(dev
);
608 if (!dev_priv
->noaccel
) {
609 switch (dev_priv
->card_type
) {
611 nv04_fifo_create(dev
);
616 if (dev_priv
->chipset
< 0x17)
617 nv10_fifo_create(dev
);
619 nv17_fifo_create(dev
);
622 nv40_fifo_create(dev
);
625 if (dev_priv
->chipset
== 0x50)
626 nv50_fifo_create(dev
);
628 nv84_fifo_create(dev
);
632 nvc0_fifo_create(dev
);
635 nve0_fifo_create(dev
);
641 switch (dev_priv
->card_type
) {
643 nv04_fence_create(dev
);
650 if (dev_priv
->chipset
< 0x84)
651 nv10_fence_create(dev
);
653 nv84_fence_create(dev
);
658 nvc0_fence_create(dev
);
664 switch (dev_priv
->card_type
) {
670 nv04_software_create(dev
);
673 nv50_software_create(dev
);
678 nvc0_software_create(dev
);
684 switch (dev_priv
->card_type
) {
686 nv04_graph_create(dev
);
689 nv10_graph_create(dev
);
693 nv20_graph_create(dev
);
696 nv40_graph_create(dev
);
699 nv50_graph_create(dev
);
703 nvc0_graph_create(dev
);
706 nve0_graph_create(dev
);
712 switch (dev_priv
->chipset
) {
719 nv84_crypt_create(dev
);
724 nv98_crypt_create(dev
);
728 switch (dev_priv
->card_type
) {
730 switch (dev_priv
->chipset
) {
734 nva3_copy_create(dev
);
739 if (!(nv_rd32(dev
, 0x022500) & 0x00000200))
740 nvc0_copy_create(dev
, 1);
742 if (!(nv_rd32(dev
, 0x022500) & 0x00000100))
743 nvc0_copy_create(dev
, 0);
749 if (dev_priv
->chipset
>= 0xa3 || dev_priv
->chipset
== 0x98) {
750 nv84_bsp_create(dev
);
752 nv98_ppp_create(dev
);
754 if (dev_priv
->chipset
>= 0x84) {
755 nv50_mpeg_create(dev
);
756 nv84_bsp_create(dev
);
759 if (dev_priv
->chipset
>= 0x50) {
760 nv50_mpeg_create(dev
);
762 if (dev_priv
->card_type
== NV_40
||
763 dev_priv
->chipset
== 0x31 ||
764 dev_priv
->chipset
== 0x34 ||
765 dev_priv
->chipset
== 0x36) {
766 nv31_mpeg_create(dev
);
769 for (e
= 0; e
< NVOBJ_ENGINE_NR
; e
++) {
770 if (dev_priv
->eng
[e
]) {
771 ret
= dev_priv
->eng
[e
]->init(dev
, e
);
778 ret
= nouveau_irq_init(dev
);
782 ret
= nouveau_display_create(dev
);
786 nouveau_backlight_init(dev
);
787 nouveau_pm_init(dev
);
789 if (dev_priv
->eng
[NVOBJ_ENGINE_GR
]) {
790 ret
= nouveau_card_channel_init(dev
);
795 if (dev
->mode_config
.num_crtc
) {
796 ret
= nouveau_display_init(dev
);
800 nouveau_fbcon_init(dev
);
806 nouveau_card_channel_fini(dev
);
808 nouveau_pm_fini(dev
);
809 nouveau_backlight_exit(dev
);
810 nouveau_display_destroy(dev
);
812 nouveau_irq_fini(dev
);
814 if (!dev_priv
->noaccel
) {
815 for (e
= e
- 1; e
>= 0; e
--) {
816 if (!dev_priv
->eng
[e
])
818 dev_priv
->eng
[e
]->fini(dev
, e
, false);
819 dev_priv
->eng
[e
]->destroy(dev
,e
);
822 nouveau_mem_gart_fini(dev
);
824 nouveau_mem_vram_fini(dev
);
826 engine
->instmem
.takedown(dev
);
828 nouveau_gpuobj_takedown(dev
);
830 nouveau_gpio_destroy(dev
);
832 engine
->vram
.takedown(dev
);
834 engine
->fb
.takedown(dev
);
836 engine
->timer
.takedown(dev
);
838 engine
->mc
.takedown(dev
);
840 nouveau_bios_takedown(dev
);
842 engine
->display
.late_takedown(dev
);
844 vga_switcheroo_unregister_client(dev
->pdev
);
845 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
849 static void nouveau_card_takedown(struct drm_device
*dev
)
851 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
852 struct nouveau_engine
*engine
= &dev_priv
->engine
;
855 if (dev
->mode_config
.num_crtc
) {
856 nouveau_fbcon_fini(dev
);
857 nouveau_display_fini(dev
);
860 nouveau_card_channel_fini(dev
);
861 nouveau_pm_fini(dev
);
862 nouveau_backlight_exit(dev
);
863 nouveau_display_destroy(dev
);
865 if (!dev_priv
->noaccel
) {
866 for (e
= NVOBJ_ENGINE_NR
- 1; e
>= 0; e
--) {
867 if (dev_priv
->eng
[e
]) {
868 dev_priv
->eng
[e
]->fini(dev
, e
, false);
869 dev_priv
->eng
[e
]->destroy(dev
,e
);
874 if (dev_priv
->vga_ram
) {
875 nouveau_bo_unpin(dev_priv
->vga_ram
);
876 nouveau_bo_ref(NULL
, &dev_priv
->vga_ram
);
879 mutex_lock(&dev
->struct_mutex
);
880 ttm_bo_clean_mm(&dev_priv
->ttm
.bdev
, TTM_PL_VRAM
);
881 ttm_bo_clean_mm(&dev_priv
->ttm
.bdev
, TTM_PL_TT
);
882 mutex_unlock(&dev
->struct_mutex
);
883 nouveau_mem_gart_fini(dev
);
884 nouveau_mem_vram_fini(dev
);
886 engine
->instmem
.takedown(dev
);
887 nouveau_gpuobj_takedown(dev
);
889 nouveau_gpio_destroy(dev
);
890 engine
->vram
.takedown(dev
);
891 engine
->fb
.takedown(dev
);
892 engine
->timer
.takedown(dev
);
893 engine
->mc
.takedown(dev
);
895 nouveau_bios_takedown(dev
);
896 engine
->display
.late_takedown(dev
);
898 nouveau_irq_fini(dev
);
900 vga_switcheroo_unregister_client(dev
->pdev
);
901 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
905 nouveau_open(struct drm_device
*dev
, struct drm_file
*file_priv
)
907 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
908 struct nouveau_fpriv
*fpriv
;
911 fpriv
= kzalloc(sizeof(*fpriv
), GFP_KERNEL
);
912 if (unlikely(!fpriv
))
915 spin_lock_init(&fpriv
->lock
);
916 INIT_LIST_HEAD(&fpriv
->channels
);
918 if (dev_priv
->card_type
== NV_50
) {
919 ret
= nouveau_vm_new(dev
, 0, (1ULL << 40), 0x0020000000ULL
,
926 if (dev_priv
->card_type
>= NV_C0
) {
927 ret
= nouveau_vm_new(dev
, 0, (1ULL << 40), 0x0008000000ULL
,
935 file_priv
->driver_priv
= fpriv
;
939 /* here a client dies, release the stuff that was allocated for its
941 void nouveau_preclose(struct drm_device
*dev
, struct drm_file
*file_priv
)
943 nouveau_channel_cleanup(dev
, file_priv
);
947 nouveau_postclose(struct drm_device
*dev
, struct drm_file
*file_priv
)
949 struct nouveau_fpriv
*fpriv
= nouveau_fpriv(file_priv
);
950 nouveau_vm_ref(NULL
, &fpriv
->vm
, NULL
);
954 /* first module load, setup the mmio/fb mapping */
955 /* KMS: we need mmio at load time, not when the first drm client opens. */
956 int nouveau_firstopen(struct drm_device
*dev
)
961 /* if we have an OF card, copy vbios to RAMIN */
962 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device
*dev
)
964 #if defined(__powerpc__)
966 const uint32_t *bios
;
967 struct device_node
*dn
= pci_device_to_OF_node(dev
->pdev
);
969 NV_INFO(dev
, "Unable to get the OF node\n");
973 bios
= of_get_property(dn
, "NVDA,BMP", &size
);
975 for (i
= 0; i
< size
; i
+= 4)
976 nv_wi32(dev
, i
, bios
[i
/4]);
977 NV_INFO(dev
, "OF bios successfully copied (%d bytes)\n", size
);
979 NV_INFO(dev
, "Unable to get the OF bios\n");
984 static struct apertures_struct
*nouveau_get_apertures(struct drm_device
*dev
)
986 struct pci_dev
*pdev
= dev
->pdev
;
987 struct apertures_struct
*aper
= alloc_apertures(3);
991 aper
->ranges
[0].base
= pci_resource_start(pdev
, 1);
992 aper
->ranges
[0].size
= pci_resource_len(pdev
, 1);
995 if (pci_resource_len(pdev
, 2)) {
996 aper
->ranges
[aper
->count
].base
= pci_resource_start(pdev
, 2);
997 aper
->ranges
[aper
->count
].size
= pci_resource_len(pdev
, 2);
1001 if (pci_resource_len(pdev
, 3)) {
1002 aper
->ranges
[aper
->count
].base
= pci_resource_start(pdev
, 3);
1003 aper
->ranges
[aper
->count
].size
= pci_resource_len(pdev
, 3);
1010 static int nouveau_remove_conflicting_drivers(struct drm_device
*dev
)
1012 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1013 bool primary
= false;
1014 dev_priv
->apertures
= nouveau_get_apertures(dev
);
1015 if (!dev_priv
->apertures
)
1019 primary
= dev
->pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
1022 remove_conflicting_framebuffers(dev_priv
->apertures
, "nouveaufb", primary
);
1026 int nouveau_load(struct drm_device
*dev
, unsigned long flags
)
1028 struct drm_nouveau_private
*dev_priv
;
1029 unsigned long long offset
, length
;
1030 uint32_t reg0
= ~0, strap
;
1033 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
1038 dev
->dev_private
= dev_priv
;
1039 dev_priv
->dev
= dev
;
1041 pci_set_master(dev
->pdev
);
1043 dev_priv
->flags
= flags
& NOUVEAU_FLAGS
;
1045 NV_DEBUG(dev
, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1046 dev
->pci_vendor
, dev
->pci_device
, dev
->pdev
->class);
1048 /* first up, map the start of mmio and determine the chipset */
1049 dev_priv
->mmio
= ioremap(pci_resource_start(dev
->pdev
, 0), PAGE_SIZE
);
1050 if (dev_priv
->mmio
) {
1052 /* put the card into big-endian mode if it's not */
1053 if (nv_rd32(dev
, NV03_PMC_BOOT_1
) != 0x01000001)
1054 nv_wr32(dev
, NV03_PMC_BOOT_1
, 0x01000001);
1055 DRM_MEMORYBARRIER();
1058 /* determine chipset and derive architecture from it */
1059 reg0
= nv_rd32(dev
, NV03_PMC_BOOT_0
);
1060 if ((reg0
& 0x0f000000) > 0) {
1061 dev_priv
->chipset
= (reg0
& 0xff00000) >> 20;
1062 switch (dev_priv
->chipset
& 0xf0) {
1066 dev_priv
->card_type
= dev_priv
->chipset
& 0xf0;
1070 dev_priv
->card_type
= NV_40
;
1076 dev_priv
->card_type
= NV_50
;
1079 dev_priv
->card_type
= NV_C0
;
1082 dev_priv
->card_type
= NV_D0
;
1085 dev_priv
->card_type
= NV_E0
;
1091 if ((reg0
& 0xff00fff0) == 0x20004000) {
1092 if (reg0
& 0x00f00000)
1093 dev_priv
->chipset
= 0x05;
1095 dev_priv
->chipset
= 0x04;
1096 dev_priv
->card_type
= NV_04
;
1099 iounmap(dev_priv
->mmio
);
1102 if (!dev_priv
->card_type
) {
1103 NV_ERROR(dev
, "unsupported chipset 0x%08x\n", reg0
);
1108 NV_INFO(dev
, "Detected an NV%02x generation card (0x%08x)\n",
1109 dev_priv
->card_type
, reg0
);
1111 /* map the mmio regs, limiting the amount to preserve vmap space */
1112 offset
= pci_resource_start(dev
->pdev
, 0);
1113 length
= pci_resource_len(dev
->pdev
, 0);
1114 if (dev_priv
->card_type
< NV_E0
)
1115 length
= min(length
, (unsigned long long)0x00800000);
1117 dev_priv
->mmio
= ioremap(offset
, length
);
1118 if (!dev_priv
->mmio
) {
1119 NV_ERROR(dev
, "Unable to initialize the mmio mapping. "
1120 "Please report your setup to " DRIVER_EMAIL
"\n");
1124 NV_DEBUG(dev
, "regs mapped ok at 0x%llx\n", offset
);
1126 /* determine frequency of timing crystal */
1127 strap
= nv_rd32(dev
, 0x101000);
1128 if ( dev_priv
->chipset
< 0x17 ||
1129 (dev_priv
->chipset
>= 0x20 && dev_priv
->chipset
<= 0x25))
1130 strap
&= 0x00000040;
1132 strap
&= 0x00400040;
1135 case 0x00000000: dev_priv
->crystal
= 13500; break;
1136 case 0x00000040: dev_priv
->crystal
= 14318; break;
1137 case 0x00400000: dev_priv
->crystal
= 27000; break;
1138 case 0x00400040: dev_priv
->crystal
= 25000; break;
1141 NV_DEBUG(dev
, "crystal freq: %dKHz\n", dev_priv
->crystal
);
1143 /* Determine whether we'll attempt acceleration or not, some
1144 * cards are disabled by default here due to them being known
1145 * non-functional, or never been tested due to lack of hw.
1147 dev_priv
->noaccel
= !!nouveau_noaccel
;
1148 if (nouveau_noaccel
== -1) {
1149 switch (dev_priv
->chipset
) {
1150 case 0xd9: /* known broken */
1151 case 0xe4: /* needs binary driver firmware */
1152 case 0xe7: /* needs binary driver firmware */
1153 NV_INFO(dev
, "acceleration disabled by default, pass "
1154 "noaccel=0 to force enable\n");
1155 dev_priv
->noaccel
= true;
1158 dev_priv
->noaccel
= false;
1163 ret
= nouveau_remove_conflicting_drivers(dev
);
1167 /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1168 if (dev_priv
->card_type
>= NV_40
) {
1170 if (pci_resource_len(dev
->pdev
, ramin_bar
) == 0)
1173 dev_priv
->ramin_size
= pci_resource_len(dev
->pdev
, ramin_bar
);
1175 ioremap(pci_resource_start(dev
->pdev
, ramin_bar
),
1176 dev_priv
->ramin_size
);
1177 if (!dev_priv
->ramin
) {
1178 NV_ERROR(dev
, "Failed to map PRAMIN BAR\n");
1183 dev_priv
->ramin_size
= 1 * 1024 * 1024;
1184 dev_priv
->ramin
= ioremap(offset
+ NV_RAMIN
,
1185 dev_priv
->ramin_size
);
1186 if (!dev_priv
->ramin
) {
1187 NV_ERROR(dev
, "Failed to map BAR0 PRAMIN.\n");
1193 nouveau_OF_copy_vbios_to_ramin(dev
);
1196 if (dev
->pci_device
== 0x01a0)
1197 dev_priv
->flags
|= NV_NFORCE
;
1198 else if (dev
->pci_device
== 0x01f0)
1199 dev_priv
->flags
|= NV_NFORCE2
;
1201 /* For kernel modesetting, init card now and bring up fbcon */
1202 ret
= nouveau_card_init(dev
);
1209 iounmap(dev_priv
->ramin
);
1211 iounmap(dev_priv
->mmio
);
1214 dev
->dev_private
= NULL
;
1219 void nouveau_lastclose(struct drm_device
*dev
)
1221 vga_switcheroo_process_delayed_switch();
1224 int nouveau_unload(struct drm_device
*dev
)
1226 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1228 nouveau_card_takedown(dev
);
1230 iounmap(dev_priv
->mmio
);
1231 iounmap(dev_priv
->ramin
);
1234 dev
->dev_private
= NULL
;
1238 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1240 nouveau_wait_eq(struct drm_device
*dev
, uint64_t timeout
,
1241 uint32_t reg
, uint32_t mask
, uint32_t val
)
1243 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1244 struct nouveau_timer_engine
*ptimer
= &dev_priv
->engine
.timer
;
1245 uint64_t start
= ptimer
->read(dev
);
1248 if ((nv_rd32(dev
, reg
) & mask
) == val
)
1250 } while (ptimer
->read(dev
) - start
< timeout
);
1255 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1257 nouveau_wait_ne(struct drm_device
*dev
, uint64_t timeout
,
1258 uint32_t reg
, uint32_t mask
, uint32_t val
)
1260 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1261 struct nouveau_timer_engine
*ptimer
= &dev_priv
->engine
.timer
;
1262 uint64_t start
= ptimer
->read(dev
);
1265 if ((nv_rd32(dev
, reg
) & mask
) != val
)
1267 } while (ptimer
->read(dev
) - start
< timeout
);
1272 /* Wait until cond(data) == true, up until timeout has hit */
1274 nouveau_wait_cb(struct drm_device
*dev
, u64 timeout
,
1275 bool (*cond
)(void *), void *data
)
1277 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1278 struct nouveau_timer_engine
*ptimer
= &dev_priv
->engine
.timer
;
1279 u64 start
= ptimer
->read(dev
);
1282 if (cond(data
) == true)
1284 } while (ptimer
->read(dev
) - start
< timeout
);
1289 /* Waits for PGRAPH to go completely idle */
1290 bool nouveau_wait_for_idle(struct drm_device
*dev
)
1292 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1295 if (dev_priv
->card_type
== NV_40
)
1296 mask
&= ~NV40_PGRAPH_STATUS_SYNC_STALL
;
1298 if (!nv_wait(dev
, NV04_PGRAPH_STATUS
, mask
, 0)) {
1299 NV_ERROR(dev
, "PGRAPH idle timed out with status 0x%08x\n",
1300 nv_rd32(dev
, NV04_PGRAPH_STATUS
));