2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #include <linux/swab.h>
29 #include "drm_sarea.h"
30 #include "drm_crtc_helper.h"
31 #include <linux/vgaarb.h>
32 #include <linux/vga_switcheroo.h>
34 #include "nouveau_drv.h"
35 #include "nouveau_drm.h"
36 #include "nv50_display.h"
38 static int nouveau_stub_init(struct drm_device
*dev
) { return 0; }
39 static void nouveau_stub_takedown(struct drm_device
*dev
) {}
41 static int nouveau_init_engine_ptrs(struct drm_device
*dev
)
43 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
44 struct nouveau_engine
*engine
= &dev_priv
->engine
;
46 switch (dev_priv
->chipset
& 0xf0) {
48 engine
->instmem
.init
= nv04_instmem_init
;
49 engine
->instmem
.takedown
= nv04_instmem_takedown
;
50 engine
->instmem
.suspend
= nv04_instmem_suspend
;
51 engine
->instmem
.resume
= nv04_instmem_resume
;
52 engine
->instmem
.populate
= nv04_instmem_populate
;
53 engine
->instmem
.clear
= nv04_instmem_clear
;
54 engine
->instmem
.bind
= nv04_instmem_bind
;
55 engine
->instmem
.unbind
= nv04_instmem_unbind
;
56 engine
->instmem
.prepare_access
= nv04_instmem_prepare_access
;
57 engine
->instmem
.finish_access
= nv04_instmem_finish_access
;
58 engine
->mc
.init
= nv04_mc_init
;
59 engine
->mc
.takedown
= nv04_mc_takedown
;
60 engine
->timer
.init
= nv04_timer_init
;
61 engine
->timer
.read
= nv04_timer_read
;
62 engine
->timer
.takedown
= nv04_timer_takedown
;
63 engine
->fb
.init
= nv04_fb_init
;
64 engine
->fb
.takedown
= nv04_fb_takedown
;
65 engine
->graph
.grclass
= nv04_graph_grclass
;
66 engine
->graph
.init
= nv04_graph_init
;
67 engine
->graph
.takedown
= nv04_graph_takedown
;
68 engine
->graph
.fifo_access
= nv04_graph_fifo_access
;
69 engine
->graph
.channel
= nv04_graph_channel
;
70 engine
->graph
.create_context
= nv04_graph_create_context
;
71 engine
->graph
.destroy_context
= nv04_graph_destroy_context
;
72 engine
->graph
.load_context
= nv04_graph_load_context
;
73 engine
->graph
.unload_context
= nv04_graph_unload_context
;
74 engine
->fifo
.channels
= 16;
75 engine
->fifo
.init
= nv04_fifo_init
;
76 engine
->fifo
.takedown
= nouveau_stub_takedown
;
77 engine
->fifo
.disable
= nv04_fifo_disable
;
78 engine
->fifo
.enable
= nv04_fifo_enable
;
79 engine
->fifo
.reassign
= nv04_fifo_reassign
;
80 engine
->fifo
.cache_flush
= nv04_fifo_cache_flush
;
81 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
82 engine
->fifo
.channel_id
= nv04_fifo_channel_id
;
83 engine
->fifo
.create_context
= nv04_fifo_create_context
;
84 engine
->fifo
.destroy_context
= nv04_fifo_destroy_context
;
85 engine
->fifo
.load_context
= nv04_fifo_load_context
;
86 engine
->fifo
.unload_context
= nv04_fifo_unload_context
;
89 engine
->instmem
.init
= nv04_instmem_init
;
90 engine
->instmem
.takedown
= nv04_instmem_takedown
;
91 engine
->instmem
.suspend
= nv04_instmem_suspend
;
92 engine
->instmem
.resume
= nv04_instmem_resume
;
93 engine
->instmem
.populate
= nv04_instmem_populate
;
94 engine
->instmem
.clear
= nv04_instmem_clear
;
95 engine
->instmem
.bind
= nv04_instmem_bind
;
96 engine
->instmem
.unbind
= nv04_instmem_unbind
;
97 engine
->instmem
.prepare_access
= nv04_instmem_prepare_access
;
98 engine
->instmem
.finish_access
= nv04_instmem_finish_access
;
99 engine
->mc
.init
= nv04_mc_init
;
100 engine
->mc
.takedown
= nv04_mc_takedown
;
101 engine
->timer
.init
= nv04_timer_init
;
102 engine
->timer
.read
= nv04_timer_read
;
103 engine
->timer
.takedown
= nv04_timer_takedown
;
104 engine
->fb
.init
= nv10_fb_init
;
105 engine
->fb
.takedown
= nv10_fb_takedown
;
106 engine
->fb
.set_region_tiling
= nv10_fb_set_region_tiling
;
107 engine
->graph
.grclass
= nv10_graph_grclass
;
108 engine
->graph
.init
= nv10_graph_init
;
109 engine
->graph
.takedown
= nv10_graph_takedown
;
110 engine
->graph
.channel
= nv10_graph_channel
;
111 engine
->graph
.create_context
= nv10_graph_create_context
;
112 engine
->graph
.destroy_context
= nv10_graph_destroy_context
;
113 engine
->graph
.fifo_access
= nv04_graph_fifo_access
;
114 engine
->graph
.load_context
= nv10_graph_load_context
;
115 engine
->graph
.unload_context
= nv10_graph_unload_context
;
116 engine
->graph
.set_region_tiling
= nv10_graph_set_region_tiling
;
117 engine
->fifo
.channels
= 32;
118 engine
->fifo
.init
= nv10_fifo_init
;
119 engine
->fifo
.takedown
= nouveau_stub_takedown
;
120 engine
->fifo
.disable
= nv04_fifo_disable
;
121 engine
->fifo
.enable
= nv04_fifo_enable
;
122 engine
->fifo
.reassign
= nv04_fifo_reassign
;
123 engine
->fifo
.cache_flush
= nv04_fifo_cache_flush
;
124 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
125 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
126 engine
->fifo
.create_context
= nv10_fifo_create_context
;
127 engine
->fifo
.destroy_context
= nv10_fifo_destroy_context
;
128 engine
->fifo
.load_context
= nv10_fifo_load_context
;
129 engine
->fifo
.unload_context
= nv10_fifo_unload_context
;
132 engine
->instmem
.init
= nv04_instmem_init
;
133 engine
->instmem
.takedown
= nv04_instmem_takedown
;
134 engine
->instmem
.suspend
= nv04_instmem_suspend
;
135 engine
->instmem
.resume
= nv04_instmem_resume
;
136 engine
->instmem
.populate
= nv04_instmem_populate
;
137 engine
->instmem
.clear
= nv04_instmem_clear
;
138 engine
->instmem
.bind
= nv04_instmem_bind
;
139 engine
->instmem
.unbind
= nv04_instmem_unbind
;
140 engine
->instmem
.prepare_access
= nv04_instmem_prepare_access
;
141 engine
->instmem
.finish_access
= nv04_instmem_finish_access
;
142 engine
->mc
.init
= nv04_mc_init
;
143 engine
->mc
.takedown
= nv04_mc_takedown
;
144 engine
->timer
.init
= nv04_timer_init
;
145 engine
->timer
.read
= nv04_timer_read
;
146 engine
->timer
.takedown
= nv04_timer_takedown
;
147 engine
->fb
.init
= nv10_fb_init
;
148 engine
->fb
.takedown
= nv10_fb_takedown
;
149 engine
->fb
.set_region_tiling
= nv10_fb_set_region_tiling
;
150 engine
->graph
.grclass
= nv20_graph_grclass
;
151 engine
->graph
.init
= nv20_graph_init
;
152 engine
->graph
.takedown
= nv20_graph_takedown
;
153 engine
->graph
.channel
= nv10_graph_channel
;
154 engine
->graph
.create_context
= nv20_graph_create_context
;
155 engine
->graph
.destroy_context
= nv20_graph_destroy_context
;
156 engine
->graph
.fifo_access
= nv04_graph_fifo_access
;
157 engine
->graph
.load_context
= nv20_graph_load_context
;
158 engine
->graph
.unload_context
= nv20_graph_unload_context
;
159 engine
->graph
.set_region_tiling
= nv20_graph_set_region_tiling
;
160 engine
->fifo
.channels
= 32;
161 engine
->fifo
.init
= nv10_fifo_init
;
162 engine
->fifo
.takedown
= nouveau_stub_takedown
;
163 engine
->fifo
.disable
= nv04_fifo_disable
;
164 engine
->fifo
.enable
= nv04_fifo_enable
;
165 engine
->fifo
.reassign
= nv04_fifo_reassign
;
166 engine
->fifo
.cache_flush
= nv04_fifo_cache_flush
;
167 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
168 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
169 engine
->fifo
.create_context
= nv10_fifo_create_context
;
170 engine
->fifo
.destroy_context
= nv10_fifo_destroy_context
;
171 engine
->fifo
.load_context
= nv10_fifo_load_context
;
172 engine
->fifo
.unload_context
= nv10_fifo_unload_context
;
175 engine
->instmem
.init
= nv04_instmem_init
;
176 engine
->instmem
.takedown
= nv04_instmem_takedown
;
177 engine
->instmem
.suspend
= nv04_instmem_suspend
;
178 engine
->instmem
.resume
= nv04_instmem_resume
;
179 engine
->instmem
.populate
= nv04_instmem_populate
;
180 engine
->instmem
.clear
= nv04_instmem_clear
;
181 engine
->instmem
.bind
= nv04_instmem_bind
;
182 engine
->instmem
.unbind
= nv04_instmem_unbind
;
183 engine
->instmem
.prepare_access
= nv04_instmem_prepare_access
;
184 engine
->instmem
.finish_access
= nv04_instmem_finish_access
;
185 engine
->mc
.init
= nv04_mc_init
;
186 engine
->mc
.takedown
= nv04_mc_takedown
;
187 engine
->timer
.init
= nv04_timer_init
;
188 engine
->timer
.read
= nv04_timer_read
;
189 engine
->timer
.takedown
= nv04_timer_takedown
;
190 engine
->fb
.init
= nv10_fb_init
;
191 engine
->fb
.takedown
= nv10_fb_takedown
;
192 engine
->fb
.set_region_tiling
= nv10_fb_set_region_tiling
;
193 engine
->graph
.grclass
= nv30_graph_grclass
;
194 engine
->graph
.init
= nv30_graph_init
;
195 engine
->graph
.takedown
= nv20_graph_takedown
;
196 engine
->graph
.fifo_access
= nv04_graph_fifo_access
;
197 engine
->graph
.channel
= nv10_graph_channel
;
198 engine
->graph
.create_context
= nv20_graph_create_context
;
199 engine
->graph
.destroy_context
= nv20_graph_destroy_context
;
200 engine
->graph
.load_context
= nv20_graph_load_context
;
201 engine
->graph
.unload_context
= nv20_graph_unload_context
;
202 engine
->graph
.set_region_tiling
= nv20_graph_set_region_tiling
;
203 engine
->fifo
.channels
= 32;
204 engine
->fifo
.init
= nv10_fifo_init
;
205 engine
->fifo
.takedown
= nouveau_stub_takedown
;
206 engine
->fifo
.disable
= nv04_fifo_disable
;
207 engine
->fifo
.enable
= nv04_fifo_enable
;
208 engine
->fifo
.reassign
= nv04_fifo_reassign
;
209 engine
->fifo
.cache_flush
= nv04_fifo_cache_flush
;
210 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
211 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
212 engine
->fifo
.create_context
= nv10_fifo_create_context
;
213 engine
->fifo
.destroy_context
= nv10_fifo_destroy_context
;
214 engine
->fifo
.load_context
= nv10_fifo_load_context
;
215 engine
->fifo
.unload_context
= nv10_fifo_unload_context
;
219 engine
->instmem
.init
= nv04_instmem_init
;
220 engine
->instmem
.takedown
= nv04_instmem_takedown
;
221 engine
->instmem
.suspend
= nv04_instmem_suspend
;
222 engine
->instmem
.resume
= nv04_instmem_resume
;
223 engine
->instmem
.populate
= nv04_instmem_populate
;
224 engine
->instmem
.clear
= nv04_instmem_clear
;
225 engine
->instmem
.bind
= nv04_instmem_bind
;
226 engine
->instmem
.unbind
= nv04_instmem_unbind
;
227 engine
->instmem
.prepare_access
= nv04_instmem_prepare_access
;
228 engine
->instmem
.finish_access
= nv04_instmem_finish_access
;
229 engine
->mc
.init
= nv40_mc_init
;
230 engine
->mc
.takedown
= nv40_mc_takedown
;
231 engine
->timer
.init
= nv04_timer_init
;
232 engine
->timer
.read
= nv04_timer_read
;
233 engine
->timer
.takedown
= nv04_timer_takedown
;
234 engine
->fb
.init
= nv40_fb_init
;
235 engine
->fb
.takedown
= nv40_fb_takedown
;
236 engine
->fb
.set_region_tiling
= nv40_fb_set_region_tiling
;
237 engine
->graph
.grclass
= nv40_graph_grclass
;
238 engine
->graph
.init
= nv40_graph_init
;
239 engine
->graph
.takedown
= nv40_graph_takedown
;
240 engine
->graph
.fifo_access
= nv04_graph_fifo_access
;
241 engine
->graph
.channel
= nv40_graph_channel
;
242 engine
->graph
.create_context
= nv40_graph_create_context
;
243 engine
->graph
.destroy_context
= nv40_graph_destroy_context
;
244 engine
->graph
.load_context
= nv40_graph_load_context
;
245 engine
->graph
.unload_context
= nv40_graph_unload_context
;
246 engine
->graph
.set_region_tiling
= nv40_graph_set_region_tiling
;
247 engine
->fifo
.channels
= 32;
248 engine
->fifo
.init
= nv40_fifo_init
;
249 engine
->fifo
.takedown
= nouveau_stub_takedown
;
250 engine
->fifo
.disable
= nv04_fifo_disable
;
251 engine
->fifo
.enable
= nv04_fifo_enable
;
252 engine
->fifo
.reassign
= nv04_fifo_reassign
;
253 engine
->fifo
.cache_flush
= nv04_fifo_cache_flush
;
254 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
255 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
256 engine
->fifo
.create_context
= nv40_fifo_create_context
;
257 engine
->fifo
.destroy_context
= nv40_fifo_destroy_context
;
258 engine
->fifo
.load_context
= nv40_fifo_load_context
;
259 engine
->fifo
.unload_context
= nv40_fifo_unload_context
;
262 case 0x80: /* gotta love NVIDIA's consistency.. */
265 engine
->instmem
.init
= nv50_instmem_init
;
266 engine
->instmem
.takedown
= nv50_instmem_takedown
;
267 engine
->instmem
.suspend
= nv50_instmem_suspend
;
268 engine
->instmem
.resume
= nv50_instmem_resume
;
269 engine
->instmem
.populate
= nv50_instmem_populate
;
270 engine
->instmem
.clear
= nv50_instmem_clear
;
271 engine
->instmem
.bind
= nv50_instmem_bind
;
272 engine
->instmem
.unbind
= nv50_instmem_unbind
;
273 engine
->instmem
.prepare_access
= nv50_instmem_prepare_access
;
274 engine
->instmem
.finish_access
= nv50_instmem_finish_access
;
275 engine
->mc
.init
= nv50_mc_init
;
276 engine
->mc
.takedown
= nv50_mc_takedown
;
277 engine
->timer
.init
= nv04_timer_init
;
278 engine
->timer
.read
= nv04_timer_read
;
279 engine
->timer
.takedown
= nv04_timer_takedown
;
280 engine
->fb
.init
= nouveau_stub_init
;
281 engine
->fb
.takedown
= nouveau_stub_takedown
;
282 engine
->graph
.grclass
= nv50_graph_grclass
;
283 engine
->graph
.init
= nv50_graph_init
;
284 engine
->graph
.takedown
= nv50_graph_takedown
;
285 engine
->graph
.fifo_access
= nv50_graph_fifo_access
;
286 engine
->graph
.channel
= nv50_graph_channel
;
287 engine
->graph
.create_context
= nv50_graph_create_context
;
288 engine
->graph
.destroy_context
= nv50_graph_destroy_context
;
289 engine
->graph
.load_context
= nv50_graph_load_context
;
290 engine
->graph
.unload_context
= nv50_graph_unload_context
;
291 engine
->fifo
.channels
= 128;
292 engine
->fifo
.init
= nv50_fifo_init
;
293 engine
->fifo
.takedown
= nv50_fifo_takedown
;
294 engine
->fifo
.disable
= nv04_fifo_disable
;
295 engine
->fifo
.enable
= nv04_fifo_enable
;
296 engine
->fifo
.reassign
= nv04_fifo_reassign
;
297 engine
->fifo
.channel_id
= nv50_fifo_channel_id
;
298 engine
->fifo
.create_context
= nv50_fifo_create_context
;
299 engine
->fifo
.destroy_context
= nv50_fifo_destroy_context
;
300 engine
->fifo
.load_context
= nv50_fifo_load_context
;
301 engine
->fifo
.unload_context
= nv50_fifo_unload_context
;
304 NV_ERROR(dev
, "NV%02x unsupported\n", dev_priv
->chipset
);
312 nouveau_vga_set_decode(void *priv
, bool state
)
314 struct drm_device
*dev
= priv
;
315 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
317 if (dev_priv
->chipset
>= 0x40)
318 nv_wr32(dev
, 0x88054, state
);
320 nv_wr32(dev
, 0x1854, state
);
323 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
324 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
326 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
330 nouveau_card_init_channel(struct drm_device
*dev
)
332 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
333 struct nouveau_gpuobj
*gpuobj
;
336 ret
= nouveau_channel_alloc(dev
, &dev_priv
->channel
,
337 (struct drm_file
*)-2,
343 ret
= nouveau_gpuobj_dma_new(dev_priv
->channel
, NV_CLASS_DMA_IN_MEMORY
,
344 0, nouveau_mem_fb_amount(dev
),
345 NV_DMA_ACCESS_RW
, NV_DMA_TARGET_VIDMEM
,
350 ret
= nouveau_gpuobj_ref_add(dev
, dev_priv
->channel
, NvDmaVRAM
,
356 ret
= nouveau_gpuobj_gart_dma_new(dev_priv
->channel
, 0,
357 dev_priv
->gart_info
.aper_size
,
358 NV_DMA_ACCESS_RW
, &gpuobj
, NULL
);
362 ret
= nouveau_gpuobj_ref_add(dev
, dev_priv
->channel
, NvDmaGART
,
369 nouveau_gpuobj_del(dev
, &gpuobj
);
370 nouveau_channel_free(dev_priv
->channel
);
371 dev_priv
->channel
= NULL
;
375 static void nouveau_switcheroo_set_state(struct pci_dev
*pdev
,
376 enum vga_switcheroo_state state
)
378 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
379 if (state
== VGA_SWITCHEROO_ON
) {
380 printk(KERN_ERR
"VGA switcheroo: switched nouveau on\n");
381 nouveau_pci_resume(pdev
);
383 printk(KERN_ERR
"VGA switcheroo: switched nouveau off\n");
384 nouveau_pci_suspend(pdev
, pmm
);
388 static bool nouveau_switcheroo_can_switch(struct pci_dev
*pdev
)
390 struct drm_device
*dev
= pci_get_drvdata(pdev
);
393 spin_lock(&dev
->count_lock
);
394 can_switch
= (dev
->open_count
== 0);
395 spin_unlock(&dev
->count_lock
);
400 nouveau_card_init(struct drm_device
*dev
)
402 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
403 struct nouveau_engine
*engine
;
406 NV_DEBUG(dev
, "prev state = %d\n", dev_priv
->init_state
);
408 if (dev_priv
->init_state
== NOUVEAU_CARD_INIT_DONE
)
411 vga_client_register(dev
->pdev
, dev
, NULL
, nouveau_vga_set_decode
);
412 vga_switcheroo_register_client(dev
->pdev
, nouveau_switcheroo_set_state
,
413 nouveau_switcheroo_can_switch
);
415 /* Initialise internal driver API hooks */
416 ret
= nouveau_init_engine_ptrs(dev
);
419 engine
= &dev_priv
->engine
;
420 dev_priv
->init_state
= NOUVEAU_CARD_INIT_FAILED
;
421 spin_lock_init(&dev_priv
->context_switch_lock
);
423 /* Parse BIOS tables / Run init tables if card not POSTed */
424 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
425 ret
= nouveau_bios_init(dev
);
430 ret
= nouveau_gpuobj_early_init(dev
);
434 /* Initialise instance memory, must happen before mem_init so we
435 * know exactly how much VRAM we're able to use for "normal"
438 ret
= engine
->instmem
.init(dev
);
440 goto out_gpuobj_early
;
442 /* Setup the memory manager */
443 ret
= nouveau_mem_init(dev
);
447 ret
= nouveau_gpuobj_init(dev
);
452 ret
= engine
->mc
.init(dev
);
457 ret
= engine
->timer
.init(dev
);
462 ret
= engine
->fb
.init(dev
);
467 engine
->graph
.accel_blocked
= true;
470 ret
= engine
->graph
.init(dev
);
475 ret
= engine
->fifo
.init(dev
);
480 /* this call irq_preinstall, register irq handler and
481 * call irq_postinstall
483 ret
= drm_irq_install(dev
);
487 ret
= drm_vblank_init(dev
, 0);
491 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
493 if (!engine
->graph
.accel_blocked
) {
494 ret
= nouveau_card_init_channel(dev
);
499 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
500 if (dev_priv
->card_type
>= NV_50
)
501 ret
= nv50_display_create(dev
);
503 ret
= nv04_display_create(dev
);
508 ret
= nouveau_backlight_init(dev
);
510 NV_ERROR(dev
, "Error %d registering backlight\n", ret
);
512 dev_priv
->init_state
= NOUVEAU_CARD_INIT_DONE
;
514 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
515 drm_helper_initial_config(dev
);
520 drm_irq_uninstall(dev
);
522 if (!nouveau_noaccel
)
523 engine
->fifo
.takedown(dev
);
525 if (!nouveau_noaccel
)
526 engine
->graph
.takedown(dev
);
528 engine
->fb
.takedown(dev
);
530 engine
->timer
.takedown(dev
);
532 engine
->mc
.takedown(dev
);
534 nouveau_gpuobj_takedown(dev
);
536 nouveau_mem_close(dev
);
538 engine
->instmem
.takedown(dev
);
540 nouveau_gpuobj_late_takedown(dev
);
542 nouveau_bios_takedown(dev
);
544 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
548 static void nouveau_card_takedown(struct drm_device
*dev
)
550 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
551 struct nouveau_engine
*engine
= &dev_priv
->engine
;
553 NV_DEBUG(dev
, "prev state = %d\n", dev_priv
->init_state
);
555 if (dev_priv
->init_state
!= NOUVEAU_CARD_INIT_DOWN
) {
556 nouveau_backlight_exit(dev
);
558 if (dev_priv
->channel
) {
559 nouveau_channel_free(dev_priv
->channel
);
560 dev_priv
->channel
= NULL
;
563 if (!nouveau_noaccel
) {
564 engine
->fifo
.takedown(dev
);
565 engine
->graph
.takedown(dev
);
567 engine
->fb
.takedown(dev
);
568 engine
->timer
.takedown(dev
);
569 engine
->mc
.takedown(dev
);
571 mutex_lock(&dev
->struct_mutex
);
572 ttm_bo_clean_mm(&dev_priv
->ttm
.bdev
, TTM_PL_VRAM
);
573 ttm_bo_clean_mm(&dev_priv
->ttm
.bdev
, TTM_PL_TT
);
574 mutex_unlock(&dev
->struct_mutex
);
575 nouveau_sgdma_takedown(dev
);
577 nouveau_gpuobj_takedown(dev
);
578 nouveau_mem_close(dev
);
579 engine
->instmem
.takedown(dev
);
581 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
582 drm_irq_uninstall(dev
);
584 nouveau_gpuobj_late_takedown(dev
);
585 nouveau_bios_takedown(dev
);
587 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
589 dev_priv
->init_state
= NOUVEAU_CARD_INIT_DOWN
;
593 /* here a client dies, release the stuff that was allocated for its
595 void nouveau_preclose(struct drm_device
*dev
, struct drm_file
*file_priv
)
597 nouveau_channel_cleanup(dev
, file_priv
);
600 /* first module load, setup the mmio/fb mapping */
601 /* KMS: we need mmio at load time, not when the first drm client opens. */
602 int nouveau_firstopen(struct drm_device
*dev
)
607 /* if we have an OF card, copy vbios to RAMIN */
608 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device
*dev
)
610 #if defined(__powerpc__)
612 const uint32_t *bios
;
613 struct device_node
*dn
= pci_device_to_OF_node(dev
->pdev
);
615 NV_INFO(dev
, "Unable to get the OF node\n");
619 bios
= of_get_property(dn
, "NVDA,BMP", &size
);
621 for (i
= 0; i
< size
; i
+= 4)
622 nv_wi32(dev
, i
, bios
[i
/4]);
623 NV_INFO(dev
, "OF bios successfully copied (%d bytes)\n", size
);
625 NV_INFO(dev
, "Unable to get the OF bios\n");
630 int nouveau_load(struct drm_device
*dev
, unsigned long flags
)
632 struct drm_nouveau_private
*dev_priv
;
634 resource_size_t mmio_start_offs
;
636 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
639 dev
->dev_private
= dev_priv
;
642 dev_priv
->flags
= flags
& NOUVEAU_FLAGS
;
643 dev_priv
->init_state
= NOUVEAU_CARD_INIT_DOWN
;
645 NV_DEBUG(dev
, "vendor: 0x%X device: 0x%X class: 0x%X\n",
646 dev
->pci_vendor
, dev
->pci_device
, dev
->pdev
->class);
648 dev_priv
->wq
= create_workqueue("nouveau");
652 /* resource 0 is mmio regs */
653 /* resource 1 is linear FB */
654 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
655 /* resource 6 is bios */
657 /* map the mmio regs */
658 mmio_start_offs
= pci_resource_start(dev
->pdev
, 0);
659 dev_priv
->mmio
= ioremap(mmio_start_offs
, 0x00800000);
660 if (!dev_priv
->mmio
) {
661 NV_ERROR(dev
, "Unable to initialize the mmio mapping. "
662 "Please report your setup to " DRIVER_EMAIL
"\n");
665 NV_DEBUG(dev
, "regs mapped ok at 0x%llx\n",
666 (unsigned long long)mmio_start_offs
);
669 /* Put the card in BE mode if it's not */
670 if (nv_rd32(dev
, NV03_PMC_BOOT_1
))
671 nv_wr32(dev
, NV03_PMC_BOOT_1
, 0x00000001);
676 /* Time to determine the card architecture */
677 reg0
= nv_rd32(dev
, NV03_PMC_BOOT_0
);
679 /* We're dealing with >=NV10 */
680 if ((reg0
& 0x0f000000) > 0) {
681 /* Bit 27-20 contain the architecture in hex */
682 dev_priv
->chipset
= (reg0
& 0xff00000) >> 20;
684 } else if ((reg0
& 0xff00fff0) == 0x20004000) {
685 if (reg0
& 0x00f00000)
686 dev_priv
->chipset
= 0x05;
688 dev_priv
->chipset
= 0x04;
690 dev_priv
->chipset
= 0xff;
692 switch (dev_priv
->chipset
& 0xf0) {
697 dev_priv
->card_type
= dev_priv
->chipset
& 0xf0;
701 dev_priv
->card_type
= NV_40
;
707 dev_priv
->card_type
= NV_50
;
710 NV_INFO(dev
, "Unsupported chipset 0x%08x\n", reg0
);
714 NV_INFO(dev
, "Detected an NV%2x generation card (0x%08x)\n",
715 dev_priv
->card_type
, reg0
);
717 /* map larger RAMIN aperture on NV40 cards */
718 dev_priv
->ramin
= NULL
;
719 if (dev_priv
->card_type
>= NV_40
) {
721 if (pci_resource_len(dev
->pdev
, ramin_bar
) == 0)
724 dev_priv
->ramin_size
= pci_resource_len(dev
->pdev
, ramin_bar
);
725 dev_priv
->ramin
= ioremap(
726 pci_resource_start(dev
->pdev
, ramin_bar
),
727 dev_priv
->ramin_size
);
728 if (!dev_priv
->ramin
) {
729 NV_ERROR(dev
, "Failed to init RAMIN mapping, "
730 "limited instance memory available\n");
734 /* On older cards (or if the above failed), create a map covering
735 * the BAR0 PRAMIN aperture */
736 if (!dev_priv
->ramin
) {
737 dev_priv
->ramin_size
= 1 * 1024 * 1024;
738 dev_priv
->ramin
= ioremap(mmio_start_offs
+ NV_RAMIN
,
739 dev_priv
->ramin_size
);
740 if (!dev_priv
->ramin
) {
741 NV_ERROR(dev
, "Failed to map BAR0 PRAMIN.\n");
746 nouveau_OF_copy_vbios_to_ramin(dev
);
749 if (dev
->pci_device
== 0x01a0)
750 dev_priv
->flags
|= NV_NFORCE
;
751 else if (dev
->pci_device
== 0x01f0)
752 dev_priv
->flags
|= NV_NFORCE2
;
754 /* For kernel modesetting, init card now and bring up fbcon */
755 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
756 int ret
= nouveau_card_init(dev
);
764 static void nouveau_close(struct drm_device
*dev
)
766 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
768 /* In the case of an error dev_priv may not be allocated yet */
770 nouveau_card_takedown(dev
);
773 /* KMS: we need mmio at load time, not when the first drm client opens. */
774 void nouveau_lastclose(struct drm_device
*dev
)
776 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
782 int nouveau_unload(struct drm_device
*dev
)
784 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
786 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
787 if (dev_priv
->card_type
>= NV_50
)
788 nv50_display_destroy(dev
);
790 nv04_display_destroy(dev
);
794 iounmap(dev_priv
->mmio
);
795 iounmap(dev_priv
->ramin
);
798 dev
->dev_private
= NULL
;
802 int nouveau_ioctl_getparam(struct drm_device
*dev
, void *data
,
803 struct drm_file
*file_priv
)
805 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
806 struct drm_nouveau_getparam
*getparam
= data
;
808 NOUVEAU_CHECK_INITIALISED_WITH_RETURN
;
810 switch (getparam
->param
) {
811 case NOUVEAU_GETPARAM_CHIPSET_ID
:
812 getparam
->value
= dev_priv
->chipset
;
814 case NOUVEAU_GETPARAM_PCI_VENDOR
:
815 getparam
->value
= dev
->pci_vendor
;
817 case NOUVEAU_GETPARAM_PCI_DEVICE
:
818 getparam
->value
= dev
->pci_device
;
820 case NOUVEAU_GETPARAM_BUS_TYPE
:
821 if (drm_device_is_agp(dev
))
822 getparam
->value
= NV_AGP
;
823 else if (drm_device_is_pcie(dev
))
824 getparam
->value
= NV_PCIE
;
826 getparam
->value
= NV_PCI
;
828 case NOUVEAU_GETPARAM_FB_PHYSICAL
:
829 getparam
->value
= dev_priv
->fb_phys
;
831 case NOUVEAU_GETPARAM_AGP_PHYSICAL
:
832 getparam
->value
= dev_priv
->gart_info
.aper_base
;
834 case NOUVEAU_GETPARAM_PCI_PHYSICAL
:
836 getparam
->value
= (unsigned long)dev
->sg
->virtual;
838 NV_ERROR(dev
, "Requested PCIGART address, "
839 "while no PCIGART was created\n");
843 case NOUVEAU_GETPARAM_FB_SIZE
:
844 getparam
->value
= dev_priv
->fb_available_size
;
846 case NOUVEAU_GETPARAM_AGP_SIZE
:
847 getparam
->value
= dev_priv
->gart_info
.aper_size
;
849 case NOUVEAU_GETPARAM_VM_VRAM_BASE
:
850 getparam
->value
= dev_priv
->vm_vram_base
;
852 case NOUVEAU_GETPARAM_GRAPH_UNITS
:
853 /* NV40 and NV50 versions are quite different, but register
854 * address is the same. User is supposed to know the card
855 * family anyway... */
856 if (dev_priv
->chipset
>= 0x40) {
857 getparam
->value
= nv_rd32(dev
, NV40_PMC_GRAPH_UNITS
);
862 NV_ERROR(dev
, "unknown parameter %lld\n", getparam
->param
);
870 nouveau_ioctl_setparam(struct drm_device
*dev
, void *data
,
871 struct drm_file
*file_priv
)
873 struct drm_nouveau_setparam
*setparam
= data
;
875 NOUVEAU_CHECK_INITIALISED_WITH_RETURN
;
877 switch (setparam
->param
) {
879 NV_ERROR(dev
, "unknown parameter %lld\n", setparam
->param
);
886 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
887 bool nouveau_wait_until(struct drm_device
*dev
, uint64_t timeout
,
888 uint32_t reg
, uint32_t mask
, uint32_t val
)
890 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
891 struct nouveau_timer_engine
*ptimer
= &dev_priv
->engine
.timer
;
892 uint64_t start
= ptimer
->read(dev
);
895 if ((nv_rd32(dev
, reg
) & mask
) == val
)
897 } while (ptimer
->read(dev
) - start
< timeout
);
902 /* Waits for PGRAPH to go completely idle */
903 bool nouveau_wait_for_idle(struct drm_device
*dev
)
905 if (!nv_wait(NV04_PGRAPH_STATUS
, 0xffffffff, 0x00000000)) {
906 NV_ERROR(dev
, "PGRAPH idle timed out with status 0x%08x\n",
907 nv_rd32(dev
, NV04_PGRAPH_STATUS
));