2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #include <linux/swab.h>
27 #include <linux/slab.h>
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_pm.h"
40 #include "nv50_display.h"
42 static void nouveau_stub_takedown(struct drm_device
*dev
) {}
43 static int nouveau_stub_init(struct drm_device
*dev
) { return 0; }
45 static int nouveau_init_engine_ptrs(struct drm_device
*dev
)
47 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
48 struct nouveau_engine
*engine
= &dev_priv
->engine
;
50 switch (dev_priv
->chipset
& 0xf0) {
52 engine
->instmem
.init
= nv04_instmem_init
;
53 engine
->instmem
.takedown
= nv04_instmem_takedown
;
54 engine
->instmem
.suspend
= nv04_instmem_suspend
;
55 engine
->instmem
.resume
= nv04_instmem_resume
;
56 engine
->instmem
.get
= nv04_instmem_get
;
57 engine
->instmem
.put
= nv04_instmem_put
;
58 engine
->instmem
.map
= nv04_instmem_map
;
59 engine
->instmem
.unmap
= nv04_instmem_unmap
;
60 engine
->instmem
.flush
= nv04_instmem_flush
;
61 engine
->mc
.init
= nv04_mc_init
;
62 engine
->mc
.takedown
= nv04_mc_takedown
;
63 engine
->timer
.init
= nv04_timer_init
;
64 engine
->timer
.read
= nv04_timer_read
;
65 engine
->timer
.takedown
= nv04_timer_takedown
;
66 engine
->fb
.init
= nv04_fb_init
;
67 engine
->fb
.takedown
= nv04_fb_takedown
;
68 engine
->fifo
.channels
= 16;
69 engine
->fifo
.init
= nv04_fifo_init
;
70 engine
->fifo
.takedown
= nv04_fifo_fini
;
71 engine
->fifo
.disable
= nv04_fifo_disable
;
72 engine
->fifo
.enable
= nv04_fifo_enable
;
73 engine
->fifo
.reassign
= nv04_fifo_reassign
;
74 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
75 engine
->fifo
.channel_id
= nv04_fifo_channel_id
;
76 engine
->fifo
.create_context
= nv04_fifo_create_context
;
77 engine
->fifo
.destroy_context
= nv04_fifo_destroy_context
;
78 engine
->fifo
.load_context
= nv04_fifo_load_context
;
79 engine
->fifo
.unload_context
= nv04_fifo_unload_context
;
80 engine
->display
.early_init
= nv04_display_early_init
;
81 engine
->display
.late_takedown
= nv04_display_late_takedown
;
82 engine
->display
.create
= nv04_display_create
;
83 engine
->display
.init
= nv04_display_init
;
84 engine
->display
.destroy
= nv04_display_destroy
;
85 engine
->gpio
.init
= nouveau_stub_init
;
86 engine
->gpio
.takedown
= nouveau_stub_takedown
;
87 engine
->gpio
.get
= NULL
;
88 engine
->gpio
.set
= NULL
;
89 engine
->gpio
.irq_enable
= NULL
;
90 engine
->pm
.clock_get
= nv04_pm_clock_get
;
91 engine
->pm
.clock_pre
= nv04_pm_clock_pre
;
92 engine
->pm
.clock_set
= nv04_pm_clock_set
;
93 engine
->vram
.init
= nouveau_mem_detect
;
94 engine
->vram
.flags_valid
= nouveau_mem_flags_valid
;
97 engine
->instmem
.init
= nv04_instmem_init
;
98 engine
->instmem
.takedown
= nv04_instmem_takedown
;
99 engine
->instmem
.suspend
= nv04_instmem_suspend
;
100 engine
->instmem
.resume
= nv04_instmem_resume
;
101 engine
->instmem
.get
= nv04_instmem_get
;
102 engine
->instmem
.put
= nv04_instmem_put
;
103 engine
->instmem
.map
= nv04_instmem_map
;
104 engine
->instmem
.unmap
= nv04_instmem_unmap
;
105 engine
->instmem
.flush
= nv04_instmem_flush
;
106 engine
->mc
.init
= nv04_mc_init
;
107 engine
->mc
.takedown
= nv04_mc_takedown
;
108 engine
->timer
.init
= nv04_timer_init
;
109 engine
->timer
.read
= nv04_timer_read
;
110 engine
->timer
.takedown
= nv04_timer_takedown
;
111 engine
->fb
.init
= nv10_fb_init
;
112 engine
->fb
.takedown
= nv10_fb_takedown
;
113 engine
->fb
.init_tile_region
= nv10_fb_init_tile_region
;
114 engine
->fb
.set_tile_region
= nv10_fb_set_tile_region
;
115 engine
->fb
.free_tile_region
= nv10_fb_free_tile_region
;
116 engine
->fifo
.channels
= 32;
117 engine
->fifo
.init
= nv10_fifo_init
;
118 engine
->fifo
.takedown
= nv04_fifo_fini
;
119 engine
->fifo
.disable
= nv04_fifo_disable
;
120 engine
->fifo
.enable
= nv04_fifo_enable
;
121 engine
->fifo
.reassign
= nv04_fifo_reassign
;
122 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
123 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
124 engine
->fifo
.create_context
= nv10_fifo_create_context
;
125 engine
->fifo
.destroy_context
= nv04_fifo_destroy_context
;
126 engine
->fifo
.load_context
= nv10_fifo_load_context
;
127 engine
->fifo
.unload_context
= nv10_fifo_unload_context
;
128 engine
->display
.early_init
= nv04_display_early_init
;
129 engine
->display
.late_takedown
= nv04_display_late_takedown
;
130 engine
->display
.create
= nv04_display_create
;
131 engine
->display
.init
= nv04_display_init
;
132 engine
->display
.destroy
= nv04_display_destroy
;
133 engine
->gpio
.init
= nouveau_stub_init
;
134 engine
->gpio
.takedown
= nouveau_stub_takedown
;
135 engine
->gpio
.get
= nv10_gpio_get
;
136 engine
->gpio
.set
= nv10_gpio_set
;
137 engine
->gpio
.irq_enable
= NULL
;
138 engine
->pm
.clock_get
= nv04_pm_clock_get
;
139 engine
->pm
.clock_pre
= nv04_pm_clock_pre
;
140 engine
->pm
.clock_set
= nv04_pm_clock_set
;
141 engine
->vram
.init
= nouveau_mem_detect
;
142 engine
->vram
.flags_valid
= nouveau_mem_flags_valid
;
145 engine
->instmem
.init
= nv04_instmem_init
;
146 engine
->instmem
.takedown
= nv04_instmem_takedown
;
147 engine
->instmem
.suspend
= nv04_instmem_suspend
;
148 engine
->instmem
.resume
= nv04_instmem_resume
;
149 engine
->instmem
.get
= nv04_instmem_get
;
150 engine
->instmem
.put
= nv04_instmem_put
;
151 engine
->instmem
.map
= nv04_instmem_map
;
152 engine
->instmem
.unmap
= nv04_instmem_unmap
;
153 engine
->instmem
.flush
= nv04_instmem_flush
;
154 engine
->mc
.init
= nv04_mc_init
;
155 engine
->mc
.takedown
= nv04_mc_takedown
;
156 engine
->timer
.init
= nv04_timer_init
;
157 engine
->timer
.read
= nv04_timer_read
;
158 engine
->timer
.takedown
= nv04_timer_takedown
;
159 engine
->fb
.init
= nv10_fb_init
;
160 engine
->fb
.takedown
= nv10_fb_takedown
;
161 engine
->fb
.init_tile_region
= nv10_fb_init_tile_region
;
162 engine
->fb
.set_tile_region
= nv10_fb_set_tile_region
;
163 engine
->fb
.free_tile_region
= nv10_fb_free_tile_region
;
164 engine
->fifo
.channels
= 32;
165 engine
->fifo
.init
= nv10_fifo_init
;
166 engine
->fifo
.takedown
= nv04_fifo_fini
;
167 engine
->fifo
.disable
= nv04_fifo_disable
;
168 engine
->fifo
.enable
= nv04_fifo_enable
;
169 engine
->fifo
.reassign
= nv04_fifo_reassign
;
170 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
171 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
172 engine
->fifo
.create_context
= nv10_fifo_create_context
;
173 engine
->fifo
.destroy_context
= nv04_fifo_destroy_context
;
174 engine
->fifo
.load_context
= nv10_fifo_load_context
;
175 engine
->fifo
.unload_context
= nv10_fifo_unload_context
;
176 engine
->display
.early_init
= nv04_display_early_init
;
177 engine
->display
.late_takedown
= nv04_display_late_takedown
;
178 engine
->display
.create
= nv04_display_create
;
179 engine
->display
.init
= nv04_display_init
;
180 engine
->display
.destroy
= nv04_display_destroy
;
181 engine
->gpio
.init
= nouveau_stub_init
;
182 engine
->gpio
.takedown
= nouveau_stub_takedown
;
183 engine
->gpio
.get
= nv10_gpio_get
;
184 engine
->gpio
.set
= nv10_gpio_set
;
185 engine
->gpio
.irq_enable
= NULL
;
186 engine
->pm
.clock_get
= nv04_pm_clock_get
;
187 engine
->pm
.clock_pre
= nv04_pm_clock_pre
;
188 engine
->pm
.clock_set
= nv04_pm_clock_set
;
189 engine
->vram
.init
= nouveau_mem_detect
;
190 engine
->vram
.flags_valid
= nouveau_mem_flags_valid
;
193 engine
->instmem
.init
= nv04_instmem_init
;
194 engine
->instmem
.takedown
= nv04_instmem_takedown
;
195 engine
->instmem
.suspend
= nv04_instmem_suspend
;
196 engine
->instmem
.resume
= nv04_instmem_resume
;
197 engine
->instmem
.get
= nv04_instmem_get
;
198 engine
->instmem
.put
= nv04_instmem_put
;
199 engine
->instmem
.map
= nv04_instmem_map
;
200 engine
->instmem
.unmap
= nv04_instmem_unmap
;
201 engine
->instmem
.flush
= nv04_instmem_flush
;
202 engine
->mc
.init
= nv04_mc_init
;
203 engine
->mc
.takedown
= nv04_mc_takedown
;
204 engine
->timer
.init
= nv04_timer_init
;
205 engine
->timer
.read
= nv04_timer_read
;
206 engine
->timer
.takedown
= nv04_timer_takedown
;
207 engine
->fb
.init
= nv30_fb_init
;
208 engine
->fb
.takedown
= nv30_fb_takedown
;
209 engine
->fb
.init_tile_region
= nv30_fb_init_tile_region
;
210 engine
->fb
.set_tile_region
= nv10_fb_set_tile_region
;
211 engine
->fb
.free_tile_region
= nv30_fb_free_tile_region
;
212 engine
->fifo
.channels
= 32;
213 engine
->fifo
.init
= nv10_fifo_init
;
214 engine
->fifo
.takedown
= nv04_fifo_fini
;
215 engine
->fifo
.disable
= nv04_fifo_disable
;
216 engine
->fifo
.enable
= nv04_fifo_enable
;
217 engine
->fifo
.reassign
= nv04_fifo_reassign
;
218 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
219 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
220 engine
->fifo
.create_context
= nv10_fifo_create_context
;
221 engine
->fifo
.destroy_context
= nv04_fifo_destroy_context
;
222 engine
->fifo
.load_context
= nv10_fifo_load_context
;
223 engine
->fifo
.unload_context
= nv10_fifo_unload_context
;
224 engine
->display
.early_init
= nv04_display_early_init
;
225 engine
->display
.late_takedown
= nv04_display_late_takedown
;
226 engine
->display
.create
= nv04_display_create
;
227 engine
->display
.init
= nv04_display_init
;
228 engine
->display
.destroy
= nv04_display_destroy
;
229 engine
->gpio
.init
= nouveau_stub_init
;
230 engine
->gpio
.takedown
= nouveau_stub_takedown
;
231 engine
->gpio
.get
= nv10_gpio_get
;
232 engine
->gpio
.set
= nv10_gpio_set
;
233 engine
->gpio
.irq_enable
= NULL
;
234 engine
->pm
.clock_get
= nv04_pm_clock_get
;
235 engine
->pm
.clock_pre
= nv04_pm_clock_pre
;
236 engine
->pm
.clock_set
= nv04_pm_clock_set
;
237 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
238 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
239 engine
->vram
.init
= nouveau_mem_detect
;
240 engine
->vram
.flags_valid
= nouveau_mem_flags_valid
;
244 engine
->instmem
.init
= nv04_instmem_init
;
245 engine
->instmem
.takedown
= nv04_instmem_takedown
;
246 engine
->instmem
.suspend
= nv04_instmem_suspend
;
247 engine
->instmem
.resume
= nv04_instmem_resume
;
248 engine
->instmem
.get
= nv04_instmem_get
;
249 engine
->instmem
.put
= nv04_instmem_put
;
250 engine
->instmem
.map
= nv04_instmem_map
;
251 engine
->instmem
.unmap
= nv04_instmem_unmap
;
252 engine
->instmem
.flush
= nv04_instmem_flush
;
253 engine
->mc
.init
= nv40_mc_init
;
254 engine
->mc
.takedown
= nv40_mc_takedown
;
255 engine
->timer
.init
= nv04_timer_init
;
256 engine
->timer
.read
= nv04_timer_read
;
257 engine
->timer
.takedown
= nv04_timer_takedown
;
258 engine
->fb
.init
= nv40_fb_init
;
259 engine
->fb
.takedown
= nv40_fb_takedown
;
260 engine
->fb
.init_tile_region
= nv30_fb_init_tile_region
;
261 engine
->fb
.set_tile_region
= nv40_fb_set_tile_region
;
262 engine
->fb
.free_tile_region
= nv30_fb_free_tile_region
;
263 engine
->fifo
.channels
= 32;
264 engine
->fifo
.init
= nv40_fifo_init
;
265 engine
->fifo
.takedown
= nv04_fifo_fini
;
266 engine
->fifo
.disable
= nv04_fifo_disable
;
267 engine
->fifo
.enable
= nv04_fifo_enable
;
268 engine
->fifo
.reassign
= nv04_fifo_reassign
;
269 engine
->fifo
.cache_pull
= nv04_fifo_cache_pull
;
270 engine
->fifo
.channel_id
= nv10_fifo_channel_id
;
271 engine
->fifo
.create_context
= nv40_fifo_create_context
;
272 engine
->fifo
.destroy_context
= nv04_fifo_destroy_context
;
273 engine
->fifo
.load_context
= nv40_fifo_load_context
;
274 engine
->fifo
.unload_context
= nv40_fifo_unload_context
;
275 engine
->display
.early_init
= nv04_display_early_init
;
276 engine
->display
.late_takedown
= nv04_display_late_takedown
;
277 engine
->display
.create
= nv04_display_create
;
278 engine
->display
.init
= nv04_display_init
;
279 engine
->display
.destroy
= nv04_display_destroy
;
280 engine
->gpio
.init
= nouveau_stub_init
;
281 engine
->gpio
.takedown
= nouveau_stub_takedown
;
282 engine
->gpio
.get
= nv10_gpio_get
;
283 engine
->gpio
.set
= nv10_gpio_set
;
284 engine
->gpio
.irq_enable
= NULL
;
285 engine
->pm
.clock_get
= nv04_pm_clock_get
;
286 engine
->pm
.clock_pre
= nv04_pm_clock_pre
;
287 engine
->pm
.clock_set
= nv04_pm_clock_set
;
288 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
289 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
290 engine
->pm
.temp_get
= nv40_temp_get
;
291 engine
->vram
.init
= nouveau_mem_detect
;
292 engine
->vram
.flags_valid
= nouveau_mem_flags_valid
;
295 case 0x80: /* gotta love NVIDIA's consistency.. */
298 engine
->instmem
.init
= nv50_instmem_init
;
299 engine
->instmem
.takedown
= nv50_instmem_takedown
;
300 engine
->instmem
.suspend
= nv50_instmem_suspend
;
301 engine
->instmem
.resume
= nv50_instmem_resume
;
302 engine
->instmem
.get
= nv50_instmem_get
;
303 engine
->instmem
.put
= nv50_instmem_put
;
304 engine
->instmem
.map
= nv50_instmem_map
;
305 engine
->instmem
.unmap
= nv50_instmem_unmap
;
306 if (dev_priv
->chipset
== 0x50)
307 engine
->instmem
.flush
= nv50_instmem_flush
;
309 engine
->instmem
.flush
= nv84_instmem_flush
;
310 engine
->mc
.init
= nv50_mc_init
;
311 engine
->mc
.takedown
= nv50_mc_takedown
;
312 engine
->timer
.init
= nv04_timer_init
;
313 engine
->timer
.read
= nv04_timer_read
;
314 engine
->timer
.takedown
= nv04_timer_takedown
;
315 engine
->fb
.init
= nv50_fb_init
;
316 engine
->fb
.takedown
= nv50_fb_takedown
;
317 engine
->fifo
.channels
= 128;
318 engine
->fifo
.init
= nv50_fifo_init
;
319 engine
->fifo
.takedown
= nv50_fifo_takedown
;
320 engine
->fifo
.disable
= nv04_fifo_disable
;
321 engine
->fifo
.enable
= nv04_fifo_enable
;
322 engine
->fifo
.reassign
= nv04_fifo_reassign
;
323 engine
->fifo
.channel_id
= nv50_fifo_channel_id
;
324 engine
->fifo
.create_context
= nv50_fifo_create_context
;
325 engine
->fifo
.destroy_context
= nv50_fifo_destroy_context
;
326 engine
->fifo
.load_context
= nv50_fifo_load_context
;
327 engine
->fifo
.unload_context
= nv50_fifo_unload_context
;
328 engine
->fifo
.tlb_flush
= nv50_fifo_tlb_flush
;
329 engine
->display
.early_init
= nv50_display_early_init
;
330 engine
->display
.late_takedown
= nv50_display_late_takedown
;
331 engine
->display
.create
= nv50_display_create
;
332 engine
->display
.init
= nv50_display_init
;
333 engine
->display
.destroy
= nv50_display_destroy
;
334 engine
->gpio
.init
= nv50_gpio_init
;
335 engine
->gpio
.takedown
= nv50_gpio_fini
;
336 engine
->gpio
.get
= nv50_gpio_get
;
337 engine
->gpio
.set
= nv50_gpio_set
;
338 engine
->gpio
.irq_register
= nv50_gpio_irq_register
;
339 engine
->gpio
.irq_unregister
= nv50_gpio_irq_unregister
;
340 engine
->gpio
.irq_enable
= nv50_gpio_irq_enable
;
341 switch (dev_priv
->chipset
) {
352 engine
->pm
.clock_get
= nv50_pm_clock_get
;
353 engine
->pm
.clock_pre
= nv50_pm_clock_pre
;
354 engine
->pm
.clock_set
= nv50_pm_clock_set
;
357 engine
->pm
.clock_get
= nva3_pm_clock_get
;
358 engine
->pm
.clock_pre
= nva3_pm_clock_pre
;
359 engine
->pm
.clock_set
= nva3_pm_clock_set
;
362 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
363 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
364 if (dev_priv
->chipset
>= 0x84)
365 engine
->pm
.temp_get
= nv84_temp_get
;
367 engine
->pm
.temp_get
= nv40_temp_get
;
368 engine
->vram
.init
= nv50_vram_init
;
369 engine
->vram
.get
= nv50_vram_new
;
370 engine
->vram
.put
= nv50_vram_del
;
371 engine
->vram
.flags_valid
= nv50_vram_flags_valid
;
374 engine
->instmem
.init
= nvc0_instmem_init
;
375 engine
->instmem
.takedown
= nvc0_instmem_takedown
;
376 engine
->instmem
.suspend
= nvc0_instmem_suspend
;
377 engine
->instmem
.resume
= nvc0_instmem_resume
;
378 engine
->instmem
.get
= nv50_instmem_get
;
379 engine
->instmem
.put
= nv50_instmem_put
;
380 engine
->instmem
.map
= nv50_instmem_map
;
381 engine
->instmem
.unmap
= nv50_instmem_unmap
;
382 engine
->instmem
.flush
= nv84_instmem_flush
;
383 engine
->mc
.init
= nv50_mc_init
;
384 engine
->mc
.takedown
= nv50_mc_takedown
;
385 engine
->timer
.init
= nv04_timer_init
;
386 engine
->timer
.read
= nv04_timer_read
;
387 engine
->timer
.takedown
= nv04_timer_takedown
;
388 engine
->fb
.init
= nvc0_fb_init
;
389 engine
->fb
.takedown
= nvc0_fb_takedown
;
390 engine
->fifo
.channels
= 128;
391 engine
->fifo
.init
= nvc0_fifo_init
;
392 engine
->fifo
.takedown
= nvc0_fifo_takedown
;
393 engine
->fifo
.disable
= nvc0_fifo_disable
;
394 engine
->fifo
.enable
= nvc0_fifo_enable
;
395 engine
->fifo
.reassign
= nvc0_fifo_reassign
;
396 engine
->fifo
.channel_id
= nvc0_fifo_channel_id
;
397 engine
->fifo
.create_context
= nvc0_fifo_create_context
;
398 engine
->fifo
.destroy_context
= nvc0_fifo_destroy_context
;
399 engine
->fifo
.load_context
= nvc0_fifo_load_context
;
400 engine
->fifo
.unload_context
= nvc0_fifo_unload_context
;
401 engine
->display
.early_init
= nv50_display_early_init
;
402 engine
->display
.late_takedown
= nv50_display_late_takedown
;
403 engine
->display
.create
= nv50_display_create
;
404 engine
->display
.init
= nv50_display_init
;
405 engine
->display
.destroy
= nv50_display_destroy
;
406 engine
->gpio
.init
= nv50_gpio_init
;
407 engine
->gpio
.takedown
= nouveau_stub_takedown
;
408 engine
->gpio
.get
= nv50_gpio_get
;
409 engine
->gpio
.set
= nv50_gpio_set
;
410 engine
->gpio
.irq_register
= nv50_gpio_irq_register
;
411 engine
->gpio
.irq_unregister
= nv50_gpio_irq_unregister
;
412 engine
->gpio
.irq_enable
= nv50_gpio_irq_enable
;
413 engine
->vram
.init
= nvc0_vram_init
;
414 engine
->vram
.get
= nvc0_vram_new
;
415 engine
->vram
.put
= nv50_vram_del
;
416 engine
->vram
.flags_valid
= nvc0_vram_flags_valid
;
419 NV_ERROR(dev
, "NV%02x unsupported\n", dev_priv
->chipset
);
427 nouveau_vga_set_decode(void *priv
, bool state
)
429 struct drm_device
*dev
= priv
;
430 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
432 if (dev_priv
->chipset
>= 0x40)
433 nv_wr32(dev
, 0x88054, state
);
435 nv_wr32(dev
, 0x1854, state
);
438 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
439 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
441 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
445 nouveau_card_init_channel(struct drm_device
*dev
)
447 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
450 ret
= nouveau_channel_alloc(dev
, &dev_priv
->channel
,
451 (struct drm_file
*)-2, NvDmaFB
, NvDmaTT
);
455 mutex_unlock(&dev_priv
->channel
->mutex
);
459 static void nouveau_switcheroo_set_state(struct pci_dev
*pdev
,
460 enum vga_switcheroo_state state
)
462 struct drm_device
*dev
= pci_get_drvdata(pdev
);
463 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
464 if (state
== VGA_SWITCHEROO_ON
) {
465 printk(KERN_ERR
"VGA switcheroo: switched nouveau on\n");
466 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
467 nouveau_pci_resume(pdev
);
468 drm_kms_helper_poll_enable(dev
);
469 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
471 printk(KERN_ERR
"VGA switcheroo: switched nouveau off\n");
472 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
473 drm_kms_helper_poll_disable(dev
);
474 nouveau_pci_suspend(pdev
, pmm
);
475 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
479 static void nouveau_switcheroo_reprobe(struct pci_dev
*pdev
)
481 struct drm_device
*dev
= pci_get_drvdata(pdev
);
482 nouveau_fbcon_output_poll_changed(dev
);
485 static bool nouveau_switcheroo_can_switch(struct pci_dev
*pdev
)
487 struct drm_device
*dev
= pci_get_drvdata(pdev
);
490 spin_lock(&dev
->count_lock
);
491 can_switch
= (dev
->open_count
== 0);
492 spin_unlock(&dev
->count_lock
);
497 nouveau_card_init(struct drm_device
*dev
)
499 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
500 struct nouveau_engine
*engine
;
503 vga_client_register(dev
->pdev
, dev
, NULL
, nouveau_vga_set_decode
);
504 vga_switcheroo_register_client(dev
->pdev
, nouveau_switcheroo_set_state
,
505 nouveau_switcheroo_reprobe
,
506 nouveau_switcheroo_can_switch
);
508 /* Initialise internal driver API hooks */
509 ret
= nouveau_init_engine_ptrs(dev
);
512 engine
= &dev_priv
->engine
;
513 spin_lock_init(&dev_priv
->channels
.lock
);
514 spin_lock_init(&dev_priv
->tile
.lock
);
515 spin_lock_init(&dev_priv
->context_switch_lock
);
516 spin_lock_init(&dev_priv
->vm_lock
);
518 /* Make the CRTCs and I2C buses accessible */
519 ret
= engine
->display
.early_init(dev
);
523 /* Parse BIOS tables / Run init tables if card not POSTed */
524 ret
= nouveau_bios_init(dev
);
526 goto out_display_early
;
528 nouveau_pm_init(dev
);
530 ret
= nouveau_mem_vram_init(dev
);
534 ret
= nouveau_gpuobj_init(dev
);
538 ret
= engine
->instmem
.init(dev
);
542 ret
= nouveau_mem_gart_init(dev
);
547 ret
= engine
->mc
.init(dev
);
552 ret
= engine
->gpio
.init(dev
);
557 ret
= engine
->timer
.init(dev
);
562 ret
= engine
->fb
.init(dev
);
566 switch (dev_priv
->card_type
) {
568 nv04_graph_create(dev
);
571 nv10_graph_create(dev
);
575 nv20_graph_create(dev
);
578 nv40_graph_create(dev
);
581 nv50_graph_create(dev
);
584 nvc0_graph_create(dev
);
590 switch (dev_priv
->chipset
) {
597 nv84_crypt_create(dev
);
601 switch (dev_priv
->card_type
) {
603 switch (dev_priv
->chipset
) {
608 nva3_copy_create(dev
);
613 nvc0_copy_create(dev
, 0);
614 nvc0_copy_create(dev
, 1);
620 if (!nouveau_noaccel
) {
621 for (e
= 0; e
< NVOBJ_ENGINE_NR
; e
++) {
622 if (dev_priv
->eng
[e
]) {
623 ret
= dev_priv
->eng
[e
]->init(dev
, e
);
630 ret
= engine
->fifo
.init(dev
);
635 ret
= engine
->display
.create(dev
);
639 ret
= drm_vblank_init(dev
, nv_two_heads(dev
) ? 2 : 1);
643 ret
= nouveau_irq_init(dev
);
647 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
649 if (dev_priv
->eng
[NVOBJ_ENGINE_GR
]) {
650 ret
= nouveau_fence_init(dev
);
654 ret
= nouveau_card_init_channel(dev
);
659 nouveau_fbcon_init(dev
);
660 drm_kms_helper_poll_init(dev
);
664 nouveau_fence_fini(dev
);
666 nouveau_irq_fini(dev
);
668 drm_vblank_cleanup(dev
);
669 engine
->display
.destroy(dev
);
671 if (!nouveau_noaccel
)
672 engine
->fifo
.takedown(dev
);
674 if (!nouveau_noaccel
) {
675 for (e
= e
- 1; e
>= 0; e
--) {
676 if (!dev_priv
->eng
[e
])
678 dev_priv
->eng
[e
]->fini(dev
, e
);
679 dev_priv
->eng
[e
]->destroy(dev
,e
);
683 engine
->fb
.takedown(dev
);
685 engine
->timer
.takedown(dev
);
687 engine
->gpio
.takedown(dev
);
689 engine
->mc
.takedown(dev
);
691 nouveau_mem_gart_fini(dev
);
693 engine
->instmem
.takedown(dev
);
695 nouveau_gpuobj_takedown(dev
);
697 nouveau_mem_vram_fini(dev
);
699 nouveau_pm_fini(dev
);
700 nouveau_bios_takedown(dev
);
702 engine
->display
.late_takedown(dev
);
704 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
708 static void nouveau_card_takedown(struct drm_device
*dev
)
710 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
711 struct nouveau_engine
*engine
= &dev_priv
->engine
;
714 if (dev_priv
->channel
) {
715 nouveau_fence_fini(dev
);
716 nouveau_channel_put_unlocked(&dev_priv
->channel
);
719 if (!nouveau_noaccel
) {
720 engine
->fifo
.takedown(dev
);
721 for (e
= NVOBJ_ENGINE_NR
- 1; e
>= 0; e
--) {
722 if (dev_priv
->eng
[e
]) {
723 dev_priv
->eng
[e
]->fini(dev
, e
);
724 dev_priv
->eng
[e
]->destroy(dev
,e
);
728 engine
->fb
.takedown(dev
);
729 engine
->timer
.takedown(dev
);
730 engine
->gpio
.takedown(dev
);
731 engine
->mc
.takedown(dev
);
732 engine
->display
.late_takedown(dev
);
734 mutex_lock(&dev
->struct_mutex
);
735 ttm_bo_clean_mm(&dev_priv
->ttm
.bdev
, TTM_PL_VRAM
);
736 ttm_bo_clean_mm(&dev_priv
->ttm
.bdev
, TTM_PL_TT
);
737 mutex_unlock(&dev
->struct_mutex
);
738 nouveau_mem_gart_fini(dev
);
740 engine
->instmem
.takedown(dev
);
741 nouveau_gpuobj_takedown(dev
);
742 nouveau_mem_vram_fini(dev
);
744 nouveau_irq_fini(dev
);
745 drm_vblank_cleanup(dev
);
747 nouveau_pm_fini(dev
);
748 nouveau_bios_takedown(dev
);
750 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
753 /* here a client dies, release the stuff that was allocated for its
755 void nouveau_preclose(struct drm_device
*dev
, struct drm_file
*file_priv
)
757 nouveau_channel_cleanup(dev
, file_priv
);
760 /* first module load, setup the mmio/fb mapping */
761 /* KMS: we need mmio at load time, not when the first drm client opens. */
762 int nouveau_firstopen(struct drm_device
*dev
)
767 /* if we have an OF card, copy vbios to RAMIN */
768 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device
*dev
)
770 #if defined(__powerpc__)
772 const uint32_t *bios
;
773 struct device_node
*dn
= pci_device_to_OF_node(dev
->pdev
);
775 NV_INFO(dev
, "Unable to get the OF node\n");
779 bios
= of_get_property(dn
, "NVDA,BMP", &size
);
781 for (i
= 0; i
< size
; i
+= 4)
782 nv_wi32(dev
, i
, bios
[i
/4]);
783 NV_INFO(dev
, "OF bios successfully copied (%d bytes)\n", size
);
785 NV_INFO(dev
, "Unable to get the OF bios\n");
790 static struct apertures_struct
*nouveau_get_apertures(struct drm_device
*dev
)
792 struct pci_dev
*pdev
= dev
->pdev
;
793 struct apertures_struct
*aper
= alloc_apertures(3);
797 aper
->ranges
[0].base
= pci_resource_start(pdev
, 1);
798 aper
->ranges
[0].size
= pci_resource_len(pdev
, 1);
801 if (pci_resource_len(pdev
, 2)) {
802 aper
->ranges
[aper
->count
].base
= pci_resource_start(pdev
, 2);
803 aper
->ranges
[aper
->count
].size
= pci_resource_len(pdev
, 2);
807 if (pci_resource_len(pdev
, 3)) {
808 aper
->ranges
[aper
->count
].base
= pci_resource_start(pdev
, 3);
809 aper
->ranges
[aper
->count
].size
= pci_resource_len(pdev
, 3);
816 static int nouveau_remove_conflicting_drivers(struct drm_device
*dev
)
818 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
819 bool primary
= false;
820 dev_priv
->apertures
= nouveau_get_apertures(dev
);
821 if (!dev_priv
->apertures
)
825 primary
= dev
->pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
828 remove_conflicting_framebuffers(dev_priv
->apertures
, "nouveaufb", primary
);
832 int nouveau_load(struct drm_device
*dev
, unsigned long flags
)
834 struct drm_nouveau_private
*dev_priv
;
836 resource_size_t mmio_start_offs
;
839 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
844 dev
->dev_private
= dev_priv
;
847 dev_priv
->flags
= flags
& NOUVEAU_FLAGS
;
849 NV_DEBUG(dev
, "vendor: 0x%X device: 0x%X class: 0x%X\n",
850 dev
->pci_vendor
, dev
->pci_device
, dev
->pdev
->class);
852 /* resource 0 is mmio regs */
853 /* resource 1 is linear FB */
854 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
855 /* resource 6 is bios */
857 /* map the mmio regs */
858 mmio_start_offs
= pci_resource_start(dev
->pdev
, 0);
859 dev_priv
->mmio
= ioremap(mmio_start_offs
, 0x00800000);
860 if (!dev_priv
->mmio
) {
861 NV_ERROR(dev
, "Unable to initialize the mmio mapping. "
862 "Please report your setup to " DRIVER_EMAIL
"\n");
866 NV_DEBUG(dev
, "regs mapped ok at 0x%llx\n",
867 (unsigned long long)mmio_start_offs
);
870 /* Put the card in BE mode if it's not */
871 if (nv_rd32(dev
, NV03_PMC_BOOT_1
))
872 nv_wr32(dev
, NV03_PMC_BOOT_1
, 0x00000001);
877 /* Time to determine the card architecture */
878 reg0
= nv_rd32(dev
, NV03_PMC_BOOT_0
);
879 dev_priv
->stepping
= 0; /* XXX: add stepping for pre-NV10? */
881 /* We're dealing with >=NV10 */
882 if ((reg0
& 0x0f000000) > 0) {
883 /* Bit 27-20 contain the architecture in hex */
884 dev_priv
->chipset
= (reg0
& 0xff00000) >> 20;
885 dev_priv
->stepping
= (reg0
& 0xff);
887 } else if ((reg0
& 0xff00fff0) == 0x20004000) {
888 if (reg0
& 0x00f00000)
889 dev_priv
->chipset
= 0x05;
891 dev_priv
->chipset
= 0x04;
893 dev_priv
->chipset
= 0xff;
895 switch (dev_priv
->chipset
& 0xf0) {
900 dev_priv
->card_type
= dev_priv
->chipset
& 0xf0;
904 dev_priv
->card_type
= NV_40
;
910 dev_priv
->card_type
= NV_50
;
913 dev_priv
->card_type
= NV_C0
;
916 NV_INFO(dev
, "Unsupported chipset 0x%08x\n", reg0
);
921 NV_INFO(dev
, "Detected an NV%2x generation card (0x%08x)\n",
922 dev_priv
->card_type
, reg0
);
924 ret
= nouveau_remove_conflicting_drivers(dev
);
928 /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
929 if (dev_priv
->card_type
>= NV_40
) {
931 if (pci_resource_len(dev
->pdev
, ramin_bar
) == 0)
934 dev_priv
->ramin_size
= pci_resource_len(dev
->pdev
, ramin_bar
);
936 ioremap(pci_resource_start(dev
->pdev
, ramin_bar
),
937 dev_priv
->ramin_size
);
938 if (!dev_priv
->ramin
) {
939 NV_ERROR(dev
, "Failed to PRAMIN BAR");
944 dev_priv
->ramin_size
= 1 * 1024 * 1024;
945 dev_priv
->ramin
= ioremap(mmio_start_offs
+ NV_RAMIN
,
946 dev_priv
->ramin_size
);
947 if (!dev_priv
->ramin
) {
948 NV_ERROR(dev
, "Failed to map BAR0 PRAMIN.\n");
954 nouveau_OF_copy_vbios_to_ramin(dev
);
957 if (dev
->pci_device
== 0x01a0)
958 dev_priv
->flags
|= NV_NFORCE
;
959 else if (dev
->pci_device
== 0x01f0)
960 dev_priv
->flags
|= NV_NFORCE2
;
962 /* For kernel modesetting, init card now and bring up fbcon */
963 ret
= nouveau_card_init(dev
);
970 iounmap(dev_priv
->ramin
);
972 iounmap(dev_priv
->mmio
);
975 dev
->dev_private
= NULL
;
980 void nouveau_lastclose(struct drm_device
*dev
)
982 vga_switcheroo_process_delayed_switch();
985 int nouveau_unload(struct drm_device
*dev
)
987 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
988 struct nouveau_engine
*engine
= &dev_priv
->engine
;
990 drm_kms_helper_poll_fini(dev
);
991 nouveau_fbcon_fini(dev
);
992 engine
->display
.destroy(dev
);
993 nouveau_card_takedown(dev
);
995 iounmap(dev_priv
->mmio
);
996 iounmap(dev_priv
->ramin
);
999 dev
->dev_private
= NULL
;
1003 int nouveau_ioctl_getparam(struct drm_device
*dev
, void *data
,
1004 struct drm_file
*file_priv
)
1006 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1007 struct drm_nouveau_getparam
*getparam
= data
;
1009 switch (getparam
->param
) {
1010 case NOUVEAU_GETPARAM_CHIPSET_ID
:
1011 getparam
->value
= dev_priv
->chipset
;
1013 case NOUVEAU_GETPARAM_PCI_VENDOR
:
1014 getparam
->value
= dev
->pci_vendor
;
1016 case NOUVEAU_GETPARAM_PCI_DEVICE
:
1017 getparam
->value
= dev
->pci_device
;
1019 case NOUVEAU_GETPARAM_BUS_TYPE
:
1020 if (drm_pci_device_is_agp(dev
))
1021 getparam
->value
= NV_AGP
;
1022 else if (drm_pci_device_is_pcie(dev
))
1023 getparam
->value
= NV_PCIE
;
1025 getparam
->value
= NV_PCI
;
1027 case NOUVEAU_GETPARAM_FB_SIZE
:
1028 getparam
->value
= dev_priv
->fb_available_size
;
1030 case NOUVEAU_GETPARAM_AGP_SIZE
:
1031 getparam
->value
= dev_priv
->gart_info
.aper_size
;
1033 case NOUVEAU_GETPARAM_VM_VRAM_BASE
:
1034 getparam
->value
= 0; /* deprecated */
1036 case NOUVEAU_GETPARAM_PTIMER_TIME
:
1037 getparam
->value
= dev_priv
->engine
.timer
.read(dev
);
1039 case NOUVEAU_GETPARAM_HAS_BO_USAGE
:
1040 getparam
->value
= 1;
1042 case NOUVEAU_GETPARAM_HAS_PAGEFLIP
:
1043 getparam
->value
= 1;
1045 case NOUVEAU_GETPARAM_GRAPH_UNITS
:
1046 /* NV40 and NV50 versions are quite different, but register
1047 * address is the same. User is supposed to know the card
1048 * family anyway... */
1049 if (dev_priv
->chipset
>= 0x40) {
1050 getparam
->value
= nv_rd32(dev
, NV40_PMC_GRAPH_UNITS
);
1055 NV_DEBUG(dev
, "unknown parameter %lld\n", getparam
->param
);
1063 nouveau_ioctl_setparam(struct drm_device
*dev
, void *data
,
1064 struct drm_file
*file_priv
)
1066 struct drm_nouveau_setparam
*setparam
= data
;
1068 switch (setparam
->param
) {
1070 NV_DEBUG(dev
, "unknown parameter %lld\n", setparam
->param
);
1077 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1079 nouveau_wait_eq(struct drm_device
*dev
, uint64_t timeout
,
1080 uint32_t reg
, uint32_t mask
, uint32_t val
)
1082 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1083 struct nouveau_timer_engine
*ptimer
= &dev_priv
->engine
.timer
;
1084 uint64_t start
= ptimer
->read(dev
);
1087 if ((nv_rd32(dev
, reg
) & mask
) == val
)
1089 } while (ptimer
->read(dev
) - start
< timeout
);
1094 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1096 nouveau_wait_ne(struct drm_device
*dev
, uint64_t timeout
,
1097 uint32_t reg
, uint32_t mask
, uint32_t val
)
1099 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1100 struct nouveau_timer_engine
*ptimer
= &dev_priv
->engine
.timer
;
1101 uint64_t start
= ptimer
->read(dev
);
1104 if ((nv_rd32(dev
, reg
) & mask
) != val
)
1106 } while (ptimer
->read(dev
) - start
< timeout
);
1111 /* Waits for PGRAPH to go completely idle */
1112 bool nouveau_wait_for_idle(struct drm_device
*dev
)
1114 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
1117 if (dev_priv
->card_type
== NV_40
)
1118 mask
&= ~NV40_PGRAPH_STATUS_SYNC_STALL
;
1120 if (!nv_wait(dev
, NV04_PGRAPH_STATUS
, mask
, 0)) {
1121 NV_ERROR(dev
, "PGRAPH idle timed out with status 0x%08x\n",
1122 nv_rd32(dev
, NV04_PGRAPH_STATUS
));