2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Ben Skeggs <bskeggs@redhat.com>
30 * Roy Spliet <r.spliet@student.tudelft.nl>
36 #include "nouveau_drv.h"
37 #include "nouveau_pm.h"
38 #include "nouveau_mm.h"
39 #include "nouveau_vm.h"
40 #include "nouveau_fifo.h"
41 #include "nouveau_fence.h"
44 * NV10-NV40 tiling helpers
48 nv10_mem_update_tile_region(struct drm_device
*dev
,
49 struct nouveau_tile_reg
*tile
, uint32_t addr
,
50 uint32_t size
, uint32_t pitch
, uint32_t flags
)
52 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
53 struct nouveau_fb_engine
*pfb
= &dev_priv
->engine
.fb
;
54 int i
= tile
- dev_priv
->tile
.reg
, j
;
57 nouveau_fence_unref(&tile
->fence
);
60 pfb
->free_tile_region(dev
, i
);
63 pfb
->init_tile_region(dev
, i
, addr
, size
, pitch
, flags
);
65 spin_lock_irqsave(&dev_priv
->context_switch_lock
, save
);
66 nv_wr32(dev
, NV03_PFIFO_CACHES
, 0);
67 nv04_fifo_cache_pull(dev
, false);
69 nouveau_wait_for_idle(dev
);
71 pfb
->set_tile_region(dev
, i
);
72 for (j
= 0; j
< NVOBJ_ENGINE_NR
; j
++) {
73 if (dev_priv
->eng
[j
] && dev_priv
->eng
[j
]->set_tile_region
)
74 dev_priv
->eng
[j
]->set_tile_region(dev
, i
);
77 nv04_fifo_cache_pull(dev
, true);
78 nv_wr32(dev
, NV03_PFIFO_CACHES
, 1);
79 spin_unlock_irqrestore(&dev_priv
->context_switch_lock
, save
);
82 static struct nouveau_tile_reg
*
83 nv10_mem_get_tile_region(struct drm_device
*dev
, int i
)
85 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
86 struct nouveau_tile_reg
*tile
= &dev_priv
->tile
.reg
[i
];
88 spin_lock(&dev_priv
->tile
.lock
);
91 (!tile
->fence
|| nouveau_fence_done(tile
->fence
)))
96 spin_unlock(&dev_priv
->tile
.lock
);
101 nv10_mem_put_tile_region(struct drm_device
*dev
, struct nouveau_tile_reg
*tile
,
102 struct nouveau_fence
*fence
)
104 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
107 spin_lock(&dev_priv
->tile
.lock
);
109 /* Mark it as pending. */
111 nouveau_fence_ref(fence
);
115 spin_unlock(&dev_priv
->tile
.lock
);
119 struct nouveau_tile_reg
*
120 nv10_mem_set_tiling(struct drm_device
*dev
, uint32_t addr
, uint32_t size
,
121 uint32_t pitch
, uint32_t flags
)
123 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
124 struct nouveau_fb_engine
*pfb
= &dev_priv
->engine
.fb
;
125 struct nouveau_tile_reg
*tile
, *found
= NULL
;
128 for (i
= 0; i
< pfb
->num_tiles
; i
++) {
129 tile
= nv10_mem_get_tile_region(dev
, i
);
131 if (pitch
&& !found
) {
135 } else if (tile
&& tile
->pitch
) {
136 /* Kill an unused tile region. */
137 nv10_mem_update_tile_region(dev
, tile
, 0, 0, 0, 0);
140 nv10_mem_put_tile_region(dev
, tile
, NULL
);
144 nv10_mem_update_tile_region(dev
, found
, addr
, size
,
153 nouveau_mem_vram_fini(struct drm_device
*dev
)
155 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
157 ttm_bo_device_release(&dev_priv
->ttm
.bdev
);
159 nouveau_ttm_global_release(dev_priv
);
161 if (dev_priv
->fb_mtrr
>= 0) {
162 drm_mtrr_del(dev_priv
->fb_mtrr
,
163 pci_resource_start(dev
->pdev
, 1),
164 pci_resource_len(dev
->pdev
, 1), DRM_MTRR_WC
);
165 dev_priv
->fb_mtrr
= -1;
170 nouveau_mem_gart_fini(struct drm_device
*dev
)
172 nouveau_sgdma_takedown(dev
);
174 if (drm_core_has_AGP(dev
) && dev
->agp
) {
175 struct drm_agp_mem
*entry
, *tempe
;
177 /* Remove AGP resources, but leave dev->agp
178 intact until drv_cleanup is called. */
179 list_for_each_entry_safe(entry
, tempe
, &dev
->agp
->memory
, head
) {
181 drm_unbind_agp(entry
->memory
);
182 drm_free_agp(entry
->memory
, entry
->pages
);
185 INIT_LIST_HEAD(&dev
->agp
->memory
);
187 if (dev
->agp
->acquired
)
188 drm_agp_release(dev
);
190 dev
->agp
->acquired
= 0;
191 dev
->agp
->enabled
= 0;
196 nouveau_mem_flags_valid(struct drm_device
*dev
, u32 tile_flags
)
198 if (!(tile_flags
& NOUVEAU_GEM_TILE_LAYOUT_MASK
))
206 get_agp_mode(struct drm_device
*dev
, unsigned long mode
)
208 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
211 * FW seems to be broken on nv18, it makes the card lock up
214 if (dev_priv
->chipset
== 0x18)
215 mode
&= ~PCI_AGP_COMMAND_FW
;
218 * AGP mode set in the command line.
220 if (nouveau_agpmode
> 0) {
221 bool agpv3
= mode
& 0x8;
222 int rate
= agpv3
? nouveau_agpmode
/ 4 : nouveau_agpmode
;
224 mode
= (mode
& ~0x7) | (rate
& 0x7);
232 nouveau_mem_reset_agp(struct drm_device
*dev
)
235 uint32_t saved_pci_nv_1
, pmc_enable
;
238 /* First of all, disable fast writes, otherwise if it's
239 * already enabled in the AGP bridge and we disable the card's
240 * AGP controller we might be locking ourselves out of it. */
241 if ((nv_rd32(dev
, NV04_PBUS_PCI_NV_19
) |
242 dev
->agp
->mode
) & PCI_AGP_COMMAND_FW
) {
243 struct drm_agp_info info
;
244 struct drm_agp_mode mode
;
246 ret
= drm_agp_info(dev
, &info
);
250 mode
.mode
= get_agp_mode(dev
, info
.mode
) & ~PCI_AGP_COMMAND_FW
;
251 ret
= drm_agp_enable(dev
, mode
);
256 saved_pci_nv_1
= nv_rd32(dev
, NV04_PBUS_PCI_NV_1
);
258 /* clear busmaster bit */
259 nv_wr32(dev
, NV04_PBUS_PCI_NV_1
, saved_pci_nv_1
& ~0x4);
261 nv_wr32(dev
, NV04_PBUS_PCI_NV_19
, 0);
263 /* power cycle pgraph, if enabled */
264 pmc_enable
= nv_rd32(dev
, NV03_PMC_ENABLE
);
265 if (pmc_enable
& NV_PMC_ENABLE_PGRAPH
) {
266 nv_wr32(dev
, NV03_PMC_ENABLE
,
267 pmc_enable
& ~NV_PMC_ENABLE_PGRAPH
);
268 nv_wr32(dev
, NV03_PMC_ENABLE
, nv_rd32(dev
, NV03_PMC_ENABLE
) |
269 NV_PMC_ENABLE_PGRAPH
);
272 /* and restore (gives effect of resetting AGP) */
273 nv_wr32(dev
, NV04_PBUS_PCI_NV_1
, saved_pci_nv_1
);
280 nouveau_mem_init_agp(struct drm_device
*dev
)
283 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
284 struct drm_agp_info info
;
285 struct drm_agp_mode mode
;
288 if (!dev
->agp
->acquired
) {
289 ret
= drm_agp_acquire(dev
);
291 NV_ERROR(dev
, "Unable to acquire AGP: %d\n", ret
);
296 nouveau_mem_reset_agp(dev
);
298 ret
= drm_agp_info(dev
, &info
);
300 NV_ERROR(dev
, "Unable to get AGP info: %d\n", ret
);
304 /* see agp.h for the AGPSTAT_* modes available */
305 mode
.mode
= get_agp_mode(dev
, info
.mode
);
306 ret
= drm_agp_enable(dev
, mode
);
308 NV_ERROR(dev
, "Unable to enable AGP: %d\n", ret
);
312 dev_priv
->gart_info
.type
= NOUVEAU_GART_AGP
;
313 dev_priv
->gart_info
.aper_base
= info
.aperture_base
;
314 dev_priv
->gart_info
.aper_size
= info
.aperture_size
;
319 static const struct vram_types
{
322 } vram_type_map
[] = {
323 { NV_MEM_TYPE_STOLEN
, "stolen system memory" },
324 { NV_MEM_TYPE_SGRAM
, "SGRAM" },
325 { NV_MEM_TYPE_SDRAM
, "SDRAM" },
326 { NV_MEM_TYPE_DDR1
, "DDR1" },
327 { NV_MEM_TYPE_DDR2
, "DDR2" },
328 { NV_MEM_TYPE_DDR3
, "DDR3" },
329 { NV_MEM_TYPE_GDDR2
, "GDDR2" },
330 { NV_MEM_TYPE_GDDR3
, "GDDR3" },
331 { NV_MEM_TYPE_GDDR4
, "GDDR4" },
332 { NV_MEM_TYPE_GDDR5
, "GDDR5" },
333 { NV_MEM_TYPE_UNKNOWN
, "unknown type" }
337 nouveau_mem_vram_init(struct drm_device
*dev
)
339 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
340 struct ttm_bo_device
*bdev
= &dev_priv
->ttm
.bdev
;
341 const struct vram_types
*vram_type
;
345 if (dev_priv
->card_type
>= NV_50
) {
346 if (pci_dma_supported(dev
->pdev
, DMA_BIT_MASK(40)))
349 if (0 && pci_is_pcie(dev
->pdev
) &&
350 dev_priv
->chipset
> 0x40 &&
351 dev_priv
->chipset
!= 0x45) {
352 if (pci_dma_supported(dev
->pdev
, DMA_BIT_MASK(39)))
356 ret
= pci_set_dma_mask(dev
->pdev
, DMA_BIT_MASK(dma_bits
));
359 ret
= pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(dma_bits
));
361 /* Reset to default value. */
362 pci_set_consistent_dma_mask(dev
->pdev
, DMA_BIT_MASK(32));
366 ret
= nouveau_ttm_global_init(dev_priv
);
370 ret
= ttm_bo_device_init(&dev_priv
->ttm
.bdev
,
371 dev_priv
->ttm
.bo_global_ref
.ref
.object
,
372 &nouveau_bo_driver
, DRM_FILE_PAGE_OFFSET
,
373 dma_bits
<= 32 ? true : false);
375 NV_ERROR(dev
, "Error initialising bo driver: %d\n", ret
);
379 vram_type
= vram_type_map
;
380 while (vram_type
->value
!= NV_MEM_TYPE_UNKNOWN
) {
381 if (nouveau_vram_type
) {
382 if (!strcasecmp(nouveau_vram_type
, vram_type
->name
))
384 dev_priv
->vram_type
= vram_type
->value
;
386 if (vram_type
->value
== dev_priv
->vram_type
)
392 NV_INFO(dev
, "Detected %dMiB VRAM (%s)\n",
393 (int)(dev_priv
->vram_size
>> 20), vram_type
->name
);
394 if (dev_priv
->vram_sys_base
) {
395 NV_INFO(dev
, "Stolen system memory at: 0x%010llx\n",
396 dev_priv
->vram_sys_base
);
399 dev_priv
->fb_available_size
= dev_priv
->vram_size
;
400 dev_priv
->fb_mappable_pages
= dev_priv
->fb_available_size
;
401 if (dev_priv
->fb_mappable_pages
> pci_resource_len(dev
->pdev
, 1))
402 dev_priv
->fb_mappable_pages
= pci_resource_len(dev
->pdev
, 1);
403 dev_priv
->fb_mappable_pages
>>= PAGE_SHIFT
;
405 dev_priv
->fb_available_size
-= dev_priv
->ramin_rsvd_vram
;
406 dev_priv
->fb_aper_free
= dev_priv
->fb_available_size
;
409 ret
= ttm_bo_init_mm(bdev
, TTM_PL_VRAM
,
410 dev_priv
->fb_available_size
>> PAGE_SHIFT
);
412 NV_ERROR(dev
, "Failed VRAM mm init: %d\n", ret
);
416 if (dev_priv
->card_type
< NV_50
) {
417 ret
= nouveau_bo_new(dev
, 256*1024, 0, TTM_PL_FLAG_VRAM
,
418 0, 0, NULL
, &dev_priv
->vga_ram
);
420 ret
= nouveau_bo_pin(dev_priv
->vga_ram
,
424 NV_WARN(dev
, "failed to reserve VGA memory\n");
425 nouveau_bo_ref(NULL
, &dev_priv
->vga_ram
);
429 dev_priv
->fb_mtrr
= drm_mtrr_add(pci_resource_start(dev
->pdev
, 1),
430 pci_resource_len(dev
->pdev
, 1),
436 nouveau_mem_gart_init(struct drm_device
*dev
)
438 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
439 struct ttm_bo_device
*bdev
= &dev_priv
->ttm
.bdev
;
442 dev_priv
->gart_info
.type
= NOUVEAU_GART_NONE
;
444 #if !defined(__powerpc__) && !defined(__ia64__)
445 if (drm_pci_device_is_agp(dev
) && dev
->agp
&& nouveau_agpmode
) {
446 ret
= nouveau_mem_init_agp(dev
);
448 NV_ERROR(dev
, "Error initialising AGP: %d\n", ret
);
452 if (dev_priv
->gart_info
.type
== NOUVEAU_GART_NONE
) {
453 ret
= nouveau_sgdma_init(dev
);
455 NV_ERROR(dev
, "Error initialising PCI(E): %d\n", ret
);
460 NV_INFO(dev
, "%d MiB GART (aperture)\n",
461 (int)(dev_priv
->gart_info
.aper_size
>> 20));
462 dev_priv
->gart_info
.aper_free
= dev_priv
->gart_info
.aper_size
;
464 ret
= ttm_bo_init_mm(bdev
, TTM_PL_TT
,
465 dev_priv
->gart_info
.aper_size
>> PAGE_SHIFT
);
467 NV_ERROR(dev
, "Failed TT mm init: %d\n", ret
);
475 nv40_mem_timing_calc(struct drm_device
*dev
, u32 freq
,
476 struct nouveau_pm_tbl_entry
*e
, u8 len
,
477 struct nouveau_pm_memtiming
*boot
,
478 struct nouveau_pm_memtiming
*t
)
480 t
->reg
[0] = (e
->tRP
<< 24 | e
->tRAS
<< 16 | e
->tRFC
<< 8 | e
->tRC
);
482 /* XXX: I don't trust the -1's and +1's... they must come
484 t
->reg
[1] = (e
->tWR
+ 2 + (t
->tCWL
- 1)) << 24 |
486 (e
->tWTR
+ 2 + (t
->tCWL
- 1)) << 8 |
487 (e
->tCL
+ 2 - (t
->tCWL
- 1));
489 t
->reg
[2] = 0x20200000 |
490 ((t
->tCWL
- 1) << 24 |
495 NV_DEBUG(dev
, "Entry %d: 220: %08x %08x %08x\n", t
->id
,
496 t
->reg
[0], t
->reg
[1], t
->reg
[2]);
501 nv50_mem_timing_calc(struct drm_device
*dev
, u32 freq
,
502 struct nouveau_pm_tbl_entry
*e
, u8 len
,
503 struct nouveau_pm_memtiming
*boot
,
504 struct nouveau_pm_memtiming
*t
)
506 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
508 uint8_t unk18
= 1, unk20
= 0, unk21
= 0, tmp7_3
;
510 if (bit_table(dev
, 'P', &P
))
513 switch (min(len
, (u8
) 22)) {
526 t
->reg
[0] = (e
->tRP
<< 24 | e
->tRAS
<< 16 | e
->tRFC
<< 8 | e
->tRC
);
528 t
->reg
[1] = (e
->tWR
+ 2 + (t
->tCWL
- 1)) << 24 |
529 max(unk18
, (u8
) 1) << 16 |
530 (e
->tWTR
+ 2 + (t
->tCWL
- 1)) << 8;
532 t
->reg
[2] = ((t
->tCWL
- 1) << 24 |
537 t
->reg
[4] = e
->tUNK_13
<< 8 | e
->tUNK_13
;
539 t
->reg
[5] = (e
->tRFC
<< 24 | max(e
->tRCDRD
, e
->tRCDWR
) << 16 | e
->tRP
);
541 t
->reg
[8] = boot
->reg
[8] & 0xffffff00;
543 if (P
.version
== 1) {
544 t
->reg
[1] |= (e
->tCL
+ 2 - (t
->tCWL
- 1));
546 t
->reg
[3] = (0x14 + e
->tCL
) << 24 |
551 t
->reg
[4] |= boot
->reg
[4] & 0xffff0000;
553 t
->reg
[6] = (0x33 - t
->tCWL
) << 16 |
555 (0x2e + e
->tCL
- t
->tCWL
);
557 t
->reg
[7] = 0x4000202 | (e
->tCL
- 1) << 16;
559 /* XXX: P.version == 1 only has DDR2 and GDDR3? */
560 if (dev_priv
->vram_type
== NV_MEM_TYPE_DDR2
) {
561 t
->reg
[5] |= (e
->tCL
+ 3) << 8;
562 t
->reg
[6] |= (t
->tCWL
- 2) << 8;
563 t
->reg
[8] |= (e
->tCL
- 4);
565 t
->reg
[5] |= (e
->tCL
+ 2) << 8;
566 t
->reg
[6] |= t
->tCWL
<< 8;
567 t
->reg
[8] |= (e
->tCL
- 2);
570 t
->reg
[1] |= (5 + e
->tCL
- (t
->tCWL
));
572 /* XXX: 0xb? 0x30? */
573 t
->reg
[3] = (0x30 + e
->tCL
) << 24 |
574 (boot
->reg
[3] & 0x00ff0000)|
575 (0xb + e
->tCL
) << 8 |
578 t
->reg
[4] |= (unk20
<< 24 | unk21
<< 16);
581 t
->reg
[5] |= (t
->tCWL
+ 6) << 8;
583 t
->reg
[6] = (0x5a + e
->tCL
) << 16 |
584 (6 - e
->tCL
+ t
->tCWL
) << 8 |
585 (0x50 + e
->tCL
- t
->tCWL
);
587 tmp7_3
= (boot
->reg
[7] & 0xff000000) >> 24;
588 t
->reg
[7] = (tmp7_3
<< 24) |
589 ((tmp7_3
- 6 + e
->tCL
) << 16) |
593 NV_DEBUG(dev
, "Entry %d: 220: %08x %08x %08x %08x\n", t
->id
,
594 t
->reg
[0], t
->reg
[1], t
->reg
[2], t
->reg
[3]);
595 NV_DEBUG(dev
, " 230: %08x %08x %08x %08x\n",
596 t
->reg
[4], t
->reg
[5], t
->reg
[6], t
->reg
[7]);
597 NV_DEBUG(dev
, " 240: %08x\n", t
->reg
[8]);
602 nvc0_mem_timing_calc(struct drm_device
*dev
, u32 freq
,
603 struct nouveau_pm_tbl_entry
*e
, u8 len
,
604 struct nouveau_pm_memtiming
*boot
,
605 struct nouveau_pm_memtiming
*t
)
610 t
->reg
[0] = (e
->tRP
<< 24 | (e
->tRAS
& 0x7f) << 17 |
611 e
->tRFC
<< 8 | e
->tRC
);
613 t
->reg
[1] = (boot
->reg
[1] & 0xff000000) |
614 (e
->tRCDWR
& 0x0f) << 20 |
615 (e
->tRCDRD
& 0x0f) << 14 |
619 t
->reg
[2] = (boot
->reg
[2] & 0xff0000ff) |
620 e
->tWR
<< 16 | e
->tWTR
<< 8;
622 t
->reg
[3] = (e
->tUNK_20
& 0x1f) << 9 |
623 (e
->tUNK_21
& 0xf) << 5 |
626 t
->reg
[4] = (boot
->reg
[4] & 0xfff00fff) |
627 (e
->tRRD
&0x1f) << 15;
629 NV_DEBUG(dev
, "Entry %d: 290: %08x %08x %08x %08x\n", t
->id
,
630 t
->reg
[0], t
->reg
[1], t
->reg
[2], t
->reg
[3]);
631 NV_DEBUG(dev
, " 2a0: %08x\n", t
->reg
[4]);
636 * MR generation methods
640 nouveau_mem_ddr2_mr(struct drm_device
*dev
, u32 freq
,
641 struct nouveau_pm_tbl_entry
*e
, u8 len
,
642 struct nouveau_pm_memtiming
*boot
,
643 struct nouveau_pm_memtiming
*t
)
645 t
->drive_strength
= 0;
649 t
->odt
= e
->RAM_FT1
& 0x07;
652 if (e
->tCL
>= NV_MEM_CL_DDR2_MAX
) {
653 NV_WARN(dev
, "(%u) Invalid tCL: %u", t
->id
, e
->tCL
);
657 if (e
->tWR
>= NV_MEM_WR_DDR2_MAX
) {
658 NV_WARN(dev
, "(%u) Invalid tWR: %u", t
->id
, e
->tWR
);
663 NV_WARN(dev
, "(%u) Invalid odt value, assuming disabled: %x",
668 t
->mr
[0] = (boot
->mr
[0] & 0x100f) |
671 t
->mr
[1] = (boot
->mr
[1] & 0x101fbb) |
672 (t
->odt
& 0x1) << 2 |
675 NV_DEBUG(dev
, "(%u) MR: %08x", t
->id
, t
->mr
[0]);
679 uint8_t nv_mem_wr_lut_ddr3
[NV_MEM_WR_DDR3_MAX
] = {
680 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
683 nouveau_mem_ddr3_mr(struct drm_device
*dev
, u32 freq
,
684 struct nouveau_pm_tbl_entry
*e
, u8 len
,
685 struct nouveau_pm_memtiming
*boot
,
686 struct nouveau_pm_memtiming
*t
)
690 t
->drive_strength
= 0;
694 t
->odt
= e
->RAM_FT1
& 0x07;
697 if (e
->tCL
>= NV_MEM_CL_DDR3_MAX
|| e
->tCL
< 4) {
698 NV_WARN(dev
, "(%u) Invalid tCL: %u", t
->id
, e
->tCL
);
702 if (e
->tWR
>= NV_MEM_WR_DDR3_MAX
|| e
->tWR
< 4) {
703 NV_WARN(dev
, "(%u) Invalid tWR: %u", t
->id
, e
->tWR
);
708 NV_WARN(dev
, "(%u) Invalid tCWL: %u", t
->id
, e
->tCWL
);
712 t
->mr
[0] = (boot
->mr
[0] & 0x180b) |
716 (nv_mem_wr_lut_ddr3
[e
->tWR
]) << 9;
717 t
->mr
[1] = (boot
->mr
[1] & 0x101dbb) |
718 (t
->odt
& 0x1) << 2 |
719 (t
->odt
& 0x2) << 5 |
721 t
->mr
[2] = (boot
->mr
[2] & 0x20ffb7) | (e
->tCWL
- 5) << 3;
723 NV_DEBUG(dev
, "(%u) MR: %08x %08x", t
->id
, t
->mr
[0], t
->mr
[2]);
727 uint8_t nv_mem_cl_lut_gddr3
[NV_MEM_CL_GDDR3_MAX
] = {
728 0, 0, 0, 0, 4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11};
729 uint8_t nv_mem_wr_lut_gddr3
[NV_MEM_WR_GDDR3_MAX
] = {
730 0, 0, 0, 0, 0, 2, 3, 8, 9, 10, 11, 0, 0, 1, 1, 0, 3};
733 nouveau_mem_gddr3_mr(struct drm_device
*dev
, u32 freq
,
734 struct nouveau_pm_tbl_entry
*e
, u8 len
,
735 struct nouveau_pm_memtiming
*boot
,
736 struct nouveau_pm_memtiming
*t
)
739 t
->drive_strength
= boot
->drive_strength
;
742 t
->drive_strength
= (e
->RAM_FT1
& 0x30) >> 4;
743 t
->odt
= e
->RAM_FT1
& 0x07;
746 if (e
->tCL
>= NV_MEM_CL_GDDR3_MAX
) {
747 NV_WARN(dev
, "(%u) Invalid tCL: %u", t
->id
, e
->tCL
);
751 if (e
->tWR
>= NV_MEM_WR_GDDR3_MAX
) {
752 NV_WARN(dev
, "(%u) Invalid tWR: %u", t
->id
, e
->tWR
);
757 NV_WARN(dev
, "(%u) Invalid odt value, assuming autocal: %x",
762 t
->mr
[0] = (boot
->mr
[0] & 0xe0b) |
764 ((nv_mem_cl_lut_gddr3
[e
->tCL
] & 0x7) << 4) |
765 ((nv_mem_cl_lut_gddr3
[e
->tCL
] & 0x8) >> 2);
766 t
->mr
[1] = (boot
->mr
[1] & 0x100f40) | t
->drive_strength
|
768 (nv_mem_wr_lut_gddr3
[e
->tWR
] & 0xf) << 4;
769 t
->mr
[2] = boot
->mr
[2];
771 NV_DEBUG(dev
, "(%u) MR: %08x %08x %08x", t
->id
,
772 t
->mr
[0], t
->mr
[1], t
->mr
[2]);
777 nouveau_mem_gddr5_mr(struct drm_device
*dev
, u32 freq
,
778 struct nouveau_pm_tbl_entry
*e
, u8 len
,
779 struct nouveau_pm_memtiming
*boot
,
780 struct nouveau_pm_memtiming
*t
)
783 t
->drive_strength
= boot
->drive_strength
;
786 t
->drive_strength
= (e
->RAM_FT1
& 0x30) >> 4;
787 t
->odt
= e
->RAM_FT1
& 0x03;
790 if (e
->tCL
>= NV_MEM_CL_GDDR5_MAX
) {
791 NV_WARN(dev
, "(%u) Invalid tCL: %u", t
->id
, e
->tCL
);
795 if (e
->tWR
>= NV_MEM_WR_GDDR5_MAX
) {
796 NV_WARN(dev
, "(%u) Invalid tWR: %u", t
->id
, e
->tWR
);
801 NV_WARN(dev
, "(%u) Invalid odt value, assuming autocal: %x",
806 t
->mr
[0] = (boot
->mr
[0] & 0x007) |
807 ((e
->tCL
- 5) << 3) |
809 t
->mr
[1] = (boot
->mr
[1] & 0x1007f0) |
813 NV_DEBUG(dev
, "(%u) MR: %08x %08x", t
->id
, t
->mr
[0], t
->mr
[1]);
818 nouveau_mem_timing_calc(struct drm_device
*dev
, u32 freq
,
819 struct nouveau_pm_memtiming
*t
)
821 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
822 struct nouveau_pm_engine
*pm
= &dev_priv
->engine
.pm
;
823 struct nouveau_pm_memtiming
*boot
= &pm
->boot
.timing
;
824 struct nouveau_pm_tbl_entry
*e
;
825 u8 ver
, len
, *ptr
, *ramcfg
;
828 ptr
= nouveau_perf_timing(dev
, freq
, &ver
, &len
);
829 if (!ptr
|| ptr
[0] == 0x00) {
833 e
= (struct nouveau_pm_tbl_entry
*)ptr
;
835 t
->tCWL
= boot
->tCWL
;
837 switch (dev_priv
->card_type
) {
839 ret
= nv40_mem_timing_calc(dev
, freq
, e
, len
, boot
, t
);
842 ret
= nv50_mem_timing_calc(dev
, freq
, e
, len
, boot
, t
);
846 ret
= nvc0_mem_timing_calc(dev
, freq
, e
, len
, boot
, t
);
853 switch (dev_priv
->vram_type
* !ret
) {
854 case NV_MEM_TYPE_GDDR3
:
855 ret
= nouveau_mem_gddr3_mr(dev
, freq
, e
, len
, boot
, t
);
857 case NV_MEM_TYPE_GDDR5
:
858 ret
= nouveau_mem_gddr5_mr(dev
, freq
, e
, len
, boot
, t
);
860 case NV_MEM_TYPE_DDR2
:
861 ret
= nouveau_mem_ddr2_mr(dev
, freq
, e
, len
, boot
, t
);
863 case NV_MEM_TYPE_DDR3
:
864 ret
= nouveau_mem_ddr3_mr(dev
, freq
, e
, len
, boot
, t
);
871 ramcfg
= nouveau_perf_ramcfg(dev
, freq
, &ver
, &len
);
876 dll_off
= !!(ramcfg
[3] & 0x04);
878 dll_off
= !!(ramcfg
[2] & 0x40);
880 switch (dev_priv
->vram_type
) {
881 case NV_MEM_TYPE_GDDR3
:
882 t
->mr
[1] &= ~0x00000040;
883 t
->mr
[1] |= 0x00000040 * dll_off
;
886 t
->mr
[1] &= ~0x00000001;
887 t
->mr
[1] |= 0x00000001 * dll_off
;
896 nouveau_mem_timing_read(struct drm_device
*dev
, struct nouveau_pm_memtiming
*t
)
898 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
899 u32 timing_base
, timing_regs
, mr_base
;
902 if (dev_priv
->card_type
>= 0xC0) {
903 timing_base
= 0x10f290;
906 timing_base
= 0x100220;
912 switch (dev_priv
->card_type
) {
928 for(i
= 0; i
< timing_regs
; i
++)
929 t
->reg
[i
] = nv_rd32(dev
, timing_base
+ (0x04 * i
));
932 if (dev_priv
->card_type
< NV_C0
) {
933 t
->tCWL
= ((nv_rd32(dev
, 0x100228) & 0x0f000000) >> 24) + 1;
934 } else if (dev_priv
->card_type
<= NV_D0
) {
935 t
->tCWL
= ((nv_rd32(dev
, 0x10f294) & 0x00000f80) >> 7);
938 t
->mr
[0] = nv_rd32(dev
, mr_base
);
939 t
->mr
[1] = nv_rd32(dev
, mr_base
+ 0x04);
940 t
->mr
[2] = nv_rd32(dev
, mr_base
+ 0x20);
941 t
->mr
[3] = nv_rd32(dev
, mr_base
+ 0x24);
944 t
->drive_strength
= 0;
946 switch (dev_priv
->vram_type
) {
947 case NV_MEM_TYPE_DDR3
:
948 t
->odt
|= (t
->mr
[1] & 0x200) >> 7;
949 case NV_MEM_TYPE_DDR2
:
950 t
->odt
|= (t
->mr
[1] & 0x04) >> 2 |
951 (t
->mr
[1] & 0x40) >> 5;
953 case NV_MEM_TYPE_GDDR3
:
954 case NV_MEM_TYPE_GDDR5
:
955 t
->drive_strength
= t
->mr
[1] & 0x03;
956 t
->odt
= (t
->mr
[1] & 0x0c) >> 2;
964 nouveau_mem_exec(struct nouveau_mem_exec_func
*exec
,
965 struct nouveau_pm_level
*perflvl
)
967 struct drm_nouveau_private
*dev_priv
= exec
->dev
->dev_private
;
968 struct nouveau_pm_memtiming
*info
= &perflvl
->timing
;
969 u32 tMRD
= 1000, tCKSRE
= 0, tCKSRX
= 0, tXS
= 0, tDLLK
= 0;
970 u32 mr
[3] = { info
->mr
[0], info
->mr
[1], info
->mr
[2] };
973 switch (dev_priv
->vram_type
) {
974 case NV_MEM_TYPE_DDR2
:
976 mr1_dlloff
= 0x00000001;
978 case NV_MEM_TYPE_DDR3
:
982 mr1_dlloff
= 0x00000001;
984 case NV_MEM_TYPE_GDDR3
:
986 mr1_dlloff
= 0x00000040;
989 NV_ERROR(exec
->dev
, "cannot reclock unsupported memtype\n");
993 /* fetch current MRs */
994 switch (dev_priv
->vram_type
) {
995 case NV_MEM_TYPE_GDDR3
:
996 case NV_MEM_TYPE_DDR3
:
997 mr
[2] = exec
->mrg(exec
, 2);
999 mr
[1] = exec
->mrg(exec
, 1);
1000 mr
[0] = exec
->mrg(exec
, 0);
1004 /* DLL 'on' -> DLL 'off' mode, disable before entering self-refresh */
1005 if (!(mr
[1] & mr1_dlloff
) && (info
->mr
[1] & mr1_dlloff
)) {
1006 exec
->precharge(exec
);
1007 exec
->mrs (exec
, 1, mr
[1] | mr1_dlloff
);
1008 exec
->wait(exec
, tMRD
);
1011 /* enter self-refresh mode */
1012 exec
->precharge(exec
);
1013 exec
->refresh(exec
);
1014 exec
->refresh(exec
);
1015 exec
->refresh_auto(exec
, false);
1016 exec
->refresh_self(exec
, true);
1017 exec
->wait(exec
, tCKSRE
);
1019 /* modify input clock frequency */
1020 exec
->clock_set(exec
);
1022 /* exit self-refresh mode */
1023 exec
->wait(exec
, tCKSRX
);
1024 exec
->precharge(exec
);
1025 exec
->refresh_self(exec
, false);
1026 exec
->refresh_auto(exec
, true);
1027 exec
->wait(exec
, tXS
);
1028 exec
->wait(exec
, tXS
);
1031 if (mr
[2] != info
->mr
[2]) {
1032 exec
->mrs (exec
, 2, info
->mr
[2]);
1033 exec
->wait(exec
, tMRD
);
1036 if (mr
[1] != info
->mr
[1]) {
1037 /* need to keep DLL off until later, at least on GDDR3 */
1038 exec
->mrs (exec
, 1, info
->mr
[1] | (mr
[1] & mr1_dlloff
));
1039 exec
->wait(exec
, tMRD
);
1042 if (mr
[0] != info
->mr
[0]) {
1043 exec
->mrs (exec
, 0, info
->mr
[0]);
1044 exec
->wait(exec
, tMRD
);
1047 /* update PFB timing registers */
1048 exec
->timing_set(exec
);
1050 /* DLL (enable + ) reset */
1051 if (!(info
->mr
[1] & mr1_dlloff
)) {
1052 if (mr
[1] & mr1_dlloff
) {
1053 exec
->mrs (exec
, 1, info
->mr
[1]);
1054 exec
->wait(exec
, tMRD
);
1056 exec
->mrs (exec
, 0, info
->mr
[0] | 0x00000100);
1057 exec
->wait(exec
, tMRD
);
1058 exec
->mrs (exec
, 0, info
->mr
[0] | 0x00000000);
1059 exec
->wait(exec
, tMRD
);
1060 exec
->wait(exec
, tDLLK
);
1061 if (dev_priv
->vram_type
== NV_MEM_TYPE_GDDR3
)
1062 exec
->precharge(exec
);
1069 nouveau_mem_vbios_type(struct drm_device
*dev
)
1072 u8 ramcfg
= (nv_rd32(dev
, 0x101000) & 0x0000003c) >> 2;
1073 if (!bit_table(dev
, 'M', &M
) || M
.version
!= 2 || M
.length
< 5) {
1074 u8
*table
= ROMPTR(dev
, M
.data
[3]);
1075 if (table
&& table
[0] == 0x10 && ramcfg
< table
[3]) {
1076 u8
*entry
= table
+ table
[1] + (ramcfg
* table
[2]);
1077 switch (entry
[0] & 0x0f) {
1078 case 0: return NV_MEM_TYPE_DDR2
;
1079 case 1: return NV_MEM_TYPE_DDR3
;
1080 case 2: return NV_MEM_TYPE_GDDR3
;
1081 case 3: return NV_MEM_TYPE_GDDR5
;
1088 return NV_MEM_TYPE_UNKNOWN
;
1092 nouveau_vram_manager_init(struct ttm_mem_type_manager
*man
, unsigned long psize
)
1099 nouveau_vram_manager_fini(struct ttm_mem_type_manager
*man
)
1106 nouveau_mem_node_cleanup(struct nouveau_mem
*node
)
1108 if (node
->vma
[0].node
) {
1109 nouveau_vm_unmap(&node
->vma
[0]);
1110 nouveau_vm_put(&node
->vma
[0]);
1113 if (node
->vma
[1].node
) {
1114 nouveau_vm_unmap(&node
->vma
[1]);
1115 nouveau_vm_put(&node
->vma
[1]);
1120 nouveau_vram_manager_del(struct ttm_mem_type_manager
*man
,
1121 struct ttm_mem_reg
*mem
)
1123 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(man
->bdev
);
1124 struct nouveau_vram_engine
*vram
= &dev_priv
->engine
.vram
;
1125 struct drm_device
*dev
= dev_priv
->dev
;
1127 nouveau_mem_node_cleanup(mem
->mm_node
);
1128 vram
->put(dev
, (struct nouveau_mem
**)&mem
->mm_node
);
1132 nouveau_vram_manager_new(struct ttm_mem_type_manager
*man
,
1133 struct ttm_buffer_object
*bo
,
1134 struct ttm_placement
*placement
,
1135 struct ttm_mem_reg
*mem
)
1137 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(man
->bdev
);
1138 struct nouveau_vram_engine
*vram
= &dev_priv
->engine
.vram
;
1139 struct drm_device
*dev
= dev_priv
->dev
;
1140 struct nouveau_bo
*nvbo
= nouveau_bo(bo
);
1141 struct nouveau_mem
*node
;
1145 if (nvbo
->tile_flags
& NOUVEAU_GEM_TILE_NONCONTIG
)
1146 size_nc
= 1 << nvbo
->page_shift
;
1148 ret
= vram
->get(dev
, mem
->num_pages
<< PAGE_SHIFT
,
1149 mem
->page_alignment
<< PAGE_SHIFT
, size_nc
,
1150 (nvbo
->tile_flags
>> 8) & 0x3ff, &node
);
1152 mem
->mm_node
= NULL
;
1153 return (ret
== -ENOSPC
) ? 0 : ret
;
1156 node
->page_shift
= nvbo
->page_shift
;
1158 mem
->mm_node
= node
;
1159 mem
->start
= node
->offset
>> PAGE_SHIFT
;
1164 nouveau_vram_manager_debug(struct ttm_mem_type_manager
*man
, const char *prefix
)
1166 struct nouveau_mm
*mm
= man
->priv
;
1167 struct nouveau_mm_node
*r
;
1168 u32 total
= 0, free
= 0;
1170 mutex_lock(&mm
->mutex
);
1171 list_for_each_entry(r
, &mm
->nodes
, nl_entry
) {
1172 printk(KERN_DEBUG
"%s %d: 0x%010llx 0x%010llx\n",
1173 prefix
, r
->type
, ((u64
)r
->offset
<< 12),
1174 (((u64
)r
->offset
+ r
->length
) << 12));
1180 mutex_unlock(&mm
->mutex
);
1182 printk(KERN_DEBUG
"%s total: 0x%010llx free: 0x%010llx\n",
1183 prefix
, (u64
)total
<< 12, (u64
)free
<< 12);
1184 printk(KERN_DEBUG
"%s block: 0x%08x\n",
1185 prefix
, mm
->block_size
<< 12);
1188 const struct ttm_mem_type_manager_func nouveau_vram_manager
= {
1189 nouveau_vram_manager_init
,
1190 nouveau_vram_manager_fini
,
1191 nouveau_vram_manager_new
,
1192 nouveau_vram_manager_del
,
1193 nouveau_vram_manager_debug
1197 nouveau_gart_manager_init(struct ttm_mem_type_manager
*man
, unsigned long psize
)
1203 nouveau_gart_manager_fini(struct ttm_mem_type_manager
*man
)
1209 nouveau_gart_manager_del(struct ttm_mem_type_manager
*man
,
1210 struct ttm_mem_reg
*mem
)
1212 nouveau_mem_node_cleanup(mem
->mm_node
);
1213 kfree(mem
->mm_node
);
1214 mem
->mm_node
= NULL
;
1218 nouveau_gart_manager_new(struct ttm_mem_type_manager
*man
,
1219 struct ttm_buffer_object
*bo
,
1220 struct ttm_placement
*placement
,
1221 struct ttm_mem_reg
*mem
)
1223 struct drm_nouveau_private
*dev_priv
= nouveau_bdev(bo
->bdev
);
1224 struct nouveau_mem
*node
;
1226 if (unlikely((mem
->num_pages
<< PAGE_SHIFT
) >=
1227 dev_priv
->gart_info
.aper_size
))
1230 node
= kzalloc(sizeof(*node
), GFP_KERNEL
);
1233 node
->page_shift
= 12;
1235 mem
->mm_node
= node
;
1241 nouveau_gart_manager_debug(struct ttm_mem_type_manager
*man
, const char *prefix
)
1245 const struct ttm_mem_type_manager_func nouveau_gart_manager
= {
1246 nouveau_gart_manager_init
,
1247 nouveau_gart_manager_fini
,
1248 nouveau_gart_manager_new
,
1249 nouveau_gart_manager_del
,
1250 nouveau_gart_manager_debug