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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50 };
51
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 struct nouveau_grctx;
58
59 #define MAX_NUM_DCB_ENTRIES 16
60
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
63
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73 };
74
75 struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
87 bool validate_mapped;
88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
96 struct nouveau_tile_reg *tile;
97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101 };
102
103 static inline struct nouveau_bo *
104 nouveau_bo(struct ttm_buffer_object *bo)
105 {
106 return container_of(bo, struct nouveau_bo, bo);
107 }
108
109 static inline struct nouveau_bo *
110 nouveau_gem_object(struct drm_gem_object *gem)
111 {
112 return gem ? gem->driver_private : NULL;
113 }
114
115 /* TODO: submit equivalent to TTM generic API upstream? */
116 static inline void __iomem *
117 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
118 {
119 bool is_iomem;
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
123 return ioptr;
124 }
125
126 enum nouveau_flags {
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
129 };
130
131 #define NVOBJ_ENGINE_SW 0
132 #define NVOBJ_ENGINE_GR 1
133 #define NVOBJ_ENGINE_DISPLAY 2
134 #define NVOBJ_ENGINE_INT 0xdeadbeef
135
136 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
137 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
138 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
139 #define NVOBJ_FLAG_FAKE (1 << 3)
140 struct nouveau_gpuobj {
141 struct list_head list;
142
143 struct nouveau_channel *im_channel;
144 struct drm_mm_node *im_pramin;
145 struct nouveau_bo *im_backing;
146 uint32_t im_backing_start;
147 uint32_t *im_backing_suspend;
148 int im_bound;
149
150 uint32_t flags;
151 int refcount;
152
153 uint32_t engine;
154 uint32_t class;
155
156 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
157 void *priv;
158 };
159
160 struct nouveau_gpuobj_ref {
161 struct list_head list;
162
163 struct nouveau_gpuobj *gpuobj;
164 uint32_t instance;
165
166 struct nouveau_channel *channel;
167 int handle;
168 };
169
170 struct nouveau_channel {
171 struct drm_device *dev;
172 int id;
173
174 /* owner of this fifo */
175 struct drm_file *file_priv;
176 /* mapping of the fifo itself */
177 struct drm_local_map *map;
178
179 /* mapping of the regs controling the fifo */
180 void __iomem *user;
181 uint32_t user_get;
182 uint32_t user_put;
183
184 /* Fencing */
185 struct {
186 /* lock protects the pending list only */
187 spinlock_t lock;
188 struct list_head pending;
189 uint32_t sequence;
190 uint32_t sequence_ack;
191 uint32_t last_sequence_irq;
192 } fence;
193
194 /* DMA push buffer */
195 struct nouveau_gpuobj_ref *pushbuf;
196 struct nouveau_bo *pushbuf_bo;
197 uint32_t pushbuf_base;
198
199 /* Notifier memory */
200 struct nouveau_bo *notifier_bo;
201 struct drm_mm notifier_heap;
202
203 /* PFIFO context */
204 struct nouveau_gpuobj_ref *ramfc;
205 struct nouveau_gpuobj_ref *cache;
206
207 /* PGRAPH context */
208 /* XXX may be merge 2 pointers as private data ??? */
209 struct nouveau_gpuobj_ref *ramin_grctx;
210 void *pgraph_ctx;
211
212 /* NV50 VM */
213 struct nouveau_gpuobj *vm_pd;
214 struct nouveau_gpuobj_ref *vm_gart_pt;
215 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
216
217 /* Objects */
218 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
219 struct drm_mm ramin_heap; /* Private PRAMIN heap */
220 struct nouveau_gpuobj_ref *ramht; /* Hash table */
221 struct list_head ramht_refs; /* Objects referenced by RAMHT */
222
223 /* GPU object info for stuff used in-kernel (mm_enabled) */
224 uint32_t m2mf_ntfy;
225 uint32_t vram_handle;
226 uint32_t gart_handle;
227 bool accel_done;
228
229 /* Push buffer state (only for drm's channel on !mm_enabled) */
230 struct {
231 int max;
232 int free;
233 int cur;
234 int put;
235 /* access via pushbuf_bo */
236
237 int ib_base;
238 int ib_max;
239 int ib_free;
240 int ib_put;
241 } dma;
242
243 uint32_t sw_subchannel[8];
244
245 struct {
246 struct nouveau_gpuobj *vblsem;
247 uint32_t vblsem_offset;
248 uint32_t vblsem_rval;
249 struct list_head vbl_wait;
250 } nvsw;
251
252 struct {
253 bool active;
254 char name[32];
255 struct drm_info_list info;
256 } debugfs;
257 };
258
259 struct nouveau_instmem_engine {
260 void *priv;
261
262 int (*init)(struct drm_device *dev);
263 void (*takedown)(struct drm_device *dev);
264 int (*suspend)(struct drm_device *dev);
265 void (*resume)(struct drm_device *dev);
266
267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
268 uint32_t *size);
269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
272 void (*flush)(struct drm_device *);
273 };
274
275 struct nouveau_mc_engine {
276 int (*init)(struct drm_device *dev);
277 void (*takedown)(struct drm_device *dev);
278 };
279
280 struct nouveau_timer_engine {
281 int (*init)(struct drm_device *dev);
282 void (*takedown)(struct drm_device *dev);
283 uint64_t (*read)(struct drm_device *dev);
284 };
285
286 struct nouveau_fb_engine {
287 int num_tiles;
288
289 int (*init)(struct drm_device *dev);
290 void (*takedown)(struct drm_device *dev);
291
292 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
293 uint32_t size, uint32_t pitch);
294 };
295
296 struct nouveau_fifo_engine {
297 int channels;
298
299 struct nouveau_gpuobj_ref *playlist[2];
300 int cur_playlist;
301
302 int (*init)(struct drm_device *);
303 void (*takedown)(struct drm_device *);
304
305 void (*disable)(struct drm_device *);
306 void (*enable)(struct drm_device *);
307 bool (*reassign)(struct drm_device *, bool enable);
308 bool (*cache_flush)(struct drm_device *dev);
309 bool (*cache_pull)(struct drm_device *dev, bool enable);
310
311 int (*channel_id)(struct drm_device *);
312
313 int (*create_context)(struct nouveau_channel *);
314 void (*destroy_context)(struct nouveau_channel *);
315 int (*load_context)(struct nouveau_channel *);
316 int (*unload_context)(struct drm_device *);
317 };
318
319 struct nouveau_pgraph_object_method {
320 int id;
321 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
322 uint32_t data);
323 };
324
325 struct nouveau_pgraph_object_class {
326 int id;
327 bool software;
328 struct nouveau_pgraph_object_method *methods;
329 };
330
331 struct nouveau_pgraph_engine {
332 struct nouveau_pgraph_object_class *grclass;
333 bool accel_blocked;
334 int grctx_size;
335
336 int (*init)(struct drm_device *);
337 void (*takedown)(struct drm_device *);
338
339 void (*fifo_access)(struct drm_device *, bool);
340
341 struct nouveau_channel *(*channel)(struct drm_device *);
342 int (*create_context)(struct nouveau_channel *);
343 void (*destroy_context)(struct nouveau_channel *);
344 int (*load_context)(struct nouveau_channel *);
345 int (*unload_context)(struct drm_device *);
346
347 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
348 uint32_t size, uint32_t pitch);
349 };
350
351 struct nouveau_engine {
352 struct nouveau_instmem_engine instmem;
353 struct nouveau_mc_engine mc;
354 struct nouveau_timer_engine timer;
355 struct nouveau_fb_engine fb;
356 struct nouveau_pgraph_engine graph;
357 struct nouveau_fifo_engine fifo;
358 };
359
360 struct nouveau_pll_vals {
361 union {
362 struct {
363 #ifdef __BIG_ENDIAN
364 uint8_t N1, M1, N2, M2;
365 #else
366 uint8_t M1, N1, M2, N2;
367 #endif
368 };
369 struct {
370 uint16_t NM1, NM2;
371 } __attribute__((packed));
372 };
373 int log2P;
374
375 int refclk;
376 };
377
378 enum nv04_fp_display_regs {
379 FP_DISPLAY_END,
380 FP_TOTAL,
381 FP_CRTC,
382 FP_SYNC_START,
383 FP_SYNC_END,
384 FP_VALID_START,
385 FP_VALID_END
386 };
387
388 struct nv04_crtc_reg {
389 unsigned char MiscOutReg; /* */
390 uint8_t CRTC[0x9f];
391 uint8_t CR58[0x10];
392 uint8_t Sequencer[5];
393 uint8_t Graphics[9];
394 uint8_t Attribute[21];
395 unsigned char DAC[768]; /* Internal Colorlookuptable */
396
397 /* PCRTC regs */
398 uint32_t fb_start;
399 uint32_t crtc_cfg;
400 uint32_t cursor_cfg;
401 uint32_t gpio_ext;
402 uint32_t crtc_830;
403 uint32_t crtc_834;
404 uint32_t crtc_850;
405 uint32_t crtc_eng_ctrl;
406
407 /* PRAMDAC regs */
408 uint32_t nv10_cursync;
409 struct nouveau_pll_vals pllvals;
410 uint32_t ramdac_gen_ctrl;
411 uint32_t ramdac_630;
412 uint32_t ramdac_634;
413 uint32_t tv_setup;
414 uint32_t tv_vtotal;
415 uint32_t tv_vskew;
416 uint32_t tv_vsync_delay;
417 uint32_t tv_htotal;
418 uint32_t tv_hskew;
419 uint32_t tv_hsync_delay;
420 uint32_t tv_hsync_delay2;
421 uint32_t fp_horiz_regs[7];
422 uint32_t fp_vert_regs[7];
423 uint32_t dither;
424 uint32_t fp_control;
425 uint32_t dither_regs[6];
426 uint32_t fp_debug_0;
427 uint32_t fp_debug_1;
428 uint32_t fp_debug_2;
429 uint32_t fp_margin_color;
430 uint32_t ramdac_8c0;
431 uint32_t ramdac_a20;
432 uint32_t ramdac_a24;
433 uint32_t ramdac_a34;
434 uint32_t ctv_regs[38];
435 };
436
437 struct nv04_output_reg {
438 uint32_t output;
439 int head;
440 };
441
442 struct nv04_mode_state {
443 uint32_t bpp;
444 uint32_t width;
445 uint32_t height;
446 uint32_t interlace;
447 uint32_t repaint0;
448 uint32_t repaint1;
449 uint32_t screen;
450 uint32_t scale;
451 uint32_t dither;
452 uint32_t extra;
453 uint32_t fifo;
454 uint32_t pixel;
455 uint32_t horiz;
456 int arbitration0;
457 int arbitration1;
458 uint32_t pll;
459 uint32_t pllB;
460 uint32_t vpll;
461 uint32_t vpll2;
462 uint32_t vpllB;
463 uint32_t vpll2B;
464 uint32_t pllsel;
465 uint32_t sel_clk;
466 uint32_t general;
467 uint32_t crtcOwner;
468 uint32_t head;
469 uint32_t head2;
470 uint32_t cursorConfig;
471 uint32_t cursor0;
472 uint32_t cursor1;
473 uint32_t cursor2;
474 uint32_t timingH;
475 uint32_t timingV;
476 uint32_t displayV;
477 uint32_t crtcSync;
478
479 struct nv04_crtc_reg crtc_reg[2];
480 };
481
482 enum nouveau_card_type {
483 NV_04 = 0x00,
484 NV_10 = 0x10,
485 NV_20 = 0x20,
486 NV_30 = 0x30,
487 NV_40 = 0x40,
488 NV_50 = 0x50,
489 };
490
491 struct drm_nouveau_private {
492 struct drm_device *dev;
493
494 /* the card type, takes NV_* as values */
495 enum nouveau_card_type card_type;
496 /* exact chipset, derived from NV_PMC_BOOT_0 */
497 int chipset;
498 int flags;
499
500 void __iomem *mmio;
501 void __iomem *ramin;
502 uint32_t ramin_size;
503
504 struct nouveau_bo *vga_ram;
505
506 struct workqueue_struct *wq;
507 struct work_struct irq_work;
508 struct work_struct hpd_work;
509
510 struct list_head vbl_waiting;
511
512 struct {
513 struct ttm_global_reference mem_global_ref;
514 struct ttm_bo_global_ref bo_global_ref;
515 struct ttm_bo_device bdev;
516 spinlock_t bo_list_lock;
517 struct list_head bo_list;
518 atomic_t validate_sequence;
519 } ttm;
520
521 int fifo_alloc_count;
522 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
523
524 struct nouveau_engine engine;
525 struct nouveau_channel *channel;
526
527 /* For PFIFO and PGRAPH. */
528 spinlock_t context_switch_lock;
529
530 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
531 struct nouveau_gpuobj *ramht;
532 uint32_t ramin_rsvd_vram;
533 uint32_t ramht_offset;
534 uint32_t ramht_size;
535 uint32_t ramht_bits;
536 uint32_t ramfc_offset;
537 uint32_t ramfc_size;
538 uint32_t ramro_offset;
539 uint32_t ramro_size;
540
541 struct {
542 enum {
543 NOUVEAU_GART_NONE = 0,
544 NOUVEAU_GART_AGP,
545 NOUVEAU_GART_SGDMA
546 } type;
547 uint64_t aper_base;
548 uint64_t aper_size;
549 uint64_t aper_free;
550
551 struct nouveau_gpuobj *sg_ctxdma;
552 struct page *sg_dummy_page;
553 dma_addr_t sg_dummy_bus;
554 } gart_info;
555
556 /* nv10-nv40 tiling regions */
557 struct {
558 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
559 spinlock_t lock;
560 } tile;
561
562 /* VRAM/fb configuration */
563 uint64_t vram_size;
564 uint64_t vram_sys_base;
565
566 uint64_t fb_phys;
567 uint64_t fb_available_size;
568 uint64_t fb_mappable_pages;
569 uint64_t fb_aper_free;
570 int fb_mtrr;
571
572 /* G8x/G9x virtual address space */
573 uint64_t vm_gart_base;
574 uint64_t vm_gart_size;
575 uint64_t vm_vram_base;
576 uint64_t vm_vram_size;
577 uint64_t vm_end;
578 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
579 int vm_vram_pt_nr;
580
581 struct drm_mm ramin_heap;
582
583 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
584 uint32_t ctx_table_size;
585 struct nouveau_gpuobj_ref *ctx_table;
586
587 struct list_head gpuobj_list;
588
589 struct nvbios vbios;
590
591 struct nv04_mode_state mode_reg;
592 struct nv04_mode_state saved_reg;
593 uint32_t saved_vga_font[4][16384];
594 uint32_t crtc_owner;
595 uint32_t dac_users[4];
596
597 struct nouveau_suspend_resume {
598 uint32_t *ramin_copy;
599 } susres;
600
601 struct backlight_device *backlight;
602
603 struct nouveau_channel *evo;
604 struct {
605 struct dcb_entry *dcb;
606 u16 script;
607 u32 pclk;
608 } evo_irq;
609
610 struct {
611 struct dentry *channel_root;
612 } debugfs;
613
614 struct nouveau_fbdev *nfbdev;
615 struct apertures_struct *apertures;
616 };
617
618 static inline struct drm_nouveau_private *
619 nouveau_bdev(struct ttm_bo_device *bd)
620 {
621 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
622 }
623
624 static inline int
625 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
626 {
627 struct nouveau_bo *prev;
628
629 if (!pnvbo)
630 return -EINVAL;
631 prev = *pnvbo;
632
633 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
634 if (prev) {
635 struct ttm_buffer_object *bo = &prev->bo;
636
637 ttm_bo_unref(&bo);
638 }
639
640 return 0;
641 }
642
643 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
644 struct drm_nouveau_private *nv = dev->dev_private; \
645 if (!nouveau_channel_owner(dev, (cl), (id))) { \
646 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
647 DRM_CURRENTPID, (id)); \
648 return -EPERM; \
649 } \
650 (ch) = nv->fifos[(id)]; \
651 } while (0)
652
653 /* nouveau_drv.c */
654 extern int nouveau_noagp;
655 extern int nouveau_duallink;
656 extern int nouveau_uscript_lvds;
657 extern int nouveau_uscript_tmds;
658 extern int nouveau_vram_pushbuf;
659 extern int nouveau_vram_notify;
660 extern int nouveau_fbpercrtc;
661 extern int nouveau_tv_disable;
662 extern char *nouveau_tv_norm;
663 extern int nouveau_reg_debug;
664 extern char *nouveau_vbios;
665 extern int nouveau_ignorelid;
666 extern int nouveau_nofbaccel;
667 extern int nouveau_noaccel;
668 extern int nouveau_override_conntype;
669
670 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
671 extern int nouveau_pci_resume(struct pci_dev *pdev);
672
673 /* nouveau_state.c */
674 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
675 extern int nouveau_load(struct drm_device *, unsigned long flags);
676 extern int nouveau_firstopen(struct drm_device *);
677 extern void nouveau_lastclose(struct drm_device *);
678 extern int nouveau_unload(struct drm_device *);
679 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
680 struct drm_file *);
681 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
682 struct drm_file *);
683 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
684 uint32_t reg, uint32_t mask, uint32_t val);
685 extern bool nouveau_wait_for_idle(struct drm_device *);
686 extern int nouveau_card_init(struct drm_device *);
687
688 /* nouveau_mem.c */
689 extern int nouveau_mem_detect(struct drm_device *dev);
690 extern int nouveau_mem_init(struct drm_device *);
691 extern int nouveau_mem_init_agp(struct drm_device *);
692 extern void nouveau_mem_close(struct drm_device *);
693 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
694 uint32_t addr,
695 uint32_t size,
696 uint32_t pitch);
697 extern void nv10_mem_expire_tiling(struct drm_device *dev,
698 struct nouveau_tile_reg *tile,
699 struct nouveau_fence *fence);
700 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
701 uint32_t size, uint32_t flags,
702 uint64_t phys);
703 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
704 uint32_t size);
705
706 /* nouveau_notifier.c */
707 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
708 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
709 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
710 int cout, uint32_t *offset);
711 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
712 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
713 struct drm_file *);
714 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
715 struct drm_file *);
716
717 /* nouveau_channel.c */
718 extern struct drm_ioctl_desc nouveau_ioctls[];
719 extern int nouveau_max_ioctl;
720 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
721 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
722 int channel);
723 extern int nouveau_channel_alloc(struct drm_device *dev,
724 struct nouveau_channel **chan,
725 struct drm_file *file_priv,
726 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
727 extern void nouveau_channel_free(struct nouveau_channel *);
728
729 /* nouveau_object.c */
730 extern int nouveau_gpuobj_early_init(struct drm_device *);
731 extern int nouveau_gpuobj_init(struct drm_device *);
732 extern void nouveau_gpuobj_takedown(struct drm_device *);
733 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
734 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
735 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
736 extern void nouveau_gpuobj_resume(struct drm_device *dev);
737 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
738 uint32_t vram_h, uint32_t tt_h);
739 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
740 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
741 uint32_t size, int align, uint32_t flags,
742 struct nouveau_gpuobj **);
743 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
744 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
745 uint32_t handle, struct nouveau_gpuobj *,
746 struct nouveau_gpuobj_ref **);
747 extern int nouveau_gpuobj_ref_del(struct drm_device *,
748 struct nouveau_gpuobj_ref **);
749 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
750 struct nouveau_gpuobj_ref **ref_ret);
751 extern int nouveau_gpuobj_new_ref(struct drm_device *,
752 struct nouveau_channel *alloc_chan,
753 struct nouveau_channel *ref_chan,
754 uint32_t handle, uint32_t size, int align,
755 uint32_t flags, struct nouveau_gpuobj_ref **);
756 extern int nouveau_gpuobj_new_fake(struct drm_device *,
757 uint32_t p_offset, uint32_t b_offset,
758 uint32_t size, uint32_t flags,
759 struct nouveau_gpuobj **,
760 struct nouveau_gpuobj_ref**);
761 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
762 uint64_t offset, uint64_t size, int access,
763 int target, struct nouveau_gpuobj **);
764 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
765 uint64_t offset, uint64_t size,
766 int access, struct nouveau_gpuobj **,
767 uint32_t *o_ret);
768 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
769 struct nouveau_gpuobj **);
770 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
771 struct nouveau_gpuobj **);
772 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
773 struct drm_file *);
774 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
775 struct drm_file *);
776
777 /* nouveau_irq.c */
778 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
779 extern void nouveau_irq_preinstall(struct drm_device *);
780 extern int nouveau_irq_postinstall(struct drm_device *);
781 extern void nouveau_irq_uninstall(struct drm_device *);
782
783 /* nouveau_sgdma.c */
784 extern int nouveau_sgdma_init(struct drm_device *);
785 extern void nouveau_sgdma_takedown(struct drm_device *);
786 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
787 uint32_t *page);
788 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
789
790 /* nouveau_debugfs.c */
791 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
792 extern int nouveau_debugfs_init(struct drm_minor *);
793 extern void nouveau_debugfs_takedown(struct drm_minor *);
794 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
795 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
796 #else
797 static inline int
798 nouveau_debugfs_init(struct drm_minor *minor)
799 {
800 return 0;
801 }
802
803 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
804 {
805 }
806
807 static inline int
808 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
809 {
810 return 0;
811 }
812
813 static inline void
814 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
815 {
816 }
817 #endif
818
819 /* nouveau_dma.c */
820 extern void nouveau_dma_pre_init(struct nouveau_channel *);
821 extern int nouveau_dma_init(struct nouveau_channel *);
822 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
823
824 /* nouveau_acpi.c */
825 #define ROM_BIOS_PAGE 4096
826 #if defined(CONFIG_ACPI)
827 void nouveau_register_dsm_handler(void);
828 void nouveau_unregister_dsm_handler(void);
829 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
830 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
831 #else
832 static inline void nouveau_register_dsm_handler(void) {}
833 static inline void nouveau_unregister_dsm_handler(void) {}
834 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
835 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
836 #endif
837
838 /* nouveau_backlight.c */
839 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
840 extern int nouveau_backlight_init(struct drm_device *);
841 extern void nouveau_backlight_exit(struct drm_device *);
842 #else
843 static inline int nouveau_backlight_init(struct drm_device *dev)
844 {
845 return 0;
846 }
847
848 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
849 #endif
850
851 /* nouveau_bios.c */
852 extern int nouveau_bios_init(struct drm_device *);
853 extern void nouveau_bios_takedown(struct drm_device *dev);
854 extern int nouveau_run_vbios_init(struct drm_device *);
855 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
856 struct dcb_entry *);
857 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
858 enum dcb_gpio_tag);
859 extern struct dcb_connector_table_entry *
860 nouveau_bios_connector_entry(struct drm_device *, int index);
861 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
862 struct pll_lims *);
863 extern int nouveau_bios_run_display_table(struct drm_device *,
864 struct dcb_entry *,
865 uint32_t script, int pxclk);
866 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
867 int *length);
868 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
869 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
870 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
871 bool *dl, bool *if_is_24bit);
872 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
873 int head, int pxclk);
874 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
875 enum LVDS_script, int pxclk);
876
877 /* nouveau_ttm.c */
878 int nouveau_ttm_global_init(struct drm_nouveau_private *);
879 void nouveau_ttm_global_release(struct drm_nouveau_private *);
880 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
881
882 /* nouveau_dp.c */
883 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
884 uint8_t *data, int data_nr);
885 bool nouveau_dp_detect(struct drm_encoder *);
886 bool nouveau_dp_link_train(struct drm_encoder *);
887
888 /* nv04_fb.c */
889 extern int nv04_fb_init(struct drm_device *);
890 extern void nv04_fb_takedown(struct drm_device *);
891
892 /* nv10_fb.c */
893 extern int nv10_fb_init(struct drm_device *);
894 extern void nv10_fb_takedown(struct drm_device *);
895 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
896 uint32_t, uint32_t);
897
898 /* nv40_fb.c */
899 extern int nv40_fb_init(struct drm_device *);
900 extern void nv40_fb_takedown(struct drm_device *);
901 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
902 uint32_t, uint32_t);
903
904 /* nv50_fb.c */
905 extern int nv50_fb_init(struct drm_device *);
906 extern void nv50_fb_takedown(struct drm_device *);
907
908 /* nv04_fifo.c */
909 extern int nv04_fifo_init(struct drm_device *);
910 extern void nv04_fifo_disable(struct drm_device *);
911 extern void nv04_fifo_enable(struct drm_device *);
912 extern bool nv04_fifo_reassign(struct drm_device *, bool);
913 extern bool nv04_fifo_cache_flush(struct drm_device *);
914 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
915 extern int nv04_fifo_channel_id(struct drm_device *);
916 extern int nv04_fifo_create_context(struct nouveau_channel *);
917 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
918 extern int nv04_fifo_load_context(struct nouveau_channel *);
919 extern int nv04_fifo_unload_context(struct drm_device *);
920
921 /* nv10_fifo.c */
922 extern int nv10_fifo_init(struct drm_device *);
923 extern int nv10_fifo_channel_id(struct drm_device *);
924 extern int nv10_fifo_create_context(struct nouveau_channel *);
925 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
926 extern int nv10_fifo_load_context(struct nouveau_channel *);
927 extern int nv10_fifo_unload_context(struct drm_device *);
928
929 /* nv40_fifo.c */
930 extern int nv40_fifo_init(struct drm_device *);
931 extern int nv40_fifo_create_context(struct nouveau_channel *);
932 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
933 extern int nv40_fifo_load_context(struct nouveau_channel *);
934 extern int nv40_fifo_unload_context(struct drm_device *);
935
936 /* nv50_fifo.c */
937 extern int nv50_fifo_init(struct drm_device *);
938 extern void nv50_fifo_takedown(struct drm_device *);
939 extern int nv50_fifo_channel_id(struct drm_device *);
940 extern int nv50_fifo_create_context(struct nouveau_channel *);
941 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
942 extern int nv50_fifo_load_context(struct nouveau_channel *);
943 extern int nv50_fifo_unload_context(struct drm_device *);
944
945 /* nv04_graph.c */
946 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
947 extern int nv04_graph_init(struct drm_device *);
948 extern void nv04_graph_takedown(struct drm_device *);
949 extern void nv04_graph_fifo_access(struct drm_device *, bool);
950 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
951 extern int nv04_graph_create_context(struct nouveau_channel *);
952 extern void nv04_graph_destroy_context(struct nouveau_channel *);
953 extern int nv04_graph_load_context(struct nouveau_channel *);
954 extern int nv04_graph_unload_context(struct drm_device *);
955 extern void nv04_graph_context_switch(struct drm_device *);
956
957 /* nv10_graph.c */
958 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
959 extern int nv10_graph_init(struct drm_device *);
960 extern void nv10_graph_takedown(struct drm_device *);
961 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
962 extern int nv10_graph_create_context(struct nouveau_channel *);
963 extern void nv10_graph_destroy_context(struct nouveau_channel *);
964 extern int nv10_graph_load_context(struct nouveau_channel *);
965 extern int nv10_graph_unload_context(struct drm_device *);
966 extern void nv10_graph_context_switch(struct drm_device *);
967 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
968 uint32_t, uint32_t);
969
970 /* nv20_graph.c */
971 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
972 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
973 extern int nv20_graph_create_context(struct nouveau_channel *);
974 extern void nv20_graph_destroy_context(struct nouveau_channel *);
975 extern int nv20_graph_load_context(struct nouveau_channel *);
976 extern int nv20_graph_unload_context(struct drm_device *);
977 extern int nv20_graph_init(struct drm_device *);
978 extern void nv20_graph_takedown(struct drm_device *);
979 extern int nv30_graph_init(struct drm_device *);
980 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
981 uint32_t, uint32_t);
982
983 /* nv40_graph.c */
984 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
985 extern int nv40_graph_init(struct drm_device *);
986 extern void nv40_graph_takedown(struct drm_device *);
987 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
988 extern int nv40_graph_create_context(struct nouveau_channel *);
989 extern void nv40_graph_destroy_context(struct nouveau_channel *);
990 extern int nv40_graph_load_context(struct nouveau_channel *);
991 extern int nv40_graph_unload_context(struct drm_device *);
992 extern void nv40_grctx_init(struct nouveau_grctx *);
993 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
994 uint32_t, uint32_t);
995
996 /* nv50_graph.c */
997 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
998 extern int nv50_graph_init(struct drm_device *);
999 extern void nv50_graph_takedown(struct drm_device *);
1000 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1001 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1002 extern int nv50_graph_create_context(struct nouveau_channel *);
1003 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1004 extern int nv50_graph_load_context(struct nouveau_channel *);
1005 extern int nv50_graph_unload_context(struct drm_device *);
1006 extern void nv50_graph_context_switch(struct drm_device *);
1007 extern int nv50_grctx_init(struct nouveau_grctx *);
1008
1009 /* nv04_instmem.c */
1010 extern int nv04_instmem_init(struct drm_device *);
1011 extern void nv04_instmem_takedown(struct drm_device *);
1012 extern int nv04_instmem_suspend(struct drm_device *);
1013 extern void nv04_instmem_resume(struct drm_device *);
1014 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1015 uint32_t *size);
1016 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1017 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1018 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1019 extern void nv04_instmem_flush(struct drm_device *);
1020
1021 /* nv50_instmem.c */
1022 extern int nv50_instmem_init(struct drm_device *);
1023 extern void nv50_instmem_takedown(struct drm_device *);
1024 extern int nv50_instmem_suspend(struct drm_device *);
1025 extern void nv50_instmem_resume(struct drm_device *);
1026 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1027 uint32_t *size);
1028 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1029 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1030 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1031 extern void nv50_instmem_flush(struct drm_device *);
1032 extern void nv50_vm_flush(struct drm_device *, int engine);
1033
1034 /* nv04_mc.c */
1035 extern int nv04_mc_init(struct drm_device *);
1036 extern void nv04_mc_takedown(struct drm_device *);
1037
1038 /* nv40_mc.c */
1039 extern int nv40_mc_init(struct drm_device *);
1040 extern void nv40_mc_takedown(struct drm_device *);
1041
1042 /* nv50_mc.c */
1043 extern int nv50_mc_init(struct drm_device *);
1044 extern void nv50_mc_takedown(struct drm_device *);
1045
1046 /* nv04_timer.c */
1047 extern int nv04_timer_init(struct drm_device *);
1048 extern uint64_t nv04_timer_read(struct drm_device *);
1049 extern void nv04_timer_takedown(struct drm_device *);
1050
1051 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1052 unsigned long arg);
1053
1054 /* nv04_dac.c */
1055 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1056 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1057 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1058 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1059 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1060
1061 /* nv04_dfp.c */
1062 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1063 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1064 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1065 int head, bool dl);
1066 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1067 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1068
1069 /* nv04_tv.c */
1070 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1071 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1072
1073 /* nv17_tv.c */
1074 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1075
1076 /* nv04_display.c */
1077 extern int nv04_display_create(struct drm_device *);
1078 extern void nv04_display_destroy(struct drm_device *);
1079 extern void nv04_display_restore(struct drm_device *);
1080
1081 /* nv04_crtc.c */
1082 extern int nv04_crtc_create(struct drm_device *, int index);
1083
1084 /* nouveau_bo.c */
1085 extern struct ttm_bo_driver nouveau_bo_driver;
1086 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1087 int size, int align, uint32_t flags,
1088 uint32_t tile_mode, uint32_t tile_flags,
1089 bool no_vm, bool mappable, struct nouveau_bo **);
1090 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1091 extern int nouveau_bo_unpin(struct nouveau_bo *);
1092 extern int nouveau_bo_map(struct nouveau_bo *);
1093 extern void nouveau_bo_unmap(struct nouveau_bo *);
1094 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1095 uint32_t busy);
1096 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1097 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1098 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1099 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1100
1101 /* nouveau_fence.c */
1102 struct nouveau_fence;
1103 extern int nouveau_fence_init(struct nouveau_channel *);
1104 extern void nouveau_fence_fini(struct nouveau_channel *);
1105 extern void nouveau_fence_update(struct nouveau_channel *);
1106 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1107 bool emit);
1108 extern int nouveau_fence_emit(struct nouveau_fence *);
1109 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1110 extern bool nouveau_fence_signalled(void *obj, void *arg);
1111 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1112 extern int nouveau_fence_flush(void *obj, void *arg);
1113 extern void nouveau_fence_unref(void **obj);
1114 extern void *nouveau_fence_ref(void *obj);
1115 extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1116
1117 /* nouveau_gem.c */
1118 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1119 int size, int align, uint32_t flags,
1120 uint32_t tile_mode, uint32_t tile_flags,
1121 bool no_vm, bool mappable, struct nouveau_bo **);
1122 extern int nouveau_gem_object_new(struct drm_gem_object *);
1123 extern void nouveau_gem_object_del(struct drm_gem_object *);
1124 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1125 struct drm_file *);
1126 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1127 struct drm_file *);
1128 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1129 struct drm_file *);
1130 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1131 struct drm_file *);
1132 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1133 struct drm_file *);
1134
1135 /* nv17_gpio.c */
1136 int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1137 int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1138
1139 /* nv50_gpio.c */
1140 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1141 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1142
1143 /* nv50_calc. */
1144 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1145 int *N1, int *M1, int *N2, int *M2, int *P);
1146 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1147 int clk, int *N, int *fN, int *M, int *P);
1148
1149 #ifndef ioread32_native
1150 #ifdef __BIG_ENDIAN
1151 #define ioread16_native ioread16be
1152 #define iowrite16_native iowrite16be
1153 #define ioread32_native ioread32be
1154 #define iowrite32_native iowrite32be
1155 #else /* def __BIG_ENDIAN */
1156 #define ioread16_native ioread16
1157 #define iowrite16_native iowrite16
1158 #define ioread32_native ioread32
1159 #define iowrite32_native iowrite32
1160 #endif /* def __BIG_ENDIAN else */
1161 #endif /* !ioread32_native */
1162
1163 /* channel control reg access */
1164 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1165 {
1166 return ioread32_native(chan->user + reg);
1167 }
1168
1169 static inline void nvchan_wr32(struct nouveau_channel *chan,
1170 unsigned reg, u32 val)
1171 {
1172 iowrite32_native(val, chan->user + reg);
1173 }
1174
1175 /* register access */
1176 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1177 {
1178 struct drm_nouveau_private *dev_priv = dev->dev_private;
1179 return ioread32_native(dev_priv->mmio + reg);
1180 }
1181
1182 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1183 {
1184 struct drm_nouveau_private *dev_priv = dev->dev_private;
1185 iowrite32_native(val, dev_priv->mmio + reg);
1186 }
1187
1188 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1189 {
1190 struct drm_nouveau_private *dev_priv = dev->dev_private;
1191 return ioread8(dev_priv->mmio + reg);
1192 }
1193
1194 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1195 {
1196 struct drm_nouveau_private *dev_priv = dev->dev_private;
1197 iowrite8(val, dev_priv->mmio + reg);
1198 }
1199
1200 #define nv_wait(reg, mask, val) \
1201 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1202
1203 /* PRAMIN access */
1204 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1205 {
1206 struct drm_nouveau_private *dev_priv = dev->dev_private;
1207 return ioread32_native(dev_priv->ramin + offset);
1208 }
1209
1210 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1211 {
1212 struct drm_nouveau_private *dev_priv = dev->dev_private;
1213 iowrite32_native(val, dev_priv->ramin + offset);
1214 }
1215
1216 /* object access */
1217 static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1218 unsigned index)
1219 {
1220 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1221 }
1222
1223 static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1224 unsigned index, u32 val)
1225 {
1226 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1227 }
1228
1229 /*
1230 * Logging
1231 * Argument d is (struct drm_device *).
1232 */
1233 #define NV_PRINTK(level, d, fmt, arg...) \
1234 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1235 pci_name(d->pdev), ##arg)
1236 #ifndef NV_DEBUG_NOTRACE
1237 #define NV_DEBUG(d, fmt, arg...) do { \
1238 if (drm_debug & DRM_UT_DRIVER) { \
1239 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1240 __LINE__, ##arg); \
1241 } \
1242 } while (0)
1243 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1244 if (drm_debug & DRM_UT_KMS) { \
1245 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1246 __LINE__, ##arg); \
1247 } \
1248 } while (0)
1249 #else
1250 #define NV_DEBUG(d, fmt, arg...) do { \
1251 if (drm_debug & DRM_UT_DRIVER) \
1252 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1253 } while (0)
1254 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1255 if (drm_debug & DRM_UT_KMS) \
1256 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1257 } while (0)
1258 #endif
1259 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1260 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1261 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1262 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1263 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1264
1265 /* nouveau_reg_debug bitmask */
1266 enum {
1267 NOUVEAU_REG_DEBUG_MC = 0x1,
1268 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1269 NOUVEAU_REG_DEBUG_FB = 0x4,
1270 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1271 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1272 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1273 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1274 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1275 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1276 NOUVEAU_REG_DEBUG_EVO = 0x200,
1277 };
1278
1279 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1280 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1281 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1282 } while (0)
1283
1284 static inline bool
1285 nv_two_heads(struct drm_device *dev)
1286 {
1287 struct drm_nouveau_private *dev_priv = dev->dev_private;
1288 const int impl = dev->pci_device & 0x0ff0;
1289
1290 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1291 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1292 return true;
1293
1294 return false;
1295 }
1296
1297 static inline bool
1298 nv_gf4_disp_arch(struct drm_device *dev)
1299 {
1300 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1301 }
1302
1303 static inline bool
1304 nv_two_reg_pll(struct drm_device *dev)
1305 {
1306 struct drm_nouveau_private *dev_priv = dev->dev_private;
1307 const int impl = dev->pci_device & 0x0ff0;
1308
1309 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1310 return true;
1311 return false;
1312 }
1313
1314 #define NV_SW 0x0000506e
1315 #define NV_SW_DMA_SEMAPHORE 0x00000060
1316 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1317 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1318 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1319 #define NV_SW_DMA_VBLSEM 0x0000018c
1320 #define NV_SW_VBLSEM_OFFSET 0x00000400
1321 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1322 #define NV_SW_VBLSEM_RELEASE 0x00000408
1323
1324 #endif /* __NOUVEAU_DRV_H__ */
kernel source for telekom puls (alcatel/mediatek)