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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50 };
51
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 #include "nouveau_util.h"
58
59 struct nouveau_grctx;
60 struct nouveau_mem;
61 #include "nouveau_vm.h"
62
63 #define MAX_NUM_DCB_ENTRIES 16
64
65 #define NOUVEAU_MAX_CHANNEL_NR 128
66 #define NOUVEAU_MAX_TILE_NR 15
67
68 struct nouveau_mem {
69 struct drm_device *dev;
70
71 struct nouveau_vma bar_vma;
72 struct nouveau_vma tmp_vma;
73 u8 page_shift;
74
75 struct drm_mm_node *tag;
76 struct list_head regions;
77 dma_addr_t *pages;
78 u32 memtype;
79 u64 offset;
80 u64 size;
81 };
82
83 struct nouveau_tile_reg {
84 bool used;
85 uint32_t addr;
86 uint32_t limit;
87 uint32_t pitch;
88 uint32_t zcomp;
89 struct drm_mm_node *tag_mem;
90 struct nouveau_fence *fence;
91 };
92
93 struct nouveau_bo {
94 struct ttm_buffer_object bo;
95 struct ttm_placement placement;
96 u32 valid_domains;
97 u32 placements[3];
98 u32 busy_placements[3];
99 struct ttm_bo_kmap_obj kmap;
100 struct list_head head;
101
102 /* protected by ttm_bo_reserve() */
103 struct drm_file *reserved_by;
104 struct list_head entry;
105 int pbbo_index;
106 bool validate_mapped;
107
108 struct nouveau_channel *channel;
109
110 struct nouveau_vma vma;
111
112 uint32_t tile_mode;
113 uint32_t tile_flags;
114 struct nouveau_tile_reg *tile;
115
116 struct drm_gem_object *gem;
117 int pin_refcnt;
118 };
119
120 #define nouveau_bo_tile_layout(nvbo) \
121 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
122
123 static inline struct nouveau_bo *
124 nouveau_bo(struct ttm_buffer_object *bo)
125 {
126 return container_of(bo, struct nouveau_bo, bo);
127 }
128
129 static inline struct nouveau_bo *
130 nouveau_gem_object(struct drm_gem_object *gem)
131 {
132 return gem ? gem->driver_private : NULL;
133 }
134
135 /* TODO: submit equivalent to TTM generic API upstream? */
136 static inline void __iomem *
137 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
138 {
139 bool is_iomem;
140 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
141 &nvbo->kmap, &is_iomem);
142 WARN_ON_ONCE(ioptr && !is_iomem);
143 return ioptr;
144 }
145
146 enum nouveau_flags {
147 NV_NFORCE = 0x10000000,
148 NV_NFORCE2 = 0x20000000
149 };
150
151 #define NVOBJ_ENGINE_SW 0
152 #define NVOBJ_ENGINE_GR 1
153 #define NVOBJ_ENGINE_PPP 2
154 #define NVOBJ_ENGINE_COPY 3
155 #define NVOBJ_ENGINE_VP 4
156 #define NVOBJ_ENGINE_CRYPT 5
157 #define NVOBJ_ENGINE_BSP 6
158 #define NVOBJ_ENGINE_DISPLAY 0xcafe0001
159 #define NVOBJ_ENGINE_INT 0xdeadbeef
160
161 #define NVOBJ_FLAG_DONT_MAP (1 << 0)
162 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
163 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
164 #define NVOBJ_FLAG_VM (1 << 3)
165 #define NVOBJ_FLAG_VM_USER (1 << 4)
166
167 #define NVOBJ_CINST_GLOBAL 0xdeadbeef
168
169 struct nouveau_gpuobj {
170 struct drm_device *dev;
171 struct kref refcount;
172 struct list_head list;
173
174 void *node;
175 u32 *suspend;
176
177 uint32_t flags;
178
179 u32 size;
180 u32 pinst;
181 u32 cinst;
182 u64 vinst;
183
184 uint32_t engine;
185 uint32_t class;
186
187 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
188 void *priv;
189 };
190
191 struct nouveau_page_flip_state {
192 struct list_head head;
193 struct drm_pending_vblank_event *event;
194 int crtc, bpp, pitch, x, y;
195 uint64_t offset;
196 };
197
198 enum nouveau_channel_mutex_class {
199 NOUVEAU_UCHANNEL_MUTEX,
200 NOUVEAU_KCHANNEL_MUTEX
201 };
202
203 struct nouveau_channel {
204 struct drm_device *dev;
205 int id;
206
207 /* references to the channel data structure */
208 struct kref ref;
209 /* users of the hardware channel resources, the hardware
210 * context will be kicked off when it reaches zero. */
211 atomic_t users;
212 struct mutex mutex;
213
214 /* owner of this fifo */
215 struct drm_file *file_priv;
216 /* mapping of the fifo itself */
217 struct drm_local_map *map;
218
219 /* mapping of the regs controlling the fifo */
220 void __iomem *user;
221 uint32_t user_get;
222 uint32_t user_put;
223
224 /* Fencing */
225 struct {
226 /* lock protects the pending list only */
227 spinlock_t lock;
228 struct list_head pending;
229 uint32_t sequence;
230 uint32_t sequence_ack;
231 atomic_t last_sequence_irq;
232 } fence;
233
234 /* DMA push buffer */
235 struct nouveau_gpuobj *pushbuf;
236 struct nouveau_bo *pushbuf_bo;
237 uint32_t pushbuf_base;
238
239 /* Notifier memory */
240 struct nouveau_bo *notifier_bo;
241 struct drm_mm notifier_heap;
242
243 /* PFIFO context */
244 struct nouveau_gpuobj *ramfc;
245 struct nouveau_gpuobj *cache;
246 void *fifo_priv;
247
248 /* PGRAPH context */
249 /* XXX may be merge 2 pointers as private data ??? */
250 struct nouveau_gpuobj *ramin_grctx;
251 struct nouveau_gpuobj *crypt_ctx;
252 void *pgraph_ctx;
253
254 /* NV50 VM */
255 struct nouveau_vm *vm;
256 struct nouveau_gpuobj *vm_pd;
257
258 /* Objects */
259 struct nouveau_gpuobj *ramin; /* Private instmem */
260 struct drm_mm ramin_heap; /* Private PRAMIN heap */
261 struct nouveau_ramht *ramht; /* Hash table */
262
263 /* GPU object info for stuff used in-kernel (mm_enabled) */
264 uint32_t m2mf_ntfy;
265 uint32_t vram_handle;
266 uint32_t gart_handle;
267 bool accel_done;
268
269 /* Push buffer state (only for drm's channel on !mm_enabled) */
270 struct {
271 int max;
272 int free;
273 int cur;
274 int put;
275 /* access via pushbuf_bo */
276
277 int ib_base;
278 int ib_max;
279 int ib_free;
280 int ib_put;
281 } dma;
282
283 uint32_t sw_subchannel[8];
284
285 struct {
286 struct nouveau_gpuobj *vblsem;
287 uint32_t vblsem_head;
288 uint32_t vblsem_offset;
289 uint32_t vblsem_rval;
290 struct list_head vbl_wait;
291 struct list_head flip;
292 } nvsw;
293
294 struct {
295 bool active;
296 char name[32];
297 struct drm_info_list info;
298 } debugfs;
299 };
300
301 struct nouveau_instmem_engine {
302 void *priv;
303
304 int (*init)(struct drm_device *dev);
305 void (*takedown)(struct drm_device *dev);
306 int (*suspend)(struct drm_device *dev);
307 void (*resume)(struct drm_device *dev);
308
309 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align);
310 void (*put)(struct nouveau_gpuobj *);
311 int (*map)(struct nouveau_gpuobj *);
312 void (*unmap)(struct nouveau_gpuobj *);
313
314 void (*flush)(struct drm_device *);
315 };
316
317 struct nouveau_mc_engine {
318 int (*init)(struct drm_device *dev);
319 void (*takedown)(struct drm_device *dev);
320 };
321
322 struct nouveau_timer_engine {
323 int (*init)(struct drm_device *dev);
324 void (*takedown)(struct drm_device *dev);
325 uint64_t (*read)(struct drm_device *dev);
326 };
327
328 struct nouveau_fb_engine {
329 int num_tiles;
330 struct drm_mm tag_heap;
331 void *priv;
332
333 int (*init)(struct drm_device *dev);
334 void (*takedown)(struct drm_device *dev);
335
336 void (*init_tile_region)(struct drm_device *dev, int i,
337 uint32_t addr, uint32_t size,
338 uint32_t pitch, uint32_t flags);
339 void (*set_tile_region)(struct drm_device *dev, int i);
340 void (*free_tile_region)(struct drm_device *dev, int i);
341 };
342
343 struct nouveau_fifo_engine {
344 void *priv;
345 int channels;
346
347 struct nouveau_gpuobj *playlist[2];
348 int cur_playlist;
349
350 int (*init)(struct drm_device *);
351 void (*takedown)(struct drm_device *);
352
353 void (*disable)(struct drm_device *);
354 void (*enable)(struct drm_device *);
355 bool (*reassign)(struct drm_device *, bool enable);
356 bool (*cache_pull)(struct drm_device *dev, bool enable);
357
358 int (*channel_id)(struct drm_device *);
359
360 int (*create_context)(struct nouveau_channel *);
361 void (*destroy_context)(struct nouveau_channel *);
362 int (*load_context)(struct nouveau_channel *);
363 int (*unload_context)(struct drm_device *);
364 void (*tlb_flush)(struct drm_device *dev);
365 };
366
367 struct nouveau_pgraph_engine {
368 bool accel_blocked;
369 bool registered;
370 int grctx_size;
371 void *priv;
372
373 /* NV2x/NV3x context table (0x400780) */
374 struct nouveau_gpuobj *ctx_table;
375
376 int (*init)(struct drm_device *);
377 void (*takedown)(struct drm_device *);
378
379 void (*fifo_access)(struct drm_device *, bool);
380
381 struct nouveau_channel *(*channel)(struct drm_device *);
382 int (*create_context)(struct nouveau_channel *);
383 void (*destroy_context)(struct nouveau_channel *);
384 int (*load_context)(struct nouveau_channel *);
385 int (*unload_context)(struct drm_device *);
386 void (*tlb_flush)(struct drm_device *dev);
387
388 void (*set_tile_region)(struct drm_device *dev, int i);
389 };
390
391 struct nouveau_display_engine {
392 void *priv;
393 int (*early_init)(struct drm_device *);
394 void (*late_takedown)(struct drm_device *);
395 int (*create)(struct drm_device *);
396 int (*init)(struct drm_device *);
397 void (*destroy)(struct drm_device *);
398 };
399
400 struct nouveau_gpio_engine {
401 void *priv;
402
403 int (*init)(struct drm_device *);
404 void (*takedown)(struct drm_device *);
405
406 int (*get)(struct drm_device *, enum dcb_gpio_tag);
407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
408
409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag,
410 void (*)(void *, int), void *);
411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag,
412 void (*)(void *, int), void *);
413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
414 };
415
416 struct nouveau_pm_voltage_level {
417 u8 voltage;
418 u8 vid;
419 };
420
421 struct nouveau_pm_voltage {
422 bool supported;
423 u8 vid_mask;
424
425 struct nouveau_pm_voltage_level *level;
426 int nr_level;
427 };
428
429 #define NOUVEAU_PM_MAX_LEVEL 8
430 struct nouveau_pm_level {
431 struct device_attribute dev_attr;
432 char name[32];
433 int id;
434
435 u32 core;
436 u32 memory;
437 u32 shader;
438 u32 unk05;
439
440 u8 voltage;
441 u8 fanspeed;
442
443 u16 memscript;
444 };
445
446 struct nouveau_pm_temp_sensor_constants {
447 u16 offset_constant;
448 s16 offset_mult;
449 u16 offset_div;
450 u16 slope_mult;
451 u16 slope_div;
452 };
453
454 struct nouveau_pm_threshold_temp {
455 s16 critical;
456 s16 down_clock;
457 s16 fan_boost;
458 };
459
460 struct nouveau_pm_memtiming {
461 u32 reg_100220;
462 u32 reg_100224;
463 u32 reg_100228;
464 u32 reg_10022c;
465 u32 reg_100230;
466 u32 reg_100234;
467 u32 reg_100238;
468 u32 reg_10023c;
469 };
470
471 struct nouveau_pm_memtimings {
472 bool supported;
473 struct nouveau_pm_memtiming *timing;
474 int nr_timing;
475 };
476
477 struct nouveau_pm_engine {
478 struct nouveau_pm_voltage voltage;
479 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
480 int nr_perflvl;
481 struct nouveau_pm_memtimings memtimings;
482 struct nouveau_pm_temp_sensor_constants sensor_constants;
483 struct nouveau_pm_threshold_temp threshold_temp;
484
485 struct nouveau_pm_level boot;
486 struct nouveau_pm_level *cur;
487
488 struct device *hwmon;
489 struct notifier_block acpi_nb;
490
491 int (*clock_get)(struct drm_device *, u32 id);
492 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
493 u32 id, int khz);
494 void (*clock_set)(struct drm_device *, void *);
495 int (*voltage_get)(struct drm_device *);
496 int (*voltage_set)(struct drm_device *, int voltage);
497 int (*fanspeed_get)(struct drm_device *);
498 int (*fanspeed_set)(struct drm_device *, int fanspeed);
499 int (*temp_get)(struct drm_device *);
500 };
501
502 struct nouveau_crypt_engine {
503 bool registered;
504
505 int (*init)(struct drm_device *);
506 void (*takedown)(struct drm_device *);
507 int (*create_context)(struct nouveau_channel *);
508 void (*destroy_context)(struct nouveau_channel *);
509 void (*tlb_flush)(struct drm_device *dev);
510 };
511
512 struct nouveau_vram_engine {
513 int (*init)(struct drm_device *);
514 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
515 u32 type, struct nouveau_mem **);
516 void (*put)(struct drm_device *, struct nouveau_mem **);
517
518 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
519 };
520
521 struct nouveau_engine {
522 struct nouveau_instmem_engine instmem;
523 struct nouveau_mc_engine mc;
524 struct nouveau_timer_engine timer;
525 struct nouveau_fb_engine fb;
526 struct nouveau_pgraph_engine graph;
527 struct nouveau_fifo_engine fifo;
528 struct nouveau_display_engine display;
529 struct nouveau_gpio_engine gpio;
530 struct nouveau_pm_engine pm;
531 struct nouveau_crypt_engine crypt;
532 struct nouveau_vram_engine vram;
533 };
534
535 struct nouveau_pll_vals {
536 union {
537 struct {
538 #ifdef __BIG_ENDIAN
539 uint8_t N1, M1, N2, M2;
540 #else
541 uint8_t M1, N1, M2, N2;
542 #endif
543 };
544 struct {
545 uint16_t NM1, NM2;
546 } __attribute__((packed));
547 };
548 int log2P;
549
550 int refclk;
551 };
552
553 enum nv04_fp_display_regs {
554 FP_DISPLAY_END,
555 FP_TOTAL,
556 FP_CRTC,
557 FP_SYNC_START,
558 FP_SYNC_END,
559 FP_VALID_START,
560 FP_VALID_END
561 };
562
563 struct nv04_crtc_reg {
564 unsigned char MiscOutReg;
565 uint8_t CRTC[0xa0];
566 uint8_t CR58[0x10];
567 uint8_t Sequencer[5];
568 uint8_t Graphics[9];
569 uint8_t Attribute[21];
570 unsigned char DAC[768];
571
572 /* PCRTC regs */
573 uint32_t fb_start;
574 uint32_t crtc_cfg;
575 uint32_t cursor_cfg;
576 uint32_t gpio_ext;
577 uint32_t crtc_830;
578 uint32_t crtc_834;
579 uint32_t crtc_850;
580 uint32_t crtc_eng_ctrl;
581
582 /* PRAMDAC regs */
583 uint32_t nv10_cursync;
584 struct nouveau_pll_vals pllvals;
585 uint32_t ramdac_gen_ctrl;
586 uint32_t ramdac_630;
587 uint32_t ramdac_634;
588 uint32_t tv_setup;
589 uint32_t tv_vtotal;
590 uint32_t tv_vskew;
591 uint32_t tv_vsync_delay;
592 uint32_t tv_htotal;
593 uint32_t tv_hskew;
594 uint32_t tv_hsync_delay;
595 uint32_t tv_hsync_delay2;
596 uint32_t fp_horiz_regs[7];
597 uint32_t fp_vert_regs[7];
598 uint32_t dither;
599 uint32_t fp_control;
600 uint32_t dither_regs[6];
601 uint32_t fp_debug_0;
602 uint32_t fp_debug_1;
603 uint32_t fp_debug_2;
604 uint32_t fp_margin_color;
605 uint32_t ramdac_8c0;
606 uint32_t ramdac_a20;
607 uint32_t ramdac_a24;
608 uint32_t ramdac_a34;
609 uint32_t ctv_regs[38];
610 };
611
612 struct nv04_output_reg {
613 uint32_t output;
614 int head;
615 };
616
617 struct nv04_mode_state {
618 struct nv04_crtc_reg crtc_reg[2];
619 uint32_t pllsel;
620 uint32_t sel_clk;
621 };
622
623 enum nouveau_card_type {
624 NV_04 = 0x00,
625 NV_10 = 0x10,
626 NV_20 = 0x20,
627 NV_30 = 0x30,
628 NV_40 = 0x40,
629 NV_50 = 0x50,
630 NV_C0 = 0xc0,
631 };
632
633 struct drm_nouveau_private {
634 struct drm_device *dev;
635
636 /* the card type, takes NV_* as values */
637 enum nouveau_card_type card_type;
638 /* exact chipset, derived from NV_PMC_BOOT_0 */
639 int chipset;
640 int flags;
641
642 void __iomem *mmio;
643
644 spinlock_t ramin_lock;
645 void __iomem *ramin;
646 u32 ramin_size;
647 u32 ramin_base;
648 bool ramin_available;
649 struct drm_mm ramin_heap;
650 struct list_head gpuobj_list;
651 struct list_head classes;
652
653 struct nouveau_bo *vga_ram;
654
655 /* interrupt handling */
656 void (*irq_handler[32])(struct drm_device *);
657 bool msi_enabled;
658
659 struct list_head vbl_waiting;
660
661 struct {
662 struct drm_global_reference mem_global_ref;
663 struct ttm_bo_global_ref bo_global_ref;
664 struct ttm_bo_device bdev;
665 atomic_t validate_sequence;
666 } ttm;
667
668 struct {
669 spinlock_t lock;
670 struct drm_mm heap;
671 struct nouveau_bo *bo;
672 } fence;
673
674 struct {
675 spinlock_t lock;
676 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
677 } channels;
678
679 struct nouveau_engine engine;
680 struct nouveau_channel *channel;
681
682 /* For PFIFO and PGRAPH. */
683 spinlock_t context_switch_lock;
684
685 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
686 struct nouveau_ramht *ramht;
687 struct nouveau_gpuobj *ramfc;
688 struct nouveau_gpuobj *ramro;
689
690 uint32_t ramin_rsvd_vram;
691
692 struct {
693 enum {
694 NOUVEAU_GART_NONE = 0,
695 NOUVEAU_GART_AGP, /* AGP */
696 NOUVEAU_GART_PDMA, /* paged dma object */
697 NOUVEAU_GART_HW /* on-chip gart/vm */
698 } type;
699 uint64_t aper_base;
700 uint64_t aper_size;
701 uint64_t aper_free;
702
703 struct ttm_backend_func *func;
704
705 struct {
706 struct page *page;
707 dma_addr_t addr;
708 } dummy;
709
710 struct nouveau_gpuobj *sg_ctxdma;
711 } gart_info;
712
713 /* nv10-nv40 tiling regions */
714 struct {
715 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
716 spinlock_t lock;
717 } tile;
718
719 /* VRAM/fb configuration */
720 uint64_t vram_size;
721 uint64_t vram_sys_base;
722 u32 vram_rblock_size;
723
724 uint64_t fb_phys;
725 uint64_t fb_available_size;
726 uint64_t fb_mappable_pages;
727 uint64_t fb_aper_free;
728 int fb_mtrr;
729
730 /* BAR control (NV50-) */
731 struct nouveau_vm *bar1_vm;
732 struct nouveau_vm *bar3_vm;
733
734 /* G8x/G9x virtual address space */
735 struct nouveau_vm *chan_vm;
736
737 struct nvbios vbios;
738
739 struct nv04_mode_state mode_reg;
740 struct nv04_mode_state saved_reg;
741 uint32_t saved_vga_font[4][16384];
742 uint32_t crtc_owner;
743 uint32_t dac_users[4];
744
745 struct nouveau_suspend_resume {
746 uint32_t *ramin_copy;
747 } susres;
748
749 struct backlight_device *backlight;
750
751 struct {
752 struct dentry *channel_root;
753 } debugfs;
754
755 struct nouveau_fbdev *nfbdev;
756 struct apertures_struct *apertures;
757
758 bool powered_down;
759 };
760
761 static inline struct drm_nouveau_private *
762 nouveau_private(struct drm_device *dev)
763 {
764 return dev->dev_private;
765 }
766
767 static inline struct drm_nouveau_private *
768 nouveau_bdev(struct ttm_bo_device *bd)
769 {
770 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
771 }
772
773 static inline int
774 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
775 {
776 struct nouveau_bo *prev;
777
778 if (!pnvbo)
779 return -EINVAL;
780 prev = *pnvbo;
781
782 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
783 if (prev) {
784 struct ttm_buffer_object *bo = &prev->bo;
785
786 ttm_bo_unref(&bo);
787 }
788
789 return 0;
790 }
791
792 /* nouveau_drv.c */
793 extern int nouveau_agpmode;
794 extern int nouveau_duallink;
795 extern int nouveau_uscript_lvds;
796 extern int nouveau_uscript_tmds;
797 extern int nouveau_vram_pushbuf;
798 extern int nouveau_vram_notify;
799 extern int nouveau_fbpercrtc;
800 extern int nouveau_tv_disable;
801 extern char *nouveau_tv_norm;
802 extern int nouveau_reg_debug;
803 extern char *nouveau_vbios;
804 extern int nouveau_ignorelid;
805 extern int nouveau_nofbaccel;
806 extern int nouveau_noaccel;
807 extern int nouveau_force_post;
808 extern int nouveau_override_conntype;
809 extern char *nouveau_perflvl;
810 extern int nouveau_perflvl_wr;
811 extern int nouveau_msi;
812
813 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
814 extern int nouveau_pci_resume(struct pci_dev *pdev);
815
816 /* nouveau_state.c */
817 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
818 extern int nouveau_load(struct drm_device *, unsigned long flags);
819 extern int nouveau_firstopen(struct drm_device *);
820 extern void nouveau_lastclose(struct drm_device *);
821 extern int nouveau_unload(struct drm_device *);
822 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
823 struct drm_file *);
824 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
825 struct drm_file *);
826 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
827 uint32_t reg, uint32_t mask, uint32_t val);
828 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
829 uint32_t reg, uint32_t mask, uint32_t val);
830 extern bool nouveau_wait_for_idle(struct drm_device *);
831 extern int nouveau_card_init(struct drm_device *);
832
833 /* nouveau_mem.c */
834 extern int nouveau_mem_vram_init(struct drm_device *);
835 extern void nouveau_mem_vram_fini(struct drm_device *);
836 extern int nouveau_mem_gart_init(struct drm_device *);
837 extern void nouveau_mem_gart_fini(struct drm_device *);
838 extern int nouveau_mem_init_agp(struct drm_device *);
839 extern int nouveau_mem_reset_agp(struct drm_device *);
840 extern void nouveau_mem_close(struct drm_device *);
841 extern int nouveau_mem_detect(struct drm_device *);
842 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
843 extern struct nouveau_tile_reg *nv10_mem_set_tiling(
844 struct drm_device *dev, uint32_t addr, uint32_t size,
845 uint32_t pitch, uint32_t flags);
846 extern void nv10_mem_put_tile_region(struct drm_device *dev,
847 struct nouveau_tile_reg *tile,
848 struct nouveau_fence *fence);
849 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
850 extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
851
852 /* nouveau_notifier.c */
853 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
854 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
855 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
856 int cout, uint32_t start, uint32_t end,
857 uint32_t *offset);
858 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
859 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
860 struct drm_file *);
861 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
862 struct drm_file *);
863
864 /* nouveau_channel.c */
865 extern struct drm_ioctl_desc nouveau_ioctls[];
866 extern int nouveau_max_ioctl;
867 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
868 extern int nouveau_channel_alloc(struct drm_device *dev,
869 struct nouveau_channel **chan,
870 struct drm_file *file_priv,
871 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
872 extern struct nouveau_channel *
873 nouveau_channel_get_unlocked(struct nouveau_channel *);
874 extern struct nouveau_channel *
875 nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
876 extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
877 extern void nouveau_channel_put(struct nouveau_channel **);
878 extern void nouveau_channel_ref(struct nouveau_channel *chan,
879 struct nouveau_channel **pchan);
880 extern void nouveau_channel_idle(struct nouveau_channel *chan);
881
882 /* nouveau_object.c */
883 #define NVOBJ_CLASS(d,c,e) do { \
884 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
885 if (ret) \
886 return ret; \
887 } while(0)
888
889 #define NVOBJ_MTHD(d,c,m,e) do { \
890 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
891 if (ret) \
892 return ret; \
893 } while(0)
894
895 extern int nouveau_gpuobj_early_init(struct drm_device *);
896 extern int nouveau_gpuobj_init(struct drm_device *);
897 extern void nouveau_gpuobj_takedown(struct drm_device *);
898 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
899 extern void nouveau_gpuobj_resume(struct drm_device *dev);
900 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
901 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
902 int (*exec)(struct nouveau_channel *,
903 u32 class, u32 mthd, u32 data));
904 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
905 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
906 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
907 uint32_t vram_h, uint32_t tt_h);
908 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
909 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
910 uint32_t size, int align, uint32_t flags,
911 struct nouveau_gpuobj **);
912 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
913 struct nouveau_gpuobj **);
914 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
915 u32 size, u32 flags,
916 struct nouveau_gpuobj **);
917 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
918 uint64_t offset, uint64_t size, int access,
919 int target, struct nouveau_gpuobj **);
920 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
921 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
922 u64 size, int target, int access, u32 type,
923 u32 comp, struct nouveau_gpuobj **pobj);
924 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
925 int class, u64 base, u64 size, int target,
926 int access, u32 type, u32 comp);
927 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
928 struct drm_file *);
929 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
930 struct drm_file *);
931
932 /* nouveau_irq.c */
933 extern int nouveau_irq_init(struct drm_device *);
934 extern void nouveau_irq_fini(struct drm_device *);
935 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
936 extern void nouveau_irq_register(struct drm_device *, int status_bit,
937 void (*)(struct drm_device *));
938 extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
939 extern void nouveau_irq_preinstall(struct drm_device *);
940 extern int nouveau_irq_postinstall(struct drm_device *);
941 extern void nouveau_irq_uninstall(struct drm_device *);
942
943 /* nouveau_sgdma.c */
944 extern int nouveau_sgdma_init(struct drm_device *);
945 extern void nouveau_sgdma_takedown(struct drm_device *);
946 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
947 uint32_t offset);
948 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
949
950 /* nouveau_debugfs.c */
951 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
952 extern int nouveau_debugfs_init(struct drm_minor *);
953 extern void nouveau_debugfs_takedown(struct drm_minor *);
954 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
955 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
956 #else
957 static inline int
958 nouveau_debugfs_init(struct drm_minor *minor)
959 {
960 return 0;
961 }
962
963 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
964 {
965 }
966
967 static inline int
968 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
969 {
970 return 0;
971 }
972
973 static inline void
974 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
975 {
976 }
977 #endif
978
979 /* nouveau_dma.c */
980 extern void nouveau_dma_pre_init(struct nouveau_channel *);
981 extern int nouveau_dma_init(struct nouveau_channel *);
982 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
983
984 /* nouveau_acpi.c */
985 #define ROM_BIOS_PAGE 4096
986 #if defined(CONFIG_ACPI)
987 void nouveau_register_dsm_handler(void);
988 void nouveau_unregister_dsm_handler(void);
989 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
990 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
991 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
992 #else
993 static inline void nouveau_register_dsm_handler(void) {}
994 static inline void nouveau_unregister_dsm_handler(void) {}
995 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
996 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
997 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
998 #endif
999
1000 /* nouveau_backlight.c */
1001 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1002 extern int nouveau_backlight_init(struct drm_connector *);
1003 extern void nouveau_backlight_exit(struct drm_connector *);
1004 #else
1005 static inline int nouveau_backlight_init(struct drm_connector *dev)
1006 {
1007 return 0;
1008 }
1009
1010 static inline void nouveau_backlight_exit(struct drm_connector *dev) { }
1011 #endif
1012
1013 /* nouveau_bios.c */
1014 extern int nouveau_bios_init(struct drm_device *);
1015 extern void nouveau_bios_takedown(struct drm_device *dev);
1016 extern int nouveau_run_vbios_init(struct drm_device *);
1017 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1018 struct dcb_entry *);
1019 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
1020 enum dcb_gpio_tag);
1021 extern struct dcb_connector_table_entry *
1022 nouveau_bios_connector_entry(struct drm_device *, int index);
1023 extern u32 get_pll_register(struct drm_device *, enum pll_types);
1024 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1025 struct pll_lims *);
1026 extern int nouveau_bios_run_display_table(struct drm_device *,
1027 struct dcb_entry *,
1028 uint32_t script, int pxclk);
1029 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
1030 int *length);
1031 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1032 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1033 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1034 bool *dl, bool *if_is_24bit);
1035 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1036 int head, int pxclk);
1037 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1038 enum LVDS_script, int pxclk);
1039
1040 /* nouveau_ttm.c */
1041 int nouveau_ttm_global_init(struct drm_nouveau_private *);
1042 void nouveau_ttm_global_release(struct drm_nouveau_private *);
1043 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1044
1045 /* nouveau_dp.c */
1046 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1047 uint8_t *data, int data_nr);
1048 bool nouveau_dp_detect(struct drm_encoder *);
1049 bool nouveau_dp_link_train(struct drm_encoder *);
1050
1051 /* nv04_fb.c */
1052 extern int nv04_fb_init(struct drm_device *);
1053 extern void nv04_fb_takedown(struct drm_device *);
1054
1055 /* nv10_fb.c */
1056 extern int nv10_fb_init(struct drm_device *);
1057 extern void nv10_fb_takedown(struct drm_device *);
1058 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1059 uint32_t addr, uint32_t size,
1060 uint32_t pitch, uint32_t flags);
1061 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1062 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1063
1064 /* nv30_fb.c */
1065 extern int nv30_fb_init(struct drm_device *);
1066 extern void nv30_fb_takedown(struct drm_device *);
1067 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1068 uint32_t addr, uint32_t size,
1069 uint32_t pitch, uint32_t flags);
1070 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1071
1072 /* nv40_fb.c */
1073 extern int nv40_fb_init(struct drm_device *);
1074 extern void nv40_fb_takedown(struct drm_device *);
1075 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1076
1077 /* nv50_fb.c */
1078 extern int nv50_fb_init(struct drm_device *);
1079 extern void nv50_fb_takedown(struct drm_device *);
1080 extern void nv50_fb_vm_trap(struct drm_device *, int display);
1081
1082 /* nvc0_fb.c */
1083 extern int nvc0_fb_init(struct drm_device *);
1084 extern void nvc0_fb_takedown(struct drm_device *);
1085
1086 /* nv04_fifo.c */
1087 extern int nv04_fifo_init(struct drm_device *);
1088 extern void nv04_fifo_fini(struct drm_device *);
1089 extern void nv04_fifo_disable(struct drm_device *);
1090 extern void nv04_fifo_enable(struct drm_device *);
1091 extern bool nv04_fifo_reassign(struct drm_device *, bool);
1092 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
1093 extern int nv04_fifo_channel_id(struct drm_device *);
1094 extern int nv04_fifo_create_context(struct nouveau_channel *);
1095 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1096 extern int nv04_fifo_load_context(struct nouveau_channel *);
1097 extern int nv04_fifo_unload_context(struct drm_device *);
1098 extern void nv04_fifo_isr(struct drm_device *);
1099
1100 /* nv10_fifo.c */
1101 extern int nv10_fifo_init(struct drm_device *);
1102 extern int nv10_fifo_channel_id(struct drm_device *);
1103 extern int nv10_fifo_create_context(struct nouveau_channel *);
1104 extern int nv10_fifo_load_context(struct nouveau_channel *);
1105 extern int nv10_fifo_unload_context(struct drm_device *);
1106
1107 /* nv40_fifo.c */
1108 extern int nv40_fifo_init(struct drm_device *);
1109 extern int nv40_fifo_create_context(struct nouveau_channel *);
1110 extern int nv40_fifo_load_context(struct nouveau_channel *);
1111 extern int nv40_fifo_unload_context(struct drm_device *);
1112
1113 /* nv50_fifo.c */
1114 extern int nv50_fifo_init(struct drm_device *);
1115 extern void nv50_fifo_takedown(struct drm_device *);
1116 extern int nv50_fifo_channel_id(struct drm_device *);
1117 extern int nv50_fifo_create_context(struct nouveau_channel *);
1118 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1119 extern int nv50_fifo_load_context(struct nouveau_channel *);
1120 extern int nv50_fifo_unload_context(struct drm_device *);
1121 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1122
1123 /* nvc0_fifo.c */
1124 extern int nvc0_fifo_init(struct drm_device *);
1125 extern void nvc0_fifo_takedown(struct drm_device *);
1126 extern void nvc0_fifo_disable(struct drm_device *);
1127 extern void nvc0_fifo_enable(struct drm_device *);
1128 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1129 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1130 extern int nvc0_fifo_channel_id(struct drm_device *);
1131 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1132 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1133 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1134 extern int nvc0_fifo_unload_context(struct drm_device *);
1135
1136 /* nv04_graph.c */
1137 extern int nv04_graph_init(struct drm_device *);
1138 extern void nv04_graph_takedown(struct drm_device *);
1139 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1140 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1141 extern int nv04_graph_create_context(struct nouveau_channel *);
1142 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1143 extern int nv04_graph_load_context(struct nouveau_channel *);
1144 extern int nv04_graph_unload_context(struct drm_device *);
1145 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1146 u32 class, u32 mthd, u32 data);
1147 extern struct nouveau_bitfield nv04_graph_nsource[];
1148
1149 /* nv10_graph.c */
1150 extern int nv10_graph_init(struct drm_device *);
1151 extern void nv10_graph_takedown(struct drm_device *);
1152 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1153 extern int nv10_graph_create_context(struct nouveau_channel *);
1154 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1155 extern int nv10_graph_load_context(struct nouveau_channel *);
1156 extern int nv10_graph_unload_context(struct drm_device *);
1157 extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
1158 extern struct nouveau_bitfield nv10_graph_intr[];
1159 extern struct nouveau_bitfield nv10_graph_nstatus[];
1160
1161 /* nv20_graph.c */
1162 extern int nv20_graph_create_context(struct nouveau_channel *);
1163 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1164 extern int nv20_graph_load_context(struct nouveau_channel *);
1165 extern int nv20_graph_unload_context(struct drm_device *);
1166 extern int nv20_graph_init(struct drm_device *);
1167 extern void nv20_graph_takedown(struct drm_device *);
1168 extern int nv30_graph_init(struct drm_device *);
1169 extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
1170
1171 /* nv40_graph.c */
1172 extern int nv40_graph_init(struct drm_device *);
1173 extern void nv40_graph_takedown(struct drm_device *);
1174 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1175 extern int nv40_graph_create_context(struct nouveau_channel *);
1176 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1177 extern int nv40_graph_load_context(struct nouveau_channel *);
1178 extern int nv40_graph_unload_context(struct drm_device *);
1179 extern void nv40_grctx_init(struct nouveau_grctx *);
1180 extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
1181
1182 /* nv50_graph.c */
1183 extern int nv50_graph_init(struct drm_device *);
1184 extern void nv50_graph_takedown(struct drm_device *);
1185 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1186 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1187 extern int nv50_graph_create_context(struct nouveau_channel *);
1188 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1189 extern int nv50_graph_load_context(struct nouveau_channel *);
1190 extern int nv50_graph_unload_context(struct drm_device *);
1191 extern int nv50_grctx_init(struct nouveau_grctx *);
1192 extern void nv50_graph_tlb_flush(struct drm_device *dev);
1193 extern void nv84_graph_tlb_flush(struct drm_device *dev);
1194 extern struct nouveau_enum nv50_data_error_names[];
1195
1196 /* nvc0_graph.c */
1197 extern int nvc0_graph_init(struct drm_device *);
1198 extern void nvc0_graph_takedown(struct drm_device *);
1199 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1200 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1201 extern int nvc0_graph_create_context(struct nouveau_channel *);
1202 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1203 extern int nvc0_graph_load_context(struct nouveau_channel *);
1204 extern int nvc0_graph_unload_context(struct drm_device *);
1205
1206 /* nv84_crypt.c */
1207 extern int nv84_crypt_init(struct drm_device *dev);
1208 extern void nv84_crypt_fini(struct drm_device *dev);
1209 extern int nv84_crypt_create_context(struct nouveau_channel *);
1210 extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1211 extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1212
1213 /* nv04_instmem.c */
1214 extern int nv04_instmem_init(struct drm_device *);
1215 extern void nv04_instmem_takedown(struct drm_device *);
1216 extern int nv04_instmem_suspend(struct drm_device *);
1217 extern void nv04_instmem_resume(struct drm_device *);
1218 extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1219 extern void nv04_instmem_put(struct nouveau_gpuobj *);
1220 extern int nv04_instmem_map(struct nouveau_gpuobj *);
1221 extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1222 extern void nv04_instmem_flush(struct drm_device *);
1223
1224 /* nv50_instmem.c */
1225 extern int nv50_instmem_init(struct drm_device *);
1226 extern void nv50_instmem_takedown(struct drm_device *);
1227 extern int nv50_instmem_suspend(struct drm_device *);
1228 extern void nv50_instmem_resume(struct drm_device *);
1229 extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1230 extern void nv50_instmem_put(struct nouveau_gpuobj *);
1231 extern int nv50_instmem_map(struct nouveau_gpuobj *);
1232 extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1233 extern void nv50_instmem_flush(struct drm_device *);
1234 extern void nv84_instmem_flush(struct drm_device *);
1235
1236 /* nvc0_instmem.c */
1237 extern int nvc0_instmem_init(struct drm_device *);
1238 extern void nvc0_instmem_takedown(struct drm_device *);
1239 extern int nvc0_instmem_suspend(struct drm_device *);
1240 extern void nvc0_instmem_resume(struct drm_device *);
1241
1242 /* nv04_mc.c */
1243 extern int nv04_mc_init(struct drm_device *);
1244 extern void nv04_mc_takedown(struct drm_device *);
1245
1246 /* nv40_mc.c */
1247 extern int nv40_mc_init(struct drm_device *);
1248 extern void nv40_mc_takedown(struct drm_device *);
1249
1250 /* nv50_mc.c */
1251 extern int nv50_mc_init(struct drm_device *);
1252 extern void nv50_mc_takedown(struct drm_device *);
1253
1254 /* nv04_timer.c */
1255 extern int nv04_timer_init(struct drm_device *);
1256 extern uint64_t nv04_timer_read(struct drm_device *);
1257 extern void nv04_timer_takedown(struct drm_device *);
1258
1259 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1260 unsigned long arg);
1261
1262 /* nv04_dac.c */
1263 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1264 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1265 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1266 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1267 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1268
1269 /* nv04_dfp.c */
1270 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1271 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1272 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1273 int head, bool dl);
1274 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1275 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1276
1277 /* nv04_tv.c */
1278 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1279 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1280
1281 /* nv17_tv.c */
1282 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1283
1284 /* nv04_display.c */
1285 extern int nv04_display_early_init(struct drm_device *);
1286 extern void nv04_display_late_takedown(struct drm_device *);
1287 extern int nv04_display_create(struct drm_device *);
1288 extern int nv04_display_init(struct drm_device *);
1289 extern void nv04_display_destroy(struct drm_device *);
1290
1291 /* nv04_crtc.c */
1292 extern int nv04_crtc_create(struct drm_device *, int index);
1293
1294 /* nouveau_bo.c */
1295 extern struct ttm_bo_driver nouveau_bo_driver;
1296 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1297 int size, int align, uint32_t flags,
1298 uint32_t tile_mode, uint32_t tile_flags,
1299 struct nouveau_bo **);
1300 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1301 extern int nouveau_bo_unpin(struct nouveau_bo *);
1302 extern int nouveau_bo_map(struct nouveau_bo *);
1303 extern void nouveau_bo_unmap(struct nouveau_bo *);
1304 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1305 uint32_t busy);
1306 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1307 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1308 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1309 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1310 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1311 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1312 bool no_wait_reserve, bool no_wait_gpu);
1313
1314 /* nouveau_fence.c */
1315 struct nouveau_fence;
1316 extern int nouveau_fence_init(struct drm_device *);
1317 extern void nouveau_fence_fini(struct drm_device *);
1318 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1319 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1320 extern void nouveau_fence_update(struct nouveau_channel *);
1321 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1322 bool emit);
1323 extern int nouveau_fence_emit(struct nouveau_fence *);
1324 extern void nouveau_fence_work(struct nouveau_fence *fence,
1325 void (*work)(void *priv, bool signalled),
1326 void *priv);
1327 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1328
1329 extern bool __nouveau_fence_signalled(void *obj, void *arg);
1330 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1331 extern int __nouveau_fence_flush(void *obj, void *arg);
1332 extern void __nouveau_fence_unref(void **obj);
1333 extern void *__nouveau_fence_ref(void *obj);
1334
1335 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1336 {
1337 return __nouveau_fence_signalled(obj, NULL);
1338 }
1339 static inline int
1340 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1341 {
1342 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1343 }
1344 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1345 static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1346 {
1347 return __nouveau_fence_flush(obj, NULL);
1348 }
1349 static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1350 {
1351 __nouveau_fence_unref((void **)obj);
1352 }
1353 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1354 {
1355 return __nouveau_fence_ref(obj);
1356 }
1357
1358 /* nouveau_gem.c */
1359 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1360 int size, int align, uint32_t domain,
1361 uint32_t tile_mode, uint32_t tile_flags,
1362 struct nouveau_bo **);
1363 extern int nouveau_gem_object_new(struct drm_gem_object *);
1364 extern void nouveau_gem_object_del(struct drm_gem_object *);
1365 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1366 struct drm_file *);
1367 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1368 struct drm_file *);
1369 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1370 struct drm_file *);
1371 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1372 struct drm_file *);
1373 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1374 struct drm_file *);
1375
1376 /* nouveau_display.c */
1377 int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1378 void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1379 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1380 struct drm_pending_vblank_event *event);
1381 int nouveau_finish_page_flip(struct nouveau_channel *,
1382 struct nouveau_page_flip_state *);
1383
1384 /* nv10_gpio.c */
1385 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1386 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1387
1388 /* nv50_gpio.c */
1389 int nv50_gpio_init(struct drm_device *dev);
1390 void nv50_gpio_fini(struct drm_device *dev);
1391 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1392 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1393 int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag,
1394 void (*)(void *, int), void *);
1395 void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag,
1396 void (*)(void *, int), void *);
1397 bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1398
1399 /* nv50_calc. */
1400 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1401 int *N1, int *M1, int *N2, int *M2, int *P);
1402 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1403 int clk, int *N, int *fN, int *M, int *P);
1404
1405 #ifndef ioread32_native
1406 #ifdef __BIG_ENDIAN
1407 #define ioread16_native ioread16be
1408 #define iowrite16_native iowrite16be
1409 #define ioread32_native ioread32be
1410 #define iowrite32_native iowrite32be
1411 #else /* def __BIG_ENDIAN */
1412 #define ioread16_native ioread16
1413 #define iowrite16_native iowrite16
1414 #define ioread32_native ioread32
1415 #define iowrite32_native iowrite32
1416 #endif /* def __BIG_ENDIAN else */
1417 #endif /* !ioread32_native */
1418
1419 /* channel control reg access */
1420 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1421 {
1422 return ioread32_native(chan->user + reg);
1423 }
1424
1425 static inline void nvchan_wr32(struct nouveau_channel *chan,
1426 unsigned reg, u32 val)
1427 {
1428 iowrite32_native(val, chan->user + reg);
1429 }
1430
1431 /* register access */
1432 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1433 {
1434 struct drm_nouveau_private *dev_priv = dev->dev_private;
1435 return ioread32_native(dev_priv->mmio + reg);
1436 }
1437
1438 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1439 {
1440 struct drm_nouveau_private *dev_priv = dev->dev_private;
1441 iowrite32_native(val, dev_priv->mmio + reg);
1442 }
1443
1444 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1445 {
1446 u32 tmp = nv_rd32(dev, reg);
1447 nv_wr32(dev, reg, (tmp & ~mask) | val);
1448 return tmp;
1449 }
1450
1451 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1452 {
1453 struct drm_nouveau_private *dev_priv = dev->dev_private;
1454 return ioread8(dev_priv->mmio + reg);
1455 }
1456
1457 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1458 {
1459 struct drm_nouveau_private *dev_priv = dev->dev_private;
1460 iowrite8(val, dev_priv->mmio + reg);
1461 }
1462
1463 #define nv_wait(dev, reg, mask, val) \
1464 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1465 #define nv_wait_ne(dev, reg, mask, val) \
1466 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1467
1468 /* PRAMIN access */
1469 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1470 {
1471 struct drm_nouveau_private *dev_priv = dev->dev_private;
1472 return ioread32_native(dev_priv->ramin + offset);
1473 }
1474
1475 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1476 {
1477 struct drm_nouveau_private *dev_priv = dev->dev_private;
1478 iowrite32_native(val, dev_priv->ramin + offset);
1479 }
1480
1481 /* object access */
1482 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1483 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1484
1485 /*
1486 * Logging
1487 * Argument d is (struct drm_device *).
1488 */
1489 #define NV_PRINTK(level, d, fmt, arg...) \
1490 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1491 pci_name(d->pdev), ##arg)
1492 #ifndef NV_DEBUG_NOTRACE
1493 #define NV_DEBUG(d, fmt, arg...) do { \
1494 if (drm_debug & DRM_UT_DRIVER) { \
1495 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1496 __LINE__, ##arg); \
1497 } \
1498 } while (0)
1499 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1500 if (drm_debug & DRM_UT_KMS) { \
1501 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1502 __LINE__, ##arg); \
1503 } \
1504 } while (0)
1505 #else
1506 #define NV_DEBUG(d, fmt, arg...) do { \
1507 if (drm_debug & DRM_UT_DRIVER) \
1508 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1509 } while (0)
1510 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1511 if (drm_debug & DRM_UT_KMS) \
1512 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1513 } while (0)
1514 #endif
1515 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1516 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1517 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1518 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1519 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1520
1521 /* nouveau_reg_debug bitmask */
1522 enum {
1523 NOUVEAU_REG_DEBUG_MC = 0x1,
1524 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1525 NOUVEAU_REG_DEBUG_FB = 0x4,
1526 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1527 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1528 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1529 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1530 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1531 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1532 NOUVEAU_REG_DEBUG_EVO = 0x200,
1533 };
1534
1535 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1536 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1537 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1538 } while (0)
1539
1540 static inline bool
1541 nv_two_heads(struct drm_device *dev)
1542 {
1543 struct drm_nouveau_private *dev_priv = dev->dev_private;
1544 const int impl = dev->pci_device & 0x0ff0;
1545
1546 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1547 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1548 return true;
1549
1550 return false;
1551 }
1552
1553 static inline bool
1554 nv_gf4_disp_arch(struct drm_device *dev)
1555 {
1556 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1557 }
1558
1559 static inline bool
1560 nv_two_reg_pll(struct drm_device *dev)
1561 {
1562 struct drm_nouveau_private *dev_priv = dev->dev_private;
1563 const int impl = dev->pci_device & 0x0ff0;
1564
1565 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1566 return true;
1567 return false;
1568 }
1569
1570 static inline bool
1571 nv_match_device(struct drm_device *dev, unsigned device,
1572 unsigned sub_vendor, unsigned sub_device)
1573 {
1574 return dev->pdev->device == device &&
1575 dev->pdev->subsystem_vendor == sub_vendor &&
1576 dev->pdev->subsystem_device == sub_device;
1577 }
1578
1579 /* returns 1 if device is one of the nv4x using the 0x4497 object class,
1580 * helpful to determine a number of other hardware features
1581 */
1582 static inline int
1583 nv44_graph_class(struct drm_device *dev)
1584 {
1585 struct drm_nouveau_private *dev_priv = dev->dev_private;
1586
1587 if ((dev_priv->chipset & 0xf0) == 0x60)
1588 return 1;
1589
1590 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1591 }
1592
1593 /* memory type/access flags, do not match hardware values */
1594 #define NV_MEM_ACCESS_RO 1
1595 #define NV_MEM_ACCESS_WO 2
1596 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1597 #define NV_MEM_ACCESS_SYS 4
1598 #define NV_MEM_ACCESS_VM 8
1599
1600 #define NV_MEM_TARGET_VRAM 0
1601 #define NV_MEM_TARGET_PCI 1
1602 #define NV_MEM_TARGET_PCI_NOSNOOP 2
1603 #define NV_MEM_TARGET_VM 3
1604 #define NV_MEM_TARGET_GART 4
1605
1606 #define NV_MEM_TYPE_VM 0x7f
1607 #define NV_MEM_COMP_VM 0x03
1608
1609 /* NV_SW object class */
1610 #define NV_SW 0x0000506e
1611 #define NV_SW_DMA_SEMAPHORE 0x00000060
1612 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1613 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1614 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1615 #define NV_SW_YIELD 0x00000080
1616 #define NV_SW_DMA_VBLSEM 0x0000018c
1617 #define NV_SW_VBLSEM_OFFSET 0x00000400
1618 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1619 #define NV_SW_VBLSEM_RELEASE 0x00000408
1620 #define NV_SW_PAGE_FLIP 0x00000500
1621
1622 #endif /* __NOUVEAU_DRV_H__ */
kernel source for telekom puls (alcatel/mediatek)