Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rusty...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / core / subdev / ltcg / nvc0.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <subdev/ltcg.h>
26 #include <subdev/fb.h>
27 #include <subdev/timer.h>
28
29 struct nvc0_ltcg_priv {
30 struct nouveau_ltcg base;
31 u32 part_nr;
32 u32 subp_nr;
33 struct nouveau_mm tags;
34 u32 num_tags;
35 struct nouveau_mm_node *tag_ram;
36 };
37
38 static void
39 nvc0_ltcg_subp_isr(struct nvc0_ltcg_priv *priv, int unit, int subp)
40 {
41 u32 subp_base = 0x141000 + (unit * 0x2000) + (subp * 0x400);
42 u32 stat = nv_rd32(priv, subp_base + 0x020);
43
44 if (stat) {
45 nv_info(priv, "LTC%d_LTS%d: 0x%08x\n", unit, subp, stat);
46 nv_wr32(priv, subp_base + 0x020, stat);
47 }
48 }
49
50 static void
51 nvc0_ltcg_intr(struct nouveau_subdev *subdev)
52 {
53 struct nvc0_ltcg_priv *priv = (void *)subdev;
54 u32 units;
55
56 units = nv_rd32(priv, 0x00017c);
57 while (units) {
58 u32 subp, unit = ffs(units) - 1;
59 for (subp = 0; subp < priv->subp_nr; subp++)
60 nvc0_ltcg_subp_isr(priv, unit, subp);
61 units &= ~(1 << unit);
62 }
63
64 /* we do something horribly wrong and upset PMFB a lot, so mask off
65 * interrupts from it after the first one until it's fixed
66 */
67 nv_mask(priv, 0x000640, 0x02000000, 0x00000000);
68 }
69
70 static int
71 nvc0_ltcg_tags_alloc(struct nouveau_ltcg *ltcg, u32 n,
72 struct nouveau_mm_node **pnode)
73 {
74 struct nvc0_ltcg_priv *priv = (struct nvc0_ltcg_priv *)ltcg;
75 int ret;
76
77 ret = nouveau_mm_head(&priv->tags, 1, n, n, 1, pnode);
78 if (ret)
79 *pnode = NULL;
80
81 return ret;
82 }
83
84 static void
85 nvc0_ltcg_tags_free(struct nouveau_ltcg *ltcg, struct nouveau_mm_node **pnode)
86 {
87 struct nvc0_ltcg_priv *priv = (struct nvc0_ltcg_priv *)ltcg;
88
89 nouveau_mm_free(&priv->tags, pnode);
90 }
91
92 static void
93 nvc0_ltcg_tags_clear(struct nouveau_ltcg *ltcg, u32 first, u32 count)
94 {
95 struct nvc0_ltcg_priv *priv = (struct nvc0_ltcg_priv *)ltcg;
96 u32 last = first + count - 1;
97 int p, i;
98
99 BUG_ON((first > last) || (last >= priv->num_tags));
100
101 nv_wr32(priv, 0x17e8cc, first);
102 nv_wr32(priv, 0x17e8d0, last);
103 nv_wr32(priv, 0x17e8c8, 0x4); /* trigger clear */
104
105 /* wait until it's finished with clearing */
106 for (p = 0; p < priv->part_nr; ++p) {
107 for (i = 0; i < priv->subp_nr; ++i)
108 nv_wait(priv, 0x1410c8 + p * 0x2000 + i * 0x400, ~0, 0);
109 }
110 }
111
112 /* TODO: Figure out tag memory details and drop the over-cautious allocation.
113 */
114 static int
115 nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv)
116 {
117 u32 tag_size, tag_margin, tag_align;
118 int ret;
119
120 nv_wr32(priv, 0x17e8d8, priv->part_nr);
121 if (nv_device(pfb)->card_type >= NV_E0)
122 nv_wr32(priv, 0x17e000, priv->part_nr);
123
124 /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */
125 priv->num_tags = (pfb->ram.size >> 17) / 4;
126 if (priv->num_tags > (1 << 17))
127 priv->num_tags = 1 << 17; /* we have 17 bits in PTE */
128 priv->num_tags = (priv->num_tags + 63) & ~63; /* round up to 64 */
129
130 tag_align = priv->part_nr * 0x800;
131 tag_margin = (tag_align < 0x6000) ? 0x6000 : tag_align;
132
133 /* 4 part 4 sub: 0x2000 bytes for 56 tags */
134 /* 3 part 4 sub: 0x6000 bytes for 168 tags */
135 /*
136 * About 147 bytes per tag. Let's be safe and allocate x2, which makes
137 * 0x4980 bytes for 64 tags, and round up to 0x6000 bytes for 64 tags.
138 *
139 * For 4 GiB of memory we'll have 8192 tags which makes 3 MiB, < 0.1 %.
140 */
141 tag_size = (priv->num_tags / 64) * 0x6000 + tag_margin;
142 tag_size += tag_align;
143 tag_size = (tag_size + 0xfff) >> 12; /* round up */
144
145 ret = nouveau_mm_tail(&pfb->vram, 0, tag_size, tag_size, 1,
146 &priv->tag_ram);
147 if (ret) {
148 priv->num_tags = 0;
149 } else {
150 u64 tag_base = (priv->tag_ram->offset << 12) + tag_margin;
151
152 tag_base += tag_align - 1;
153 ret = do_div(tag_base, tag_align);
154
155 nv_wr32(priv, 0x17e8d4, tag_base);
156 }
157 ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
158
159 return ret;
160 }
161
162 static int
163 nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
164 struct nouveau_oclass *oclass, void *data, u32 size,
165 struct nouveau_object **pobject)
166 {
167 struct nvc0_ltcg_priv *priv;
168 struct nouveau_fb *pfb = nouveau_fb(parent);
169 u32 parts, mask;
170 int ret, i;
171
172 ret = nouveau_ltcg_create(parent, engine, oclass, &priv);
173 *pobject = nv_object(priv);
174 if (ret)
175 return ret;
176
177 parts = nv_rd32(priv, 0x022438);
178 mask = nv_rd32(priv, 0x022554);
179 for (i = 0; i < parts; i++) {
180 if (!(mask & (1 << i)))
181 priv->part_nr++;
182 }
183 priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28;
184
185 nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
186
187 ret = nvc0_ltcg_init_tag_ram(pfb, priv);
188 if (ret)
189 return ret;
190
191 priv->base.tags_alloc = nvc0_ltcg_tags_alloc;
192 priv->base.tags_free = nvc0_ltcg_tags_free;
193 priv->base.tags_clear = nvc0_ltcg_tags_clear;
194
195 nv_subdev(priv)->intr = nvc0_ltcg_intr;
196 return 0;
197 }
198
199 static void
200 nvc0_ltcg_dtor(struct nouveau_object *object)
201 {
202 struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object;
203 struct nvc0_ltcg_priv *priv = (struct nvc0_ltcg_priv *)ltcg;
204 struct nouveau_fb *pfb = nouveau_fb(ltcg->base.base.parent);
205
206 nouveau_mm_fini(&priv->tags);
207 nouveau_mm_free(&pfb->vram, &priv->tag_ram);
208
209 nouveau_ltcg_destroy(ltcg);
210 }
211
212 struct nouveau_oclass
213 nvc0_ltcg_oclass = {
214 .handle = NV_SUBDEV(LTCG, 0xc0),
215 .ofuncs = &(struct nouveau_ofuncs) {
216 .ctor = nvc0_ltcg_ctor,
217 .dtor = nvc0_ltcg_dtor,
218 .init = _nouveau_ltcg_init,
219 .fini = _nouveau_ltcg_fini,
220 },
221 };