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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_sdvo.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc.h"
34 #include "intel_drv.h"
35 #include "drm_edid.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "intel_sdvo_regs.h"
39 #include <linux/dmi.h>
40
41 static char *tv_format_names[] = {
42 "NTSC_M" , "NTSC_J" , "NTSC_443",
43 "PAL_B" , "PAL_D" , "PAL_G" ,
44 "PAL_H" , "PAL_I" , "PAL_M" ,
45 "PAL_N" , "PAL_NC" , "PAL_60" ,
46 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
47 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
48 "SECAM_60"
49 };
50
51 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
52
53 struct intel_sdvo_priv {
54 u8 slave_addr;
55
56 /* Register for the SDVO device: SDVOB or SDVOC */
57 int output_device;
58
59 /* Active outputs controlled by this SDVO output */
60 uint16_t controlled_output;
61
62 /*
63 * Capabilities of the SDVO device returned by
64 * i830_sdvo_get_capabilities()
65 */
66 struct intel_sdvo_caps caps;
67
68 /* Pixel clock limitations reported by the SDVO device, in kHz */
69 int pixel_clock_min, pixel_clock_max;
70
71 /*
72 * For multiple function SDVO device,
73 * this is for current attached outputs.
74 */
75 uint16_t attached_output;
76
77 /**
78 * This is set if we're going to treat the device as TV-out.
79 *
80 * While we have these nice friendly flags for output types that ought
81 * to decide this for us, the S-Video output on our HDMI+S-Video card
82 * shows up as RGB1 (VGA).
83 */
84 bool is_tv;
85
86 /* This is for current tv format name */
87 char *tv_format_name;
88
89 /* This contains all current supported TV format */
90 char *tv_format_supported[TV_FORMAT_NUM];
91 int format_supported_num;
92 struct drm_property *tv_format_property;
93 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
94
95 /**
96 * This is set if we treat the device as HDMI, instead of DVI.
97 */
98 bool is_hdmi;
99
100 /**
101 * This is set if we detect output of sdvo device as LVDS.
102 */
103 bool is_lvds;
104
105 /**
106 * This is sdvo flags for input timing.
107 */
108 uint8_t sdvo_flags;
109
110 /**
111 * This is sdvo fixed pannel mode pointer
112 */
113 struct drm_display_mode *sdvo_lvds_fixed_mode;
114
115 /**
116 * Returned SDTV resolutions allowed for the current format, if the
117 * device reported it.
118 */
119 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
120
121 /*
122 * supported encoding mode, used to determine whether HDMI is
123 * supported
124 */
125 struct intel_sdvo_encode encode;
126
127 /* DDC bus used by this SDVO output */
128 uint8_t ddc_bus;
129
130 /* Mac mini hack -- use the same DDC as the analog connector */
131 struct i2c_adapter *analog_ddc_bus;
132
133 int save_sdvo_mult;
134 u16 save_active_outputs;
135 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
136 struct intel_sdvo_dtd save_output_dtd[16];
137 u32 save_SDVOX;
138 /* add the property for the SDVO-TV */
139 struct drm_property *left_property;
140 struct drm_property *right_property;
141 struct drm_property *top_property;
142 struct drm_property *bottom_property;
143 struct drm_property *hpos_property;
144 struct drm_property *vpos_property;
145
146 /* add the property for the SDVO-TV/LVDS */
147 struct drm_property *brightness_property;
148 struct drm_property *contrast_property;
149 struct drm_property *saturation_property;
150 struct drm_property *hue_property;
151
152 /* Add variable to record current setting for the above property */
153 u32 left_margin, right_margin, top_margin, bottom_margin;
154 /* this is to get the range of margin.*/
155 u32 max_hscan, max_vscan;
156 u32 max_hpos, cur_hpos;
157 u32 max_vpos, cur_vpos;
158 u32 cur_brightness, max_brightness;
159 u32 cur_contrast, max_contrast;
160 u32 cur_saturation, max_saturation;
161 u32 cur_hue, max_hue;
162 };
163
164 static bool
165 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags);
166
167 /**
168 * Writes the SDVOB or SDVOC with the given value, but always writes both
169 * SDVOB and SDVOC to work around apparent hardware issues (according to
170 * comments in the BIOS).
171 */
172 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
173 {
174 struct drm_device *dev = intel_output->base.dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
177 u32 bval = val, cval = val;
178 int i;
179
180 if (sdvo_priv->output_device == SDVOB) {
181 cval = I915_READ(SDVOC);
182 } else {
183 bval = I915_READ(SDVOB);
184 }
185 /*
186 * Write the registers twice for luck. Sometimes,
187 * writing them only once doesn't appear to 'stick'.
188 * The BIOS does this too. Yay, magic
189 */
190 for (i = 0; i < 2; i++)
191 {
192 I915_WRITE(SDVOB, bval);
193 I915_READ(SDVOB);
194 I915_WRITE(SDVOC, cval);
195 I915_READ(SDVOC);
196 }
197 }
198
199 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
200 u8 *ch)
201 {
202 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
203 u8 out_buf[2];
204 u8 buf[2];
205 int ret;
206
207 struct i2c_msg msgs[] = {
208 {
209 .addr = sdvo_priv->slave_addr >> 1,
210 .flags = 0,
211 .len = 1,
212 .buf = out_buf,
213 },
214 {
215 .addr = sdvo_priv->slave_addr >> 1,
216 .flags = I2C_M_RD,
217 .len = 1,
218 .buf = buf,
219 }
220 };
221
222 out_buf[0] = addr;
223 out_buf[1] = 0;
224
225 if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2)
226 {
227 *ch = buf[0];
228 return true;
229 }
230
231 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
232 return false;
233 }
234
235 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
236 u8 ch)
237 {
238 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
239 u8 out_buf[2];
240 struct i2c_msg msgs[] = {
241 {
242 .addr = sdvo_priv->slave_addr >> 1,
243 .flags = 0,
244 .len = 2,
245 .buf = out_buf,
246 }
247 };
248
249 out_buf[0] = addr;
250 out_buf[1] = ch;
251
252 if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1)
253 {
254 return true;
255 }
256 return false;
257 }
258
259 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
260 /** Mapping of command numbers to names, for debug output */
261 static const struct _sdvo_cmd_name {
262 u8 cmd;
263 char *name;
264 } sdvo_cmd_names[] = {
265 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
266 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
267 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
268 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
269 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
270 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
271 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
272 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
273 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
274 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
275 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
276 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
277 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
278 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
279 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
280 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
281 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
282 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
283 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
308 /* Add the op code for SDVO enhancements */
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
333 /* HDMI op code */
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
354 };
355
356 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
357 #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
358
359 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
360 void *args, int args_len)
361 {
362 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
363 int i;
364
365 DRM_DEBUG_KMS("%s: W: %02X ",
366 SDVO_NAME(sdvo_priv), cmd);
367 for (i = 0; i < args_len; i++)
368 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
369 for (; i < 8; i++)
370 DRM_LOG_KMS(" ");
371 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
372 if (cmd == sdvo_cmd_names[i].cmd) {
373 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
374 break;
375 }
376 }
377 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
378 DRM_LOG_KMS("(%02X)", cmd);
379 DRM_LOG_KMS("\n");
380 }
381
382 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
383 void *args, int args_len)
384 {
385 int i;
386
387 intel_sdvo_debug_write(intel_output, cmd, args, args_len);
388
389 for (i = 0; i < args_len; i++) {
390 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
391 ((u8*)args)[i]);
392 }
393
394 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
395 }
396
397 static const char *cmd_status_names[] = {
398 "Power on",
399 "Success",
400 "Not supported",
401 "Invalid arg",
402 "Pending",
403 "Target not specified",
404 "Scaling not supported"
405 };
406
407 static void intel_sdvo_debug_response(struct intel_output *intel_output,
408 void *response, int response_len,
409 u8 status)
410 {
411 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
412 int i;
413
414 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
415 for (i = 0; i < response_len; i++)
416 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
417 for (; i < 8; i++)
418 DRM_LOG_KMS(" ");
419 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
420 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
421 else
422 DRM_LOG_KMS("(??? %d)", status);
423 DRM_LOG_KMS("\n");
424 }
425
426 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
427 void *response, int response_len)
428 {
429 int i;
430 u8 status;
431 u8 retry = 50;
432
433 while (retry--) {
434 /* Read the command response */
435 for (i = 0; i < response_len; i++) {
436 intel_sdvo_read_byte(intel_output,
437 SDVO_I2C_RETURN_0 + i,
438 &((u8 *)response)[i]);
439 }
440
441 /* read the return status */
442 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
443 &status);
444
445 intel_sdvo_debug_response(intel_output, response, response_len,
446 status);
447 if (status != SDVO_CMD_STATUS_PENDING)
448 return status;
449
450 mdelay(50);
451 }
452
453 return status;
454 }
455
456 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
457 {
458 if (mode->clock >= 100000)
459 return 1;
460 else if (mode->clock >= 50000)
461 return 2;
462 else
463 return 4;
464 }
465
466 /**
467 * Try to read the response after issuie the DDC switch command. But it
468 * is noted that we must do the action of reading response and issuing DDC
469 * switch command in one I2C transaction. Otherwise when we try to start
470 * another I2C transaction after issuing the DDC bus switch, it will be
471 * switched to the internal SDVO register.
472 */
473 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
474 u8 target)
475 {
476 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
477 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
478 struct i2c_msg msgs[] = {
479 {
480 .addr = sdvo_priv->slave_addr >> 1,
481 .flags = 0,
482 .len = 2,
483 .buf = out_buf,
484 },
485 /* the following two are to read the response */
486 {
487 .addr = sdvo_priv->slave_addr >> 1,
488 .flags = 0,
489 .len = 1,
490 .buf = cmd_buf,
491 },
492 {
493 .addr = sdvo_priv->slave_addr >> 1,
494 .flags = I2C_M_RD,
495 .len = 1,
496 .buf = ret_value,
497 },
498 };
499
500 intel_sdvo_debug_write(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
501 &target, 1);
502 /* write the DDC switch command argument */
503 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0, target);
504
505 out_buf[0] = SDVO_I2C_OPCODE;
506 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
507 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
508 cmd_buf[1] = 0;
509 ret_value[0] = 0;
510 ret_value[1] = 0;
511
512 ret = i2c_transfer(intel_output->i2c_bus, msgs, 3);
513 if (ret != 3) {
514 /* failure in I2C transfer */
515 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
516 return;
517 }
518 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
519 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
520 ret_value[0]);
521 return;
522 }
523 return;
524 }
525
526 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
527 {
528 struct intel_sdvo_set_target_input_args targets = {0};
529 u8 status;
530
531 if (target_0 && target_1)
532 return SDVO_CMD_STATUS_NOTSUPP;
533
534 if (target_1)
535 targets.target_1 = 1;
536
537 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
538 sizeof(targets));
539
540 status = intel_sdvo_read_response(intel_output, NULL, 0);
541
542 return (status == SDVO_CMD_STATUS_SUCCESS);
543 }
544
545 /**
546 * Return whether each input is trained.
547 *
548 * This function is making an assumption about the layout of the response,
549 * which should be checked against the docs.
550 */
551 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
552 {
553 struct intel_sdvo_get_trained_inputs_response response;
554 u8 status;
555
556 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
557 status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
558 if (status != SDVO_CMD_STATUS_SUCCESS)
559 return false;
560
561 *input_1 = response.input0_trained;
562 *input_2 = response.input1_trained;
563 return true;
564 }
565
566 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
567 u16 *outputs)
568 {
569 u8 status;
570
571 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
572 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
573
574 return (status == SDVO_CMD_STATUS_SUCCESS);
575 }
576
577 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
578 u16 outputs)
579 {
580 u8 status;
581
582 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
583 sizeof(outputs));
584 status = intel_sdvo_read_response(intel_output, NULL, 0);
585 return (status == SDVO_CMD_STATUS_SUCCESS);
586 }
587
588 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
589 int mode)
590 {
591 u8 status, state = SDVO_ENCODER_STATE_ON;
592
593 switch (mode) {
594 case DRM_MODE_DPMS_ON:
595 state = SDVO_ENCODER_STATE_ON;
596 break;
597 case DRM_MODE_DPMS_STANDBY:
598 state = SDVO_ENCODER_STATE_STANDBY;
599 break;
600 case DRM_MODE_DPMS_SUSPEND:
601 state = SDVO_ENCODER_STATE_SUSPEND;
602 break;
603 case DRM_MODE_DPMS_OFF:
604 state = SDVO_ENCODER_STATE_OFF;
605 break;
606 }
607
608 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
609 sizeof(state));
610 status = intel_sdvo_read_response(intel_output, NULL, 0);
611
612 return (status == SDVO_CMD_STATUS_SUCCESS);
613 }
614
615 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
616 int *clock_min,
617 int *clock_max)
618 {
619 struct intel_sdvo_pixel_clock_range clocks;
620 u8 status;
621
622 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
623 NULL, 0);
624
625 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
626
627 if (status != SDVO_CMD_STATUS_SUCCESS)
628 return false;
629
630 /* Convert the values from units of 10 kHz to kHz. */
631 *clock_min = clocks.min * 10;
632 *clock_max = clocks.max * 10;
633
634 return true;
635 }
636
637 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
638 u16 outputs)
639 {
640 u8 status;
641
642 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
643 sizeof(outputs));
644
645 status = intel_sdvo_read_response(intel_output, NULL, 0);
646 return (status == SDVO_CMD_STATUS_SUCCESS);
647 }
648
649 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
650 struct intel_sdvo_dtd *dtd)
651 {
652 u8 status;
653
654 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
655 status = intel_sdvo_read_response(intel_output, &dtd->part1,
656 sizeof(dtd->part1));
657 if (status != SDVO_CMD_STATUS_SUCCESS)
658 return false;
659
660 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
661 status = intel_sdvo_read_response(intel_output, &dtd->part2,
662 sizeof(dtd->part2));
663 if (status != SDVO_CMD_STATUS_SUCCESS)
664 return false;
665
666 return true;
667 }
668
669 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
670 struct intel_sdvo_dtd *dtd)
671 {
672 return intel_sdvo_get_timing(intel_output,
673 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
674 }
675
676 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
677 struct intel_sdvo_dtd *dtd)
678 {
679 return intel_sdvo_get_timing(intel_output,
680 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
681 }
682
683 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
684 struct intel_sdvo_dtd *dtd)
685 {
686 u8 status;
687
688 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
689 status = intel_sdvo_read_response(intel_output, NULL, 0);
690 if (status != SDVO_CMD_STATUS_SUCCESS)
691 return false;
692
693 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
694 status = intel_sdvo_read_response(intel_output, NULL, 0);
695 if (status != SDVO_CMD_STATUS_SUCCESS)
696 return false;
697
698 return true;
699 }
700
701 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
702 struct intel_sdvo_dtd *dtd)
703 {
704 return intel_sdvo_set_timing(intel_output,
705 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
706 }
707
708 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
709 struct intel_sdvo_dtd *dtd)
710 {
711 return intel_sdvo_set_timing(intel_output,
712 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
713 }
714
715 static bool
716 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
717 uint16_t clock,
718 uint16_t width,
719 uint16_t height)
720 {
721 struct intel_sdvo_preferred_input_timing_args args;
722 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
723 uint8_t status;
724
725 memset(&args, 0, sizeof(args));
726 args.clock = clock;
727 args.width = width;
728 args.height = height;
729 args.interlace = 0;
730
731 if (sdvo_priv->is_lvds &&
732 (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
733 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
734 args.scaled = 1;
735
736 intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
737 &args, sizeof(args));
738 status = intel_sdvo_read_response(output, NULL, 0);
739 if (status != SDVO_CMD_STATUS_SUCCESS)
740 return false;
741
742 return true;
743 }
744
745 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
746 struct intel_sdvo_dtd *dtd)
747 {
748 bool status;
749
750 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
751 NULL, 0);
752
753 status = intel_sdvo_read_response(output, &dtd->part1,
754 sizeof(dtd->part1));
755 if (status != SDVO_CMD_STATUS_SUCCESS)
756 return false;
757
758 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
759 NULL, 0);
760
761 status = intel_sdvo_read_response(output, &dtd->part2,
762 sizeof(dtd->part2));
763 if (status != SDVO_CMD_STATUS_SUCCESS)
764 return false;
765
766 return false;
767 }
768
769 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
770 {
771 u8 response, status;
772
773 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
774 status = intel_sdvo_read_response(intel_output, &response, 1);
775
776 if (status != SDVO_CMD_STATUS_SUCCESS) {
777 DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
778 return SDVO_CLOCK_RATE_MULT_1X;
779 } else {
780 DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response);
781 }
782
783 return response;
784 }
785
786 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
787 {
788 u8 status;
789
790 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
791 status = intel_sdvo_read_response(intel_output, NULL, 0);
792 if (status != SDVO_CMD_STATUS_SUCCESS)
793 return false;
794
795 return true;
796 }
797
798 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
799 struct drm_display_mode *mode)
800 {
801 uint16_t width, height;
802 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
803 uint16_t h_sync_offset, v_sync_offset;
804
805 width = mode->crtc_hdisplay;
806 height = mode->crtc_vdisplay;
807
808 /* do some mode translations */
809 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
810 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
811
812 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
813 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
814
815 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
816 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
817
818 dtd->part1.clock = mode->clock / 10;
819 dtd->part1.h_active = width & 0xff;
820 dtd->part1.h_blank = h_blank_len & 0xff;
821 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
822 ((h_blank_len >> 8) & 0xf);
823 dtd->part1.v_active = height & 0xff;
824 dtd->part1.v_blank = v_blank_len & 0xff;
825 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
826 ((v_blank_len >> 8) & 0xf);
827
828 dtd->part2.h_sync_off = h_sync_offset & 0xff;
829 dtd->part2.h_sync_width = h_sync_len & 0xff;
830 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
831 (v_sync_len & 0xf);
832 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
833 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
834 ((v_sync_len & 0x30) >> 4);
835
836 dtd->part2.dtd_flags = 0x18;
837 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
838 dtd->part2.dtd_flags |= 0x2;
839 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
840 dtd->part2.dtd_flags |= 0x4;
841
842 dtd->part2.sdvo_flags = 0;
843 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
844 dtd->part2.reserved = 0;
845 }
846
847 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
848 struct intel_sdvo_dtd *dtd)
849 {
850 mode->hdisplay = dtd->part1.h_active;
851 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
852 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
853 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
854 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
855 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
856 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
857 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
858
859 mode->vdisplay = dtd->part1.v_active;
860 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
861 mode->vsync_start = mode->vdisplay;
862 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
863 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
864 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
865 mode->vsync_end = mode->vsync_start +
866 (dtd->part2.v_sync_off_width & 0xf);
867 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
868 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
869 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
870
871 mode->clock = dtd->part1.clock * 10;
872
873 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
874 if (dtd->part2.dtd_flags & 0x2)
875 mode->flags |= DRM_MODE_FLAG_PHSYNC;
876 if (dtd->part2.dtd_flags & 0x4)
877 mode->flags |= DRM_MODE_FLAG_PVSYNC;
878 }
879
880 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
881 struct intel_sdvo_encode *encode)
882 {
883 uint8_t status;
884
885 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
886 status = intel_sdvo_read_response(output, encode, sizeof(*encode));
887 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
888 memset(encode, 0, sizeof(*encode));
889 return false;
890 }
891
892 return true;
893 }
894
895 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
896 {
897 uint8_t status;
898
899 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
900 status = intel_sdvo_read_response(output, NULL, 0);
901
902 return (status == SDVO_CMD_STATUS_SUCCESS);
903 }
904
905 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
906 uint8_t mode)
907 {
908 uint8_t status;
909
910 intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
911 status = intel_sdvo_read_response(output, NULL, 0);
912
913 return (status == SDVO_CMD_STATUS_SUCCESS);
914 }
915
916 #if 0
917 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
918 {
919 int i, j;
920 uint8_t set_buf_index[2];
921 uint8_t av_split;
922 uint8_t buf_size;
923 uint8_t buf[48];
924 uint8_t *pos;
925
926 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
927 intel_sdvo_read_response(output, &av_split, 1);
928
929 for (i = 0; i <= av_split; i++) {
930 set_buf_index[0] = i; set_buf_index[1] = 0;
931 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
932 set_buf_index, 2);
933 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
934 intel_sdvo_read_response(output, &buf_size, 1);
935
936 pos = buf;
937 for (j = 0; j <= buf_size; j += 8) {
938 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
939 NULL, 0);
940 intel_sdvo_read_response(output, pos, 8);
941 pos += 8;
942 }
943 }
944 }
945 #endif
946
947 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
948 uint8_t *data, int8_t size, uint8_t tx_rate)
949 {
950 uint8_t set_buf_index[2];
951
952 set_buf_index[0] = index;
953 set_buf_index[1] = 0;
954
955 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
956
957 for (; size > 0; size -= 8) {
958 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
959 data += 8;
960 }
961
962 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
963 }
964
965 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
966 {
967 uint8_t csum = 0;
968 int i;
969
970 for (i = 0; i < size; i++)
971 csum += data[i];
972
973 return 0x100 - csum;
974 }
975
976 #define DIP_TYPE_AVI 0x82
977 #define DIP_VERSION_AVI 0x2
978 #define DIP_LEN_AVI 13
979
980 struct dip_infoframe {
981 uint8_t type;
982 uint8_t version;
983 uint8_t len;
984 uint8_t checksum;
985 union {
986 struct {
987 /* Packet Byte #1 */
988 uint8_t S:2;
989 uint8_t B:2;
990 uint8_t A:1;
991 uint8_t Y:2;
992 uint8_t rsvd1:1;
993 /* Packet Byte #2 */
994 uint8_t R:4;
995 uint8_t M:2;
996 uint8_t C:2;
997 /* Packet Byte #3 */
998 uint8_t SC:2;
999 uint8_t Q:2;
1000 uint8_t EC:3;
1001 uint8_t ITC:1;
1002 /* Packet Byte #4 */
1003 uint8_t VIC:7;
1004 uint8_t rsvd2:1;
1005 /* Packet Byte #5 */
1006 uint8_t PR:4;
1007 uint8_t rsvd3:4;
1008 /* Packet Byte #6~13 */
1009 uint16_t top_bar_end;
1010 uint16_t bottom_bar_start;
1011 uint16_t left_bar_end;
1012 uint16_t right_bar_start;
1013 } avi;
1014 struct {
1015 /* Packet Byte #1 */
1016 uint8_t channel_count:3;
1017 uint8_t rsvd1:1;
1018 uint8_t coding_type:4;
1019 /* Packet Byte #2 */
1020 uint8_t sample_size:2; /* SS0, SS1 */
1021 uint8_t sample_frequency:3;
1022 uint8_t rsvd2:3;
1023 /* Packet Byte #3 */
1024 uint8_t coding_type_private:5;
1025 uint8_t rsvd3:3;
1026 /* Packet Byte #4 */
1027 uint8_t channel_allocation;
1028 /* Packet Byte #5 */
1029 uint8_t rsvd4:3;
1030 uint8_t level_shift:4;
1031 uint8_t downmix_inhibit:1;
1032 } audio;
1033 uint8_t payload[28];
1034 } __attribute__ ((packed)) u;
1035 } __attribute__((packed));
1036
1037 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
1038 struct drm_display_mode * mode)
1039 {
1040 struct dip_infoframe avi_if = {
1041 .type = DIP_TYPE_AVI,
1042 .version = DIP_VERSION_AVI,
1043 .len = DIP_LEN_AVI,
1044 };
1045
1046 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
1047 4 + avi_if.len);
1048 intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
1049 SDVO_HBUF_TX_VSYNC);
1050 }
1051
1052 static void intel_sdvo_set_tv_format(struct intel_output *output)
1053 {
1054
1055 struct intel_sdvo_tv_format format;
1056 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1057 uint32_t format_map, i;
1058 uint8_t status;
1059
1060 for (i = 0; i < TV_FORMAT_NUM; i++)
1061 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1062 break;
1063
1064 format_map = 1 << i;
1065 memset(&format, 0, sizeof(format));
1066 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1067 sizeof(format) : sizeof(format_map));
1068
1069 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map,
1070 sizeof(format));
1071
1072 status = intel_sdvo_read_response(output, NULL, 0);
1073 if (status != SDVO_CMD_STATUS_SUCCESS)
1074 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
1075 SDVO_NAME(sdvo_priv));
1076 }
1077
1078 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1079 struct drm_display_mode *mode,
1080 struct drm_display_mode *adjusted_mode)
1081 {
1082 struct intel_output *output = enc_to_intel_output(encoder);
1083 struct intel_sdvo_priv *dev_priv = output->dev_priv;
1084
1085 if (dev_priv->is_tv) {
1086 struct intel_sdvo_dtd output_dtd;
1087 bool success;
1088
1089 /* We need to construct preferred input timings based on our
1090 * output timings. To do that, we have to set the output
1091 * timings, even though this isn't really the right place in
1092 * the sequence to do it. Oh well.
1093 */
1094
1095
1096 /* Set output timings */
1097 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1098 intel_sdvo_set_target_output(output,
1099 dev_priv->controlled_output);
1100 intel_sdvo_set_output_timing(output, &output_dtd);
1101
1102 /* Set the input timing to the screen. Assume always input 0. */
1103 intel_sdvo_set_target_input(output, true, false);
1104
1105
1106 success = intel_sdvo_create_preferred_input_timing(output,
1107 mode->clock / 10,
1108 mode->hdisplay,
1109 mode->vdisplay);
1110 if (success) {
1111 struct intel_sdvo_dtd input_dtd;
1112
1113 intel_sdvo_get_preferred_input_timing(output,
1114 &input_dtd);
1115 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1116 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1117
1118 drm_mode_set_crtcinfo(adjusted_mode, 0);
1119
1120 mode->clock = adjusted_mode->clock;
1121
1122 adjusted_mode->clock *=
1123 intel_sdvo_get_pixel_multiplier(mode);
1124 } else {
1125 return false;
1126 }
1127 } else if (dev_priv->is_lvds) {
1128 struct intel_sdvo_dtd output_dtd;
1129 bool success;
1130
1131 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1132 /* Set output timings */
1133 intel_sdvo_get_dtd_from_mode(&output_dtd,
1134 dev_priv->sdvo_lvds_fixed_mode);
1135
1136 intel_sdvo_set_target_output(output,
1137 dev_priv->controlled_output);
1138 intel_sdvo_set_output_timing(output, &output_dtd);
1139
1140 /* Set the input timing to the screen. Assume always input 0. */
1141 intel_sdvo_set_target_input(output, true, false);
1142
1143
1144 success = intel_sdvo_create_preferred_input_timing(
1145 output,
1146 mode->clock / 10,
1147 mode->hdisplay,
1148 mode->vdisplay);
1149
1150 if (success) {
1151 struct intel_sdvo_dtd input_dtd;
1152
1153 intel_sdvo_get_preferred_input_timing(output,
1154 &input_dtd);
1155 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1156 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1157
1158 drm_mode_set_crtcinfo(adjusted_mode, 0);
1159
1160 mode->clock = adjusted_mode->clock;
1161
1162 adjusted_mode->clock *=
1163 intel_sdvo_get_pixel_multiplier(mode);
1164 } else {
1165 return false;
1166 }
1167
1168 } else {
1169 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1170 * SDVO device will be told of the multiplier during mode_set.
1171 */
1172 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1173 }
1174 return true;
1175 }
1176
1177 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1178 struct drm_display_mode *mode,
1179 struct drm_display_mode *adjusted_mode)
1180 {
1181 struct drm_device *dev = encoder->dev;
1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183 struct drm_crtc *crtc = encoder->crtc;
1184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1185 struct intel_output *output = enc_to_intel_output(encoder);
1186 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1187 u32 sdvox = 0;
1188 int sdvo_pixel_multiply;
1189 struct intel_sdvo_in_out_map in_out;
1190 struct intel_sdvo_dtd input_dtd;
1191 u8 status;
1192
1193 if (!mode)
1194 return;
1195
1196 /* First, set the input mapping for the first input to our controlled
1197 * output. This is only correct if we're a single-input device, in
1198 * which case the first input is the output from the appropriate SDVO
1199 * channel on the motherboard. In a two-input device, the first input
1200 * will be SDVOB and the second SDVOC.
1201 */
1202 in_out.in0 = sdvo_priv->controlled_output;
1203 in_out.in1 = 0;
1204
1205 intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1206 &in_out, sizeof(in_out));
1207 status = intel_sdvo_read_response(output, NULL, 0);
1208
1209 if (sdvo_priv->is_hdmi) {
1210 intel_sdvo_set_avi_infoframe(output, mode);
1211 sdvox |= SDVO_AUDIO_ENABLE;
1212 }
1213
1214 /* We have tried to get input timing in mode_fixup, and filled into
1215 adjusted_mode */
1216 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1217 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1218 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1219 } else
1220 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1221
1222 /* If it's a TV, we already set the output timing in mode_fixup.
1223 * Otherwise, the output timing is equal to the input timing.
1224 */
1225 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
1226 /* Set the output timing to the screen */
1227 intel_sdvo_set_target_output(output,
1228 sdvo_priv->controlled_output);
1229 intel_sdvo_set_output_timing(output, &input_dtd);
1230 }
1231
1232 /* Set the input timing to the screen. Assume always input 0. */
1233 intel_sdvo_set_target_input(output, true, false);
1234
1235 if (sdvo_priv->is_tv)
1236 intel_sdvo_set_tv_format(output);
1237
1238 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1239 * provide the device with a timing it can support, if it supports that
1240 * feature. However, presumably we would need to adjust the CRTC to
1241 * output the preferred timing, and we don't support that currently.
1242 */
1243 #if 0
1244 success = intel_sdvo_create_preferred_input_timing(output, clock,
1245 width, height);
1246 if (success) {
1247 struct intel_sdvo_dtd *input_dtd;
1248
1249 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1250 intel_sdvo_set_input_timing(output, &input_dtd);
1251 }
1252 #else
1253 intel_sdvo_set_input_timing(output, &input_dtd);
1254 #endif
1255
1256 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1257 case 1:
1258 intel_sdvo_set_clock_rate_mult(output,
1259 SDVO_CLOCK_RATE_MULT_1X);
1260 break;
1261 case 2:
1262 intel_sdvo_set_clock_rate_mult(output,
1263 SDVO_CLOCK_RATE_MULT_2X);
1264 break;
1265 case 4:
1266 intel_sdvo_set_clock_rate_mult(output,
1267 SDVO_CLOCK_RATE_MULT_4X);
1268 break;
1269 }
1270
1271 /* Set the SDVO control regs. */
1272 if (IS_I965G(dev)) {
1273 sdvox |= SDVO_BORDER_ENABLE |
1274 SDVO_VSYNC_ACTIVE_HIGH |
1275 SDVO_HSYNC_ACTIVE_HIGH;
1276 } else {
1277 sdvox |= I915_READ(sdvo_priv->output_device);
1278 switch (sdvo_priv->output_device) {
1279 case SDVOB:
1280 sdvox &= SDVOB_PRESERVE_MASK;
1281 break;
1282 case SDVOC:
1283 sdvox &= SDVOC_PRESERVE_MASK;
1284 break;
1285 }
1286 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1287 }
1288 if (intel_crtc->pipe == 1)
1289 sdvox |= SDVO_PIPE_B_SELECT;
1290
1291 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1292 if (IS_I965G(dev)) {
1293 /* done in crtc_mode_set as the dpll_md reg must be written early */
1294 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1295 /* done in crtc_mode_set as it lives inside the dpll register */
1296 } else {
1297 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1298 }
1299
1300 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1301 sdvox |= SDVO_STALL_SELECT;
1302 intel_sdvo_write_sdvox(output, sdvox);
1303 }
1304
1305 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1306 {
1307 struct drm_device *dev = encoder->dev;
1308 struct drm_i915_private *dev_priv = dev->dev_private;
1309 struct intel_output *intel_output = enc_to_intel_output(encoder);
1310 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1311 u32 temp;
1312
1313 if (mode != DRM_MODE_DPMS_ON) {
1314 intel_sdvo_set_active_outputs(intel_output, 0);
1315 if (0)
1316 intel_sdvo_set_encoder_power_state(intel_output, mode);
1317
1318 if (mode == DRM_MODE_DPMS_OFF) {
1319 temp = I915_READ(sdvo_priv->output_device);
1320 if ((temp & SDVO_ENABLE) != 0) {
1321 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1322 }
1323 }
1324 } else {
1325 bool input1, input2;
1326 int i;
1327 u8 status;
1328
1329 temp = I915_READ(sdvo_priv->output_device);
1330 if ((temp & SDVO_ENABLE) == 0)
1331 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1332 for (i = 0; i < 2; i++)
1333 intel_wait_for_vblank(dev);
1334
1335 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1336 &input2);
1337
1338
1339 /* Warn if the device reported failure to sync.
1340 * A lot of SDVO devices fail to notify of sync, but it's
1341 * a given it the status is a success, we succeeded.
1342 */
1343 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1344 DRM_DEBUG_KMS("First %s output reported failure to "
1345 "sync\n", SDVO_NAME(sdvo_priv));
1346 }
1347
1348 if (0)
1349 intel_sdvo_set_encoder_power_state(intel_output, mode);
1350 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1351 }
1352 return;
1353 }
1354
1355 static void intel_sdvo_save(struct drm_connector *connector)
1356 {
1357 struct drm_device *dev = connector->dev;
1358 struct drm_i915_private *dev_priv = dev->dev_private;
1359 struct intel_output *intel_output = to_intel_output(connector);
1360 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1361 int o;
1362
1363 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1364 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1365
1366 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1367 intel_sdvo_set_target_input(intel_output, true, false);
1368 intel_sdvo_get_input_timing(intel_output,
1369 &sdvo_priv->save_input_dtd_1);
1370 }
1371
1372 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1373 intel_sdvo_set_target_input(intel_output, false, true);
1374 intel_sdvo_get_input_timing(intel_output,
1375 &sdvo_priv->save_input_dtd_2);
1376 }
1377
1378 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1379 {
1380 u16 this_output = (1 << o);
1381 if (sdvo_priv->caps.output_flags & this_output)
1382 {
1383 intel_sdvo_set_target_output(intel_output, this_output);
1384 intel_sdvo_get_output_timing(intel_output,
1385 &sdvo_priv->save_output_dtd[o]);
1386 }
1387 }
1388 if (sdvo_priv->is_tv) {
1389 /* XXX: Save TV format/enhancements. */
1390 }
1391
1392 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1393 }
1394
1395 static void intel_sdvo_restore(struct drm_connector *connector)
1396 {
1397 struct drm_device *dev = connector->dev;
1398 struct intel_output *intel_output = to_intel_output(connector);
1399 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1400 int o;
1401 int i;
1402 bool input1, input2;
1403 u8 status;
1404
1405 intel_sdvo_set_active_outputs(intel_output, 0);
1406
1407 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1408 {
1409 u16 this_output = (1 << o);
1410 if (sdvo_priv->caps.output_flags & this_output) {
1411 intel_sdvo_set_target_output(intel_output, this_output);
1412 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1413 }
1414 }
1415
1416 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1417 intel_sdvo_set_target_input(intel_output, true, false);
1418 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1419 }
1420
1421 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1422 intel_sdvo_set_target_input(intel_output, false, true);
1423 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1424 }
1425
1426 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1427
1428 if (sdvo_priv->is_tv) {
1429 /* XXX: Restore TV format/enhancements. */
1430 }
1431
1432 intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1433
1434 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1435 {
1436 for (i = 0; i < 2; i++)
1437 intel_wait_for_vblank(dev);
1438 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1439 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1440 DRM_DEBUG_KMS("First %s output reported failure to "
1441 "sync\n", SDVO_NAME(sdvo_priv));
1442 }
1443
1444 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1445 }
1446
1447 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1448 struct drm_display_mode *mode)
1449 {
1450 struct intel_output *intel_output = to_intel_output(connector);
1451 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1452
1453 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1454 return MODE_NO_DBLESCAN;
1455
1456 if (sdvo_priv->pixel_clock_min > mode->clock)
1457 return MODE_CLOCK_LOW;
1458
1459 if (sdvo_priv->pixel_clock_max < mode->clock)
1460 return MODE_CLOCK_HIGH;
1461
1462 if (sdvo_priv->is_lvds == true) {
1463 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1464 return MODE_PANEL;
1465
1466 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1467 return MODE_PANEL;
1468
1469 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1470 return MODE_PANEL;
1471 }
1472
1473 return MODE_OK;
1474 }
1475
1476 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1477 {
1478 u8 status;
1479
1480 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1481 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1482 if (status != SDVO_CMD_STATUS_SUCCESS)
1483 return false;
1484
1485 return true;
1486 }
1487
1488 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1489 {
1490 struct drm_connector *connector = NULL;
1491 struct intel_output *iout = NULL;
1492 struct intel_sdvo_priv *sdvo;
1493
1494 /* find the sdvo connector */
1495 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1496 iout = to_intel_output(connector);
1497
1498 if (iout->type != INTEL_OUTPUT_SDVO)
1499 continue;
1500
1501 sdvo = iout->dev_priv;
1502
1503 if (sdvo->output_device == SDVOB && sdvoB)
1504 return connector;
1505
1506 if (sdvo->output_device == SDVOC && !sdvoB)
1507 return connector;
1508
1509 }
1510
1511 return NULL;
1512 }
1513
1514 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1515 {
1516 u8 response[2];
1517 u8 status;
1518 struct intel_output *intel_output;
1519 DRM_DEBUG_KMS("\n");
1520
1521 if (!connector)
1522 return 0;
1523
1524 intel_output = to_intel_output(connector);
1525
1526 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1527 status = intel_sdvo_read_response(intel_output, &response, 2);
1528
1529 if (response[0] !=0)
1530 return 1;
1531
1532 return 0;
1533 }
1534
1535 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1536 {
1537 u8 response[2];
1538 u8 status;
1539 struct intel_output *intel_output = to_intel_output(connector);
1540
1541 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1542 intel_sdvo_read_response(intel_output, &response, 2);
1543
1544 if (on) {
1545 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1546 status = intel_sdvo_read_response(intel_output, &response, 2);
1547
1548 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1549 } else {
1550 response[0] = 0;
1551 response[1] = 0;
1552 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1553 }
1554
1555 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1556 intel_sdvo_read_response(intel_output, &response, 2);
1557 }
1558
1559 static bool
1560 intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
1561 {
1562 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1563 int caps = 0;
1564
1565 if (sdvo_priv->caps.output_flags &
1566 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1567 caps++;
1568 if (sdvo_priv->caps.output_flags &
1569 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1570 caps++;
1571 if (sdvo_priv->caps.output_flags &
1572 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1573 caps++;
1574 if (sdvo_priv->caps.output_flags &
1575 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1576 caps++;
1577 if (sdvo_priv->caps.output_flags &
1578 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1579 caps++;
1580
1581 if (sdvo_priv->caps.output_flags &
1582 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1583 caps++;
1584
1585 if (sdvo_priv->caps.output_flags &
1586 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1587 caps++;
1588
1589 return (caps > 1);
1590 }
1591
1592 static struct drm_connector *
1593 intel_find_analog_connector(struct drm_device *dev)
1594 {
1595 struct drm_connector *connector;
1596 struct intel_output *intel_output;
1597
1598 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1599 intel_output = to_intel_output(connector);
1600 if (intel_output->type == INTEL_OUTPUT_ANALOG)
1601 return connector;
1602 }
1603 return NULL;
1604 }
1605
1606 static int
1607 intel_analog_is_connected(struct drm_device *dev)
1608 {
1609 struct drm_connector *analog_connector;
1610 analog_connector = intel_find_analog_connector(dev);
1611
1612 if (!analog_connector)
1613 return false;
1614
1615 if (analog_connector->funcs->detect(analog_connector) ==
1616 connector_status_disconnected)
1617 return false;
1618
1619 return true;
1620 }
1621
1622 enum drm_connector_status
1623 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1624 {
1625 struct intel_output *intel_output = to_intel_output(connector);
1626 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1627 enum drm_connector_status status = connector_status_connected;
1628 struct edid *edid = NULL;
1629
1630 edid = drm_get_edid(&intel_output->base,
1631 intel_output->ddc_bus);
1632
1633 /* This is only applied to SDVO cards with multiple outputs */
1634 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_output)) {
1635 uint8_t saved_ddc, temp_ddc;
1636 saved_ddc = sdvo_priv->ddc_bus;
1637 temp_ddc = sdvo_priv->ddc_bus >> 1;
1638 /*
1639 * Don't use the 1 as the argument of DDC bus switch to get
1640 * the EDID. It is used for SDVO SPD ROM.
1641 */
1642 while(temp_ddc > 1) {
1643 sdvo_priv->ddc_bus = temp_ddc;
1644 edid = drm_get_edid(&intel_output->base,
1645 intel_output->ddc_bus);
1646 if (edid) {
1647 /*
1648 * When we can get the EDID, maybe it is the
1649 * correct DDC bus. Update it.
1650 */
1651 sdvo_priv->ddc_bus = temp_ddc;
1652 break;
1653 }
1654 temp_ddc >>= 1;
1655 }
1656 if (edid == NULL)
1657 sdvo_priv->ddc_bus = saved_ddc;
1658 }
1659 /* when there is no edid and no monitor is connected with VGA
1660 * port, try to use the CRT ddc to read the EDID for DVI-connector
1661 */
1662 if (edid == NULL &&
1663 sdvo_priv->analog_ddc_bus &&
1664 !intel_analog_is_connected(intel_output->base.dev))
1665 edid = drm_get_edid(&intel_output->base,
1666 sdvo_priv->analog_ddc_bus);
1667 if (edid != NULL) {
1668 /* Don't report the output as connected if it's a DVI-I
1669 * connector with a non-digital EDID coming out.
1670 */
1671 if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1672 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1673 sdvo_priv->is_hdmi =
1674 drm_detect_hdmi_monitor(edid);
1675 else
1676 status = connector_status_disconnected;
1677 }
1678
1679 kfree(edid);
1680 intel_output->base.display_info.raw_edid = NULL;
1681
1682 } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1683 status = connector_status_disconnected;
1684
1685 return status;
1686 }
1687
1688 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1689 {
1690 uint16_t response;
1691 u8 status;
1692 struct intel_output *intel_output = to_intel_output(connector);
1693 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1694
1695 intel_sdvo_write_cmd(intel_output,
1696 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1697 if (sdvo_priv->is_tv) {
1698 /* add 30ms delay when the output type is SDVO-TV */
1699 mdelay(30);
1700 }
1701 status = intel_sdvo_read_response(intel_output, &response, 2);
1702
1703 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
1704
1705 if (status != SDVO_CMD_STATUS_SUCCESS)
1706 return connector_status_unknown;
1707
1708 if (response == 0)
1709 return connector_status_disconnected;
1710
1711 if (intel_sdvo_multifunc_encoder(intel_output) &&
1712 sdvo_priv->attached_output != response) {
1713 if (sdvo_priv->controlled_output != response &&
1714 intel_sdvo_output_setup(intel_output, response) != true)
1715 return connector_status_unknown;
1716 sdvo_priv->attached_output = response;
1717 }
1718 return intel_sdvo_hdmi_sink_detect(connector, response);
1719 }
1720
1721 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1722 {
1723 struct intel_output *intel_output = to_intel_output(connector);
1724 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1725 int num_modes;
1726
1727 /* set the bus switch and get the modes */
1728 num_modes = intel_ddc_get_modes(intel_output);
1729
1730 /*
1731 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1732 * link between analog and digital outputs. So, if the regular SDVO
1733 * DDC fails, check to see if the analog output is disconnected, in
1734 * which case we'll look there for the digital DDC data.
1735 */
1736 if (num_modes == 0 &&
1737 sdvo_priv->analog_ddc_bus &&
1738 !intel_analog_is_connected(intel_output->base.dev)) {
1739 struct i2c_adapter *digital_ddc_bus;
1740
1741 /* Switch to the analog ddc bus and try that
1742 */
1743 digital_ddc_bus = intel_output->ddc_bus;
1744 intel_output->ddc_bus = sdvo_priv->analog_ddc_bus;
1745
1746 (void) intel_ddc_get_modes(intel_output);
1747
1748 intel_output->ddc_bus = digital_ddc_bus;
1749 }
1750 }
1751
1752 /*
1753 * Set of SDVO TV modes.
1754 * Note! This is in reply order (see loop in get_tv_modes).
1755 * XXX: all 60Hz refresh?
1756 */
1757 struct drm_display_mode sdvo_tv_modes[] = {
1758 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1759 416, 0, 200, 201, 232, 233, 0,
1760 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1761 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1762 416, 0, 240, 241, 272, 273, 0,
1763 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1764 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1765 496, 0, 300, 301, 332, 333, 0,
1766 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1767 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1768 736, 0, 350, 351, 382, 383, 0,
1769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1770 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1771 736, 0, 400, 401, 432, 433, 0,
1772 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1773 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1774 736, 0, 480, 481, 512, 513, 0,
1775 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1776 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1777 800, 0, 480, 481, 512, 513, 0,
1778 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1779 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1780 800, 0, 576, 577, 608, 609, 0,
1781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1782 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1783 816, 0, 350, 351, 382, 383, 0,
1784 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1785 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1786 816, 0, 400, 401, 432, 433, 0,
1787 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1788 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1789 816, 0, 480, 481, 512, 513, 0,
1790 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1791 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1792 816, 0, 540, 541, 572, 573, 0,
1793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1794 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1795 816, 0, 576, 577, 608, 609, 0,
1796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1797 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1798 864, 0, 576, 577, 608, 609, 0,
1799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1800 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1801 896, 0, 600, 601, 632, 633, 0,
1802 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1803 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1804 928, 0, 624, 625, 656, 657, 0,
1805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1806 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1807 1016, 0, 766, 767, 798, 799, 0,
1808 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1809 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1810 1120, 0, 768, 769, 800, 801, 0,
1811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1812 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1813 1376, 0, 1024, 1025, 1056, 1057, 0,
1814 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1815 };
1816
1817 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1818 {
1819 struct intel_output *output = to_intel_output(connector);
1820 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1821 struct intel_sdvo_sdtv_resolution_request tv_res;
1822 uint32_t reply = 0, format_map = 0;
1823 int i;
1824 uint8_t status;
1825
1826
1827 /* Read the list of supported input resolutions for the selected TV
1828 * format.
1829 */
1830 for (i = 0; i < TV_FORMAT_NUM; i++)
1831 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1832 break;
1833
1834 format_map = (1 << i);
1835 memcpy(&tv_res, &format_map,
1836 sizeof(struct intel_sdvo_sdtv_resolution_request) >
1837 sizeof(format_map) ? sizeof(format_map) :
1838 sizeof(struct intel_sdvo_sdtv_resolution_request));
1839
1840 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1841
1842 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1843 &tv_res, sizeof(tv_res));
1844 status = intel_sdvo_read_response(output, &reply, 3);
1845 if (status != SDVO_CMD_STATUS_SUCCESS)
1846 return;
1847
1848 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1849 if (reply & (1 << i)) {
1850 struct drm_display_mode *nmode;
1851 nmode = drm_mode_duplicate(connector->dev,
1852 &sdvo_tv_modes[i]);
1853 if (nmode)
1854 drm_mode_probed_add(connector, nmode);
1855 }
1856
1857 }
1858
1859 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1860 {
1861 struct intel_output *intel_output = to_intel_output(connector);
1862 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1863 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1864 struct drm_display_mode *newmode;
1865
1866 /*
1867 * Attempt to get the mode list from DDC.
1868 * Assume that the preferred modes are
1869 * arranged in priority order.
1870 */
1871 intel_ddc_get_modes(intel_output);
1872 if (list_empty(&connector->probed_modes) == false)
1873 goto end;
1874
1875 /* Fetch modes from VBT */
1876 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1877 newmode = drm_mode_duplicate(connector->dev,
1878 dev_priv->sdvo_lvds_vbt_mode);
1879 if (newmode != NULL) {
1880 /* Guarantee the mode is preferred */
1881 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1882 DRM_MODE_TYPE_DRIVER);
1883 drm_mode_probed_add(connector, newmode);
1884 }
1885 }
1886
1887 end:
1888 list_for_each_entry(newmode, &connector->probed_modes, head) {
1889 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1890 sdvo_priv->sdvo_lvds_fixed_mode =
1891 drm_mode_duplicate(connector->dev, newmode);
1892 break;
1893 }
1894 }
1895
1896 }
1897
1898 static int intel_sdvo_get_modes(struct drm_connector *connector)
1899 {
1900 struct intel_output *output = to_intel_output(connector);
1901 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1902
1903 if (sdvo_priv->is_tv)
1904 intel_sdvo_get_tv_modes(connector);
1905 else if (sdvo_priv->is_lvds == true)
1906 intel_sdvo_get_lvds_modes(connector);
1907 else
1908 intel_sdvo_get_ddc_modes(connector);
1909
1910 if (list_empty(&connector->probed_modes))
1911 return 0;
1912 return 1;
1913 }
1914
1915 static
1916 void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1917 {
1918 struct intel_output *intel_output = to_intel_output(connector);
1919 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1920 struct drm_device *dev = connector->dev;
1921
1922 if (sdvo_priv->is_tv) {
1923 if (sdvo_priv->left_property)
1924 drm_property_destroy(dev, sdvo_priv->left_property);
1925 if (sdvo_priv->right_property)
1926 drm_property_destroy(dev, sdvo_priv->right_property);
1927 if (sdvo_priv->top_property)
1928 drm_property_destroy(dev, sdvo_priv->top_property);
1929 if (sdvo_priv->bottom_property)
1930 drm_property_destroy(dev, sdvo_priv->bottom_property);
1931 if (sdvo_priv->hpos_property)
1932 drm_property_destroy(dev, sdvo_priv->hpos_property);
1933 if (sdvo_priv->vpos_property)
1934 drm_property_destroy(dev, sdvo_priv->vpos_property);
1935 }
1936 if (sdvo_priv->is_tv) {
1937 if (sdvo_priv->saturation_property)
1938 drm_property_destroy(dev,
1939 sdvo_priv->saturation_property);
1940 if (sdvo_priv->contrast_property)
1941 drm_property_destroy(dev,
1942 sdvo_priv->contrast_property);
1943 if (sdvo_priv->hue_property)
1944 drm_property_destroy(dev, sdvo_priv->hue_property);
1945 }
1946 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1947 if (sdvo_priv->brightness_property)
1948 drm_property_destroy(dev,
1949 sdvo_priv->brightness_property);
1950 }
1951 return;
1952 }
1953
1954 static void intel_sdvo_destroy(struct drm_connector *connector)
1955 {
1956 struct intel_output *intel_output = to_intel_output(connector);
1957 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1958
1959 if (intel_output->i2c_bus)
1960 intel_i2c_destroy(intel_output->i2c_bus);
1961 if (intel_output->ddc_bus)
1962 intel_i2c_destroy(intel_output->ddc_bus);
1963 if (sdvo_priv->analog_ddc_bus)
1964 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
1965
1966 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1967 drm_mode_destroy(connector->dev,
1968 sdvo_priv->sdvo_lvds_fixed_mode);
1969
1970 if (sdvo_priv->tv_format_property)
1971 drm_property_destroy(connector->dev,
1972 sdvo_priv->tv_format_property);
1973
1974 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
1975 intel_sdvo_destroy_enhance_property(connector);
1976
1977 drm_sysfs_connector_remove(connector);
1978 drm_connector_cleanup(connector);
1979
1980 kfree(intel_output);
1981 }
1982
1983 static int
1984 intel_sdvo_set_property(struct drm_connector *connector,
1985 struct drm_property *property,
1986 uint64_t val)
1987 {
1988 struct intel_output *intel_output = to_intel_output(connector);
1989 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1990 struct drm_encoder *encoder = &intel_output->enc;
1991 struct drm_crtc *crtc = encoder->crtc;
1992 int ret = 0;
1993 bool changed = false;
1994 uint8_t cmd, status;
1995 uint16_t temp_value;
1996
1997 ret = drm_connector_property_set_value(connector, property, val);
1998 if (ret < 0)
1999 goto out;
2000
2001 if (property == sdvo_priv->tv_format_property) {
2002 if (val >= TV_FORMAT_NUM) {
2003 ret = -EINVAL;
2004 goto out;
2005 }
2006 if (sdvo_priv->tv_format_name ==
2007 sdvo_priv->tv_format_supported[val])
2008 goto out;
2009
2010 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val];
2011 changed = true;
2012 }
2013
2014 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
2015 cmd = 0;
2016 temp_value = val;
2017 if (sdvo_priv->left_property == property) {
2018 drm_connector_property_set_value(connector,
2019 sdvo_priv->right_property, val);
2020 if (sdvo_priv->left_margin == temp_value)
2021 goto out;
2022
2023 sdvo_priv->left_margin = temp_value;
2024 sdvo_priv->right_margin = temp_value;
2025 temp_value = sdvo_priv->max_hscan -
2026 sdvo_priv->left_margin;
2027 cmd = SDVO_CMD_SET_OVERSCAN_H;
2028 } else if (sdvo_priv->right_property == property) {
2029 drm_connector_property_set_value(connector,
2030 sdvo_priv->left_property, val);
2031 if (sdvo_priv->right_margin == temp_value)
2032 goto out;
2033
2034 sdvo_priv->left_margin = temp_value;
2035 sdvo_priv->right_margin = temp_value;
2036 temp_value = sdvo_priv->max_hscan -
2037 sdvo_priv->left_margin;
2038 cmd = SDVO_CMD_SET_OVERSCAN_H;
2039 } else if (sdvo_priv->top_property == property) {
2040 drm_connector_property_set_value(connector,
2041 sdvo_priv->bottom_property, val);
2042 if (sdvo_priv->top_margin == temp_value)
2043 goto out;
2044
2045 sdvo_priv->top_margin = temp_value;
2046 sdvo_priv->bottom_margin = temp_value;
2047 temp_value = sdvo_priv->max_vscan -
2048 sdvo_priv->top_margin;
2049 cmd = SDVO_CMD_SET_OVERSCAN_V;
2050 } else if (sdvo_priv->bottom_property == property) {
2051 drm_connector_property_set_value(connector,
2052 sdvo_priv->top_property, val);
2053 if (sdvo_priv->bottom_margin == temp_value)
2054 goto out;
2055 sdvo_priv->top_margin = temp_value;
2056 sdvo_priv->bottom_margin = temp_value;
2057 temp_value = sdvo_priv->max_vscan -
2058 sdvo_priv->top_margin;
2059 cmd = SDVO_CMD_SET_OVERSCAN_V;
2060 } else if (sdvo_priv->hpos_property == property) {
2061 if (sdvo_priv->cur_hpos == temp_value)
2062 goto out;
2063
2064 cmd = SDVO_CMD_SET_POSITION_H;
2065 sdvo_priv->cur_hpos = temp_value;
2066 } else if (sdvo_priv->vpos_property == property) {
2067 if (sdvo_priv->cur_vpos == temp_value)
2068 goto out;
2069
2070 cmd = SDVO_CMD_SET_POSITION_V;
2071 sdvo_priv->cur_vpos = temp_value;
2072 } else if (sdvo_priv->saturation_property == property) {
2073 if (sdvo_priv->cur_saturation == temp_value)
2074 goto out;
2075
2076 cmd = SDVO_CMD_SET_SATURATION;
2077 sdvo_priv->cur_saturation = temp_value;
2078 } else if (sdvo_priv->contrast_property == property) {
2079 if (sdvo_priv->cur_contrast == temp_value)
2080 goto out;
2081
2082 cmd = SDVO_CMD_SET_CONTRAST;
2083 sdvo_priv->cur_contrast = temp_value;
2084 } else if (sdvo_priv->hue_property == property) {
2085 if (sdvo_priv->cur_hue == temp_value)
2086 goto out;
2087
2088 cmd = SDVO_CMD_SET_HUE;
2089 sdvo_priv->cur_hue = temp_value;
2090 } else if (sdvo_priv->brightness_property == property) {
2091 if (sdvo_priv->cur_brightness == temp_value)
2092 goto out;
2093
2094 cmd = SDVO_CMD_SET_BRIGHTNESS;
2095 sdvo_priv->cur_brightness = temp_value;
2096 }
2097 if (cmd) {
2098 intel_sdvo_write_cmd(intel_output, cmd, &temp_value, 2);
2099 status = intel_sdvo_read_response(intel_output,
2100 NULL, 0);
2101 if (status != SDVO_CMD_STATUS_SUCCESS) {
2102 DRM_DEBUG_KMS("Incorrect SDVO command \n");
2103 return -EINVAL;
2104 }
2105 changed = true;
2106 }
2107 }
2108 if (changed && crtc)
2109 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
2110 crtc->y, crtc->fb);
2111 out:
2112 return ret;
2113 }
2114
2115 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
2116 .dpms = intel_sdvo_dpms,
2117 .mode_fixup = intel_sdvo_mode_fixup,
2118 .prepare = intel_encoder_prepare,
2119 .mode_set = intel_sdvo_mode_set,
2120 .commit = intel_encoder_commit,
2121 };
2122
2123 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2124 .dpms = drm_helper_connector_dpms,
2125 .save = intel_sdvo_save,
2126 .restore = intel_sdvo_restore,
2127 .detect = intel_sdvo_detect,
2128 .fill_modes = drm_helper_probe_single_connector_modes,
2129 .set_property = intel_sdvo_set_property,
2130 .destroy = intel_sdvo_destroy,
2131 };
2132
2133 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2134 .get_modes = intel_sdvo_get_modes,
2135 .mode_valid = intel_sdvo_mode_valid,
2136 .best_encoder = intel_best_encoder,
2137 };
2138
2139 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2140 {
2141 drm_encoder_cleanup(encoder);
2142 }
2143
2144 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2145 .destroy = intel_sdvo_enc_destroy,
2146 };
2147
2148
2149 /**
2150 * Choose the appropriate DDC bus for control bus switch command for this
2151 * SDVO output based on the controlled output.
2152 *
2153 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2154 * outputs, then LVDS outputs.
2155 */
2156 static void
2157 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
2158 {
2159 uint16_t mask = 0;
2160 unsigned int num_bits;
2161
2162 /* Make a mask of outputs less than or equal to our own priority in the
2163 * list.
2164 */
2165 switch (dev_priv->controlled_output) {
2166 case SDVO_OUTPUT_LVDS1:
2167 mask |= SDVO_OUTPUT_LVDS1;
2168 case SDVO_OUTPUT_LVDS0:
2169 mask |= SDVO_OUTPUT_LVDS0;
2170 case SDVO_OUTPUT_TMDS1:
2171 mask |= SDVO_OUTPUT_TMDS1;
2172 case SDVO_OUTPUT_TMDS0:
2173 mask |= SDVO_OUTPUT_TMDS0;
2174 case SDVO_OUTPUT_RGB1:
2175 mask |= SDVO_OUTPUT_RGB1;
2176 case SDVO_OUTPUT_RGB0:
2177 mask |= SDVO_OUTPUT_RGB0;
2178 break;
2179 }
2180
2181 /* Count bits to find what number we are in the priority list. */
2182 mask &= dev_priv->caps.output_flags;
2183 num_bits = hweight16(mask);
2184 if (num_bits > 3) {
2185 /* if more than 3 outputs, default to DDC bus 3 for now */
2186 num_bits = 3;
2187 }
2188
2189 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2190 dev_priv->ddc_bus = 1 << num_bits;
2191 }
2192
2193 static bool
2194 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
2195 {
2196 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
2197 uint8_t status;
2198
2199 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
2200
2201 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
2202 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
2203 if (status != SDVO_CMD_STATUS_SUCCESS)
2204 return false;
2205 return true;
2206 }
2207
2208 static struct intel_output *
2209 intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
2210 {
2211 struct drm_device *dev = chan->drm_dev;
2212 struct drm_connector *connector;
2213 struct intel_output *intel_output = NULL;
2214
2215 list_for_each_entry(connector,
2216 &dev->mode_config.connector_list, head) {
2217 if (to_intel_output(connector)->ddc_bus == &chan->adapter) {
2218 intel_output = to_intel_output(connector);
2219 break;
2220 }
2221 }
2222 return intel_output;
2223 }
2224
2225 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2226 struct i2c_msg msgs[], int num)
2227 {
2228 struct intel_output *intel_output;
2229 struct intel_sdvo_priv *sdvo_priv;
2230 struct i2c_algo_bit_data *algo_data;
2231 const struct i2c_algorithm *algo;
2232
2233 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
2234 intel_output =
2235 intel_sdvo_chan_to_intel_output(
2236 (struct intel_i2c_chan *)(algo_data->data));
2237 if (intel_output == NULL)
2238 return -EINVAL;
2239
2240 sdvo_priv = intel_output->dev_priv;
2241 algo = intel_output->i2c_bus->algo;
2242
2243 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
2244 return algo->master_xfer(i2c_adap, msgs, num);
2245 }
2246
2247 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2248 .master_xfer = intel_sdvo_master_xfer,
2249 };
2250
2251 static u8
2252 intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
2253 {
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255 struct sdvo_device_mapping *my_mapping, *other_mapping;
2256
2257 if (output_device == SDVOB) {
2258 my_mapping = &dev_priv->sdvo_mappings[0];
2259 other_mapping = &dev_priv->sdvo_mappings[1];
2260 } else {
2261 my_mapping = &dev_priv->sdvo_mappings[1];
2262 other_mapping = &dev_priv->sdvo_mappings[0];
2263 }
2264
2265 /* If the BIOS described our SDVO device, take advantage of it. */
2266 if (my_mapping->slave_addr)
2267 return my_mapping->slave_addr;
2268
2269 /* If the BIOS only described a different SDVO device, use the
2270 * address that it isn't using.
2271 */
2272 if (other_mapping->slave_addr) {
2273 if (other_mapping->slave_addr == 0x70)
2274 return 0x72;
2275 else
2276 return 0x70;
2277 }
2278
2279 /* No SDVO device info is found for another DVO port,
2280 * so use mapping assumption we had before BIOS parsing.
2281 */
2282 if (output_device == SDVOB)
2283 return 0x70;
2284 else
2285 return 0x72;
2286 }
2287
2288 static int intel_sdvo_bad_tv_callback(const struct dmi_system_id *id)
2289 {
2290 DRM_DEBUG_KMS("Ignoring bad SDVO TV connector for %s\n", id->ident);
2291 return 1;
2292 }
2293
2294 static struct dmi_system_id intel_sdvo_bad_tv[] = {
2295 {
2296 .callback = intel_sdvo_bad_tv_callback,
2297 .ident = "IntelG45/ICH10R/DME1737",
2298 .matches = {
2299 DMI_MATCH(DMI_SYS_VENDOR, "IBM CORPORATION"),
2300 DMI_MATCH(DMI_PRODUCT_NAME, "4800784"),
2301 },
2302 },
2303
2304 { } /* terminating entry */
2305 };
2306
2307 static bool
2308 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2309 {
2310 struct drm_connector *connector = &intel_output->base;
2311 struct drm_encoder *encoder = &intel_output->enc;
2312 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2313 bool ret = true, registered = false;
2314
2315 sdvo_priv->is_tv = false;
2316 intel_output->needs_tv_clock = false;
2317 sdvo_priv->is_lvds = false;
2318
2319 if (device_is_registered(&connector->kdev)) {
2320 drm_sysfs_connector_remove(connector);
2321 registered = true;
2322 }
2323
2324 if (flags &
2325 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
2326 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
2327 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
2328 else
2329 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
2330
2331 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2332 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2333
2334 if (intel_sdvo_get_supp_encode(intel_output,
2335 &sdvo_priv->encode) &&
2336 intel_sdvo_get_digital_encoding_mode(intel_output) &&
2337 sdvo_priv->is_hdmi) {
2338 /* enable hdmi encoding mode if supported */
2339 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
2340 intel_sdvo_set_colorimetry(intel_output,
2341 SDVO_COLORIMETRY_RGB256);
2342 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2343 intel_output->clone_mask =
2344 (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2345 (1 << INTEL_ANALOG_CLONE_BIT);
2346 }
2347 } else if ((flags & SDVO_OUTPUT_SVID0) &&
2348 !dmi_check_system(intel_sdvo_bad_tv)) {
2349
2350 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
2351 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2352 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2353 sdvo_priv->is_tv = true;
2354 intel_output->needs_tv_clock = true;
2355 intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2356 } else if (flags & SDVO_OUTPUT_RGB0) {
2357
2358 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
2359 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2360 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2361 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2362 (1 << INTEL_ANALOG_CLONE_BIT);
2363 } else if (flags & SDVO_OUTPUT_RGB1) {
2364
2365 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
2366 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2367 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2368 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2369 (1 << INTEL_ANALOG_CLONE_BIT);
2370 } else if (flags & SDVO_OUTPUT_CVBS0) {
2371
2372 sdvo_priv->controlled_output = SDVO_OUTPUT_CVBS0;
2373 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2374 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2375 sdvo_priv->is_tv = true;
2376 intel_output->needs_tv_clock = true;
2377 intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2378 } else if (flags & SDVO_OUTPUT_LVDS0) {
2379
2380 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
2381 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2382 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2383 sdvo_priv->is_lvds = true;
2384 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2385 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2386 } else if (flags & SDVO_OUTPUT_LVDS1) {
2387
2388 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
2389 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2390 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2391 sdvo_priv->is_lvds = true;
2392 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2393 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2394 } else {
2395
2396 unsigned char bytes[2];
2397
2398 sdvo_priv->controlled_output = 0;
2399 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
2400 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2401 SDVO_NAME(sdvo_priv),
2402 bytes[0], bytes[1]);
2403 ret = false;
2404 }
2405 intel_output->crtc_mask = (1 << 0) | (1 << 1);
2406
2407 if (ret && registered)
2408 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2409
2410
2411 return ret;
2412
2413 }
2414
2415 static void intel_sdvo_tv_create_property(struct drm_connector *connector)
2416 {
2417 struct intel_output *intel_output = to_intel_output(connector);
2418 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2419 struct intel_sdvo_tv_format format;
2420 uint32_t format_map, i;
2421 uint8_t status;
2422
2423 intel_sdvo_set_target_output(intel_output,
2424 sdvo_priv->controlled_output);
2425
2426 intel_sdvo_write_cmd(intel_output,
2427 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
2428 status = intel_sdvo_read_response(intel_output,
2429 &format, sizeof(format));
2430 if (status != SDVO_CMD_STATUS_SUCCESS)
2431 return;
2432
2433 memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2434 sizeof(format_map) : sizeof(format));
2435
2436 if (format_map == 0)
2437 return;
2438
2439 sdvo_priv->format_supported_num = 0;
2440 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2441 if (format_map & (1 << i)) {
2442 sdvo_priv->tv_format_supported
2443 [sdvo_priv->format_supported_num++] =
2444 tv_format_names[i];
2445 }
2446
2447
2448 sdvo_priv->tv_format_property =
2449 drm_property_create(
2450 connector->dev, DRM_MODE_PROP_ENUM,
2451 "mode", sdvo_priv->format_supported_num);
2452
2453 for (i = 0; i < sdvo_priv->format_supported_num; i++)
2454 drm_property_add_enum(
2455 sdvo_priv->tv_format_property, i,
2456 i, sdvo_priv->tv_format_supported[i]);
2457
2458 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0];
2459 drm_connector_attach_property(
2460 connector, sdvo_priv->tv_format_property, 0);
2461
2462 }
2463
2464 static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2465 {
2466 struct intel_output *intel_output = to_intel_output(connector);
2467 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2468 struct intel_sdvo_enhancements_reply sdvo_data;
2469 struct drm_device *dev = connector->dev;
2470 uint8_t status;
2471 uint16_t response, data_value[2];
2472
2473 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2474 NULL, 0);
2475 status = intel_sdvo_read_response(intel_output, &sdvo_data,
2476 sizeof(sdvo_data));
2477 if (status != SDVO_CMD_STATUS_SUCCESS) {
2478 DRM_DEBUG_KMS(" incorrect response is returned\n");
2479 return;
2480 }
2481 response = *((uint16_t *)&sdvo_data);
2482 if (!response) {
2483 DRM_DEBUG_KMS("No enhancement is supported\n");
2484 return;
2485 }
2486 if (sdvo_priv->is_tv) {
2487 /* when horizontal overscan is supported, Add the left/right
2488 * property
2489 */
2490 if (sdvo_data.overscan_h) {
2491 intel_sdvo_write_cmd(intel_output,
2492 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
2493 status = intel_sdvo_read_response(intel_output,
2494 &data_value, 4);
2495 if (status != SDVO_CMD_STATUS_SUCCESS) {
2496 DRM_DEBUG_KMS("Incorrect SDVO max "
2497 "h_overscan\n");
2498 return;
2499 }
2500 intel_sdvo_write_cmd(intel_output,
2501 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
2502 status = intel_sdvo_read_response(intel_output,
2503 &response, 2);
2504 if (status != SDVO_CMD_STATUS_SUCCESS) {
2505 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
2506 return;
2507 }
2508 sdvo_priv->max_hscan = data_value[0];
2509 sdvo_priv->left_margin = data_value[0] - response;
2510 sdvo_priv->right_margin = sdvo_priv->left_margin;
2511 sdvo_priv->left_property =
2512 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2513 "left_margin", 2);
2514 sdvo_priv->left_property->values[0] = 0;
2515 sdvo_priv->left_property->values[1] = data_value[0];
2516 drm_connector_attach_property(connector,
2517 sdvo_priv->left_property,
2518 sdvo_priv->left_margin);
2519 sdvo_priv->right_property =
2520 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2521 "right_margin", 2);
2522 sdvo_priv->right_property->values[0] = 0;
2523 sdvo_priv->right_property->values[1] = data_value[0];
2524 drm_connector_attach_property(connector,
2525 sdvo_priv->right_property,
2526 sdvo_priv->right_margin);
2527 DRM_DEBUG_KMS("h_overscan: max %d, "
2528 "default %d, current %d\n",
2529 data_value[0], data_value[1], response);
2530 }
2531 if (sdvo_data.overscan_v) {
2532 intel_sdvo_write_cmd(intel_output,
2533 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
2534 status = intel_sdvo_read_response(intel_output,
2535 &data_value, 4);
2536 if (status != SDVO_CMD_STATUS_SUCCESS) {
2537 DRM_DEBUG_KMS("Incorrect SDVO max "
2538 "v_overscan\n");
2539 return;
2540 }
2541 intel_sdvo_write_cmd(intel_output,
2542 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
2543 status = intel_sdvo_read_response(intel_output,
2544 &response, 2);
2545 if (status != SDVO_CMD_STATUS_SUCCESS) {
2546 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2547 return;
2548 }
2549 sdvo_priv->max_vscan = data_value[0];
2550 sdvo_priv->top_margin = data_value[0] - response;
2551 sdvo_priv->bottom_margin = sdvo_priv->top_margin;
2552 sdvo_priv->top_property =
2553 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2554 "top_margin", 2);
2555 sdvo_priv->top_property->values[0] = 0;
2556 sdvo_priv->top_property->values[1] = data_value[0];
2557 drm_connector_attach_property(connector,
2558 sdvo_priv->top_property,
2559 sdvo_priv->top_margin);
2560 sdvo_priv->bottom_property =
2561 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2562 "bottom_margin", 2);
2563 sdvo_priv->bottom_property->values[0] = 0;
2564 sdvo_priv->bottom_property->values[1] = data_value[0];
2565 drm_connector_attach_property(connector,
2566 sdvo_priv->bottom_property,
2567 sdvo_priv->bottom_margin);
2568 DRM_DEBUG_KMS("v_overscan: max %d, "
2569 "default %d, current %d\n",
2570 data_value[0], data_value[1], response);
2571 }
2572 if (sdvo_data.position_h) {
2573 intel_sdvo_write_cmd(intel_output,
2574 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
2575 status = intel_sdvo_read_response(intel_output,
2576 &data_value, 4);
2577 if (status != SDVO_CMD_STATUS_SUCCESS) {
2578 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2579 return;
2580 }
2581 intel_sdvo_write_cmd(intel_output,
2582 SDVO_CMD_GET_POSITION_H, NULL, 0);
2583 status = intel_sdvo_read_response(intel_output,
2584 &response, 2);
2585 if (status != SDVO_CMD_STATUS_SUCCESS) {
2586 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2587 return;
2588 }
2589 sdvo_priv->max_hpos = data_value[0];
2590 sdvo_priv->cur_hpos = response;
2591 sdvo_priv->hpos_property =
2592 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2593 "hpos", 2);
2594 sdvo_priv->hpos_property->values[0] = 0;
2595 sdvo_priv->hpos_property->values[1] = data_value[0];
2596 drm_connector_attach_property(connector,
2597 sdvo_priv->hpos_property,
2598 sdvo_priv->cur_hpos);
2599 DRM_DEBUG_KMS("h_position: max %d, "
2600 "default %d, current %d\n",
2601 data_value[0], data_value[1], response);
2602 }
2603 if (sdvo_data.position_v) {
2604 intel_sdvo_write_cmd(intel_output,
2605 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
2606 status = intel_sdvo_read_response(intel_output,
2607 &data_value, 4);
2608 if (status != SDVO_CMD_STATUS_SUCCESS) {
2609 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2610 return;
2611 }
2612 intel_sdvo_write_cmd(intel_output,
2613 SDVO_CMD_GET_POSITION_V, NULL, 0);
2614 status = intel_sdvo_read_response(intel_output,
2615 &response, 2);
2616 if (status != SDVO_CMD_STATUS_SUCCESS) {
2617 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2618 return;
2619 }
2620 sdvo_priv->max_vpos = data_value[0];
2621 sdvo_priv->cur_vpos = response;
2622 sdvo_priv->vpos_property =
2623 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2624 "vpos", 2);
2625 sdvo_priv->vpos_property->values[0] = 0;
2626 sdvo_priv->vpos_property->values[1] = data_value[0];
2627 drm_connector_attach_property(connector,
2628 sdvo_priv->vpos_property,
2629 sdvo_priv->cur_vpos);
2630 DRM_DEBUG_KMS("v_position: max %d, "
2631 "default %d, current %d\n",
2632 data_value[0], data_value[1], response);
2633 }
2634 }
2635 if (sdvo_priv->is_tv) {
2636 if (sdvo_data.saturation) {
2637 intel_sdvo_write_cmd(intel_output,
2638 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
2639 status = intel_sdvo_read_response(intel_output,
2640 &data_value, 4);
2641 if (status != SDVO_CMD_STATUS_SUCCESS) {
2642 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2643 return;
2644 }
2645 intel_sdvo_write_cmd(intel_output,
2646 SDVO_CMD_GET_SATURATION, NULL, 0);
2647 status = intel_sdvo_read_response(intel_output,
2648 &response, 2);
2649 if (status != SDVO_CMD_STATUS_SUCCESS) {
2650 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2651 return;
2652 }
2653 sdvo_priv->max_saturation = data_value[0];
2654 sdvo_priv->cur_saturation = response;
2655 sdvo_priv->saturation_property =
2656 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2657 "saturation", 2);
2658 sdvo_priv->saturation_property->values[0] = 0;
2659 sdvo_priv->saturation_property->values[1] =
2660 data_value[0];
2661 drm_connector_attach_property(connector,
2662 sdvo_priv->saturation_property,
2663 sdvo_priv->cur_saturation);
2664 DRM_DEBUG_KMS("saturation: max %d, "
2665 "default %d, current %d\n",
2666 data_value[0], data_value[1], response);
2667 }
2668 if (sdvo_data.contrast) {
2669 intel_sdvo_write_cmd(intel_output,
2670 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
2671 status = intel_sdvo_read_response(intel_output,
2672 &data_value, 4);
2673 if (status != SDVO_CMD_STATUS_SUCCESS) {
2674 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2675 return;
2676 }
2677 intel_sdvo_write_cmd(intel_output,
2678 SDVO_CMD_GET_CONTRAST, NULL, 0);
2679 status = intel_sdvo_read_response(intel_output,
2680 &response, 2);
2681 if (status != SDVO_CMD_STATUS_SUCCESS) {
2682 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2683 return;
2684 }
2685 sdvo_priv->max_contrast = data_value[0];
2686 sdvo_priv->cur_contrast = response;
2687 sdvo_priv->contrast_property =
2688 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2689 "contrast", 2);
2690 sdvo_priv->contrast_property->values[0] = 0;
2691 sdvo_priv->contrast_property->values[1] = data_value[0];
2692 drm_connector_attach_property(connector,
2693 sdvo_priv->contrast_property,
2694 sdvo_priv->cur_contrast);
2695 DRM_DEBUG_KMS("contrast: max %d, "
2696 "default %d, current %d\n",
2697 data_value[0], data_value[1], response);
2698 }
2699 if (sdvo_data.hue) {
2700 intel_sdvo_write_cmd(intel_output,
2701 SDVO_CMD_GET_MAX_HUE, NULL, 0);
2702 status = intel_sdvo_read_response(intel_output,
2703 &data_value, 4);
2704 if (status != SDVO_CMD_STATUS_SUCCESS) {
2705 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2706 return;
2707 }
2708 intel_sdvo_write_cmd(intel_output,
2709 SDVO_CMD_GET_HUE, NULL, 0);
2710 status = intel_sdvo_read_response(intel_output,
2711 &response, 2);
2712 if (status != SDVO_CMD_STATUS_SUCCESS) {
2713 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2714 return;
2715 }
2716 sdvo_priv->max_hue = data_value[0];
2717 sdvo_priv->cur_hue = response;
2718 sdvo_priv->hue_property =
2719 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2720 "hue", 2);
2721 sdvo_priv->hue_property->values[0] = 0;
2722 sdvo_priv->hue_property->values[1] =
2723 data_value[0];
2724 drm_connector_attach_property(connector,
2725 sdvo_priv->hue_property,
2726 sdvo_priv->cur_hue);
2727 DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2728 data_value[0], data_value[1], response);
2729 }
2730 }
2731 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
2732 if (sdvo_data.brightness) {
2733 intel_sdvo_write_cmd(intel_output,
2734 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
2735 status = intel_sdvo_read_response(intel_output,
2736 &data_value, 4);
2737 if (status != SDVO_CMD_STATUS_SUCCESS) {
2738 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2739 return;
2740 }
2741 intel_sdvo_write_cmd(intel_output,
2742 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
2743 status = intel_sdvo_read_response(intel_output,
2744 &response, 2);
2745 if (status != SDVO_CMD_STATUS_SUCCESS) {
2746 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
2747 return;
2748 }
2749 sdvo_priv->max_brightness = data_value[0];
2750 sdvo_priv->cur_brightness = response;
2751 sdvo_priv->brightness_property =
2752 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2753 "brightness", 2);
2754 sdvo_priv->brightness_property->values[0] = 0;
2755 sdvo_priv->brightness_property->values[1] =
2756 data_value[0];
2757 drm_connector_attach_property(connector,
2758 sdvo_priv->brightness_property,
2759 sdvo_priv->cur_brightness);
2760 DRM_DEBUG_KMS("brightness: max %d, "
2761 "default %d, current %d\n",
2762 data_value[0], data_value[1], response);
2763 }
2764 }
2765 return;
2766 }
2767
2768 bool intel_sdvo_init(struct drm_device *dev, int output_device)
2769 {
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct drm_connector *connector;
2772 struct intel_output *intel_output;
2773 struct intel_sdvo_priv *sdvo_priv;
2774
2775 u8 ch[0x40];
2776 int i;
2777
2778 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2779 if (!intel_output) {
2780 return false;
2781 }
2782
2783 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
2784 sdvo_priv->output_device = output_device;
2785
2786 intel_output->dev_priv = sdvo_priv;
2787 intel_output->type = INTEL_OUTPUT_SDVO;
2788
2789 /* setup the DDC bus. */
2790 if (output_device == SDVOB)
2791 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
2792 else
2793 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
2794
2795 if (!intel_output->i2c_bus)
2796 goto err_inteloutput;
2797
2798 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
2799
2800 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2801 intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality;
2802
2803 /* Read the regs to test if we can talk to the device */
2804 for (i = 0; i < 0x40; i++) {
2805 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
2806 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2807 output_device == SDVOB ? 'B' : 'C');
2808 goto err_i2c;
2809 }
2810 }
2811
2812 /* setup the DDC bus. */
2813 if (output_device == SDVOB) {
2814 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
2815 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2816 "SDVOB/VGA DDC BUS");
2817 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
2818 } else {
2819 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
2820 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2821 "SDVOC/VGA DDC BUS");
2822 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
2823 }
2824
2825 if (intel_output->ddc_bus == NULL)
2826 goto err_i2c;
2827
2828 /* Wrap with our custom algo which switches to DDC mode */
2829 intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2830
2831 /* In default case sdvo lvds is false */
2832 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
2833
2834 if (intel_sdvo_output_setup(intel_output,
2835 sdvo_priv->caps.output_flags) != true) {
2836 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2837 output_device == SDVOB ? 'B' : 'C');
2838 goto err_i2c;
2839 }
2840
2841
2842 connector = &intel_output->base;
2843 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2844 connector->connector_type);
2845
2846 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2847 connector->interlace_allowed = 0;
2848 connector->doublescan_allowed = 0;
2849 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2850
2851 drm_encoder_init(dev, &intel_output->enc,
2852 &intel_sdvo_enc_funcs, intel_output->enc.encoder_type);
2853
2854 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
2855
2856 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
2857 if (sdvo_priv->is_tv)
2858 intel_sdvo_tv_create_property(connector);
2859
2860 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
2861 intel_sdvo_create_enhance_property(connector);
2862
2863 drm_sysfs_connector_add(connector);
2864
2865 intel_sdvo_select_ddc_bus(sdvo_priv);
2866
2867 /* Set the input timing to the screen. Assume always input 0. */
2868 intel_sdvo_set_target_input(intel_output, true, false);
2869
2870 intel_sdvo_get_input_pixel_clock_range(intel_output,
2871 &sdvo_priv->pixel_clock_min,
2872 &sdvo_priv->pixel_clock_max);
2873
2874
2875 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2876 "clock range %dMHz - %dMHz, "
2877 "input 1: %c, input 2: %c, "
2878 "output 1: %c, output 2: %c\n",
2879 SDVO_NAME(sdvo_priv),
2880 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2881 sdvo_priv->caps.device_rev_id,
2882 sdvo_priv->pixel_clock_min / 1000,
2883 sdvo_priv->pixel_clock_max / 1000,
2884 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2885 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2886 /* check currently supported outputs */
2887 sdvo_priv->caps.output_flags &
2888 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2889 sdvo_priv->caps.output_flags &
2890 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2891
2892 return true;
2893
2894 err_i2c:
2895 if (sdvo_priv->analog_ddc_bus != NULL)
2896 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2897 if (intel_output->ddc_bus != NULL)
2898 intel_i2c_destroy(intel_output->ddc_bus);
2899 if (intel_output->i2c_bus != NULL)
2900 intel_i2c_destroy(intel_output->i2c_bus);
2901 err_inteloutput:
2902 kfree(intel_output);
2903
2904 return false;
2905 }
kernel source for telekom puls (alcatel/mediatek)