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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 /*
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
39 */
40 struct pipe_control {
41 struct drm_i915_gem_object *obj;
42 volatile u32 *cpu_page;
43 u32 gtt_offset;
44 };
45
46 static inline int ring_space(struct intel_ring_buffer *ring)
47 {
48 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
49 if (space < 0)
50 space += ring->size;
51 return space;
52 }
53
54 static int
55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
57 u32 flush_domains)
58 {
59 u32 cmd;
60 int ret;
61
62 cmd = MI_FLUSH;
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
65
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
67 cmd |= MI_READ_FLUSH;
68
69 ret = intel_ring_begin(ring, 2);
70 if (ret)
71 return ret;
72
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
76
77 return 0;
78 }
79
80 static int
81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
83 u32 flush_domains)
84 {
85 struct drm_device *dev = ring->dev;
86 u32 cmd;
87 int ret;
88
89 /*
90 * read/write caches:
91 *
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
95 *
96 * read-only caches:
97 *
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
100 *
101 * I915_GEM_DOMAIN_COMMAND may not exist?
102 *
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
105 *
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
108 *
109 * TLBs:
110 *
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
115 */
116
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
121 cmd |= MI_EXE_FLUSH;
122
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
126
127 ret = intel_ring_begin(ring, 2);
128 if (ret)
129 return ret;
130
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
134
135 return 0;
136 }
137
138 /**
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 *
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146 * 0.
147 *
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 *
151 * And the workaround for these two requires this workaround first:
152 *
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
155 * flushes.
156 *
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159 * volume 2 part 1:
160 *
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
168 *
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
174 */
175 static int
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
177 {
178 struct pipe_control *pc = ring->private;
179 u32 scratch_addr = pc->gtt_offset + 128;
180 int ret;
181
182
183 ret = intel_ring_begin(ring, 6);
184 if (ret)
185 return ret;
186
187 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
189 PIPE_CONTROL_STALL_AT_SCOREBOARD);
190 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
191 intel_ring_emit(ring, 0); /* low dword */
192 intel_ring_emit(ring, 0); /* high dword */
193 intel_ring_emit(ring, MI_NOOP);
194 intel_ring_advance(ring);
195
196 ret = intel_ring_begin(ring, 6);
197 if (ret)
198 return ret;
199
200 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
202 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, MI_NOOP);
206 intel_ring_advance(ring);
207
208 return 0;
209 }
210
211 static int
212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
213 u32 invalidate_domains, u32 flush_domains)
214 {
215 u32 flags = 0;
216 struct pipe_control *pc = ring->private;
217 u32 scratch_addr = pc->gtt_offset + 128;
218 int ret;
219
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret = intel_emit_post_sync_nonzero_flush(ring);
222 if (ret)
223 return ret;
224
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
227 * impact.
228 */
229 if (flush_domains) {
230 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 /*
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
235 */
236 flags |= PIPE_CONTROL_CS_STALL;
237 }
238 if (invalidate_domains) {
239 flags |= PIPE_CONTROL_TLB_INVALIDATE;
240 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
244 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
245 /*
246 * TLB invalidate requires a post-sync write.
247 */
248 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
249 }
250
251 ret = intel_ring_begin(ring, 4);
252 if (ret)
253 return ret;
254
255 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring, flags);
257 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
258 intel_ring_emit(ring, 0);
259 intel_ring_advance(ring);
260
261 return 0;
262 }
263
264 static int
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
266 {
267 int ret;
268
269 ret = intel_ring_begin(ring, 4);
270 if (ret)
271 return ret;
272
273 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
275 PIPE_CONTROL_STALL_AT_SCOREBOARD);
276 intel_ring_emit(ring, 0);
277 intel_ring_emit(ring, 0);
278 intel_ring_advance(ring);
279
280 return 0;
281 }
282
283 static int
284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
285 u32 invalidate_domains, u32 flush_domains)
286 {
287 u32 flags = 0;
288 struct pipe_control *pc = ring->private;
289 u32 scratch_addr = pc->gtt_offset + 128;
290 int ret;
291
292 /*
293 * Ensure that any following seqno writes only happen when the render
294 * cache is indeed flushed.
295 *
296 * Workaround: 4th PIPE_CONTROL command (except the ones with only
297 * read-cache invalidate bits set) must have the CS_STALL bit set. We
298 * don't try to be clever and just set it unconditionally.
299 */
300 flags |= PIPE_CONTROL_CS_STALL;
301
302 /* Just flush everything. Experiments have shown that reducing the
303 * number of bits based on the write domains has little performance
304 * impact.
305 */
306 if (flush_domains) {
307 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
308 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
309 }
310 if (invalidate_domains) {
311 flags |= PIPE_CONTROL_TLB_INVALIDATE;
312 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
313 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
314 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
315 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
316 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
317 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
318 /*
319 * TLB invalidate requires a post-sync write.
320 */
321 flags |= PIPE_CONTROL_QW_WRITE;
322 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
323
324 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
325
326 /* Workaround: we must issue a pipe_control with CS-stall bit
327 * set before a pipe_control command that has the state cache
328 * invalidate bit set. */
329 gen7_render_ring_cs_stall_wa(ring);
330 }
331
332 ret = intel_ring_begin(ring, 4);
333 if (ret)
334 return ret;
335
336 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
337 intel_ring_emit(ring, flags);
338 intel_ring_emit(ring, scratch_addr);
339 intel_ring_emit(ring, 0);
340 intel_ring_advance(ring);
341
342 return 0;
343 }
344
345 static void ring_write_tail(struct intel_ring_buffer *ring,
346 u32 value)
347 {
348 drm_i915_private_t *dev_priv = ring->dev->dev_private;
349 I915_WRITE_TAIL(ring, value);
350 }
351
352 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
353 {
354 drm_i915_private_t *dev_priv = ring->dev->dev_private;
355 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
356 RING_ACTHD(ring->mmio_base) : ACTHD;
357
358 return I915_READ(acthd_reg);
359 }
360
361 static int init_ring_common(struct intel_ring_buffer *ring)
362 {
363 struct drm_device *dev = ring->dev;
364 drm_i915_private_t *dev_priv = dev->dev_private;
365 struct drm_i915_gem_object *obj = ring->obj;
366 int ret = 0;
367 u32 head;
368
369 if (HAS_FORCE_WAKE(dev))
370 gen6_gt_force_wake_get(dev_priv);
371
372 /* Stop the ring if it's running. */
373 I915_WRITE_CTL(ring, 0);
374 I915_WRITE_HEAD(ring, 0);
375 ring->write_tail(ring, 0);
376
377 head = I915_READ_HEAD(ring) & HEAD_ADDR;
378
379 /* G45 ring initialization fails to reset head to zero */
380 if (head != 0) {
381 DRM_DEBUG_KMS("%s head not reset to zero "
382 "ctl %08x head %08x tail %08x start %08x\n",
383 ring->name,
384 I915_READ_CTL(ring),
385 I915_READ_HEAD(ring),
386 I915_READ_TAIL(ring),
387 I915_READ_START(ring));
388
389 I915_WRITE_HEAD(ring, 0);
390
391 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
392 DRM_ERROR("failed to set %s head to zero "
393 "ctl %08x head %08x tail %08x start %08x\n",
394 ring->name,
395 I915_READ_CTL(ring),
396 I915_READ_HEAD(ring),
397 I915_READ_TAIL(ring),
398 I915_READ_START(ring));
399 }
400 }
401
402 /* Enforce ordering by reading HEAD register back */
403 I915_READ_HEAD(ring);
404
405 /* Initialize the ring. This must happen _after_ we've cleared the ring
406 * registers with the above sequence (the readback of the HEAD registers
407 * also enforces ordering), otherwise the hw might lose the new ring
408 * register values. */
409 I915_WRITE_START(ring, obj->gtt_offset);
410 I915_WRITE_CTL(ring,
411 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
412 | RING_VALID);
413
414 /* If the head is still not zero, the ring is dead */
415 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
416 I915_READ_START(ring) == obj->gtt_offset &&
417 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
418 DRM_ERROR("%s initialization failed "
419 "ctl %08x head %08x tail %08x start %08x\n",
420 ring->name,
421 I915_READ_CTL(ring),
422 I915_READ_HEAD(ring),
423 I915_READ_TAIL(ring),
424 I915_READ_START(ring));
425 ret = -EIO;
426 goto out;
427 }
428
429 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
430 i915_kernel_lost_context(ring->dev);
431 else {
432 ring->head = I915_READ_HEAD(ring);
433 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
434 ring->space = ring_space(ring);
435 ring->last_retired_head = -1;
436 }
437
438 out:
439 if (HAS_FORCE_WAKE(dev))
440 gen6_gt_force_wake_put(dev_priv);
441
442 return ret;
443 }
444
445 static int
446 init_pipe_control(struct intel_ring_buffer *ring)
447 {
448 struct pipe_control *pc;
449 struct drm_i915_gem_object *obj;
450 int ret;
451
452 if (ring->private)
453 return 0;
454
455 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
456 if (!pc)
457 return -ENOMEM;
458
459 obj = i915_gem_alloc_object(ring->dev, 4096);
460 if (obj == NULL) {
461 DRM_ERROR("Failed to allocate seqno page\n");
462 ret = -ENOMEM;
463 goto err;
464 }
465
466 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
467
468 ret = i915_gem_object_pin(obj, 4096, true, false);
469 if (ret)
470 goto err_unref;
471
472 pc->gtt_offset = obj->gtt_offset;
473 pc->cpu_page = kmap(sg_page(obj->pages->sgl));
474 if (pc->cpu_page == NULL)
475 goto err_unpin;
476
477 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
478 ring->name, pc->gtt_offset);
479
480 pc->obj = obj;
481 ring->private = pc;
482 return 0;
483
484 err_unpin:
485 i915_gem_object_unpin(obj);
486 err_unref:
487 drm_gem_object_unreference(&obj->base);
488 err:
489 kfree(pc);
490 return ret;
491 }
492
493 static void
494 cleanup_pipe_control(struct intel_ring_buffer *ring)
495 {
496 struct pipe_control *pc = ring->private;
497 struct drm_i915_gem_object *obj;
498
499 obj = pc->obj;
500
501 kunmap(sg_page(obj->pages->sgl));
502 i915_gem_object_unpin(obj);
503 drm_gem_object_unreference(&obj->base);
504
505 kfree(pc);
506 }
507
508 static int init_render_ring(struct intel_ring_buffer *ring)
509 {
510 struct drm_device *dev = ring->dev;
511 struct drm_i915_private *dev_priv = dev->dev_private;
512 int ret = init_ring_common(ring);
513
514 if (INTEL_INFO(dev)->gen > 3)
515 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
516
517 /* We need to disable the AsyncFlip performance optimisations in order
518 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
519 * programmed to '1' on all products.
520 */
521 if (INTEL_INFO(dev)->gen >= 6)
522 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
523
524 /* Required for the hardware to program scanline values for waiting */
525 if (INTEL_INFO(dev)->gen == 6)
526 I915_WRITE(GFX_MODE,
527 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
528
529 if (IS_GEN7(dev))
530 I915_WRITE(GFX_MODE_GEN7,
531 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
532 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
533
534 if (INTEL_INFO(dev)->gen >= 5) {
535 ret = init_pipe_control(ring);
536 if (ret)
537 return ret;
538 }
539
540 if (IS_GEN6(dev)) {
541 /* From the Sandybridge PRM, volume 1 part 3, page 24:
542 * "If this bit is set, STCunit will have LRA as replacement
543 * policy. [...] This bit must be reset. LRA replacement
544 * policy is not supported."
545 */
546 I915_WRITE(CACHE_MODE_0,
547 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
548
549 /* This is not explicitly set for GEN6, so read the register.
550 * see intel_ring_mi_set_context() for why we care.
551 * TODO: consider explicitly setting the bit for GEN5
552 */
553 ring->itlb_before_ctx_switch =
554 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
555 }
556
557 if (INTEL_INFO(dev)->gen >= 6)
558 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
559
560 if (HAS_L3_GPU_CACHE(dev))
561 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
562
563 return ret;
564 }
565
566 static void render_ring_cleanup(struct intel_ring_buffer *ring)
567 {
568 struct drm_device *dev = ring->dev;
569
570 if (!ring->private)
571 return;
572
573 if (HAS_BROKEN_CS_TLB(dev))
574 drm_gem_object_unreference(to_gem_object(ring->private));
575
576 if (INTEL_INFO(dev)->gen >= 5)
577 cleanup_pipe_control(ring);
578
579 ring->private = NULL;
580 }
581
582 static void
583 update_mboxes(struct intel_ring_buffer *ring,
584 u32 mmio_offset)
585 {
586 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
587 intel_ring_emit(ring, mmio_offset);
588 intel_ring_emit(ring, ring->outstanding_lazy_request);
589 }
590
591 /**
592 * gen6_add_request - Update the semaphore mailbox registers
593 *
594 * @ring - ring that is adding a request
595 * @seqno - return seqno stuck into the ring
596 *
597 * Update the mailbox registers in the *other* rings with the current seqno.
598 * This acts like a signal in the canonical semaphore.
599 */
600 static int
601 gen6_add_request(struct intel_ring_buffer *ring)
602 {
603 u32 mbox1_reg;
604 u32 mbox2_reg;
605 int ret;
606
607 ret = intel_ring_begin(ring, 10);
608 if (ret)
609 return ret;
610
611 mbox1_reg = ring->signal_mbox[0];
612 mbox2_reg = ring->signal_mbox[1];
613
614 update_mboxes(ring, mbox1_reg);
615 update_mboxes(ring, mbox2_reg);
616 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
617 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
618 intel_ring_emit(ring, ring->outstanding_lazy_request);
619 intel_ring_emit(ring, MI_USER_INTERRUPT);
620 intel_ring_advance(ring);
621
622 return 0;
623 }
624
625 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
626 u32 seqno)
627 {
628 struct drm_i915_private *dev_priv = dev->dev_private;
629 return dev_priv->last_seqno < seqno;
630 }
631
632 /**
633 * intel_ring_sync - sync the waiter to the signaller on seqno
634 *
635 * @waiter - ring that is waiting
636 * @signaller - ring which has, or will signal
637 * @seqno - seqno which the waiter will block on
638 */
639 static int
640 gen6_ring_sync(struct intel_ring_buffer *waiter,
641 struct intel_ring_buffer *signaller,
642 u32 seqno)
643 {
644 int ret;
645 u32 dw1 = MI_SEMAPHORE_MBOX |
646 MI_SEMAPHORE_COMPARE |
647 MI_SEMAPHORE_REGISTER;
648
649 /* Throughout all of the GEM code, seqno passed implies our current
650 * seqno is >= the last seqno executed. However for hardware the
651 * comparison is strictly greater than.
652 */
653 seqno -= 1;
654
655 WARN_ON(signaller->semaphore_register[waiter->id] ==
656 MI_SEMAPHORE_SYNC_INVALID);
657
658 ret = intel_ring_begin(waiter, 4);
659 if (ret)
660 return ret;
661
662 /* If seqno wrap happened, omit the wait with no-ops */
663 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
664 intel_ring_emit(waiter,
665 dw1 |
666 signaller->semaphore_register[waiter->id]);
667 intel_ring_emit(waiter, seqno);
668 intel_ring_emit(waiter, 0);
669 intel_ring_emit(waiter, MI_NOOP);
670 } else {
671 intel_ring_emit(waiter, MI_NOOP);
672 intel_ring_emit(waiter, MI_NOOP);
673 intel_ring_emit(waiter, MI_NOOP);
674 intel_ring_emit(waiter, MI_NOOP);
675 }
676 intel_ring_advance(waiter);
677
678 return 0;
679 }
680
681 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
682 do { \
683 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
684 PIPE_CONTROL_DEPTH_STALL); \
685 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
686 intel_ring_emit(ring__, 0); \
687 intel_ring_emit(ring__, 0); \
688 } while (0)
689
690 static int
691 pc_render_add_request(struct intel_ring_buffer *ring)
692 {
693 struct pipe_control *pc = ring->private;
694 u32 scratch_addr = pc->gtt_offset + 128;
695 int ret;
696
697 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
698 * incoherent with writes to memory, i.e. completely fubar,
699 * so we need to use PIPE_NOTIFY instead.
700 *
701 * However, we also need to workaround the qword write
702 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
703 * memory before requesting an interrupt.
704 */
705 ret = intel_ring_begin(ring, 32);
706 if (ret)
707 return ret;
708
709 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
710 PIPE_CONTROL_WRITE_FLUSH |
711 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
712 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
713 intel_ring_emit(ring, ring->outstanding_lazy_request);
714 intel_ring_emit(ring, 0);
715 PIPE_CONTROL_FLUSH(ring, scratch_addr);
716 scratch_addr += 128; /* write to separate cachelines */
717 PIPE_CONTROL_FLUSH(ring, scratch_addr);
718 scratch_addr += 128;
719 PIPE_CONTROL_FLUSH(ring, scratch_addr);
720 scratch_addr += 128;
721 PIPE_CONTROL_FLUSH(ring, scratch_addr);
722 scratch_addr += 128;
723 PIPE_CONTROL_FLUSH(ring, scratch_addr);
724 scratch_addr += 128;
725 PIPE_CONTROL_FLUSH(ring, scratch_addr);
726
727 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
728 PIPE_CONTROL_WRITE_FLUSH |
729 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
730 PIPE_CONTROL_NOTIFY);
731 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
732 intel_ring_emit(ring, ring->outstanding_lazy_request);
733 intel_ring_emit(ring, 0);
734 intel_ring_advance(ring);
735
736 return 0;
737 }
738
739 static u32
740 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
741 {
742 /* Workaround to force correct ordering between irq and seqno writes on
743 * ivb (and maybe also on snb) by reading from a CS register (like
744 * ACTHD) before reading the status page. */
745 if (!lazy_coherency)
746 intel_ring_get_active_head(ring);
747 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
748 }
749
750 static u32
751 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
752 {
753 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
754 }
755
756 static void
757 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
758 {
759 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
760 }
761
762 static u32
763 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
764 {
765 struct pipe_control *pc = ring->private;
766 return pc->cpu_page[0];
767 }
768
769 static void
770 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
771 {
772 struct pipe_control *pc = ring->private;
773 pc->cpu_page[0] = seqno;
774 }
775
776 static bool
777 gen5_ring_get_irq(struct intel_ring_buffer *ring)
778 {
779 struct drm_device *dev = ring->dev;
780 drm_i915_private_t *dev_priv = dev->dev_private;
781 unsigned long flags;
782
783 if (!dev->irq_enabled)
784 return false;
785
786 spin_lock_irqsave(&dev_priv->irq_lock, flags);
787 if (ring->irq_refcount++ == 0) {
788 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
789 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
790 POSTING_READ(GTIMR);
791 }
792 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
793
794 return true;
795 }
796
797 static void
798 gen5_ring_put_irq(struct intel_ring_buffer *ring)
799 {
800 struct drm_device *dev = ring->dev;
801 drm_i915_private_t *dev_priv = dev->dev_private;
802 unsigned long flags;
803
804 spin_lock_irqsave(&dev_priv->irq_lock, flags);
805 if (--ring->irq_refcount == 0) {
806 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
807 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
808 POSTING_READ(GTIMR);
809 }
810 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
811 }
812
813 static bool
814 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
815 {
816 struct drm_device *dev = ring->dev;
817 drm_i915_private_t *dev_priv = dev->dev_private;
818 unsigned long flags;
819
820 if (!dev->irq_enabled)
821 return false;
822
823 spin_lock_irqsave(&dev_priv->irq_lock, flags);
824 if (ring->irq_refcount++ == 0) {
825 dev_priv->irq_mask &= ~ring->irq_enable_mask;
826 I915_WRITE(IMR, dev_priv->irq_mask);
827 POSTING_READ(IMR);
828 }
829 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
830
831 return true;
832 }
833
834 static void
835 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
836 {
837 struct drm_device *dev = ring->dev;
838 drm_i915_private_t *dev_priv = dev->dev_private;
839 unsigned long flags;
840
841 spin_lock_irqsave(&dev_priv->irq_lock, flags);
842 if (--ring->irq_refcount == 0) {
843 dev_priv->irq_mask |= ring->irq_enable_mask;
844 I915_WRITE(IMR, dev_priv->irq_mask);
845 POSTING_READ(IMR);
846 }
847 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
848 }
849
850 static bool
851 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
852 {
853 struct drm_device *dev = ring->dev;
854 drm_i915_private_t *dev_priv = dev->dev_private;
855 unsigned long flags;
856
857 if (!dev->irq_enabled)
858 return false;
859
860 spin_lock_irqsave(&dev_priv->irq_lock, flags);
861 if (ring->irq_refcount++ == 0) {
862 dev_priv->irq_mask &= ~ring->irq_enable_mask;
863 I915_WRITE16(IMR, dev_priv->irq_mask);
864 POSTING_READ16(IMR);
865 }
866 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
867
868 return true;
869 }
870
871 static void
872 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
873 {
874 struct drm_device *dev = ring->dev;
875 drm_i915_private_t *dev_priv = dev->dev_private;
876 unsigned long flags;
877
878 spin_lock_irqsave(&dev_priv->irq_lock, flags);
879 if (--ring->irq_refcount == 0) {
880 dev_priv->irq_mask |= ring->irq_enable_mask;
881 I915_WRITE16(IMR, dev_priv->irq_mask);
882 POSTING_READ16(IMR);
883 }
884 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
885 }
886
887 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
888 {
889 struct drm_device *dev = ring->dev;
890 drm_i915_private_t *dev_priv = ring->dev->dev_private;
891 u32 mmio = 0;
892
893 /* The ring status page addresses are no longer next to the rest of
894 * the ring registers as of gen7.
895 */
896 if (IS_GEN7(dev)) {
897 switch (ring->id) {
898 case RCS:
899 mmio = RENDER_HWS_PGA_GEN7;
900 break;
901 case BCS:
902 mmio = BLT_HWS_PGA_GEN7;
903 break;
904 case VCS:
905 mmio = BSD_HWS_PGA_GEN7;
906 break;
907 }
908 } else if (IS_GEN6(ring->dev)) {
909 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
910 } else {
911 mmio = RING_HWS_PGA(ring->mmio_base);
912 }
913
914 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
915 POSTING_READ(mmio);
916
917 /* Flush the TLB for this page */
918 if (INTEL_INFO(dev)->gen >= 6) {
919 u32 reg = RING_INSTPM(ring->mmio_base);
920 I915_WRITE(reg,
921 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
922 INSTPM_SYNC_FLUSH));
923 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
924 1000))
925 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
926 ring->name);
927 }
928 }
929
930 static int
931 bsd_ring_flush(struct intel_ring_buffer *ring,
932 u32 invalidate_domains,
933 u32 flush_domains)
934 {
935 int ret;
936
937 ret = intel_ring_begin(ring, 2);
938 if (ret)
939 return ret;
940
941 intel_ring_emit(ring, MI_FLUSH);
942 intel_ring_emit(ring, MI_NOOP);
943 intel_ring_advance(ring);
944 return 0;
945 }
946
947 static int
948 i9xx_add_request(struct intel_ring_buffer *ring)
949 {
950 int ret;
951
952 ret = intel_ring_begin(ring, 4);
953 if (ret)
954 return ret;
955
956 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
957 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
958 intel_ring_emit(ring, ring->outstanding_lazy_request);
959 intel_ring_emit(ring, MI_USER_INTERRUPT);
960 intel_ring_advance(ring);
961
962 return 0;
963 }
964
965 static bool
966 gen6_ring_get_irq(struct intel_ring_buffer *ring)
967 {
968 struct drm_device *dev = ring->dev;
969 drm_i915_private_t *dev_priv = dev->dev_private;
970 unsigned long flags;
971
972 if (!dev->irq_enabled)
973 return false;
974
975 /* It looks like we need to prevent the gt from suspending while waiting
976 * for an notifiy irq, otherwise irqs seem to get lost on at least the
977 * blt/bsd rings on ivb. */
978 gen6_gt_force_wake_get(dev_priv);
979
980 spin_lock_irqsave(&dev_priv->irq_lock, flags);
981 if (ring->irq_refcount++ == 0) {
982 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
983 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
984 GEN6_RENDER_L3_PARITY_ERROR));
985 else
986 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
987 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
988 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
989 POSTING_READ(GTIMR);
990 }
991 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
992
993 return true;
994 }
995
996 static void
997 gen6_ring_put_irq(struct intel_ring_buffer *ring)
998 {
999 struct drm_device *dev = ring->dev;
1000 drm_i915_private_t *dev_priv = dev->dev_private;
1001 unsigned long flags;
1002
1003 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1004 if (--ring->irq_refcount == 0) {
1005 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1006 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
1007 else
1008 I915_WRITE_IMR(ring, ~0);
1009 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
1010 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1011 POSTING_READ(GTIMR);
1012 }
1013 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1014
1015 gen6_gt_force_wake_put(dev_priv);
1016 }
1017
1018 static int
1019 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1020 u32 offset, u32 length,
1021 unsigned flags)
1022 {
1023 int ret;
1024
1025 ret = intel_ring_begin(ring, 2);
1026 if (ret)
1027 return ret;
1028
1029 intel_ring_emit(ring,
1030 MI_BATCH_BUFFER_START |
1031 MI_BATCH_GTT |
1032 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1033 intel_ring_emit(ring, offset);
1034 intel_ring_advance(ring);
1035
1036 return 0;
1037 }
1038
1039 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1040 #define I830_BATCH_LIMIT (256*1024)
1041 static int
1042 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1043 u32 offset, u32 len,
1044 unsigned flags)
1045 {
1046 int ret;
1047
1048 if (flags & I915_DISPATCH_PINNED) {
1049 ret = intel_ring_begin(ring, 4);
1050 if (ret)
1051 return ret;
1052
1053 intel_ring_emit(ring, MI_BATCH_BUFFER);
1054 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1055 intel_ring_emit(ring, offset + len - 8);
1056 intel_ring_emit(ring, MI_NOOP);
1057 intel_ring_advance(ring);
1058 } else {
1059 struct drm_i915_gem_object *obj = ring->private;
1060 u32 cs_offset = obj->gtt_offset;
1061
1062 if (len > I830_BATCH_LIMIT)
1063 return -ENOSPC;
1064
1065 ret = intel_ring_begin(ring, 9+3);
1066 if (ret)
1067 return ret;
1068 /* Blit the batch (which has now all relocs applied) to the stable batch
1069 * scratch bo area (so that the CS never stumbles over its tlb
1070 * invalidation bug) ... */
1071 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1072 XY_SRC_COPY_BLT_WRITE_ALPHA |
1073 XY_SRC_COPY_BLT_WRITE_RGB);
1074 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1075 intel_ring_emit(ring, 0);
1076 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1077 intel_ring_emit(ring, cs_offset);
1078 intel_ring_emit(ring, 0);
1079 intel_ring_emit(ring, 4096);
1080 intel_ring_emit(ring, offset);
1081 intel_ring_emit(ring, MI_FLUSH);
1082
1083 /* ... and execute it. */
1084 intel_ring_emit(ring, MI_BATCH_BUFFER);
1085 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1086 intel_ring_emit(ring, cs_offset + len - 8);
1087 intel_ring_advance(ring);
1088 }
1089
1090 return 0;
1091 }
1092
1093 static int
1094 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1095 u32 offset, u32 len,
1096 unsigned flags)
1097 {
1098 int ret;
1099
1100 ret = intel_ring_begin(ring, 2);
1101 if (ret)
1102 return ret;
1103
1104 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1105 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1106 intel_ring_advance(ring);
1107
1108 return 0;
1109 }
1110
1111 static void cleanup_status_page(struct intel_ring_buffer *ring)
1112 {
1113 struct drm_i915_gem_object *obj;
1114
1115 obj = ring->status_page.obj;
1116 if (obj == NULL)
1117 return;
1118
1119 kunmap(sg_page(obj->pages->sgl));
1120 i915_gem_object_unpin(obj);
1121 drm_gem_object_unreference(&obj->base);
1122 ring->status_page.obj = NULL;
1123 }
1124
1125 static int init_status_page(struct intel_ring_buffer *ring)
1126 {
1127 struct drm_device *dev = ring->dev;
1128 struct drm_i915_gem_object *obj;
1129 int ret;
1130
1131 obj = i915_gem_alloc_object(dev, 4096);
1132 if (obj == NULL) {
1133 DRM_ERROR("Failed to allocate status page\n");
1134 ret = -ENOMEM;
1135 goto err;
1136 }
1137
1138 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1139
1140 ret = i915_gem_object_pin(obj, 4096, true, false);
1141 if (ret != 0) {
1142 goto err_unref;
1143 }
1144
1145 ring->status_page.gfx_addr = obj->gtt_offset;
1146 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1147 if (ring->status_page.page_addr == NULL) {
1148 ret = -ENOMEM;
1149 goto err_unpin;
1150 }
1151 ring->status_page.obj = obj;
1152 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1153
1154 intel_ring_setup_status_page(ring);
1155 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1156 ring->name, ring->status_page.gfx_addr);
1157
1158 return 0;
1159
1160 err_unpin:
1161 i915_gem_object_unpin(obj);
1162 err_unref:
1163 drm_gem_object_unreference(&obj->base);
1164 err:
1165 return ret;
1166 }
1167
1168 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1169 {
1170 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1171 u32 addr;
1172
1173 if (!dev_priv->status_page_dmah) {
1174 dev_priv->status_page_dmah =
1175 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1176 if (!dev_priv->status_page_dmah)
1177 return -ENOMEM;
1178 }
1179
1180 addr = dev_priv->status_page_dmah->busaddr;
1181 if (INTEL_INFO(ring->dev)->gen >= 4)
1182 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1183 I915_WRITE(HWS_PGA, addr);
1184
1185 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1186 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1187
1188 return 0;
1189 }
1190
1191 static int intel_init_ring_buffer(struct drm_device *dev,
1192 struct intel_ring_buffer *ring)
1193 {
1194 struct drm_i915_gem_object *obj;
1195 struct drm_i915_private *dev_priv = dev->dev_private;
1196 int ret;
1197
1198 ring->dev = dev;
1199 INIT_LIST_HEAD(&ring->active_list);
1200 INIT_LIST_HEAD(&ring->request_list);
1201 ring->size = 32 * PAGE_SIZE;
1202 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1203
1204 init_waitqueue_head(&ring->irq_queue);
1205
1206 if (I915_NEED_GFX_HWS(dev)) {
1207 ret = init_status_page(ring);
1208 if (ret)
1209 return ret;
1210 } else {
1211 BUG_ON(ring->id != RCS);
1212 ret = init_phys_hws_pga(ring);
1213 if (ret)
1214 return ret;
1215 }
1216
1217 obj = NULL;
1218 if (!HAS_LLC(dev))
1219 obj = i915_gem_object_create_stolen(dev, ring->size);
1220 if (obj == NULL)
1221 obj = i915_gem_alloc_object(dev, ring->size);
1222 if (obj == NULL) {
1223 DRM_ERROR("Failed to allocate ringbuffer\n");
1224 ret = -ENOMEM;
1225 goto err_hws;
1226 }
1227
1228 ring->obj = obj;
1229
1230 ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1231 if (ret)
1232 goto err_unref;
1233
1234 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1235 if (ret)
1236 goto err_unpin;
1237
1238 ring->virtual_start =
1239 ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
1240 ring->size);
1241 if (ring->virtual_start == NULL) {
1242 DRM_ERROR("Failed to map ringbuffer.\n");
1243 ret = -EINVAL;
1244 goto err_unpin;
1245 }
1246
1247 ret = ring->init(ring);
1248 if (ret)
1249 goto err_unmap;
1250
1251 /* Workaround an erratum on the i830 which causes a hang if
1252 * the TAIL pointer points to within the last 2 cachelines
1253 * of the buffer.
1254 */
1255 ring->effective_size = ring->size;
1256 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1257 ring->effective_size -= 128;
1258
1259 return 0;
1260
1261 err_unmap:
1262 iounmap(ring->virtual_start);
1263 err_unpin:
1264 i915_gem_object_unpin(obj);
1265 err_unref:
1266 drm_gem_object_unreference(&obj->base);
1267 ring->obj = NULL;
1268 err_hws:
1269 cleanup_status_page(ring);
1270 return ret;
1271 }
1272
1273 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1274 {
1275 struct drm_i915_private *dev_priv;
1276 int ret;
1277
1278 if (ring->obj == NULL)
1279 return;
1280
1281 /* Disable the ring buffer. The ring must be idle at this point */
1282 dev_priv = ring->dev->dev_private;
1283 ret = intel_ring_idle(ring);
1284 if (ret)
1285 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1286 ring->name, ret);
1287
1288 I915_WRITE_CTL(ring, 0);
1289
1290 iounmap(ring->virtual_start);
1291
1292 i915_gem_object_unpin(ring->obj);
1293 drm_gem_object_unreference(&ring->obj->base);
1294 ring->obj = NULL;
1295
1296 if (ring->cleanup)
1297 ring->cleanup(ring);
1298
1299 cleanup_status_page(ring);
1300 }
1301
1302 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1303 {
1304 int ret;
1305
1306 ret = i915_wait_seqno(ring, seqno);
1307 if (!ret)
1308 i915_gem_retire_requests_ring(ring);
1309
1310 return ret;
1311 }
1312
1313 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1314 {
1315 struct drm_i915_gem_request *request;
1316 u32 seqno = 0;
1317 int ret;
1318
1319 i915_gem_retire_requests_ring(ring);
1320
1321 if (ring->last_retired_head != -1) {
1322 ring->head = ring->last_retired_head;
1323 ring->last_retired_head = -1;
1324 ring->space = ring_space(ring);
1325 if (ring->space >= n)
1326 return 0;
1327 }
1328
1329 list_for_each_entry(request, &ring->request_list, list) {
1330 int space;
1331
1332 if (request->tail == -1)
1333 continue;
1334
1335 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1336 if (space < 0)
1337 space += ring->size;
1338 if (space >= n) {
1339 seqno = request->seqno;
1340 break;
1341 }
1342
1343 /* Consume this request in case we need more space than
1344 * is available and so need to prevent a race between
1345 * updating last_retired_head and direct reads of
1346 * I915_RING_HEAD. It also provides a nice sanity check.
1347 */
1348 request->tail = -1;
1349 }
1350
1351 if (seqno == 0)
1352 return -ENOSPC;
1353
1354 ret = intel_ring_wait_seqno(ring, seqno);
1355 if (ret)
1356 return ret;
1357
1358 if (WARN_ON(ring->last_retired_head == -1))
1359 return -ENOSPC;
1360
1361 ring->head = ring->last_retired_head;
1362 ring->last_retired_head = -1;
1363 ring->space = ring_space(ring);
1364 if (WARN_ON(ring->space < n))
1365 return -ENOSPC;
1366
1367 return 0;
1368 }
1369
1370 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1371 {
1372 struct drm_device *dev = ring->dev;
1373 struct drm_i915_private *dev_priv = dev->dev_private;
1374 unsigned long end;
1375 int ret;
1376
1377 ret = intel_ring_wait_request(ring, n);
1378 if (ret != -ENOSPC)
1379 return ret;
1380
1381 trace_i915_ring_wait_begin(ring);
1382 /* With GEM the hangcheck timer should kick us out of the loop,
1383 * leaving it early runs the risk of corrupting GEM state (due
1384 * to running on almost untested codepaths). But on resume
1385 * timers don't work yet, so prevent a complete hang in that
1386 * case by choosing an insanely large timeout. */
1387 end = jiffies + 60 * HZ;
1388
1389 do {
1390 ring->head = I915_READ_HEAD(ring);
1391 ring->space = ring_space(ring);
1392 if (ring->space >= n) {
1393 trace_i915_ring_wait_end(ring);
1394 return 0;
1395 }
1396
1397 if (dev->primary->master) {
1398 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1399 if (master_priv->sarea_priv)
1400 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1401 }
1402
1403 msleep(1);
1404
1405 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1406 dev_priv->mm.interruptible);
1407 if (ret)
1408 return ret;
1409 } while (!time_after(jiffies, end));
1410 trace_i915_ring_wait_end(ring);
1411 return -EBUSY;
1412 }
1413
1414 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1415 {
1416 uint32_t __iomem *virt;
1417 int rem = ring->size - ring->tail;
1418
1419 if (ring->space < rem) {
1420 int ret = ring_wait_for_space(ring, rem);
1421 if (ret)
1422 return ret;
1423 }
1424
1425 virt = ring->virtual_start + ring->tail;
1426 rem /= 4;
1427 while (rem--)
1428 iowrite32(MI_NOOP, virt++);
1429
1430 ring->tail = 0;
1431 ring->space = ring_space(ring);
1432
1433 return 0;
1434 }
1435
1436 int intel_ring_idle(struct intel_ring_buffer *ring)
1437 {
1438 u32 seqno;
1439 int ret;
1440
1441 /* We need to add any requests required to flush the objects and ring */
1442 if (ring->outstanding_lazy_request) {
1443 ret = i915_add_request(ring, NULL, NULL);
1444 if (ret)
1445 return ret;
1446 }
1447
1448 /* Wait upon the last request to be completed */
1449 if (list_empty(&ring->request_list))
1450 return 0;
1451
1452 seqno = list_entry(ring->request_list.prev,
1453 struct drm_i915_gem_request,
1454 list)->seqno;
1455
1456 return i915_wait_seqno(ring, seqno);
1457 }
1458
1459 static int
1460 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1461 {
1462 if (ring->outstanding_lazy_request)
1463 return 0;
1464
1465 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1466 }
1467
1468 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1469 int bytes)
1470 {
1471 int ret;
1472
1473 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1474 ret = intel_wrap_ring_buffer(ring);
1475 if (unlikely(ret))
1476 return ret;
1477 }
1478
1479 if (unlikely(ring->space < bytes)) {
1480 ret = ring_wait_for_space(ring, bytes);
1481 if (unlikely(ret))
1482 return ret;
1483 }
1484
1485 return 0;
1486 }
1487
1488 int intel_ring_begin(struct intel_ring_buffer *ring,
1489 int num_dwords)
1490 {
1491 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1492 int ret;
1493
1494 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1495 dev_priv->mm.interruptible);
1496 if (ret)
1497 return ret;
1498
1499 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1500 if (ret)
1501 return ret;
1502
1503 /* Preallocate the olr before touching the ring */
1504 ret = intel_ring_alloc_seqno(ring);
1505 if (ret)
1506 return ret;
1507
1508 ring->space -= num_dwords * sizeof(uint32_t);
1509 return 0;
1510 }
1511
1512 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1513 {
1514 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1515
1516 BUG_ON(ring->outstanding_lazy_request);
1517
1518 if (INTEL_INFO(ring->dev)->gen >= 6) {
1519 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1520 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1521 }
1522
1523 ring->set_seqno(ring, seqno);
1524 }
1525
1526 void intel_ring_advance(struct intel_ring_buffer *ring)
1527 {
1528 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1529
1530 ring->tail &= ring->size - 1;
1531 if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1532 return;
1533 ring->write_tail(ring, ring->tail);
1534 }
1535
1536
1537 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1538 u32 value)
1539 {
1540 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1541
1542 /* Every tail move must follow the sequence below */
1543
1544 /* Disable notification that the ring is IDLE. The GT
1545 * will then assume that it is busy and bring it out of rc6.
1546 */
1547 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1548 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1549
1550 /* Clear the context id. Here be magic! */
1551 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1552
1553 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1554 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1555 GEN6_BSD_SLEEP_INDICATOR) == 0,
1556 50))
1557 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1558
1559 /* Now that the ring is fully powered up, update the tail */
1560 I915_WRITE_TAIL(ring, value);
1561 POSTING_READ(RING_TAIL(ring->mmio_base));
1562
1563 /* Let the ring send IDLE messages to the GT again,
1564 * and so let it sleep to conserve power when idle.
1565 */
1566 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1567 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1568 }
1569
1570 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1571 u32 invalidate, u32 flush)
1572 {
1573 uint32_t cmd;
1574 int ret;
1575
1576 ret = intel_ring_begin(ring, 4);
1577 if (ret)
1578 return ret;
1579
1580 cmd = MI_FLUSH_DW;
1581 /*
1582 * Bspec vol 1c.5 - video engine command streamer:
1583 * "If ENABLED, all TLBs will be invalidated once the flush
1584 * operation is complete. This bit is only valid when the
1585 * Post-Sync Operation field is a value of 1h or 3h."
1586 */
1587 if (invalidate & I915_GEM_GPU_DOMAINS)
1588 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1589 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1590 intel_ring_emit(ring, cmd);
1591 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1592 intel_ring_emit(ring, 0);
1593 intel_ring_emit(ring, MI_NOOP);
1594 intel_ring_advance(ring);
1595 return 0;
1596 }
1597
1598 static int
1599 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1600 u32 offset, u32 len,
1601 unsigned flags)
1602 {
1603 int ret;
1604
1605 ret = intel_ring_begin(ring, 2);
1606 if (ret)
1607 return ret;
1608
1609 intel_ring_emit(ring,
1610 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1611 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1612 /* bit0-7 is the length on GEN6+ */
1613 intel_ring_emit(ring, offset);
1614 intel_ring_advance(ring);
1615
1616 return 0;
1617 }
1618
1619 static int
1620 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1621 u32 offset, u32 len,
1622 unsigned flags)
1623 {
1624 int ret;
1625
1626 ret = intel_ring_begin(ring, 2);
1627 if (ret)
1628 return ret;
1629
1630 intel_ring_emit(ring,
1631 MI_BATCH_BUFFER_START |
1632 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1633 /* bit0-7 is the length on GEN6+ */
1634 intel_ring_emit(ring, offset);
1635 intel_ring_advance(ring);
1636
1637 return 0;
1638 }
1639
1640 /* Blitter support (SandyBridge+) */
1641
1642 static int blt_ring_flush(struct intel_ring_buffer *ring,
1643 u32 invalidate, u32 flush)
1644 {
1645 uint32_t cmd;
1646 int ret;
1647
1648 ret = intel_ring_begin(ring, 4);
1649 if (ret)
1650 return ret;
1651
1652 cmd = MI_FLUSH_DW;
1653 /*
1654 * Bspec vol 1c.3 - blitter engine command streamer:
1655 * "If ENABLED, all TLBs will be invalidated once the flush
1656 * operation is complete. This bit is only valid when the
1657 * Post-Sync Operation field is a value of 1h or 3h."
1658 */
1659 if (invalidate & I915_GEM_DOMAIN_RENDER)
1660 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1661 MI_FLUSH_DW_OP_STOREDW;
1662 intel_ring_emit(ring, cmd);
1663 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1664 intel_ring_emit(ring, 0);
1665 intel_ring_emit(ring, MI_NOOP);
1666 intel_ring_advance(ring);
1667 return 0;
1668 }
1669
1670 int intel_init_render_ring_buffer(struct drm_device *dev)
1671 {
1672 drm_i915_private_t *dev_priv = dev->dev_private;
1673 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1674
1675 ring->name = "render ring";
1676 ring->id = RCS;
1677 ring->mmio_base = RENDER_RING_BASE;
1678
1679 if (INTEL_INFO(dev)->gen >= 6) {
1680 ring->add_request = gen6_add_request;
1681 ring->flush = gen7_render_ring_flush;
1682 if (INTEL_INFO(dev)->gen == 6)
1683 ring->flush = gen6_render_ring_flush;
1684 ring->irq_get = gen6_ring_get_irq;
1685 ring->irq_put = gen6_ring_put_irq;
1686 ring->irq_enable_mask = GT_USER_INTERRUPT;
1687 ring->get_seqno = gen6_ring_get_seqno;
1688 ring->set_seqno = ring_set_seqno;
1689 ring->sync_to = gen6_ring_sync;
1690 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1691 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1692 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1693 ring->signal_mbox[0] = GEN6_VRSYNC;
1694 ring->signal_mbox[1] = GEN6_BRSYNC;
1695 } else if (IS_GEN5(dev)) {
1696 ring->add_request = pc_render_add_request;
1697 ring->flush = gen4_render_ring_flush;
1698 ring->get_seqno = pc_render_get_seqno;
1699 ring->set_seqno = pc_render_set_seqno;
1700 ring->irq_get = gen5_ring_get_irq;
1701 ring->irq_put = gen5_ring_put_irq;
1702 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1703 } else {
1704 ring->add_request = i9xx_add_request;
1705 if (INTEL_INFO(dev)->gen < 4)
1706 ring->flush = gen2_render_ring_flush;
1707 else
1708 ring->flush = gen4_render_ring_flush;
1709 ring->get_seqno = ring_get_seqno;
1710 ring->set_seqno = ring_set_seqno;
1711 if (IS_GEN2(dev)) {
1712 ring->irq_get = i8xx_ring_get_irq;
1713 ring->irq_put = i8xx_ring_put_irq;
1714 } else {
1715 ring->irq_get = i9xx_ring_get_irq;
1716 ring->irq_put = i9xx_ring_put_irq;
1717 }
1718 ring->irq_enable_mask = I915_USER_INTERRUPT;
1719 }
1720 ring->write_tail = ring_write_tail;
1721 if (IS_HASWELL(dev))
1722 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1723 else if (INTEL_INFO(dev)->gen >= 6)
1724 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1725 else if (INTEL_INFO(dev)->gen >= 4)
1726 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1727 else if (IS_I830(dev) || IS_845G(dev))
1728 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1729 else
1730 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1731 ring->init = init_render_ring;
1732 ring->cleanup = render_ring_cleanup;
1733
1734 /* Workaround batchbuffer to combat CS tlb bug. */
1735 if (HAS_BROKEN_CS_TLB(dev)) {
1736 struct drm_i915_gem_object *obj;
1737 int ret;
1738
1739 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1740 if (obj == NULL) {
1741 DRM_ERROR("Failed to allocate batch bo\n");
1742 return -ENOMEM;
1743 }
1744
1745 ret = i915_gem_object_pin(obj, 0, true, false);
1746 if (ret != 0) {
1747 drm_gem_object_unreference(&obj->base);
1748 DRM_ERROR("Failed to ping batch bo\n");
1749 return ret;
1750 }
1751
1752 ring->private = obj;
1753 }
1754
1755 return intel_init_ring_buffer(dev, ring);
1756 }
1757
1758 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1759 {
1760 drm_i915_private_t *dev_priv = dev->dev_private;
1761 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1762 int ret;
1763
1764 ring->name = "render ring";
1765 ring->id = RCS;
1766 ring->mmio_base = RENDER_RING_BASE;
1767
1768 if (INTEL_INFO(dev)->gen >= 6) {
1769 /* non-kms not supported on gen6+ */
1770 return -ENODEV;
1771 }
1772
1773 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1774 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1775 * the special gen5 functions. */
1776 ring->add_request = i9xx_add_request;
1777 if (INTEL_INFO(dev)->gen < 4)
1778 ring->flush = gen2_render_ring_flush;
1779 else
1780 ring->flush = gen4_render_ring_flush;
1781 ring->get_seqno = ring_get_seqno;
1782 ring->set_seqno = ring_set_seqno;
1783 if (IS_GEN2(dev)) {
1784 ring->irq_get = i8xx_ring_get_irq;
1785 ring->irq_put = i8xx_ring_put_irq;
1786 } else {
1787 ring->irq_get = i9xx_ring_get_irq;
1788 ring->irq_put = i9xx_ring_put_irq;
1789 }
1790 ring->irq_enable_mask = I915_USER_INTERRUPT;
1791 ring->write_tail = ring_write_tail;
1792 if (INTEL_INFO(dev)->gen >= 4)
1793 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1794 else if (IS_I830(dev) || IS_845G(dev))
1795 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1796 else
1797 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1798 ring->init = init_render_ring;
1799 ring->cleanup = render_ring_cleanup;
1800
1801 ring->dev = dev;
1802 INIT_LIST_HEAD(&ring->active_list);
1803 INIT_LIST_HEAD(&ring->request_list);
1804
1805 ring->size = size;
1806 ring->effective_size = ring->size;
1807 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1808 ring->effective_size -= 128;
1809
1810 ring->virtual_start = ioremap_wc(start, size);
1811 if (ring->virtual_start == NULL) {
1812 DRM_ERROR("can not ioremap virtual address for"
1813 " ring buffer\n");
1814 return -ENOMEM;
1815 }
1816
1817 if (!I915_NEED_GFX_HWS(dev)) {
1818 ret = init_phys_hws_pga(ring);
1819 if (ret)
1820 return ret;
1821 }
1822
1823 return 0;
1824 }
1825
1826 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1827 {
1828 drm_i915_private_t *dev_priv = dev->dev_private;
1829 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1830
1831 ring->name = "bsd ring";
1832 ring->id = VCS;
1833
1834 ring->write_tail = ring_write_tail;
1835 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1836 ring->mmio_base = GEN6_BSD_RING_BASE;
1837 /* gen6 bsd needs a special wa for tail updates */
1838 if (IS_GEN6(dev))
1839 ring->write_tail = gen6_bsd_ring_write_tail;
1840 ring->flush = gen6_ring_flush;
1841 ring->add_request = gen6_add_request;
1842 ring->get_seqno = gen6_ring_get_seqno;
1843 ring->set_seqno = ring_set_seqno;
1844 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1845 ring->irq_get = gen6_ring_get_irq;
1846 ring->irq_put = gen6_ring_put_irq;
1847 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1848 ring->sync_to = gen6_ring_sync;
1849 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1850 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1851 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1852 ring->signal_mbox[0] = GEN6_RVSYNC;
1853 ring->signal_mbox[1] = GEN6_BVSYNC;
1854 } else {
1855 ring->mmio_base = BSD_RING_BASE;
1856 ring->flush = bsd_ring_flush;
1857 ring->add_request = i9xx_add_request;
1858 ring->get_seqno = ring_get_seqno;
1859 ring->set_seqno = ring_set_seqno;
1860 if (IS_GEN5(dev)) {
1861 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1862 ring->irq_get = gen5_ring_get_irq;
1863 ring->irq_put = gen5_ring_put_irq;
1864 } else {
1865 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1866 ring->irq_get = i9xx_ring_get_irq;
1867 ring->irq_put = i9xx_ring_put_irq;
1868 }
1869 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1870 }
1871 ring->init = init_ring_common;
1872
1873 return intel_init_ring_buffer(dev, ring);
1874 }
1875
1876 int intel_init_blt_ring_buffer(struct drm_device *dev)
1877 {
1878 drm_i915_private_t *dev_priv = dev->dev_private;
1879 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1880
1881 ring->name = "blitter ring";
1882 ring->id = BCS;
1883
1884 ring->mmio_base = BLT_RING_BASE;
1885 ring->write_tail = ring_write_tail;
1886 ring->flush = blt_ring_flush;
1887 ring->add_request = gen6_add_request;
1888 ring->get_seqno = gen6_ring_get_seqno;
1889 ring->set_seqno = ring_set_seqno;
1890 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1891 ring->irq_get = gen6_ring_get_irq;
1892 ring->irq_put = gen6_ring_put_irq;
1893 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1894 ring->sync_to = gen6_ring_sync;
1895 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1896 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1897 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1898 ring->signal_mbox[0] = GEN6_RBSYNC;
1899 ring->signal_mbox[1] = GEN6_VBSYNC;
1900 ring->init = init_ring_common;
1901
1902 return intel_init_ring_buffer(dev, ring);
1903 }
1904
1905 int
1906 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1907 {
1908 int ret;
1909
1910 if (!ring->gpu_caches_dirty)
1911 return 0;
1912
1913 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1914 if (ret)
1915 return ret;
1916
1917 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1918
1919 ring->gpu_caches_dirty = false;
1920 return 0;
1921 }
1922
1923 int
1924 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1925 {
1926 uint32_t flush_domains;
1927 int ret;
1928
1929 flush_domains = 0;
1930 if (ring->gpu_caches_dirty)
1931 flush_domains = I915_GEM_GPU_DOMAINS;
1932
1933 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1934 if (ret)
1935 return ret;
1936
1937 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1938
1939 ring->gpu_caches_dirty = false;
1940 return 0;
1941 }
kernel source for telekom puls (alcatel/mediatek)