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Merge tag 'drm-intel-next-2012-12-21' of git://people.freedesktop.org/~danvet/drm...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 /*
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
39 */
40 struct pipe_control {
41 struct drm_i915_gem_object *obj;
42 volatile u32 *cpu_page;
43 u32 gtt_offset;
44 };
45
46 static inline int ring_space(struct intel_ring_buffer *ring)
47 {
48 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
49 if (space < 0)
50 space += ring->size;
51 return space;
52 }
53
54 static int
55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
57 u32 flush_domains)
58 {
59 u32 cmd;
60 int ret;
61
62 cmd = MI_FLUSH;
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
65
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
67 cmd |= MI_READ_FLUSH;
68
69 ret = intel_ring_begin(ring, 2);
70 if (ret)
71 return ret;
72
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
76
77 return 0;
78 }
79
80 static int
81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
83 u32 flush_domains)
84 {
85 struct drm_device *dev = ring->dev;
86 u32 cmd;
87 int ret;
88
89 /*
90 * read/write caches:
91 *
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
95 *
96 * read-only caches:
97 *
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
100 *
101 * I915_GEM_DOMAIN_COMMAND may not exist?
102 *
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
105 *
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
108 *
109 * TLBs:
110 *
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
115 */
116
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
121 cmd |= MI_EXE_FLUSH;
122
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
126
127 ret = intel_ring_begin(ring, 2);
128 if (ret)
129 return ret;
130
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
134
135 return 0;
136 }
137
138 /**
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 *
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146 * 0.
147 *
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 *
151 * And the workaround for these two requires this workaround first:
152 *
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
155 * flushes.
156 *
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159 * volume 2 part 1:
160 *
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
168 *
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
174 */
175 static int
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
177 {
178 struct pipe_control *pc = ring->private;
179 u32 scratch_addr = pc->gtt_offset + 128;
180 int ret;
181
182
183 ret = intel_ring_begin(ring, 6);
184 if (ret)
185 return ret;
186
187 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
189 PIPE_CONTROL_STALL_AT_SCOREBOARD);
190 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
191 intel_ring_emit(ring, 0); /* low dword */
192 intel_ring_emit(ring, 0); /* high dword */
193 intel_ring_emit(ring, MI_NOOP);
194 intel_ring_advance(ring);
195
196 ret = intel_ring_begin(ring, 6);
197 if (ret)
198 return ret;
199
200 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
202 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, MI_NOOP);
206 intel_ring_advance(ring);
207
208 return 0;
209 }
210
211 static int
212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
213 u32 invalidate_domains, u32 flush_domains)
214 {
215 u32 flags = 0;
216 struct pipe_control *pc = ring->private;
217 u32 scratch_addr = pc->gtt_offset + 128;
218 int ret;
219
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret = intel_emit_post_sync_nonzero_flush(ring);
222 if (ret)
223 return ret;
224
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
227 * impact.
228 */
229 if (flush_domains) {
230 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 /*
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
235 */
236 flags |= PIPE_CONTROL_CS_STALL;
237 }
238 if (invalidate_domains) {
239 flags |= PIPE_CONTROL_TLB_INVALIDATE;
240 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
244 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
245 /*
246 * TLB invalidate requires a post-sync write.
247 */
248 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
249 }
250
251 ret = intel_ring_begin(ring, 4);
252 if (ret)
253 return ret;
254
255 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring, flags);
257 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
258 intel_ring_emit(ring, 0);
259 intel_ring_advance(ring);
260
261 return 0;
262 }
263
264 static int
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
266 {
267 int ret;
268
269 ret = intel_ring_begin(ring, 4);
270 if (ret)
271 return ret;
272
273 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
275 PIPE_CONTROL_STALL_AT_SCOREBOARD);
276 intel_ring_emit(ring, 0);
277 intel_ring_emit(ring, 0);
278 intel_ring_advance(ring);
279
280 return 0;
281 }
282
283 static int
284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
285 u32 invalidate_domains, u32 flush_domains)
286 {
287 u32 flags = 0;
288 struct pipe_control *pc = ring->private;
289 u32 scratch_addr = pc->gtt_offset + 128;
290 int ret;
291
292 /*
293 * Ensure that any following seqno writes only happen when the render
294 * cache is indeed flushed.
295 *
296 * Workaround: 4th PIPE_CONTROL command (except the ones with only
297 * read-cache invalidate bits set) must have the CS_STALL bit set. We
298 * don't try to be clever and just set it unconditionally.
299 */
300 flags |= PIPE_CONTROL_CS_STALL;
301
302 /* Just flush everything. Experiments have shown that reducing the
303 * number of bits based on the write domains has little performance
304 * impact.
305 */
306 if (flush_domains) {
307 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
308 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
309 }
310 if (invalidate_domains) {
311 flags |= PIPE_CONTROL_TLB_INVALIDATE;
312 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
313 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
314 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
315 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
316 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
317 /*
318 * TLB invalidate requires a post-sync write.
319 */
320 flags |= PIPE_CONTROL_QW_WRITE;
321
322 /* Workaround: we must issue a pipe_control with CS-stall bit
323 * set before a pipe_control command that has the state cache
324 * invalidate bit set. */
325 gen7_render_ring_cs_stall_wa(ring);
326 }
327
328 ret = intel_ring_begin(ring, 4);
329 if (ret)
330 return ret;
331
332 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
333 intel_ring_emit(ring, flags);
334 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
335 intel_ring_emit(ring, 0);
336 intel_ring_advance(ring);
337
338 return 0;
339 }
340
341 static void ring_write_tail(struct intel_ring_buffer *ring,
342 u32 value)
343 {
344 drm_i915_private_t *dev_priv = ring->dev->dev_private;
345 I915_WRITE_TAIL(ring, value);
346 }
347
348 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
349 {
350 drm_i915_private_t *dev_priv = ring->dev->dev_private;
351 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
352 RING_ACTHD(ring->mmio_base) : ACTHD;
353
354 return I915_READ(acthd_reg);
355 }
356
357 static int init_ring_common(struct intel_ring_buffer *ring)
358 {
359 struct drm_device *dev = ring->dev;
360 drm_i915_private_t *dev_priv = dev->dev_private;
361 struct drm_i915_gem_object *obj = ring->obj;
362 int ret = 0;
363 u32 head;
364
365 if (HAS_FORCE_WAKE(dev))
366 gen6_gt_force_wake_get(dev_priv);
367
368 /* Stop the ring if it's running. */
369 I915_WRITE_CTL(ring, 0);
370 I915_WRITE_HEAD(ring, 0);
371 ring->write_tail(ring, 0);
372
373 head = I915_READ_HEAD(ring) & HEAD_ADDR;
374
375 /* G45 ring initialization fails to reset head to zero */
376 if (head != 0) {
377 DRM_DEBUG_KMS("%s head not reset to zero "
378 "ctl %08x head %08x tail %08x start %08x\n",
379 ring->name,
380 I915_READ_CTL(ring),
381 I915_READ_HEAD(ring),
382 I915_READ_TAIL(ring),
383 I915_READ_START(ring));
384
385 I915_WRITE_HEAD(ring, 0);
386
387 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
388 DRM_ERROR("failed to set %s head to zero "
389 "ctl %08x head %08x tail %08x start %08x\n",
390 ring->name,
391 I915_READ_CTL(ring),
392 I915_READ_HEAD(ring),
393 I915_READ_TAIL(ring),
394 I915_READ_START(ring));
395 }
396 }
397
398 /* Initialize the ring. This must happen _after_ we've cleared the ring
399 * registers with the above sequence (the readback of the HEAD registers
400 * also enforces ordering), otherwise the hw might lose the new ring
401 * register values. */
402 I915_WRITE_START(ring, obj->gtt_offset);
403 I915_WRITE_CTL(ring,
404 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
405 | RING_VALID);
406
407 /* If the head is still not zero, the ring is dead */
408 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
409 I915_READ_START(ring) == obj->gtt_offset &&
410 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
411 DRM_ERROR("%s initialization failed "
412 "ctl %08x head %08x tail %08x start %08x\n",
413 ring->name,
414 I915_READ_CTL(ring),
415 I915_READ_HEAD(ring),
416 I915_READ_TAIL(ring),
417 I915_READ_START(ring));
418 ret = -EIO;
419 goto out;
420 }
421
422 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
423 i915_kernel_lost_context(ring->dev);
424 else {
425 ring->head = I915_READ_HEAD(ring);
426 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
427 ring->space = ring_space(ring);
428 ring->last_retired_head = -1;
429 }
430
431 out:
432 if (HAS_FORCE_WAKE(dev))
433 gen6_gt_force_wake_put(dev_priv);
434
435 return ret;
436 }
437
438 static int
439 init_pipe_control(struct intel_ring_buffer *ring)
440 {
441 struct pipe_control *pc;
442 struct drm_i915_gem_object *obj;
443 int ret;
444
445 if (ring->private)
446 return 0;
447
448 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
449 if (!pc)
450 return -ENOMEM;
451
452 obj = i915_gem_alloc_object(ring->dev, 4096);
453 if (obj == NULL) {
454 DRM_ERROR("Failed to allocate seqno page\n");
455 ret = -ENOMEM;
456 goto err;
457 }
458
459 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
460
461 ret = i915_gem_object_pin(obj, 4096, true, false);
462 if (ret)
463 goto err_unref;
464
465 pc->gtt_offset = obj->gtt_offset;
466 pc->cpu_page = kmap(sg_page(obj->pages->sgl));
467 if (pc->cpu_page == NULL)
468 goto err_unpin;
469
470 pc->obj = obj;
471 ring->private = pc;
472 return 0;
473
474 err_unpin:
475 i915_gem_object_unpin(obj);
476 err_unref:
477 drm_gem_object_unreference(&obj->base);
478 err:
479 kfree(pc);
480 return ret;
481 }
482
483 static void
484 cleanup_pipe_control(struct intel_ring_buffer *ring)
485 {
486 struct pipe_control *pc = ring->private;
487 struct drm_i915_gem_object *obj;
488
489 if (!ring->private)
490 return;
491
492 obj = pc->obj;
493
494 kunmap(sg_page(obj->pages->sgl));
495 i915_gem_object_unpin(obj);
496 drm_gem_object_unreference(&obj->base);
497
498 kfree(pc);
499 ring->private = NULL;
500 }
501
502 static int init_render_ring(struct intel_ring_buffer *ring)
503 {
504 struct drm_device *dev = ring->dev;
505 struct drm_i915_private *dev_priv = dev->dev_private;
506 int ret = init_ring_common(ring);
507
508 if (INTEL_INFO(dev)->gen > 3) {
509 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
510 if (IS_GEN7(dev))
511 I915_WRITE(GFX_MODE_GEN7,
512 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
513 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
514 }
515
516 if (INTEL_INFO(dev)->gen >= 5) {
517 ret = init_pipe_control(ring);
518 if (ret)
519 return ret;
520 }
521
522 if (IS_GEN6(dev)) {
523 /* From the Sandybridge PRM, volume 1 part 3, page 24:
524 * "If this bit is set, STCunit will have LRA as replacement
525 * policy. [...] This bit must be reset. LRA replacement
526 * policy is not supported."
527 */
528 I915_WRITE(CACHE_MODE_0,
529 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
530
531 /* This is not explicitly set for GEN6, so read the register.
532 * see intel_ring_mi_set_context() for why we care.
533 * TODO: consider explicitly setting the bit for GEN5
534 */
535 ring->itlb_before_ctx_switch =
536 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
537 }
538
539 if (INTEL_INFO(dev)->gen >= 6)
540 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
541
542 if (HAS_L3_GPU_CACHE(dev))
543 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
544
545 return ret;
546 }
547
548 static void render_ring_cleanup(struct intel_ring_buffer *ring)
549 {
550 struct drm_device *dev = ring->dev;
551
552 if (!ring->private)
553 return;
554
555 if (HAS_BROKEN_CS_TLB(dev))
556 drm_gem_object_unreference(to_gem_object(ring->private));
557
558 cleanup_pipe_control(ring);
559 }
560
561 static void
562 update_mboxes(struct intel_ring_buffer *ring,
563 u32 mmio_offset)
564 {
565 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
566 intel_ring_emit(ring, mmio_offset);
567 intel_ring_emit(ring, ring->outstanding_lazy_request);
568 }
569
570 /**
571 * gen6_add_request - Update the semaphore mailbox registers
572 *
573 * @ring - ring that is adding a request
574 * @seqno - return seqno stuck into the ring
575 *
576 * Update the mailbox registers in the *other* rings with the current seqno.
577 * This acts like a signal in the canonical semaphore.
578 */
579 static int
580 gen6_add_request(struct intel_ring_buffer *ring)
581 {
582 u32 mbox1_reg;
583 u32 mbox2_reg;
584 int ret;
585
586 ret = intel_ring_begin(ring, 10);
587 if (ret)
588 return ret;
589
590 mbox1_reg = ring->signal_mbox[0];
591 mbox2_reg = ring->signal_mbox[1];
592
593 update_mboxes(ring, mbox1_reg);
594 update_mboxes(ring, mbox2_reg);
595 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
596 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
597 intel_ring_emit(ring, ring->outstanding_lazy_request);
598 intel_ring_emit(ring, MI_USER_INTERRUPT);
599 intel_ring_advance(ring);
600
601 return 0;
602 }
603
604 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
605 u32 seqno)
606 {
607 struct drm_i915_private *dev_priv = dev->dev_private;
608 return dev_priv->last_seqno < seqno;
609 }
610
611 /**
612 * intel_ring_sync - sync the waiter to the signaller on seqno
613 *
614 * @waiter - ring that is waiting
615 * @signaller - ring which has, or will signal
616 * @seqno - seqno which the waiter will block on
617 */
618 static int
619 gen6_ring_sync(struct intel_ring_buffer *waiter,
620 struct intel_ring_buffer *signaller,
621 u32 seqno)
622 {
623 int ret;
624 u32 dw1 = MI_SEMAPHORE_MBOX |
625 MI_SEMAPHORE_COMPARE |
626 MI_SEMAPHORE_REGISTER;
627
628 /* Throughout all of the GEM code, seqno passed implies our current
629 * seqno is >= the last seqno executed. However for hardware the
630 * comparison is strictly greater than.
631 */
632 seqno -= 1;
633
634 WARN_ON(signaller->semaphore_register[waiter->id] ==
635 MI_SEMAPHORE_SYNC_INVALID);
636
637 ret = intel_ring_begin(waiter, 4);
638 if (ret)
639 return ret;
640
641 /* If seqno wrap happened, omit the wait with no-ops */
642 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
643 intel_ring_emit(waiter,
644 dw1 |
645 signaller->semaphore_register[waiter->id]);
646 intel_ring_emit(waiter, seqno);
647 intel_ring_emit(waiter, 0);
648 intel_ring_emit(waiter, MI_NOOP);
649 } else {
650 intel_ring_emit(waiter, MI_NOOP);
651 intel_ring_emit(waiter, MI_NOOP);
652 intel_ring_emit(waiter, MI_NOOP);
653 intel_ring_emit(waiter, MI_NOOP);
654 }
655 intel_ring_advance(waiter);
656
657 return 0;
658 }
659
660 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
661 do { \
662 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
663 PIPE_CONTROL_DEPTH_STALL); \
664 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
665 intel_ring_emit(ring__, 0); \
666 intel_ring_emit(ring__, 0); \
667 } while (0)
668
669 static int
670 pc_render_add_request(struct intel_ring_buffer *ring)
671 {
672 struct pipe_control *pc = ring->private;
673 u32 scratch_addr = pc->gtt_offset + 128;
674 int ret;
675
676 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
677 * incoherent with writes to memory, i.e. completely fubar,
678 * so we need to use PIPE_NOTIFY instead.
679 *
680 * However, we also need to workaround the qword write
681 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
682 * memory before requesting an interrupt.
683 */
684 ret = intel_ring_begin(ring, 32);
685 if (ret)
686 return ret;
687
688 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
689 PIPE_CONTROL_WRITE_FLUSH |
690 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
691 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
692 intel_ring_emit(ring, ring->outstanding_lazy_request);
693 intel_ring_emit(ring, 0);
694 PIPE_CONTROL_FLUSH(ring, scratch_addr);
695 scratch_addr += 128; /* write to separate cachelines */
696 PIPE_CONTROL_FLUSH(ring, scratch_addr);
697 scratch_addr += 128;
698 PIPE_CONTROL_FLUSH(ring, scratch_addr);
699 scratch_addr += 128;
700 PIPE_CONTROL_FLUSH(ring, scratch_addr);
701 scratch_addr += 128;
702 PIPE_CONTROL_FLUSH(ring, scratch_addr);
703 scratch_addr += 128;
704 PIPE_CONTROL_FLUSH(ring, scratch_addr);
705
706 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
707 PIPE_CONTROL_WRITE_FLUSH |
708 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
709 PIPE_CONTROL_NOTIFY);
710 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
711 intel_ring_emit(ring, ring->outstanding_lazy_request);
712 intel_ring_emit(ring, 0);
713 intel_ring_advance(ring);
714
715 return 0;
716 }
717
718 static u32
719 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
720 {
721 /* Workaround to force correct ordering between irq and seqno writes on
722 * ivb (and maybe also on snb) by reading from a CS register (like
723 * ACTHD) before reading the status page. */
724 if (!lazy_coherency)
725 intel_ring_get_active_head(ring);
726 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
727 }
728
729 static u32
730 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
731 {
732 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
733 }
734
735 static void
736 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
737 {
738 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
739 }
740
741 static u32
742 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
743 {
744 struct pipe_control *pc = ring->private;
745 return pc->cpu_page[0];
746 }
747
748 static void
749 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
750 {
751 struct pipe_control *pc = ring->private;
752 pc->cpu_page[0] = seqno;
753 }
754
755 static bool
756 gen5_ring_get_irq(struct intel_ring_buffer *ring)
757 {
758 struct drm_device *dev = ring->dev;
759 drm_i915_private_t *dev_priv = dev->dev_private;
760 unsigned long flags;
761
762 if (!dev->irq_enabled)
763 return false;
764
765 spin_lock_irqsave(&dev_priv->irq_lock, flags);
766 if (ring->irq_refcount++ == 0) {
767 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
768 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
769 POSTING_READ(GTIMR);
770 }
771 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
772
773 return true;
774 }
775
776 static void
777 gen5_ring_put_irq(struct intel_ring_buffer *ring)
778 {
779 struct drm_device *dev = ring->dev;
780 drm_i915_private_t *dev_priv = dev->dev_private;
781 unsigned long flags;
782
783 spin_lock_irqsave(&dev_priv->irq_lock, flags);
784 if (--ring->irq_refcount == 0) {
785 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
786 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
787 POSTING_READ(GTIMR);
788 }
789 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
790 }
791
792 static bool
793 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
794 {
795 struct drm_device *dev = ring->dev;
796 drm_i915_private_t *dev_priv = dev->dev_private;
797 unsigned long flags;
798
799 if (!dev->irq_enabled)
800 return false;
801
802 spin_lock_irqsave(&dev_priv->irq_lock, flags);
803 if (ring->irq_refcount++ == 0) {
804 dev_priv->irq_mask &= ~ring->irq_enable_mask;
805 I915_WRITE(IMR, dev_priv->irq_mask);
806 POSTING_READ(IMR);
807 }
808 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
809
810 return true;
811 }
812
813 static void
814 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
815 {
816 struct drm_device *dev = ring->dev;
817 drm_i915_private_t *dev_priv = dev->dev_private;
818 unsigned long flags;
819
820 spin_lock_irqsave(&dev_priv->irq_lock, flags);
821 if (--ring->irq_refcount == 0) {
822 dev_priv->irq_mask |= ring->irq_enable_mask;
823 I915_WRITE(IMR, dev_priv->irq_mask);
824 POSTING_READ(IMR);
825 }
826 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
827 }
828
829 static bool
830 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
831 {
832 struct drm_device *dev = ring->dev;
833 drm_i915_private_t *dev_priv = dev->dev_private;
834 unsigned long flags;
835
836 if (!dev->irq_enabled)
837 return false;
838
839 spin_lock_irqsave(&dev_priv->irq_lock, flags);
840 if (ring->irq_refcount++ == 0) {
841 dev_priv->irq_mask &= ~ring->irq_enable_mask;
842 I915_WRITE16(IMR, dev_priv->irq_mask);
843 POSTING_READ16(IMR);
844 }
845 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
846
847 return true;
848 }
849
850 static void
851 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
852 {
853 struct drm_device *dev = ring->dev;
854 drm_i915_private_t *dev_priv = dev->dev_private;
855 unsigned long flags;
856
857 spin_lock_irqsave(&dev_priv->irq_lock, flags);
858 if (--ring->irq_refcount == 0) {
859 dev_priv->irq_mask |= ring->irq_enable_mask;
860 I915_WRITE16(IMR, dev_priv->irq_mask);
861 POSTING_READ16(IMR);
862 }
863 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
864 }
865
866 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
867 {
868 struct drm_device *dev = ring->dev;
869 drm_i915_private_t *dev_priv = ring->dev->dev_private;
870 u32 mmio = 0;
871
872 /* The ring status page addresses are no longer next to the rest of
873 * the ring registers as of gen7.
874 */
875 if (IS_GEN7(dev)) {
876 switch (ring->id) {
877 case RCS:
878 mmio = RENDER_HWS_PGA_GEN7;
879 break;
880 case BCS:
881 mmio = BLT_HWS_PGA_GEN7;
882 break;
883 case VCS:
884 mmio = BSD_HWS_PGA_GEN7;
885 break;
886 }
887 } else if (IS_GEN6(ring->dev)) {
888 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
889 } else {
890 mmio = RING_HWS_PGA(ring->mmio_base);
891 }
892
893 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
894 POSTING_READ(mmio);
895 }
896
897 static int
898 bsd_ring_flush(struct intel_ring_buffer *ring,
899 u32 invalidate_domains,
900 u32 flush_domains)
901 {
902 int ret;
903
904 ret = intel_ring_begin(ring, 2);
905 if (ret)
906 return ret;
907
908 intel_ring_emit(ring, MI_FLUSH);
909 intel_ring_emit(ring, MI_NOOP);
910 intel_ring_advance(ring);
911 return 0;
912 }
913
914 static int
915 i9xx_add_request(struct intel_ring_buffer *ring)
916 {
917 int ret;
918
919 ret = intel_ring_begin(ring, 4);
920 if (ret)
921 return ret;
922
923 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
924 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
925 intel_ring_emit(ring, ring->outstanding_lazy_request);
926 intel_ring_emit(ring, MI_USER_INTERRUPT);
927 intel_ring_advance(ring);
928
929 return 0;
930 }
931
932 static bool
933 gen6_ring_get_irq(struct intel_ring_buffer *ring)
934 {
935 struct drm_device *dev = ring->dev;
936 drm_i915_private_t *dev_priv = dev->dev_private;
937 unsigned long flags;
938
939 if (!dev->irq_enabled)
940 return false;
941
942 /* It looks like we need to prevent the gt from suspending while waiting
943 * for an notifiy irq, otherwise irqs seem to get lost on at least the
944 * blt/bsd rings on ivb. */
945 gen6_gt_force_wake_get(dev_priv);
946
947 spin_lock_irqsave(&dev_priv->irq_lock, flags);
948 if (ring->irq_refcount++ == 0) {
949 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
950 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
951 GEN6_RENDER_L3_PARITY_ERROR));
952 else
953 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
954 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
955 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
956 POSTING_READ(GTIMR);
957 }
958 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
959
960 return true;
961 }
962
963 static void
964 gen6_ring_put_irq(struct intel_ring_buffer *ring)
965 {
966 struct drm_device *dev = ring->dev;
967 drm_i915_private_t *dev_priv = dev->dev_private;
968 unsigned long flags;
969
970 spin_lock_irqsave(&dev_priv->irq_lock, flags);
971 if (--ring->irq_refcount == 0) {
972 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
973 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
974 else
975 I915_WRITE_IMR(ring, ~0);
976 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
977 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
978 POSTING_READ(GTIMR);
979 }
980 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
981
982 gen6_gt_force_wake_put(dev_priv);
983 }
984
985 static int
986 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
987 u32 offset, u32 length,
988 unsigned flags)
989 {
990 int ret;
991
992 ret = intel_ring_begin(ring, 2);
993 if (ret)
994 return ret;
995
996 intel_ring_emit(ring,
997 MI_BATCH_BUFFER_START |
998 MI_BATCH_GTT |
999 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1000 intel_ring_emit(ring, offset);
1001 intel_ring_advance(ring);
1002
1003 return 0;
1004 }
1005
1006 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1007 #define I830_BATCH_LIMIT (256*1024)
1008 static int
1009 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1010 u32 offset, u32 len,
1011 unsigned flags)
1012 {
1013 int ret;
1014
1015 if (flags & I915_DISPATCH_PINNED) {
1016 ret = intel_ring_begin(ring, 4);
1017 if (ret)
1018 return ret;
1019
1020 intel_ring_emit(ring, MI_BATCH_BUFFER);
1021 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1022 intel_ring_emit(ring, offset + len - 8);
1023 intel_ring_emit(ring, MI_NOOP);
1024 intel_ring_advance(ring);
1025 } else {
1026 struct drm_i915_gem_object *obj = ring->private;
1027 u32 cs_offset = obj->gtt_offset;
1028
1029 if (len > I830_BATCH_LIMIT)
1030 return -ENOSPC;
1031
1032 ret = intel_ring_begin(ring, 9+3);
1033 if (ret)
1034 return ret;
1035 /* Blit the batch (which has now all relocs applied) to the stable batch
1036 * scratch bo area (so that the CS never stumbles over its tlb
1037 * invalidation bug) ... */
1038 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1039 XY_SRC_COPY_BLT_WRITE_ALPHA |
1040 XY_SRC_COPY_BLT_WRITE_RGB);
1041 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1042 intel_ring_emit(ring, 0);
1043 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1044 intel_ring_emit(ring, cs_offset);
1045 intel_ring_emit(ring, 0);
1046 intel_ring_emit(ring, 4096);
1047 intel_ring_emit(ring, offset);
1048 intel_ring_emit(ring, MI_FLUSH);
1049
1050 /* ... and execute it. */
1051 intel_ring_emit(ring, MI_BATCH_BUFFER);
1052 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1053 intel_ring_emit(ring, cs_offset + len - 8);
1054 intel_ring_advance(ring);
1055 }
1056
1057 return 0;
1058 }
1059
1060 static int
1061 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1062 u32 offset, u32 len,
1063 unsigned flags)
1064 {
1065 int ret;
1066
1067 ret = intel_ring_begin(ring, 2);
1068 if (ret)
1069 return ret;
1070
1071 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1072 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1073 intel_ring_advance(ring);
1074
1075 return 0;
1076 }
1077
1078 static void cleanup_status_page(struct intel_ring_buffer *ring)
1079 {
1080 struct drm_i915_gem_object *obj;
1081
1082 obj = ring->status_page.obj;
1083 if (obj == NULL)
1084 return;
1085
1086 kunmap(sg_page(obj->pages->sgl));
1087 i915_gem_object_unpin(obj);
1088 drm_gem_object_unreference(&obj->base);
1089 ring->status_page.obj = NULL;
1090 }
1091
1092 static int init_status_page(struct intel_ring_buffer *ring)
1093 {
1094 struct drm_device *dev = ring->dev;
1095 struct drm_i915_gem_object *obj;
1096 int ret;
1097
1098 obj = i915_gem_alloc_object(dev, 4096);
1099 if (obj == NULL) {
1100 DRM_ERROR("Failed to allocate status page\n");
1101 ret = -ENOMEM;
1102 goto err;
1103 }
1104
1105 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1106
1107 ret = i915_gem_object_pin(obj, 4096, true, false);
1108 if (ret != 0) {
1109 goto err_unref;
1110 }
1111
1112 ring->status_page.gfx_addr = obj->gtt_offset;
1113 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1114 if (ring->status_page.page_addr == NULL) {
1115 ret = -ENOMEM;
1116 goto err_unpin;
1117 }
1118 ring->status_page.obj = obj;
1119 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1120
1121 intel_ring_setup_status_page(ring);
1122 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1123 ring->name, ring->status_page.gfx_addr);
1124
1125 return 0;
1126
1127 err_unpin:
1128 i915_gem_object_unpin(obj);
1129 err_unref:
1130 drm_gem_object_unreference(&obj->base);
1131 err:
1132 return ret;
1133 }
1134
1135 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1136 {
1137 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1138 u32 addr;
1139
1140 if (!dev_priv->status_page_dmah) {
1141 dev_priv->status_page_dmah =
1142 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1143 if (!dev_priv->status_page_dmah)
1144 return -ENOMEM;
1145 }
1146
1147 addr = dev_priv->status_page_dmah->busaddr;
1148 if (INTEL_INFO(ring->dev)->gen >= 4)
1149 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1150 I915_WRITE(HWS_PGA, addr);
1151
1152 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1153 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1154
1155 return 0;
1156 }
1157
1158 static int intel_init_ring_buffer(struct drm_device *dev,
1159 struct intel_ring_buffer *ring)
1160 {
1161 struct drm_i915_gem_object *obj;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 int ret;
1164
1165 ring->dev = dev;
1166 INIT_LIST_HEAD(&ring->active_list);
1167 INIT_LIST_HEAD(&ring->request_list);
1168 ring->size = 32 * PAGE_SIZE;
1169 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1170
1171 init_waitqueue_head(&ring->irq_queue);
1172
1173 if (I915_NEED_GFX_HWS(dev)) {
1174 ret = init_status_page(ring);
1175 if (ret)
1176 return ret;
1177 } else {
1178 BUG_ON(ring->id != RCS);
1179 ret = init_phys_hws_pga(ring);
1180 if (ret)
1181 return ret;
1182 }
1183
1184 obj = NULL;
1185 if (!HAS_LLC(dev))
1186 obj = i915_gem_object_create_stolen(dev, ring->size);
1187 if (obj == NULL)
1188 obj = i915_gem_alloc_object(dev, ring->size);
1189 if (obj == NULL) {
1190 DRM_ERROR("Failed to allocate ringbuffer\n");
1191 ret = -ENOMEM;
1192 goto err_hws;
1193 }
1194
1195 ring->obj = obj;
1196
1197 ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1198 if (ret)
1199 goto err_unref;
1200
1201 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1202 if (ret)
1203 goto err_unpin;
1204
1205 ring->virtual_start =
1206 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1207 ring->size);
1208 if (ring->virtual_start == NULL) {
1209 DRM_ERROR("Failed to map ringbuffer.\n");
1210 ret = -EINVAL;
1211 goto err_unpin;
1212 }
1213
1214 ret = ring->init(ring);
1215 if (ret)
1216 goto err_unmap;
1217
1218 /* Workaround an erratum on the i830 which causes a hang if
1219 * the TAIL pointer points to within the last 2 cachelines
1220 * of the buffer.
1221 */
1222 ring->effective_size = ring->size;
1223 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1224 ring->effective_size -= 128;
1225
1226 intel_ring_init_seqno(ring, dev_priv->last_seqno);
1227
1228 return 0;
1229
1230 err_unmap:
1231 iounmap(ring->virtual_start);
1232 err_unpin:
1233 i915_gem_object_unpin(obj);
1234 err_unref:
1235 drm_gem_object_unreference(&obj->base);
1236 ring->obj = NULL;
1237 err_hws:
1238 cleanup_status_page(ring);
1239 return ret;
1240 }
1241
1242 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1243 {
1244 struct drm_i915_private *dev_priv;
1245 int ret;
1246
1247 if (ring->obj == NULL)
1248 return;
1249
1250 /* Disable the ring buffer. The ring must be idle at this point */
1251 dev_priv = ring->dev->dev_private;
1252 ret = intel_ring_idle(ring);
1253 if (ret)
1254 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1255 ring->name, ret);
1256
1257 I915_WRITE_CTL(ring, 0);
1258
1259 iounmap(ring->virtual_start);
1260
1261 i915_gem_object_unpin(ring->obj);
1262 drm_gem_object_unreference(&ring->obj->base);
1263 ring->obj = NULL;
1264
1265 if (ring->cleanup)
1266 ring->cleanup(ring);
1267
1268 cleanup_status_page(ring);
1269 }
1270
1271 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1272 {
1273 int ret;
1274
1275 ret = i915_wait_seqno(ring, seqno);
1276 if (!ret)
1277 i915_gem_retire_requests_ring(ring);
1278
1279 return ret;
1280 }
1281
1282 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1283 {
1284 struct drm_i915_gem_request *request;
1285 u32 seqno = 0;
1286 int ret;
1287
1288 i915_gem_retire_requests_ring(ring);
1289
1290 if (ring->last_retired_head != -1) {
1291 ring->head = ring->last_retired_head;
1292 ring->last_retired_head = -1;
1293 ring->space = ring_space(ring);
1294 if (ring->space >= n)
1295 return 0;
1296 }
1297
1298 list_for_each_entry(request, &ring->request_list, list) {
1299 int space;
1300
1301 if (request->tail == -1)
1302 continue;
1303
1304 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1305 if (space < 0)
1306 space += ring->size;
1307 if (space >= n) {
1308 seqno = request->seqno;
1309 break;
1310 }
1311
1312 /* Consume this request in case we need more space than
1313 * is available and so need to prevent a race between
1314 * updating last_retired_head and direct reads of
1315 * I915_RING_HEAD. It also provides a nice sanity check.
1316 */
1317 request->tail = -1;
1318 }
1319
1320 if (seqno == 0)
1321 return -ENOSPC;
1322
1323 ret = intel_ring_wait_seqno(ring, seqno);
1324 if (ret)
1325 return ret;
1326
1327 if (WARN_ON(ring->last_retired_head == -1))
1328 return -ENOSPC;
1329
1330 ring->head = ring->last_retired_head;
1331 ring->last_retired_head = -1;
1332 ring->space = ring_space(ring);
1333 if (WARN_ON(ring->space < n))
1334 return -ENOSPC;
1335
1336 return 0;
1337 }
1338
1339 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1340 {
1341 struct drm_device *dev = ring->dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 unsigned long end;
1344 int ret;
1345
1346 ret = intel_ring_wait_request(ring, n);
1347 if (ret != -ENOSPC)
1348 return ret;
1349
1350 trace_i915_ring_wait_begin(ring);
1351 /* With GEM the hangcheck timer should kick us out of the loop,
1352 * leaving it early runs the risk of corrupting GEM state (due
1353 * to running on almost untested codepaths). But on resume
1354 * timers don't work yet, so prevent a complete hang in that
1355 * case by choosing an insanely large timeout. */
1356 end = jiffies + 60 * HZ;
1357
1358 do {
1359 ring->head = I915_READ_HEAD(ring);
1360 ring->space = ring_space(ring);
1361 if (ring->space >= n) {
1362 trace_i915_ring_wait_end(ring);
1363 return 0;
1364 }
1365
1366 if (dev->primary->master) {
1367 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1368 if (master_priv->sarea_priv)
1369 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1370 }
1371
1372 msleep(1);
1373
1374 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1375 if (ret)
1376 return ret;
1377 } while (!time_after(jiffies, end));
1378 trace_i915_ring_wait_end(ring);
1379 return -EBUSY;
1380 }
1381
1382 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1383 {
1384 uint32_t __iomem *virt;
1385 int rem = ring->size - ring->tail;
1386
1387 if (ring->space < rem) {
1388 int ret = ring_wait_for_space(ring, rem);
1389 if (ret)
1390 return ret;
1391 }
1392
1393 virt = ring->virtual_start + ring->tail;
1394 rem /= 4;
1395 while (rem--)
1396 iowrite32(MI_NOOP, virt++);
1397
1398 ring->tail = 0;
1399 ring->space = ring_space(ring);
1400
1401 return 0;
1402 }
1403
1404 int intel_ring_idle(struct intel_ring_buffer *ring)
1405 {
1406 u32 seqno;
1407 int ret;
1408
1409 /* We need to add any requests required to flush the objects and ring */
1410 if (ring->outstanding_lazy_request) {
1411 ret = i915_add_request(ring, NULL, NULL);
1412 if (ret)
1413 return ret;
1414 }
1415
1416 /* Wait upon the last request to be completed */
1417 if (list_empty(&ring->request_list))
1418 return 0;
1419
1420 seqno = list_entry(ring->request_list.prev,
1421 struct drm_i915_gem_request,
1422 list)->seqno;
1423
1424 return i915_wait_seqno(ring, seqno);
1425 }
1426
1427 static int
1428 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1429 {
1430 if (ring->outstanding_lazy_request)
1431 return 0;
1432
1433 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1434 }
1435
1436 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1437 int bytes)
1438 {
1439 int ret;
1440
1441 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1442 ret = intel_wrap_ring_buffer(ring);
1443 if (unlikely(ret))
1444 return ret;
1445 }
1446
1447 if (unlikely(ring->space < bytes)) {
1448 ret = ring_wait_for_space(ring, bytes);
1449 if (unlikely(ret))
1450 return ret;
1451 }
1452
1453 ring->space -= bytes;
1454 return 0;
1455 }
1456
1457 int intel_ring_begin(struct intel_ring_buffer *ring,
1458 int num_dwords)
1459 {
1460 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1461 int ret;
1462
1463 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1464 if (ret)
1465 return ret;
1466
1467 /* Preallocate the olr before touching the ring */
1468 ret = intel_ring_alloc_seqno(ring);
1469 if (ret)
1470 return ret;
1471
1472 return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1473 }
1474
1475 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1476 {
1477 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1478
1479 BUG_ON(ring->outstanding_lazy_request);
1480
1481 if (INTEL_INFO(ring->dev)->gen >= 6) {
1482 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1483 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1484 }
1485
1486 ring->set_seqno(ring, seqno);
1487 }
1488
1489 void intel_ring_advance(struct intel_ring_buffer *ring)
1490 {
1491 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1492
1493 ring->tail &= ring->size - 1;
1494 if (dev_priv->stop_rings & intel_ring_flag(ring))
1495 return;
1496 ring->write_tail(ring, ring->tail);
1497 }
1498
1499
1500 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1501 u32 value)
1502 {
1503 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1504
1505 /* Every tail move must follow the sequence below */
1506
1507 /* Disable notification that the ring is IDLE. The GT
1508 * will then assume that it is busy and bring it out of rc6.
1509 */
1510 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1511 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1512
1513 /* Clear the context id. Here be magic! */
1514 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1515
1516 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1517 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1518 GEN6_BSD_SLEEP_INDICATOR) == 0,
1519 50))
1520 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1521
1522 /* Now that the ring is fully powered up, update the tail */
1523 I915_WRITE_TAIL(ring, value);
1524 POSTING_READ(RING_TAIL(ring->mmio_base));
1525
1526 /* Let the ring send IDLE messages to the GT again,
1527 * and so let it sleep to conserve power when idle.
1528 */
1529 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1530 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1531 }
1532
1533 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1534 u32 invalidate, u32 flush)
1535 {
1536 uint32_t cmd;
1537 int ret;
1538
1539 ret = intel_ring_begin(ring, 4);
1540 if (ret)
1541 return ret;
1542
1543 cmd = MI_FLUSH_DW;
1544 /*
1545 * Bspec vol 1c.5 - video engine command streamer:
1546 * "If ENABLED, all TLBs will be invalidated once the flush
1547 * operation is complete. This bit is only valid when the
1548 * Post-Sync Operation field is a value of 1h or 3h."
1549 */
1550 if (invalidate & I915_GEM_GPU_DOMAINS)
1551 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1552 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1553 intel_ring_emit(ring, cmd);
1554 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1555 intel_ring_emit(ring, 0);
1556 intel_ring_emit(ring, MI_NOOP);
1557 intel_ring_advance(ring);
1558 return 0;
1559 }
1560
1561 static int
1562 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1563 u32 offset, u32 len,
1564 unsigned flags)
1565 {
1566 int ret;
1567
1568 ret = intel_ring_begin(ring, 2);
1569 if (ret)
1570 return ret;
1571
1572 intel_ring_emit(ring,
1573 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1574 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1575 /* bit0-7 is the length on GEN6+ */
1576 intel_ring_emit(ring, offset);
1577 intel_ring_advance(ring);
1578
1579 return 0;
1580 }
1581
1582 static int
1583 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1584 u32 offset, u32 len,
1585 unsigned flags)
1586 {
1587 int ret;
1588
1589 ret = intel_ring_begin(ring, 2);
1590 if (ret)
1591 return ret;
1592
1593 intel_ring_emit(ring,
1594 MI_BATCH_BUFFER_START |
1595 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1596 /* bit0-7 is the length on GEN6+ */
1597 intel_ring_emit(ring, offset);
1598 intel_ring_advance(ring);
1599
1600 return 0;
1601 }
1602
1603 /* Blitter support (SandyBridge+) */
1604
1605 static int blt_ring_flush(struct intel_ring_buffer *ring,
1606 u32 invalidate, u32 flush)
1607 {
1608 uint32_t cmd;
1609 int ret;
1610
1611 ret = intel_ring_begin(ring, 4);
1612 if (ret)
1613 return ret;
1614
1615 cmd = MI_FLUSH_DW;
1616 /*
1617 * Bspec vol 1c.3 - blitter engine command streamer:
1618 * "If ENABLED, all TLBs will be invalidated once the flush
1619 * operation is complete. This bit is only valid when the
1620 * Post-Sync Operation field is a value of 1h or 3h."
1621 */
1622 if (invalidate & I915_GEM_DOMAIN_RENDER)
1623 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1624 MI_FLUSH_DW_OP_STOREDW;
1625 intel_ring_emit(ring, cmd);
1626 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1627 intel_ring_emit(ring, 0);
1628 intel_ring_emit(ring, MI_NOOP);
1629 intel_ring_advance(ring);
1630 return 0;
1631 }
1632
1633 int intel_init_render_ring_buffer(struct drm_device *dev)
1634 {
1635 drm_i915_private_t *dev_priv = dev->dev_private;
1636 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1637
1638 ring->name = "render ring";
1639 ring->id = RCS;
1640 ring->mmio_base = RENDER_RING_BASE;
1641
1642 if (INTEL_INFO(dev)->gen >= 6) {
1643 ring->add_request = gen6_add_request;
1644 ring->flush = gen7_render_ring_flush;
1645 if (INTEL_INFO(dev)->gen == 6)
1646 ring->flush = gen6_render_ring_flush;
1647 ring->irq_get = gen6_ring_get_irq;
1648 ring->irq_put = gen6_ring_put_irq;
1649 ring->irq_enable_mask = GT_USER_INTERRUPT;
1650 ring->get_seqno = gen6_ring_get_seqno;
1651 ring->set_seqno = ring_set_seqno;
1652 ring->sync_to = gen6_ring_sync;
1653 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1654 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1655 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1656 ring->signal_mbox[0] = GEN6_VRSYNC;
1657 ring->signal_mbox[1] = GEN6_BRSYNC;
1658 } else if (IS_GEN5(dev)) {
1659 ring->add_request = pc_render_add_request;
1660 ring->flush = gen4_render_ring_flush;
1661 ring->get_seqno = pc_render_get_seqno;
1662 ring->set_seqno = pc_render_set_seqno;
1663 ring->irq_get = gen5_ring_get_irq;
1664 ring->irq_put = gen5_ring_put_irq;
1665 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1666 } else {
1667 ring->add_request = i9xx_add_request;
1668 if (INTEL_INFO(dev)->gen < 4)
1669 ring->flush = gen2_render_ring_flush;
1670 else
1671 ring->flush = gen4_render_ring_flush;
1672 ring->get_seqno = ring_get_seqno;
1673 ring->set_seqno = ring_set_seqno;
1674 if (IS_GEN2(dev)) {
1675 ring->irq_get = i8xx_ring_get_irq;
1676 ring->irq_put = i8xx_ring_put_irq;
1677 } else {
1678 ring->irq_get = i9xx_ring_get_irq;
1679 ring->irq_put = i9xx_ring_put_irq;
1680 }
1681 ring->irq_enable_mask = I915_USER_INTERRUPT;
1682 }
1683 ring->write_tail = ring_write_tail;
1684 if (IS_HASWELL(dev))
1685 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1686 else if (INTEL_INFO(dev)->gen >= 6)
1687 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1688 else if (INTEL_INFO(dev)->gen >= 4)
1689 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1690 else if (IS_I830(dev) || IS_845G(dev))
1691 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1692 else
1693 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1694 ring->init = init_render_ring;
1695 ring->cleanup = render_ring_cleanup;
1696
1697 /* Workaround batchbuffer to combat CS tlb bug. */
1698 if (HAS_BROKEN_CS_TLB(dev)) {
1699 struct drm_i915_gem_object *obj;
1700 int ret;
1701
1702 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1703 if (obj == NULL) {
1704 DRM_ERROR("Failed to allocate batch bo\n");
1705 return -ENOMEM;
1706 }
1707
1708 ret = i915_gem_object_pin(obj, 0, true, false);
1709 if (ret != 0) {
1710 drm_gem_object_unreference(&obj->base);
1711 DRM_ERROR("Failed to ping batch bo\n");
1712 return ret;
1713 }
1714
1715 ring->private = obj;
1716 }
1717
1718 return intel_init_ring_buffer(dev, ring);
1719 }
1720
1721 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1722 {
1723 drm_i915_private_t *dev_priv = dev->dev_private;
1724 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1725 int ret;
1726
1727 ring->name = "render ring";
1728 ring->id = RCS;
1729 ring->mmio_base = RENDER_RING_BASE;
1730
1731 if (INTEL_INFO(dev)->gen >= 6) {
1732 /* non-kms not supported on gen6+ */
1733 return -ENODEV;
1734 }
1735
1736 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1737 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1738 * the special gen5 functions. */
1739 ring->add_request = i9xx_add_request;
1740 if (INTEL_INFO(dev)->gen < 4)
1741 ring->flush = gen2_render_ring_flush;
1742 else
1743 ring->flush = gen4_render_ring_flush;
1744 ring->get_seqno = ring_get_seqno;
1745 ring->set_seqno = ring_set_seqno;
1746 if (IS_GEN2(dev)) {
1747 ring->irq_get = i8xx_ring_get_irq;
1748 ring->irq_put = i8xx_ring_put_irq;
1749 } else {
1750 ring->irq_get = i9xx_ring_get_irq;
1751 ring->irq_put = i9xx_ring_put_irq;
1752 }
1753 ring->irq_enable_mask = I915_USER_INTERRUPT;
1754 ring->write_tail = ring_write_tail;
1755 if (INTEL_INFO(dev)->gen >= 4)
1756 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1757 else if (IS_I830(dev) || IS_845G(dev))
1758 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1759 else
1760 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1761 ring->init = init_render_ring;
1762 ring->cleanup = render_ring_cleanup;
1763
1764 ring->dev = dev;
1765 INIT_LIST_HEAD(&ring->active_list);
1766 INIT_LIST_HEAD(&ring->request_list);
1767
1768 ring->size = size;
1769 ring->effective_size = ring->size;
1770 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1771 ring->effective_size -= 128;
1772
1773 ring->virtual_start = ioremap_wc(start, size);
1774 if (ring->virtual_start == NULL) {
1775 DRM_ERROR("can not ioremap virtual address for"
1776 " ring buffer\n");
1777 return -ENOMEM;
1778 }
1779
1780 if (!I915_NEED_GFX_HWS(dev)) {
1781 ret = init_phys_hws_pga(ring);
1782 if (ret)
1783 return ret;
1784 }
1785
1786 return 0;
1787 }
1788
1789 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1790 {
1791 drm_i915_private_t *dev_priv = dev->dev_private;
1792 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1793
1794 ring->name = "bsd ring";
1795 ring->id = VCS;
1796
1797 ring->write_tail = ring_write_tail;
1798 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1799 ring->mmio_base = GEN6_BSD_RING_BASE;
1800 /* gen6 bsd needs a special wa for tail updates */
1801 if (IS_GEN6(dev))
1802 ring->write_tail = gen6_bsd_ring_write_tail;
1803 ring->flush = gen6_ring_flush;
1804 ring->add_request = gen6_add_request;
1805 ring->get_seqno = gen6_ring_get_seqno;
1806 ring->set_seqno = ring_set_seqno;
1807 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1808 ring->irq_get = gen6_ring_get_irq;
1809 ring->irq_put = gen6_ring_put_irq;
1810 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1811 ring->sync_to = gen6_ring_sync;
1812 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1813 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1814 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1815 ring->signal_mbox[0] = GEN6_RVSYNC;
1816 ring->signal_mbox[1] = GEN6_BVSYNC;
1817 } else {
1818 ring->mmio_base = BSD_RING_BASE;
1819 ring->flush = bsd_ring_flush;
1820 ring->add_request = i9xx_add_request;
1821 ring->get_seqno = ring_get_seqno;
1822 ring->set_seqno = ring_set_seqno;
1823 if (IS_GEN5(dev)) {
1824 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1825 ring->irq_get = gen5_ring_get_irq;
1826 ring->irq_put = gen5_ring_put_irq;
1827 } else {
1828 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1829 ring->irq_get = i9xx_ring_get_irq;
1830 ring->irq_put = i9xx_ring_put_irq;
1831 }
1832 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1833 }
1834 ring->init = init_ring_common;
1835
1836 return intel_init_ring_buffer(dev, ring);
1837 }
1838
1839 int intel_init_blt_ring_buffer(struct drm_device *dev)
1840 {
1841 drm_i915_private_t *dev_priv = dev->dev_private;
1842 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1843
1844 ring->name = "blitter ring";
1845 ring->id = BCS;
1846
1847 ring->mmio_base = BLT_RING_BASE;
1848 ring->write_tail = ring_write_tail;
1849 ring->flush = blt_ring_flush;
1850 ring->add_request = gen6_add_request;
1851 ring->get_seqno = gen6_ring_get_seqno;
1852 ring->set_seqno = ring_set_seqno;
1853 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1854 ring->irq_get = gen6_ring_get_irq;
1855 ring->irq_put = gen6_ring_put_irq;
1856 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1857 ring->sync_to = gen6_ring_sync;
1858 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1859 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1860 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1861 ring->signal_mbox[0] = GEN6_RBSYNC;
1862 ring->signal_mbox[1] = GEN6_VBSYNC;
1863 ring->init = init_ring_common;
1864
1865 return intel_init_ring_buffer(dev, ring);
1866 }
1867
1868 int
1869 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1870 {
1871 int ret;
1872
1873 if (!ring->gpu_caches_dirty)
1874 return 0;
1875
1876 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1877 if (ret)
1878 return ret;
1879
1880 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1881
1882 ring->gpu_caches_dirty = false;
1883 return 0;
1884 }
1885
1886 int
1887 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1888 {
1889 uint32_t flush_domains;
1890 int ret;
1891
1892 flush_domains = 0;
1893 if (ring->gpu_caches_dirty)
1894 flush_domains = I915_GEM_GPU_DOMAINS;
1895
1896 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1897 if (ret)
1898 return ret;
1899
1900 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1901
1902 ring->gpu_caches_dirty = false;
1903 return 0;
1904 }
kernel source for telekom puls (alcatel/mediatek)