2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Panel Self Refresh (PSR/SRD)
27 * Since Haswell Display controller supports Panel Self-Refresh on display
28 * panels witch have a remote frame buffer (RFB) implemented according to PSR
29 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
30 * when system is idle but display is on as it eliminates display refresh
31 * request to DDR memory completely as long as the frame buffer for that
32 * display is unchanged.
34 * Panel Self Refresh must be supported by both Hardware (source) and
37 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
38 * to power down the link and memory controller. For DSI panels the same idea
39 * is called "manual mode".
41 * The implementation uses the hardware-based PSR support which automatically
42 * enters/exits self-refresh mode. The hardware takes care of sending the
43 * required DP aux message and could even retrain the link (that part isn't
44 * enabled yet though). The hardware also keeps track of any frontbuffer
45 * changes to know when to exit self-refresh mode again. Unfortunately that
46 * part doesn't work too well, hence why the i915 PSR support uses the
47 * software frontbuffer tracking to make sure it doesn't miss a screen
48 * update. For this integration intel_psr_invalidate() and intel_psr_flush()
49 * get called by the frontbuffer tracking code. Note that because of locking
50 * issues the self-refresh re-enable code is done from a work queue, which
51 * must be correctly synchronized/cancelled when shutting down the pipe."
56 #include "intel_drv.h"
59 static bool is_edp_psr(struct intel_dp
*intel_dp
)
61 return intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
;
64 static bool vlv_is_psr_active_on_pipe(struct drm_device
*dev
, int pipe
)
66 struct drm_i915_private
*dev_priv
= to_i915(dev
);
69 val
= I915_READ(VLV_PSRSTAT(pipe
)) &
70 VLV_EDP_PSR_CURR_STATE_MASK
;
71 return (val
== VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
72 (val
== VLV_EDP_PSR_ACTIVE_SF_UPDATE
);
75 static void intel_psr_write_vsc(struct intel_dp
*intel_dp
,
76 const struct edp_vsc_psr
*vsc_psr
)
78 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
79 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
80 struct drm_i915_private
*dev_priv
= to_i915(dev
);
81 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
82 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
83 i915_reg_t ctl_reg
= HSW_TVIDEO_DIP_CTL(cpu_transcoder
);
84 uint32_t *data
= (uint32_t *) vsc_psr
;
87 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
88 the video DIP being updated before program video DIP data buffer
89 registers for DIP being updated. */
90 I915_WRITE(ctl_reg
, 0);
91 POSTING_READ(ctl_reg
);
93 for (i
= 0; i
< sizeof(*vsc_psr
); i
+= 4) {
94 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder
,
98 for (; i
< VIDEO_DIP_VSC_DATA_SIZE
; i
+= 4)
99 I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder
,
102 I915_WRITE(ctl_reg
, VIDEO_DIP_ENABLE_VSC_HSW
);
103 POSTING_READ(ctl_reg
);
106 static void vlv_psr_setup_vsc(struct intel_dp
*intel_dp
)
108 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
109 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
110 struct drm_i915_private
*dev_priv
= to_i915(dev
);
111 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
112 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
115 /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
116 val
= I915_READ(VLV_VSCSDP(pipe
));
117 val
&= ~VLV_EDP_PSR_SDP_FREQ_MASK
;
118 val
|= VLV_EDP_PSR_SDP_FREQ_EVFRAME
;
119 I915_WRITE(VLV_VSCSDP(pipe
), val
);
122 static void skl_psr_setup_su_vsc(struct intel_dp
*intel_dp
)
124 struct edp_vsc_psr psr_vsc
;
125 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
126 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
127 struct drm_i915_private
*dev_priv
= to_i915(dev
);
129 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
130 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
131 psr_vsc
.sdp_header
.HB0
= 0;
132 psr_vsc
.sdp_header
.HB1
= 0x7;
133 if (dev_priv
->psr
.colorimetry_support
&&
134 dev_priv
->psr
.y_cord_support
) {
135 psr_vsc
.sdp_header
.HB2
= 0x5;
136 psr_vsc
.sdp_header
.HB3
= 0x13;
137 } else if (dev_priv
->psr
.y_cord_support
) {
138 psr_vsc
.sdp_header
.HB2
= 0x4;
139 psr_vsc
.sdp_header
.HB3
= 0xe;
141 psr_vsc
.sdp_header
.HB2
= 0x3;
142 psr_vsc
.sdp_header
.HB3
= 0xc;
145 intel_psr_write_vsc(intel_dp
, &psr_vsc
);
148 static void hsw_psr_setup_vsc(struct intel_dp
*intel_dp
)
150 struct edp_vsc_psr psr_vsc
;
152 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
153 memset(&psr_vsc
, 0, sizeof(psr_vsc
));
154 psr_vsc
.sdp_header
.HB0
= 0;
155 psr_vsc
.sdp_header
.HB1
= 0x7;
156 psr_vsc
.sdp_header
.HB2
= 0x2;
157 psr_vsc
.sdp_header
.HB3
= 0x8;
158 intel_psr_write_vsc(intel_dp
, &psr_vsc
);
161 static void vlv_psr_enable_sink(struct intel_dp
*intel_dp
)
163 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
164 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
167 static i915_reg_t
psr_aux_ctl_reg(struct drm_i915_private
*dev_priv
,
170 if (INTEL_INFO(dev_priv
)->gen
>= 9)
171 return DP_AUX_CH_CTL(port
);
173 return EDP_PSR_AUX_CTL
;
176 static i915_reg_t
psr_aux_data_reg(struct drm_i915_private
*dev_priv
,
177 enum port port
, int index
)
179 if (INTEL_INFO(dev_priv
)->gen
>= 9)
180 return DP_AUX_CH_DATA(port
, index
);
182 return EDP_PSR_AUX_DATA(index
);
185 static void hsw_psr_enable_sink(struct intel_dp
*intel_dp
)
187 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
188 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
189 struct drm_i915_private
*dev_priv
= to_i915(dev
);
190 uint32_t aux_clock_divider
;
191 i915_reg_t aux_ctl_reg
;
192 static const uint8_t aux_msg
[] = {
193 [0] = DP_AUX_NATIVE_WRITE
<< 4,
194 [1] = DP_SET_POWER
>> 8,
195 [2] = DP_SET_POWER
& 0xff,
197 [4] = DP_SET_POWER_D0
,
199 enum port port
= dig_port
->port
;
203 BUILD_BUG_ON(sizeof(aux_msg
) > 20);
205 aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, 0);
207 /* Enable AUX frame sync at sink */
208 if (dev_priv
->psr
.aux_frame_sync
)
209 drm_dp_dpcd_writeb(&intel_dp
->aux
,
210 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF
,
211 DP_AUX_FRAME_SYNC_ENABLE
);
212 /* Enable ALPM at sink for psr2 */
213 if (dev_priv
->psr
.psr2_support
&& dev_priv
->psr
.alpm
)
214 drm_dp_dpcd_writeb(&intel_dp
->aux
,
215 DP_RECEIVER_ALPM_CONFIG
,
217 if (dev_priv
->psr
.link_standby
)
218 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
219 DP_PSR_ENABLE
| DP_PSR_MAIN_LINK_ACTIVE
);
221 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
,
224 aux_ctl_reg
= psr_aux_ctl_reg(dev_priv
, port
);
226 /* Setup AUX registers */
227 for (i
= 0; i
< sizeof(aux_msg
); i
+= 4)
228 I915_WRITE(psr_aux_data_reg(dev_priv
, port
, i
>> 2),
229 intel_dp_pack_aux(&aux_msg
[i
], sizeof(aux_msg
) - i
));
231 aux_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
, 0, sizeof(aux_msg
),
233 I915_WRITE(aux_ctl_reg
, aux_ctl
);
236 static void vlv_psr_enable_source(struct intel_dp
*intel_dp
)
238 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
239 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
240 struct drm_i915_private
*dev_priv
= to_i915(dev
);
241 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
242 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
244 /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
245 I915_WRITE(VLV_PSRCTL(pipe
),
246 VLV_EDP_PSR_MODE_SW_TIMER
|
247 VLV_EDP_PSR_SRC_TRANSMITTER_STATE
|
251 static void vlv_psr_activate(struct intel_dp
*intel_dp
)
253 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
254 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
255 struct drm_i915_private
*dev_priv
= to_i915(dev
);
256 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
257 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
259 /* Let's do the transition from PSR_state 1 to PSR_state 2
260 * that is PSR transition to active - static frame transmission.
261 * Then Hardware is responsible for the transition to PSR_state 3
262 * that is PSR active - no Remote Frame Buffer (RFB) update.
264 I915_WRITE(VLV_PSRCTL(pipe
), I915_READ(VLV_PSRCTL(pipe
)) |
265 VLV_EDP_PSR_ACTIVE_ENTRY
);
268 static void intel_enable_source_psr1(struct intel_dp
*intel_dp
)
270 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
271 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
272 struct drm_i915_private
*dev_priv
= to_i915(dev
);
274 uint32_t max_sleep_time
= 0x1f;
276 * Let's respect VBT in case VBT asks a higher idle_frame value.
277 * Let's use 6 as the minimum to cover all known cases including
278 * the off-by-one issue that HW has in some cases. Also there are
279 * cases where sink should be able to train
280 * with the 5 or 6 idle patterns.
282 uint32_t idle_frames
= max(6, dev_priv
->vbt
.psr
.idle_frames
);
283 uint32_t val
= EDP_PSR_ENABLE
;
285 val
|= max_sleep_time
<< EDP_PSR_MAX_SLEEP_TIME_SHIFT
;
286 val
|= idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
;
288 if (IS_HASWELL(dev_priv
))
289 val
|= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES
;
291 if (dev_priv
->psr
.link_standby
)
292 val
|= EDP_PSR_LINK_STANDBY
;
294 if (dev_priv
->vbt
.psr
.tp1_wakeup_time
> 5)
295 val
|= EDP_PSR_TP1_TIME_2500us
;
296 else if (dev_priv
->vbt
.psr
.tp1_wakeup_time
> 1)
297 val
|= EDP_PSR_TP1_TIME_500us
;
298 else if (dev_priv
->vbt
.psr
.tp1_wakeup_time
> 0)
299 val
|= EDP_PSR_TP1_TIME_100us
;
301 val
|= EDP_PSR_TP1_TIME_0us
;
303 if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 5)
304 val
|= EDP_PSR_TP2_TP3_TIME_2500us
;
305 else if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 1)
306 val
|= EDP_PSR_TP2_TP3_TIME_500us
;
307 else if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 0)
308 val
|= EDP_PSR_TP2_TP3_TIME_100us
;
310 val
|= EDP_PSR_TP2_TP3_TIME_0us
;
312 if (intel_dp_source_supports_hbr2(intel_dp
) &&
313 drm_dp_tps3_supported(intel_dp
->dpcd
))
314 val
|= EDP_PSR_TP1_TP3_SEL
;
316 val
|= EDP_PSR_TP1_TP2_SEL
;
318 I915_WRITE(EDP_PSR_CTL
, val
);
321 static void intel_enable_source_psr2(struct intel_dp
*intel_dp
)
323 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
324 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
325 struct drm_i915_private
*dev_priv
= to_i915(dev
);
327 * Let's respect VBT in case VBT asks a higher idle_frame value.
328 * Let's use 6 as the minimum to cover all known cases including
329 * the off-by-one issue that HW has in some cases. Also there are
330 * cases where sink should be able to train
331 * with the 5 or 6 idle patterns.
333 uint32_t idle_frames
= max(6, dev_priv
->vbt
.psr
.idle_frames
);
336 val
= idle_frames
<< EDP_PSR_IDLE_FRAME_SHIFT
;
338 /* FIXME: selective update is probably totally broken because it doesn't
339 * mesh at all with our frontbuffer tracking. And the hw alone isn't
341 val
|= EDP_PSR2_ENABLE
|
342 EDP_SU_TRACK_ENABLE
|
343 EDP_FRAMES_BEFORE_SU_ENTRY
;
345 if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 5)
346 val
|= EDP_PSR2_TP2_TIME_2500
;
347 else if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 1)
348 val
|= EDP_PSR2_TP2_TIME_500
;
349 else if (dev_priv
->vbt
.psr
.tp2_tp3_wakeup_time
> 0)
350 val
|= EDP_PSR2_TP2_TIME_100
;
352 val
|= EDP_PSR2_TP2_TIME_50
;
354 I915_WRITE(EDP_PSR2_CTL
, val
);
357 static void hsw_psr_enable_source(struct intel_dp
*intel_dp
)
359 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
360 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
361 struct drm_i915_private
*dev_priv
= to_i915(dev
);
363 /* psr1 and psr2 are mutually exclusive.*/
364 if (dev_priv
->psr
.psr2_support
)
365 intel_enable_source_psr2(intel_dp
);
367 intel_enable_source_psr1(intel_dp
);
370 static bool intel_psr_match_conditions(struct intel_dp
*intel_dp
)
372 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
373 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
374 struct drm_i915_private
*dev_priv
= to_i915(dev
);
375 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
376 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
377 const struct drm_display_mode
*adjusted_mode
=
378 &intel_crtc
->config
->base
.adjusted_mode
;
381 lockdep_assert_held(&dev_priv
->psr
.lock
);
382 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
383 WARN_ON(!drm_modeset_is_locked(&crtc
->mutex
));
385 dev_priv
->psr
.source_ok
= false;
388 * HSW spec explicitly says PSR is tied to port A.
389 * BDW+ platforms with DDI implementation of PSR have different
390 * PSR registers per transcoder and we only implement transcoder EDP
391 * ones. Since by Display design transcoder EDP is tied to port A
392 * we can safely escape based on the port A.
394 if (HAS_DDI(dev_priv
) && dig_port
->port
!= PORT_A
) {
395 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
399 if (!i915
.enable_psr
) {
400 DRM_DEBUG_KMS("PSR disable by flag\n");
404 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
405 !dev_priv
->psr
.link_standby
) {
406 DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
410 if (IS_HASWELL(dev_priv
) &&
411 I915_READ(HSW_STEREO_3D_CTL(intel_crtc
->config
->cpu_transcoder
)) &
413 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
417 if (IS_HASWELL(dev_priv
) &&
418 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
419 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
423 psr_setup_time
= drm_dp_psr_setup_time(intel_dp
->psr_dpcd
);
424 if (psr_setup_time
< 0) {
425 DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
426 intel_dp
->psr_dpcd
[1]);
430 if (intel_usecs_to_scanlines(adjusted_mode
, psr_setup_time
) >
431 adjusted_mode
->crtc_vtotal
- adjusted_mode
->crtc_vdisplay
- 1) {
432 DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
437 /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
438 if (dev_priv
->psr
.psr2_support
&&
439 (intel_crtc
->config
->pipe_src_w
> 3200 ||
440 intel_crtc
->config
->pipe_src_h
> 2000)) {
441 dev_priv
->psr
.psr2_support
= false;
446 * FIXME:enable psr2 only for y-cordinate psr2 panels
447 * After gtc implementation , remove this restriction.
449 if (!dev_priv
->psr
.y_cord_support
&& dev_priv
->psr
.psr2_support
) {
450 DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
454 dev_priv
->psr
.source_ok
= true;
458 static void intel_psr_activate(struct intel_dp
*intel_dp
)
460 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
461 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
462 struct drm_i915_private
*dev_priv
= to_i915(dev
);
464 if (dev_priv
->psr
.psr2_support
)
465 WARN_ON(I915_READ(EDP_PSR2_CTL
) & EDP_PSR2_ENABLE
);
467 WARN_ON(I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
);
468 WARN_ON(dev_priv
->psr
.active
);
469 lockdep_assert_held(&dev_priv
->psr
.lock
);
471 /* Enable/Re-enable PSR on the host */
472 if (HAS_DDI(dev_priv
))
473 /* On HSW+ after we enable PSR on source it will activate it
474 * as soon as it match configure idle_frame count. So
475 * we just actually enable it here on activation time.
477 hsw_psr_enable_source(intel_dp
);
479 vlv_psr_activate(intel_dp
);
481 dev_priv
->psr
.active
= true;
485 * intel_psr_enable - Enable PSR
486 * @intel_dp: Intel DP
488 * This function can only be called after the pipe is fully trained and enabled.
490 void intel_psr_enable(struct intel_dp
*intel_dp
)
492 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
493 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
494 struct drm_i915_private
*dev_priv
= to_i915(dev
);
495 struct intel_crtc
*crtc
= to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
496 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
499 if (!HAS_PSR(dev_priv
)) {
500 DRM_DEBUG_KMS("PSR not supported on this platform\n");
504 if (!is_edp_psr(intel_dp
)) {
505 DRM_DEBUG_KMS("PSR not supported by this panel\n");
509 mutex_lock(&dev_priv
->psr
.lock
);
510 if (dev_priv
->psr
.enabled
) {
511 DRM_DEBUG_KMS("PSR already in use\n");
515 if (!intel_psr_match_conditions(intel_dp
))
518 dev_priv
->psr
.busy_frontbuffer_bits
= 0;
520 if (HAS_DDI(dev_priv
)) {
521 if (dev_priv
->psr
.psr2_support
) {
522 skl_psr_setup_su_vsc(intel_dp
);
523 chicken
= PSR2_VSC_ENABLE_PROG_HEADER
;
524 if (dev_priv
->psr
.y_cord_support
)
525 chicken
|= PSR2_ADD_VERTICAL_LINE_COUNT
;
526 I915_WRITE(CHICKEN_TRANS(cpu_transcoder
), chicken
);
527 I915_WRITE(EDP_PSR_DEBUG_CTL
,
528 EDP_PSR_DEBUG_MASK_MEMUP
|
529 EDP_PSR_DEBUG_MASK_HPD
|
530 EDP_PSR_DEBUG_MASK_LPSP
|
531 EDP_PSR_DEBUG_MASK_MAX_SLEEP
|
532 EDP_PSR_DEBUG_MASK_DISP_REG_WRITE
);
534 /* set up vsc header for psr1 */
535 hsw_psr_setup_vsc(intel_dp
);
537 * Per Spec: Avoid continuous PSR exit by masking MEMUP
538 * and HPD. also mask LPSP to avoid dependency on other
539 * drivers that might block runtime_pm besides
540 * preventing other hw tracking issues now we can rely
541 * on frontbuffer tracking.
543 I915_WRITE(EDP_PSR_DEBUG_CTL
,
544 EDP_PSR_DEBUG_MASK_MEMUP
|
545 EDP_PSR_DEBUG_MASK_HPD
|
546 EDP_PSR_DEBUG_MASK_LPSP
);
549 /* Enable PSR on the panel */
550 hsw_psr_enable_sink(intel_dp
);
552 if (INTEL_GEN(dev_priv
) >= 9)
553 intel_psr_activate(intel_dp
);
555 vlv_psr_setup_vsc(intel_dp
);
557 /* Enable PSR on the panel */
558 vlv_psr_enable_sink(intel_dp
);
560 /* On HSW+ enable_source also means go to PSR entry/active
561 * state as soon as idle_frame achieved and here would be
562 * to soon. However on VLV enable_source just enable PSR
563 * but let it on inactive state. So we might do this prior
564 * to active transition, i.e. here.
566 vlv_psr_enable_source(intel_dp
);
570 * FIXME: Activation should happen immediately since this function
571 * is just called after pipe is fully trained and enabled.
572 * However on every platform we face issues when first activation
573 * follows a modeset so quickly.
574 * - On VLV/CHV we get bank screen on first activation
575 * - On HSW/BDW we get a recoverable frozen screen until next
576 * exit-activate sequence.
578 if (INTEL_GEN(dev_priv
) < 9)
579 schedule_delayed_work(&dev_priv
->psr
.work
,
580 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
582 dev_priv
->psr
.enabled
= intel_dp
;
584 mutex_unlock(&dev_priv
->psr
.lock
);
587 static void vlv_psr_disable(struct intel_dp
*intel_dp
)
589 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
590 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
591 struct drm_i915_private
*dev_priv
= to_i915(dev
);
592 struct intel_crtc
*intel_crtc
=
593 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
596 if (dev_priv
->psr
.active
) {
597 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
598 if (intel_wait_for_register(dev_priv
,
599 VLV_PSRSTAT(intel_crtc
->pipe
),
600 VLV_EDP_PSR_IN_TRANS
,
603 WARN(1, "PSR transition took longer than expected\n");
605 val
= I915_READ(VLV_PSRCTL(intel_crtc
->pipe
));
606 val
&= ~VLV_EDP_PSR_ACTIVE_ENTRY
;
607 val
&= ~VLV_EDP_PSR_ENABLE
;
608 val
&= ~VLV_EDP_PSR_MODE_MASK
;
609 I915_WRITE(VLV_PSRCTL(intel_crtc
->pipe
), val
);
611 dev_priv
->psr
.active
= false;
613 WARN_ON(vlv_is_psr_active_on_pipe(dev
, intel_crtc
->pipe
));
617 static void hsw_psr_disable(struct intel_dp
*intel_dp
)
619 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
620 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
621 struct drm_i915_private
*dev_priv
= to_i915(dev
);
623 if (dev_priv
->psr
.active
) {
627 if (dev_priv
->psr
.aux_frame_sync
)
628 drm_dp_dpcd_writeb(&intel_dp
->aux
,
629 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF
,
632 if (dev_priv
->psr
.psr2_support
) {
633 psr_ctl
= EDP_PSR2_CTL
;
634 psr_status_mask
= EDP_PSR2_STATUS_STATE_MASK
;
638 ~(EDP_PSR2_ENABLE
| EDP_SU_TRACK_ENABLE
));
641 psr_ctl
= EDP_PSR_STATUS_CTL
;
642 psr_status_mask
= EDP_PSR_STATUS_STATE_MASK
;
645 I915_READ(psr_ctl
) & ~EDP_PSR_ENABLE
);
648 /* Wait till PSR is idle */
649 if (intel_wait_for_register(dev_priv
,
650 psr_ctl
, psr_status_mask
, 0,
652 DRM_ERROR("Timed out waiting for PSR Idle State\n");
654 dev_priv
->psr
.active
= false;
656 if (dev_priv
->psr
.psr2_support
)
657 WARN_ON(I915_READ(EDP_PSR2_CTL
) & EDP_PSR2_ENABLE
);
659 WARN_ON(I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
);
664 * intel_psr_disable - Disable PSR
665 * @intel_dp: Intel DP
667 * This function needs to be called before disabling pipe.
669 void intel_psr_disable(struct intel_dp
*intel_dp
)
671 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
672 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
673 struct drm_i915_private
*dev_priv
= to_i915(dev
);
675 mutex_lock(&dev_priv
->psr
.lock
);
676 if (!dev_priv
->psr
.enabled
) {
677 mutex_unlock(&dev_priv
->psr
.lock
);
681 /* Disable PSR on Source */
682 if (HAS_DDI(dev_priv
))
683 hsw_psr_disable(intel_dp
);
685 vlv_psr_disable(intel_dp
);
687 /* Disable PSR on Sink */
688 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_PSR_EN_CFG
, 0);
690 dev_priv
->psr
.enabled
= NULL
;
691 mutex_unlock(&dev_priv
->psr
.lock
);
693 cancel_delayed_work_sync(&dev_priv
->psr
.work
);
696 static void intel_psr_work(struct work_struct
*work
)
698 struct drm_i915_private
*dev_priv
=
699 container_of(work
, typeof(*dev_priv
), psr
.work
.work
);
700 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
701 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
702 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
704 /* We have to make sure PSR is ready for re-enable
705 * otherwise it keeps disabled until next full enable/disable cycle.
706 * PSR might take some time to get fully disabled
707 * and be ready for re-enable.
709 if (HAS_DDI(dev_priv
)) {
710 if (dev_priv
->psr
.psr2_support
) {
711 if (intel_wait_for_register(dev_priv
,
713 EDP_PSR2_STATUS_STATE_MASK
,
716 DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n");
720 if (intel_wait_for_register(dev_priv
,
722 EDP_PSR_STATUS_STATE_MASK
,
725 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
730 if (intel_wait_for_register(dev_priv
,
732 VLV_EDP_PSR_IN_TRANS
,
735 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
739 mutex_lock(&dev_priv
->psr
.lock
);
740 intel_dp
= dev_priv
->psr
.enabled
;
746 * The delayed work can race with an invalidate hence we need to
747 * recheck. Since psr_flush first clears this and then reschedules we
748 * won't ever miss a flush when bailing out here.
750 if (dev_priv
->psr
.busy_frontbuffer_bits
)
753 intel_psr_activate(intel_dp
);
755 mutex_unlock(&dev_priv
->psr
.lock
);
758 static void intel_psr_exit(struct drm_i915_private
*dev_priv
)
760 struct intel_dp
*intel_dp
= dev_priv
->psr
.enabled
;
761 struct drm_crtc
*crtc
= dp_to_dig_port(intel_dp
)->base
.base
.crtc
;
762 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
765 if (!dev_priv
->psr
.active
)
768 if (HAS_DDI(dev_priv
)) {
769 if (dev_priv
->psr
.aux_frame_sync
)
770 drm_dp_dpcd_writeb(&intel_dp
->aux
,
771 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF
,
773 if (dev_priv
->psr
.psr2_support
) {
774 val
= I915_READ(EDP_PSR2_CTL
);
775 WARN_ON(!(val
& EDP_PSR2_ENABLE
));
776 I915_WRITE(EDP_PSR2_CTL
, val
& ~EDP_PSR2_ENABLE
);
778 val
= I915_READ(EDP_PSR_CTL
);
779 WARN_ON(!(val
& EDP_PSR_ENABLE
));
780 I915_WRITE(EDP_PSR_CTL
, val
& ~EDP_PSR_ENABLE
);
783 val
= I915_READ(VLV_PSRCTL(pipe
));
785 /* Here we do the transition from PSR_state 3 to PSR_state 5
786 * directly once PSR State 4 that is active with single frame
787 * update can be skipped. PSR_state 5 that is PSR exit then
788 * Hardware is responsible to transition back to PSR_state 1
789 * that is PSR inactive. Same state after
790 * vlv_edp_psr_enable_source.
792 val
&= ~VLV_EDP_PSR_ACTIVE_ENTRY
;
793 I915_WRITE(VLV_PSRCTL(pipe
), val
);
795 /* Send AUX wake up - Spec says after transitioning to PSR
796 * active we have to send AUX wake up by writing 01h in DPCD
797 * 600h of sink device.
798 * XXX: This might slow down the transition, but without this
799 * HW doesn't complete the transition to PSR_state 1 and we
800 * never get the screen updated.
802 drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
806 dev_priv
->psr
.active
= false;
810 * intel_psr_single_frame_update - Single Frame Update
811 * @dev_priv: i915 device
812 * @frontbuffer_bits: frontbuffer plane tracking bits
814 * Some platforms support a single frame update feature that is used to
815 * send and update only one frame on Remote Frame Buffer.
816 * So far it is only implemented for Valleyview and Cherryview because
817 * hardware requires this to be done before a page flip.
819 void intel_psr_single_frame_update(struct drm_i915_private
*dev_priv
,
820 unsigned frontbuffer_bits
)
822 struct drm_crtc
*crtc
;
827 * Single frame update is already supported on BDW+ but it requires
828 * many W/A and it isn't really needed.
830 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
833 mutex_lock(&dev_priv
->psr
.lock
);
834 if (!dev_priv
->psr
.enabled
) {
835 mutex_unlock(&dev_priv
->psr
.lock
);
839 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
840 pipe
= to_intel_crtc(crtc
)->pipe
;
842 if (frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)) {
843 val
= I915_READ(VLV_PSRCTL(pipe
));
846 * We need to set this bit before writing registers for a flip.
847 * This bit will be self-clear when it gets to the PSR active state.
849 I915_WRITE(VLV_PSRCTL(pipe
), val
| VLV_EDP_PSR_SINGLE_FRAME_UPDATE
);
851 mutex_unlock(&dev_priv
->psr
.lock
);
855 * intel_psr_invalidate - Invalidade PSR
856 * @dev_priv: i915 device
857 * @frontbuffer_bits: frontbuffer plane tracking bits
859 * Since the hardware frontbuffer tracking has gaps we need to integrate
860 * with the software frontbuffer tracking. This function gets called every
861 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
862 * disabled if the frontbuffer mask contains a buffer relevant to PSR.
864 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
866 void intel_psr_invalidate(struct drm_i915_private
*dev_priv
,
867 unsigned frontbuffer_bits
)
869 struct drm_crtc
*crtc
;
872 mutex_lock(&dev_priv
->psr
.lock
);
873 if (!dev_priv
->psr
.enabled
) {
874 mutex_unlock(&dev_priv
->psr
.lock
);
878 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
879 pipe
= to_intel_crtc(crtc
)->pipe
;
881 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
882 dev_priv
->psr
.busy_frontbuffer_bits
|= frontbuffer_bits
;
884 if (frontbuffer_bits
)
885 intel_psr_exit(dev_priv
);
887 mutex_unlock(&dev_priv
->psr
.lock
);
891 * intel_psr_flush - Flush PSR
892 * @dev_priv: i915 device
893 * @frontbuffer_bits: frontbuffer plane tracking bits
894 * @origin: which operation caused the flush
896 * Since the hardware frontbuffer tracking has gaps we need to integrate
897 * with the software frontbuffer tracking. This function gets called every
898 * time frontbuffer rendering has completed and flushed out to memory. PSR
899 * can be enabled again if no other frontbuffer relevant to PSR is dirty.
901 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
903 void intel_psr_flush(struct drm_i915_private
*dev_priv
,
904 unsigned frontbuffer_bits
, enum fb_op_origin origin
)
906 struct drm_crtc
*crtc
;
909 mutex_lock(&dev_priv
->psr
.lock
);
910 if (!dev_priv
->psr
.enabled
) {
911 mutex_unlock(&dev_priv
->psr
.lock
);
915 crtc
= dp_to_dig_port(dev_priv
->psr
.enabled
)->base
.base
.crtc
;
916 pipe
= to_intel_crtc(crtc
)->pipe
;
918 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
919 dev_priv
->psr
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
921 /* By definition flush = invalidate + flush */
922 if (frontbuffer_bits
)
923 intel_psr_exit(dev_priv
);
925 if (!dev_priv
->psr
.active
&& !dev_priv
->psr
.busy_frontbuffer_bits
)
926 if (!work_busy(&dev_priv
->psr
.work
.work
))
927 schedule_delayed_work(&dev_priv
->psr
.work
,
928 msecs_to_jiffies(100));
929 mutex_unlock(&dev_priv
->psr
.lock
);
933 * intel_psr_init - Init basic PSR work and mutex.
934 * @dev_priv: i915 device private
936 * This function is called only once at driver load to initialize basic
939 void intel_psr_init(struct drm_i915_private
*dev_priv
)
941 dev_priv
->psr_mmio_base
= IS_HASWELL(dev_priv
) ?
942 HSW_EDP_PSR_BASE
: BDW_EDP_PSR_BASE
;
944 /* Per platform default: all disabled. */
945 if (i915
.enable_psr
== -1)
948 /* Set link_standby x link_off defaults */
949 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
950 /* HSW and BDW require workarounds that we don't implement. */
951 dev_priv
->psr
.link_standby
= false;
952 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
953 /* On VLV and CHV only standby mode is supported. */
954 dev_priv
->psr
.link_standby
= true;
956 /* For new platforms let's respect VBT back again */
957 dev_priv
->psr
.link_standby
= dev_priv
->vbt
.psr
.full_link
;
959 /* Override link_standby x link_off defaults */
960 if (i915
.enable_psr
== 2 && !dev_priv
->psr
.link_standby
) {
961 DRM_DEBUG_KMS("PSR: Forcing link standby\n");
962 dev_priv
->psr
.link_standby
= true;
964 if (i915
.enable_psr
== 3 && dev_priv
->psr
.link_standby
) {
965 DRM_DEBUG_KMS("PSR: Forcing main link off\n");
966 dev_priv
->psr
.link_standby
= false;
969 INIT_DELAYED_WORK(&dev_priv
->psr
.work
, intel_psr_work
);
970 mutex_init(&dev_priv
->psr
.lock
);