4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <drm/i915_drm.h>
32 #include "intel_drv.h"
34 /* Limits for overlay size. According to intel doc, the real limits are:
35 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
36 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
37 * the mininum of both. */
38 #define IMAGE_MAX_WIDTH 2048
39 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
40 /* on 830 and 845 these large limits result in the card hanging */
41 #define IMAGE_MAX_WIDTH_LEGACY 1024
42 #define IMAGE_MAX_HEIGHT_LEGACY 1088
44 /* overlay register definitions */
46 #define OCMD_TILED_SURFACE (0x1<<19)
47 #define OCMD_MIRROR_MASK (0x3<<17)
48 #define OCMD_MIRROR_MODE (0x3<<17)
49 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
50 #define OCMD_MIRROR_VERTICAL (0x2<<17)
51 #define OCMD_MIRROR_BOTH (0x3<<17)
52 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
53 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
54 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
55 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
56 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
57 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
58 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
59 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
60 #define OCMD_YUV_422_PACKED (0x8<<10)
61 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
62 #define OCMD_YUV_420_PLANAR (0xc<<10)
63 #define OCMD_YUV_422_PLANAR (0xd<<10)
64 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
65 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
66 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
67 #define OCMD_BUF_TYPE_MASK (0x1<<5)
68 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
69 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
70 #define OCMD_TEST_MODE (0x1<<4)
71 #define OCMD_BUFFER_SELECT (0x3<<2)
72 #define OCMD_BUFFER0 (0x0<<2)
73 #define OCMD_BUFFER1 (0x1<<2)
74 #define OCMD_FIELD_SELECT (0x1<<2)
75 #define OCMD_FIELD0 (0x0<<1)
76 #define OCMD_FIELD1 (0x1<<1)
77 #define OCMD_ENABLE (0x1<<0)
79 /* OCONFIG register */
80 #define OCONF_PIPE_MASK (0x1<<18)
81 #define OCONF_PIPE_A (0x0<<18)
82 #define OCONF_PIPE_B (0x1<<18)
83 #define OCONF_GAMMA2_ENABLE (0x1<<16)
84 #define OCONF_CSC_MODE_BT601 (0x0<<5)
85 #define OCONF_CSC_MODE_BT709 (0x1<<5)
86 #define OCONF_CSC_BYPASS (0x1<<4)
87 #define OCONF_CC_OUT_8BIT (0x1<<3)
88 #define OCONF_TEST_MODE (0x1<<2)
89 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
90 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
92 /* DCLRKM (dst-key) register */
93 #define DST_KEY_ENABLE (0x1<<31)
94 #define CLK_RGB24_MASK 0x0
95 #define CLK_RGB16_MASK 0x070307
96 #define CLK_RGB15_MASK 0x070707
97 #define CLK_RGB8I_MASK 0xffffff
99 #define RGB16_TO_COLORKEY(c) \
100 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
101 #define RGB15_TO_COLORKEY(c) \
102 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
104 /* overlay flip addr flag */
105 #define OFC_UPDATE 0x1
107 /* polyphase filter coefficients */
108 #define N_HORIZ_Y_TAPS 5
109 #define N_VERT_Y_TAPS 3
110 #define N_HORIZ_UV_TAPS 3
111 #define N_VERT_UV_TAPS 3
115 /* memory bufferd overlay registers */
116 struct overlay_registers
{
144 u32 RESERVED1
; /* 0x6C */
157 u32 FASTHSCALE
; /* 0xA0 */
158 u32 UVSCALEV
; /* 0xA4 */
159 u32 RESERVEDC
[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
160 u16 Y_VCOEFS
[N_VERT_Y_TAPS
* N_PHASES
]; /* 0x200 */
161 u16 RESERVEDD
[0x100 / 2 - N_VERT_Y_TAPS
* N_PHASES
];
162 u16 Y_HCOEFS
[N_HORIZ_Y_TAPS
* N_PHASES
]; /* 0x300 */
163 u16 RESERVEDE
[0x200 / 2 - N_HORIZ_Y_TAPS
* N_PHASES
];
164 u16 UV_VCOEFS
[N_VERT_UV_TAPS
* N_PHASES
]; /* 0x500 */
165 u16 RESERVEDF
[0x100 / 2 - N_VERT_UV_TAPS
* N_PHASES
];
166 u16 UV_HCOEFS
[N_HORIZ_UV_TAPS
* N_PHASES
]; /* 0x600 */
167 u16 RESERVEDG
[0x100 / 2 - N_HORIZ_UV_TAPS
* N_PHASES
];
170 struct intel_overlay
{
171 struct drm_device
*dev
;
172 struct intel_crtc
*crtc
;
173 struct drm_i915_gem_object
*vid_bo
;
174 struct drm_i915_gem_object
*old_vid_bo
;
177 u32 pfit_vscale_ratio
; /* shifted-point number, (1<<12) == 1.0 */
179 u32 brightness
, contrast
, saturation
;
180 u32 old_xscale
, old_yscale
;
181 /* register access */
183 struct drm_i915_gem_object
*reg_bo
;
185 uint32_t last_flip_req
;
186 void (*flip_tail
)(struct intel_overlay
*);
189 static struct overlay_registers __iomem
*
190 intel_overlay_map_regs(struct intel_overlay
*overlay
)
192 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
193 struct overlay_registers __iomem
*regs
;
195 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
196 regs
= (struct overlay_registers __iomem
*)overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
198 regs
= io_mapping_map_wc(dev_priv
->mm
.gtt_mapping
,
199 overlay
->reg_bo
->gtt_offset
);
204 static void intel_overlay_unmap_regs(struct intel_overlay
*overlay
,
205 struct overlay_registers __iomem
*regs
)
207 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
208 io_mapping_unmap(regs
);
211 static int intel_overlay_do_wait_request(struct intel_overlay
*overlay
,
212 struct drm_i915_gem_request
*request
,
213 void (*tail
)(struct intel_overlay
*))
215 struct drm_device
*dev
= overlay
->dev
;
216 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
217 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
220 BUG_ON(overlay
->last_flip_req
);
221 ret
= i915_add_request(ring
, NULL
, request
);
226 overlay
->last_flip_req
= request
->seqno
;
227 overlay
->flip_tail
= tail
;
228 ret
= i915_wait_seqno(ring
, overlay
->last_flip_req
);
231 i915_gem_retire_requests(dev
);
233 overlay
->last_flip_req
= 0;
237 /* Workaround for i830 bug where pipe a must be enable to change control regs */
239 i830_activate_pipe_a(struct drm_device
*dev
)
241 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
242 struct intel_crtc
*crtc
;
243 struct drm_crtc_helper_funcs
*crtc_funcs
;
244 struct drm_display_mode vesa_640x480
= {
245 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 25175, 640, 656,
246 752, 800, 0, 480, 489, 492, 525, 0,
247 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
)
250 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[0]);
251 if (crtc
->dpms_mode
== DRM_MODE_DPMS_ON
)
254 /* most i8xx have pipe a forced on, so don't trust dpms mode */
255 if (I915_READ(_PIPEACONF
) & PIPECONF_ENABLE
)
258 crtc_funcs
= crtc
->base
.helper_private
;
259 if (crtc_funcs
->dpms
== NULL
)
262 DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
264 mode
= drm_mode_duplicate(dev
, &vesa_640x480
);
266 if (!drm_crtc_helper_set_mode(&crtc
->base
, mode
,
267 crtc
->base
.x
, crtc
->base
.y
,
271 crtc_funcs
->dpms(&crtc
->base
, DRM_MODE_DPMS_ON
);
276 i830_deactivate_pipe_a(struct drm_device
*dev
)
278 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
279 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[0];
280 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
282 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
285 /* overlay needs to be disable in OCMD reg */
286 static int intel_overlay_on(struct intel_overlay
*overlay
)
288 struct drm_device
*dev
= overlay
->dev
;
289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
290 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
291 struct drm_i915_gem_request
*request
;
292 int pipe_a_quirk
= 0;
295 BUG_ON(overlay
->active
);
299 pipe_a_quirk
= i830_activate_pipe_a(dev
);
300 if (pipe_a_quirk
< 0)
304 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
305 if (request
== NULL
) {
310 ret
= intel_ring_begin(ring
, 4);
316 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_ON
);
317 intel_ring_emit(ring
, overlay
->flip_addr
| OFC_UPDATE
);
318 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
319 intel_ring_emit(ring
, MI_NOOP
);
320 intel_ring_advance(ring
);
322 ret
= intel_overlay_do_wait_request(overlay
, request
, NULL
);
325 i830_deactivate_pipe_a(dev
);
330 /* overlay needs to be enabled in OCMD reg */
331 static int intel_overlay_continue(struct intel_overlay
*overlay
,
332 bool load_polyphase_filter
)
334 struct drm_device
*dev
= overlay
->dev
;
335 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
336 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
337 struct drm_i915_gem_request
*request
;
338 u32 flip_addr
= overlay
->flip_addr
;
342 BUG_ON(!overlay
->active
);
344 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
348 if (load_polyphase_filter
)
349 flip_addr
|= OFC_UPDATE
;
351 /* check for underruns */
352 tmp
= I915_READ(DOVSTA
);
354 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp
);
356 ret
= intel_ring_begin(ring
, 2);
361 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
362 intel_ring_emit(ring
, flip_addr
);
363 intel_ring_advance(ring
);
365 ret
= i915_add_request(ring
, NULL
, request
);
371 overlay
->last_flip_req
= request
->seqno
;
375 static void intel_overlay_release_old_vid_tail(struct intel_overlay
*overlay
)
377 struct drm_i915_gem_object
*obj
= overlay
->old_vid_bo
;
379 i915_gem_object_unpin(obj
);
380 drm_gem_object_unreference(&obj
->base
);
382 overlay
->old_vid_bo
= NULL
;
385 static void intel_overlay_off_tail(struct intel_overlay
*overlay
)
387 struct drm_i915_gem_object
*obj
= overlay
->vid_bo
;
389 /* never have the overlay hw on without showing a frame */
390 BUG_ON(!overlay
->vid_bo
);
392 i915_gem_object_unpin(obj
);
393 drm_gem_object_unreference(&obj
->base
);
394 overlay
->vid_bo
= NULL
;
396 overlay
->crtc
->overlay
= NULL
;
397 overlay
->crtc
= NULL
;
401 /* overlay needs to be disabled in OCMD reg */
402 static int intel_overlay_off(struct intel_overlay
*overlay
)
404 struct drm_device
*dev
= overlay
->dev
;
405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
406 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
407 u32 flip_addr
= overlay
->flip_addr
;
408 struct drm_i915_gem_request
*request
;
411 BUG_ON(!overlay
->active
);
413 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
417 /* According to intel docs the overlay hw may hang (when switching
418 * off) without loading the filter coeffs. It is however unclear whether
419 * this applies to the disabling of the overlay or to the switching off
420 * of the hw. Do it in both cases */
421 flip_addr
|= OFC_UPDATE
;
423 ret
= intel_ring_begin(ring
, 6);
428 /* wait for overlay to go idle */
429 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
430 intel_ring_emit(ring
, flip_addr
);
431 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
432 /* turn overlay off */
433 intel_ring_emit(ring
, MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
434 intel_ring_emit(ring
, flip_addr
);
435 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
436 intel_ring_advance(ring
);
438 return intel_overlay_do_wait_request(overlay
, request
,
439 intel_overlay_off_tail
);
442 /* recover from an interruption due to a signal
443 * We have to be careful not to repeat work forever an make forward progess. */
444 static int intel_overlay_recover_from_interrupt(struct intel_overlay
*overlay
)
446 struct drm_device
*dev
= overlay
->dev
;
447 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
448 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
451 if (overlay
->last_flip_req
== 0)
454 ret
= i915_wait_seqno(ring
, overlay
->last_flip_req
);
457 i915_gem_retire_requests(dev
);
459 if (overlay
->flip_tail
)
460 overlay
->flip_tail(overlay
);
462 overlay
->last_flip_req
= 0;
466 /* Wait for pending overlay flip and release old frame.
467 * Needs to be called before the overlay register are changed
468 * via intel_overlay_(un)map_regs
470 static int intel_overlay_release_old_vid(struct intel_overlay
*overlay
)
472 struct drm_device
*dev
= overlay
->dev
;
473 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
474 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
477 /* Only wait if there is actually an old frame to release to
478 * guarantee forward progress.
480 if (!overlay
->old_vid_bo
)
483 if (I915_READ(ISR
) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT
) {
484 struct drm_i915_gem_request
*request
;
486 /* synchronous slowpath */
487 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
491 ret
= intel_ring_begin(ring
, 2);
497 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
498 intel_ring_emit(ring
, MI_NOOP
);
499 intel_ring_advance(ring
);
501 ret
= intel_overlay_do_wait_request(overlay
, request
,
502 intel_overlay_release_old_vid_tail
);
507 intel_overlay_release_old_vid_tail(overlay
);
511 struct put_image_params
{
528 static int packed_depth_bytes(u32 format
)
530 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
531 case I915_OVERLAY_YUV422
:
533 case I915_OVERLAY_YUV411
:
534 /* return 6; not implemented */
540 static int packed_width_bytes(u32 format
, short width
)
542 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
543 case I915_OVERLAY_YUV422
:
550 static int uv_hsubsampling(u32 format
)
552 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
553 case I915_OVERLAY_YUV422
:
554 case I915_OVERLAY_YUV420
:
556 case I915_OVERLAY_YUV411
:
557 case I915_OVERLAY_YUV410
:
564 static int uv_vsubsampling(u32 format
)
566 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
567 case I915_OVERLAY_YUV420
:
568 case I915_OVERLAY_YUV410
:
570 case I915_OVERLAY_YUV422
:
571 case I915_OVERLAY_YUV411
:
578 static u32
calc_swidthsw(struct drm_device
*dev
, u32 offset
, u32 width
)
580 u32 mask
, shift
, ret
;
588 ret
= ((offset
+ width
+ mask
) >> shift
) - (offset
>> shift
);
595 static const u16 y_static_hcoeffs
[N_HORIZ_Y_TAPS
* N_PHASES
] = {
596 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
597 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
598 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
599 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
600 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
601 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
602 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
603 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
604 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
605 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
606 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
607 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
608 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
609 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
610 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
611 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
612 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
615 static const u16 uv_static_hcoeffs
[N_HORIZ_UV_TAPS
* N_PHASES
] = {
616 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
617 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
618 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
619 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
620 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
621 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
622 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
623 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
624 0x3000, 0x0800, 0x3000
627 static void update_polyphase_filter(struct overlay_registers __iomem
*regs
)
629 memcpy_toio(regs
->Y_HCOEFS
, y_static_hcoeffs
, sizeof(y_static_hcoeffs
));
630 memcpy_toio(regs
->UV_HCOEFS
, uv_static_hcoeffs
,
631 sizeof(uv_static_hcoeffs
));
634 static bool update_scaling_factors(struct intel_overlay
*overlay
,
635 struct overlay_registers __iomem
*regs
,
636 struct put_image_params
*params
)
638 /* fixed point with a 12 bit shift */
639 u32 xscale
, yscale
, xscale_UV
, yscale_UV
;
641 #define FRACT_MASK 0xfff
642 bool scale_changed
= false;
643 int uv_hscale
= uv_hsubsampling(params
->format
);
644 int uv_vscale
= uv_vsubsampling(params
->format
);
646 if (params
->dst_w
> 1)
647 xscale
= ((params
->src_scan_w
- 1) << FP_SHIFT
)
650 xscale
= 1 << FP_SHIFT
;
652 if (params
->dst_h
> 1)
653 yscale
= ((params
->src_scan_h
- 1) << FP_SHIFT
)
656 yscale
= 1 << FP_SHIFT
;
658 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
659 xscale_UV
= xscale
/uv_hscale
;
660 yscale_UV
= yscale
/uv_vscale
;
661 /* make the Y scale to UV scale ratio an exact multiply */
662 xscale
= xscale_UV
* uv_hscale
;
663 yscale
= yscale_UV
* uv_vscale
;
669 if (xscale
!= overlay
->old_xscale
|| yscale
!= overlay
->old_yscale
)
670 scale_changed
= true;
671 overlay
->old_xscale
= xscale
;
672 overlay
->old_yscale
= yscale
;
674 iowrite32(((yscale
& FRACT_MASK
) << 20) |
675 ((xscale
>> FP_SHIFT
) << 16) |
676 ((xscale
& FRACT_MASK
) << 3),
679 iowrite32(((yscale_UV
& FRACT_MASK
) << 20) |
680 ((xscale_UV
>> FP_SHIFT
) << 16) |
681 ((xscale_UV
& FRACT_MASK
) << 3),
684 iowrite32((((yscale
>> FP_SHIFT
) << 16) |
685 ((yscale_UV
>> FP_SHIFT
) << 0)),
689 update_polyphase_filter(regs
);
691 return scale_changed
;
694 static void update_colorkey(struct intel_overlay
*overlay
,
695 struct overlay_registers __iomem
*regs
)
697 u32 key
= overlay
->color_key
;
699 switch (overlay
->crtc
->base
.fb
->bits_per_pixel
) {
701 iowrite32(0, ®s
->DCLRKV
);
702 iowrite32(CLK_RGB8I_MASK
| DST_KEY_ENABLE
, ®s
->DCLRKM
);
706 if (overlay
->crtc
->base
.fb
->depth
== 15) {
707 iowrite32(RGB15_TO_COLORKEY(key
), ®s
->DCLRKV
);
708 iowrite32(CLK_RGB15_MASK
| DST_KEY_ENABLE
,
711 iowrite32(RGB16_TO_COLORKEY(key
), ®s
->DCLRKV
);
712 iowrite32(CLK_RGB16_MASK
| DST_KEY_ENABLE
,
719 iowrite32(key
, ®s
->DCLRKV
);
720 iowrite32(CLK_RGB24_MASK
| DST_KEY_ENABLE
, ®s
->DCLRKM
);
725 static u32
overlay_cmd_reg(struct put_image_params
*params
)
727 u32 cmd
= OCMD_ENABLE
| OCMD_BUF_TYPE_FRAME
| OCMD_BUFFER0
;
729 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
730 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
731 case I915_OVERLAY_YUV422
:
732 cmd
|= OCMD_YUV_422_PLANAR
;
734 case I915_OVERLAY_YUV420
:
735 cmd
|= OCMD_YUV_420_PLANAR
;
737 case I915_OVERLAY_YUV411
:
738 case I915_OVERLAY_YUV410
:
739 cmd
|= OCMD_YUV_410_PLANAR
;
742 } else { /* YUV packed */
743 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
744 case I915_OVERLAY_YUV422
:
745 cmd
|= OCMD_YUV_422_PACKED
;
747 case I915_OVERLAY_YUV411
:
748 cmd
|= OCMD_YUV_411_PACKED
;
752 switch (params
->format
& I915_OVERLAY_SWAP_MASK
) {
753 case I915_OVERLAY_NO_SWAP
:
755 case I915_OVERLAY_UV_SWAP
:
758 case I915_OVERLAY_Y_SWAP
:
761 case I915_OVERLAY_Y_AND_UV_SWAP
:
762 cmd
|= OCMD_Y_AND_UV_SWAP
;
770 static int intel_overlay_do_put_image(struct intel_overlay
*overlay
,
771 struct drm_i915_gem_object
*new_bo
,
772 struct put_image_params
*params
)
775 struct overlay_registers __iomem
*regs
;
776 bool scale_changed
= false;
777 struct drm_device
*dev
= overlay
->dev
;
778 u32 swidth
, swidthsw
, sheight
, ostride
;
780 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
781 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
784 ret
= intel_overlay_release_old_vid(overlay
);
788 ret
= i915_gem_object_pin_to_display_plane(new_bo
, 0, NULL
);
792 ret
= i915_gem_object_put_fence(new_bo
);
796 if (!overlay
->active
) {
798 regs
= intel_overlay_map_regs(overlay
);
803 oconfig
= OCONF_CC_OUT_8BIT
;
804 if (IS_GEN4(overlay
->dev
))
805 oconfig
|= OCONF_CSC_MODE_BT709
;
806 oconfig
|= overlay
->crtc
->pipe
== 0 ?
807 OCONF_PIPE_A
: OCONF_PIPE_B
;
808 iowrite32(oconfig
, ®s
->OCONFIG
);
809 intel_overlay_unmap_regs(overlay
, regs
);
811 ret
= intel_overlay_on(overlay
);
816 regs
= intel_overlay_map_regs(overlay
);
822 iowrite32((params
->dst_y
<< 16) | params
->dst_x
, ®s
->DWINPOS
);
823 iowrite32((params
->dst_h
<< 16) | params
->dst_w
, ®s
->DWINSZ
);
825 if (params
->format
& I915_OVERLAY_YUV_PACKED
)
826 tmp_width
= packed_width_bytes(params
->format
, params
->src_w
);
828 tmp_width
= params
->src_w
;
830 swidth
= params
->src_w
;
831 swidthsw
= calc_swidthsw(overlay
->dev
, params
->offset_Y
, tmp_width
);
832 sheight
= params
->src_h
;
833 iowrite32(new_bo
->gtt_offset
+ params
->offset_Y
, ®s
->OBUF_0Y
);
834 ostride
= params
->stride_Y
;
836 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
837 int uv_hscale
= uv_hsubsampling(params
->format
);
838 int uv_vscale
= uv_vsubsampling(params
->format
);
840 swidth
|= (params
->src_w
/uv_hscale
) << 16;
841 tmp_U
= calc_swidthsw(overlay
->dev
, params
->offset_U
,
842 params
->src_w
/uv_hscale
);
843 tmp_V
= calc_swidthsw(overlay
->dev
, params
->offset_V
,
844 params
->src_w
/uv_hscale
);
845 swidthsw
|= max_t(u32
, tmp_U
, tmp_V
) << 16;
846 sheight
|= (params
->src_h
/uv_vscale
) << 16;
847 iowrite32(new_bo
->gtt_offset
+ params
->offset_U
, ®s
->OBUF_0U
);
848 iowrite32(new_bo
->gtt_offset
+ params
->offset_V
, ®s
->OBUF_0V
);
849 ostride
|= params
->stride_UV
<< 16;
852 iowrite32(swidth
, ®s
->SWIDTH
);
853 iowrite32(swidthsw
, ®s
->SWIDTHSW
);
854 iowrite32(sheight
, ®s
->SHEIGHT
);
855 iowrite32(ostride
, ®s
->OSTRIDE
);
857 scale_changed
= update_scaling_factors(overlay
, regs
, params
);
859 update_colorkey(overlay
, regs
);
861 iowrite32(overlay_cmd_reg(params
), ®s
->OCMD
);
863 intel_overlay_unmap_regs(overlay
, regs
);
865 ret
= intel_overlay_continue(overlay
, scale_changed
);
869 overlay
->old_vid_bo
= overlay
->vid_bo
;
870 overlay
->vid_bo
= new_bo
;
875 i915_gem_object_unpin(new_bo
);
879 int intel_overlay_switch_off(struct intel_overlay
*overlay
)
881 struct overlay_registers __iomem
*regs
;
882 struct drm_device
*dev
= overlay
->dev
;
885 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
886 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
888 ret
= intel_overlay_recover_from_interrupt(overlay
);
892 if (!overlay
->active
)
895 ret
= intel_overlay_release_old_vid(overlay
);
899 regs
= intel_overlay_map_regs(overlay
);
900 iowrite32(0, ®s
->OCMD
);
901 intel_overlay_unmap_regs(overlay
, regs
);
903 ret
= intel_overlay_off(overlay
);
907 intel_overlay_off_tail(overlay
);
911 static int check_overlay_possible_on_crtc(struct intel_overlay
*overlay
,
912 struct intel_crtc
*crtc
)
914 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
919 /* can't use the overlay with double wide pipe */
920 if (INTEL_INFO(overlay
->dev
)->gen
< 4 &&
921 (I915_READ(PIPECONF(crtc
->pipe
)) & (PIPECONF_DOUBLE_WIDE
| PIPECONF_ENABLE
)) != PIPECONF_ENABLE
)
927 static void update_pfit_vscale_ratio(struct intel_overlay
*overlay
)
929 struct drm_device
*dev
= overlay
->dev
;
930 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
931 u32 pfit_control
= I915_READ(PFIT_CONTROL
);
934 /* XXX: This is not the same logic as in the xorg driver, but more in
935 * line with the intel documentation for the i965
937 if (INTEL_INFO(dev
)->gen
>= 4) {
938 /* on i965 use the PGM reg to read out the autoscaler values */
939 ratio
= I915_READ(PFIT_PGM_RATIOS
) >> PFIT_VERT_SCALE_SHIFT_965
;
941 if (pfit_control
& VERT_AUTO_SCALE
)
942 ratio
= I915_READ(PFIT_AUTO_RATIOS
);
944 ratio
= I915_READ(PFIT_PGM_RATIOS
);
945 ratio
>>= PFIT_VERT_SCALE_SHIFT
;
948 overlay
->pfit_vscale_ratio
= ratio
;
951 static int check_overlay_dst(struct intel_overlay
*overlay
,
952 struct drm_intel_overlay_put_image
*rec
)
954 struct drm_display_mode
*mode
= &overlay
->crtc
->base
.mode
;
956 if (rec
->dst_x
< mode
->hdisplay
&&
957 rec
->dst_x
+ rec
->dst_width
<= mode
->hdisplay
&&
958 rec
->dst_y
< mode
->vdisplay
&&
959 rec
->dst_y
+ rec
->dst_height
<= mode
->vdisplay
)
965 static int check_overlay_scaling(struct put_image_params
*rec
)
969 /* downscaling limit is 8.0 */
970 tmp
= ((rec
->src_scan_h
<< 16) / rec
->dst_h
) >> 16;
973 tmp
= ((rec
->src_scan_w
<< 16) / rec
->dst_w
) >> 16;
980 static int check_overlay_src(struct drm_device
*dev
,
981 struct drm_intel_overlay_put_image
*rec
,
982 struct drm_i915_gem_object
*new_bo
)
984 int uv_hscale
= uv_hsubsampling(rec
->flags
);
985 int uv_vscale
= uv_vsubsampling(rec
->flags
);
990 /* check src dimensions */
991 if (IS_845G(dev
) || IS_I830(dev
)) {
992 if (rec
->src_height
> IMAGE_MAX_HEIGHT_LEGACY
||
993 rec
->src_width
> IMAGE_MAX_WIDTH_LEGACY
)
996 if (rec
->src_height
> IMAGE_MAX_HEIGHT
||
997 rec
->src_width
> IMAGE_MAX_WIDTH
)
1001 /* better safe than sorry, use 4 as the maximal subsampling ratio */
1002 if (rec
->src_height
< N_VERT_Y_TAPS
*4 ||
1003 rec
->src_width
< N_HORIZ_Y_TAPS
*4)
1006 /* check alignment constraints */
1007 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
1008 case I915_OVERLAY_RGB
:
1009 /* not implemented */
1012 case I915_OVERLAY_YUV_PACKED
:
1016 depth
= packed_depth_bytes(rec
->flags
);
1020 /* ignore UV planes */
1024 /* check pixel alignment */
1025 if (rec
->offset_Y
% depth
)
1029 case I915_OVERLAY_YUV_PLANAR
:
1030 if (uv_vscale
< 0 || uv_hscale
< 0)
1032 /* no offset restrictions for planar formats */
1039 if (rec
->src_width
% uv_hscale
)
1042 /* stride checking */
1043 if (IS_I830(dev
) || IS_845G(dev
))
1048 if (rec
->stride_Y
& stride_mask
|| rec
->stride_UV
& stride_mask
)
1050 if (IS_GEN4(dev
) && rec
->stride_Y
< 512)
1053 tmp
= (rec
->flags
& I915_OVERLAY_TYPE_MASK
) == I915_OVERLAY_YUV_PLANAR
?
1055 if (rec
->stride_Y
> tmp
|| rec
->stride_UV
> 2*1024)
1058 /* check buffer dimensions */
1059 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
1060 case I915_OVERLAY_RGB
:
1061 case I915_OVERLAY_YUV_PACKED
:
1062 /* always 4 Y values per depth pixels */
1063 if (packed_width_bytes(rec
->flags
, rec
->src_width
) > rec
->stride_Y
)
1066 tmp
= rec
->stride_Y
*rec
->src_height
;
1067 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
1071 case I915_OVERLAY_YUV_PLANAR
:
1072 if (rec
->src_width
> rec
->stride_Y
)
1074 if (rec
->src_width
/uv_hscale
> rec
->stride_UV
)
1077 tmp
= rec
->stride_Y
* rec
->src_height
;
1078 if (rec
->offset_Y
+ tmp
> new_bo
->base
.size
)
1081 tmp
= rec
->stride_UV
* (rec
->src_height
/ uv_vscale
);
1082 if (rec
->offset_U
+ tmp
> new_bo
->base
.size
||
1083 rec
->offset_V
+ tmp
> new_bo
->base
.size
)
1092 * Return the pipe currently connected to the panel fitter,
1093 * or -1 if the panel fitter is not present or not in use
1095 static int intel_panel_fitter_pipe(struct drm_device
*dev
)
1097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1100 /* i830 doesn't have a panel fitter */
1104 pfit_control
= I915_READ(PFIT_CONTROL
);
1106 /* See if the panel fitter is in use */
1107 if ((pfit_control
& PFIT_ENABLE
) == 0)
1110 /* 965 can place panel fitter on either pipe */
1112 return (pfit_control
>> 29) & 0x3;
1114 /* older chips can only use pipe 1 */
1118 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1119 struct drm_file
*file_priv
)
1121 struct drm_intel_overlay_put_image
*put_image_rec
= data
;
1122 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1123 struct intel_overlay
*overlay
;
1124 struct drm_mode_object
*drmmode_obj
;
1125 struct intel_crtc
*crtc
;
1126 struct drm_i915_gem_object
*new_bo
;
1127 struct put_image_params
*params
;
1130 /* No need to check for DRIVER_MODESET - we don't set it up then. */
1131 overlay
= dev_priv
->overlay
;
1133 DRM_DEBUG("userspace bug: no overlay\n");
1137 if (!(put_image_rec
->flags
& I915_OVERLAY_ENABLE
)) {
1138 mutex_lock(&dev
->mode_config
.mutex
);
1139 mutex_lock(&dev
->struct_mutex
);
1141 ret
= intel_overlay_switch_off(overlay
);
1143 mutex_unlock(&dev
->struct_mutex
);
1144 mutex_unlock(&dev
->mode_config
.mutex
);
1149 params
= kmalloc(sizeof(struct put_image_params
), GFP_KERNEL
);
1153 drmmode_obj
= drm_mode_object_find(dev
, put_image_rec
->crtc_id
,
1154 DRM_MODE_OBJECT_CRTC
);
1159 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
1161 new_bo
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
,
1162 put_image_rec
->bo_handle
));
1163 if (&new_bo
->base
== NULL
) {
1168 mutex_lock(&dev
->mode_config
.mutex
);
1169 mutex_lock(&dev
->struct_mutex
);
1171 if (new_bo
->tiling_mode
) {
1172 DRM_ERROR("buffer used for overlay image can not be tiled\n");
1177 ret
= intel_overlay_recover_from_interrupt(overlay
);
1181 if (overlay
->crtc
!= crtc
) {
1182 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
1183 ret
= intel_overlay_switch_off(overlay
);
1187 ret
= check_overlay_possible_on_crtc(overlay
, crtc
);
1191 overlay
->crtc
= crtc
;
1192 crtc
->overlay
= overlay
;
1194 /* line too wide, i.e. one-line-mode */
1195 if (mode
->hdisplay
> 1024 &&
1196 intel_panel_fitter_pipe(dev
) == crtc
->pipe
) {
1197 overlay
->pfit_active
= 1;
1198 update_pfit_vscale_ratio(overlay
);
1200 overlay
->pfit_active
= 0;
1203 ret
= check_overlay_dst(overlay
, put_image_rec
);
1207 if (overlay
->pfit_active
) {
1208 params
->dst_y
= ((((u32
)put_image_rec
->dst_y
) << 12) /
1209 overlay
->pfit_vscale_ratio
);
1210 /* shifting right rounds downwards, so add 1 */
1211 params
->dst_h
= ((((u32
)put_image_rec
->dst_height
) << 12) /
1212 overlay
->pfit_vscale_ratio
) + 1;
1214 params
->dst_y
= put_image_rec
->dst_y
;
1215 params
->dst_h
= put_image_rec
->dst_height
;
1217 params
->dst_x
= put_image_rec
->dst_x
;
1218 params
->dst_w
= put_image_rec
->dst_width
;
1220 params
->src_w
= put_image_rec
->src_width
;
1221 params
->src_h
= put_image_rec
->src_height
;
1222 params
->src_scan_w
= put_image_rec
->src_scan_width
;
1223 params
->src_scan_h
= put_image_rec
->src_scan_height
;
1224 if (params
->src_scan_h
> params
->src_h
||
1225 params
->src_scan_w
> params
->src_w
) {
1230 ret
= check_overlay_src(dev
, put_image_rec
, new_bo
);
1233 params
->format
= put_image_rec
->flags
& ~I915_OVERLAY_FLAGS_MASK
;
1234 params
->stride_Y
= put_image_rec
->stride_Y
;
1235 params
->stride_UV
= put_image_rec
->stride_UV
;
1236 params
->offset_Y
= put_image_rec
->offset_Y
;
1237 params
->offset_U
= put_image_rec
->offset_U
;
1238 params
->offset_V
= put_image_rec
->offset_V
;
1240 /* Check scaling after src size to prevent a divide-by-zero. */
1241 ret
= check_overlay_scaling(params
);
1245 ret
= intel_overlay_do_put_image(overlay
, new_bo
, params
);
1249 mutex_unlock(&dev
->struct_mutex
);
1250 mutex_unlock(&dev
->mode_config
.mutex
);
1257 mutex_unlock(&dev
->struct_mutex
);
1258 mutex_unlock(&dev
->mode_config
.mutex
);
1259 drm_gem_object_unreference_unlocked(&new_bo
->base
);
1266 static void update_reg_attrs(struct intel_overlay
*overlay
,
1267 struct overlay_registers __iomem
*regs
)
1269 iowrite32((overlay
->contrast
<< 18) | (overlay
->brightness
& 0xff),
1271 iowrite32(overlay
->saturation
, ®s
->OCLRC1
);
1274 static bool check_gamma_bounds(u32 gamma1
, u32 gamma2
)
1278 if (gamma1
& 0xff000000 || gamma2
& 0xff000000)
1281 for (i
= 0; i
< 3; i
++) {
1282 if (((gamma1
>> i
*8) & 0xff) >= ((gamma2
>> i
*8) & 0xff))
1289 static bool check_gamma5_errata(u32 gamma5
)
1293 for (i
= 0; i
< 3; i
++) {
1294 if (((gamma5
>> i
*8) & 0xff) == 0x80)
1301 static int check_gamma(struct drm_intel_overlay_attrs
*attrs
)
1303 if (!check_gamma_bounds(0, attrs
->gamma0
) ||
1304 !check_gamma_bounds(attrs
->gamma0
, attrs
->gamma1
) ||
1305 !check_gamma_bounds(attrs
->gamma1
, attrs
->gamma2
) ||
1306 !check_gamma_bounds(attrs
->gamma2
, attrs
->gamma3
) ||
1307 !check_gamma_bounds(attrs
->gamma3
, attrs
->gamma4
) ||
1308 !check_gamma_bounds(attrs
->gamma4
, attrs
->gamma5
) ||
1309 !check_gamma_bounds(attrs
->gamma5
, 0x00ffffff))
1312 if (!check_gamma5_errata(attrs
->gamma5
))
1318 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1319 struct drm_file
*file_priv
)
1321 struct drm_intel_overlay_attrs
*attrs
= data
;
1322 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1323 struct intel_overlay
*overlay
;
1324 struct overlay_registers __iomem
*regs
;
1327 /* No need to check for DRIVER_MODESET - we don't set it up then. */
1328 overlay
= dev_priv
->overlay
;
1330 DRM_DEBUG("userspace bug: no overlay\n");
1334 mutex_lock(&dev
->mode_config
.mutex
);
1335 mutex_lock(&dev
->struct_mutex
);
1338 if (!(attrs
->flags
& I915_OVERLAY_UPDATE_ATTRS
)) {
1339 attrs
->color_key
= overlay
->color_key
;
1340 attrs
->brightness
= overlay
->brightness
;
1341 attrs
->contrast
= overlay
->contrast
;
1342 attrs
->saturation
= overlay
->saturation
;
1344 if (!IS_GEN2(dev
)) {
1345 attrs
->gamma0
= I915_READ(OGAMC0
);
1346 attrs
->gamma1
= I915_READ(OGAMC1
);
1347 attrs
->gamma2
= I915_READ(OGAMC2
);
1348 attrs
->gamma3
= I915_READ(OGAMC3
);
1349 attrs
->gamma4
= I915_READ(OGAMC4
);
1350 attrs
->gamma5
= I915_READ(OGAMC5
);
1353 if (attrs
->brightness
< -128 || attrs
->brightness
> 127)
1355 if (attrs
->contrast
> 255)
1357 if (attrs
->saturation
> 1023)
1360 overlay
->color_key
= attrs
->color_key
;
1361 overlay
->brightness
= attrs
->brightness
;
1362 overlay
->contrast
= attrs
->contrast
;
1363 overlay
->saturation
= attrs
->saturation
;
1365 regs
= intel_overlay_map_regs(overlay
);
1371 update_reg_attrs(overlay
, regs
);
1373 intel_overlay_unmap_regs(overlay
, regs
);
1375 if (attrs
->flags
& I915_OVERLAY_UPDATE_GAMMA
) {
1379 if (overlay
->active
) {
1384 ret
= check_gamma(attrs
);
1388 I915_WRITE(OGAMC0
, attrs
->gamma0
);
1389 I915_WRITE(OGAMC1
, attrs
->gamma1
);
1390 I915_WRITE(OGAMC2
, attrs
->gamma2
);
1391 I915_WRITE(OGAMC3
, attrs
->gamma3
);
1392 I915_WRITE(OGAMC4
, attrs
->gamma4
);
1393 I915_WRITE(OGAMC5
, attrs
->gamma5
);
1399 mutex_unlock(&dev
->struct_mutex
);
1400 mutex_unlock(&dev
->mode_config
.mutex
);
1405 void intel_setup_overlay(struct drm_device
*dev
)
1407 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1408 struct intel_overlay
*overlay
;
1409 struct drm_i915_gem_object
*reg_bo
;
1410 struct overlay_registers __iomem
*regs
;
1413 if (!HAS_OVERLAY(dev
))
1416 overlay
= kzalloc(sizeof(struct intel_overlay
), GFP_KERNEL
);
1420 mutex_lock(&dev
->struct_mutex
);
1421 if (WARN_ON(dev_priv
->overlay
))
1426 reg_bo
= i915_gem_alloc_object(dev
, PAGE_SIZE
);
1429 overlay
->reg_bo
= reg_bo
;
1431 if (OVERLAY_NEEDS_PHYSICAL(dev
)) {
1432 ret
= i915_gem_attach_phys_object(dev
, reg_bo
,
1433 I915_GEM_PHYS_OVERLAY_REGS
,
1436 DRM_ERROR("failed to attach phys overlay regs\n");
1439 overlay
->flip_addr
= reg_bo
->phys_obj
->handle
->busaddr
;
1441 ret
= i915_gem_object_pin(reg_bo
, PAGE_SIZE
, true);
1443 DRM_ERROR("failed to pin overlay register bo\n");
1446 overlay
->flip_addr
= reg_bo
->gtt_offset
;
1448 ret
= i915_gem_object_set_to_gtt_domain(reg_bo
, true);
1450 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1455 /* init all values */
1456 overlay
->color_key
= 0x0101fe;
1457 overlay
->brightness
= -19;
1458 overlay
->contrast
= 75;
1459 overlay
->saturation
= 146;
1461 regs
= intel_overlay_map_regs(overlay
);
1465 memset_io(regs
, 0, sizeof(struct overlay_registers
));
1466 update_polyphase_filter(regs
);
1467 update_reg_attrs(overlay
, regs
);
1469 intel_overlay_unmap_regs(overlay
, regs
);
1471 dev_priv
->overlay
= overlay
;
1472 mutex_unlock(&dev
->struct_mutex
);
1473 DRM_INFO("initialized overlay support\n");
1477 if (!OVERLAY_NEEDS_PHYSICAL(dev
))
1478 i915_gem_object_unpin(reg_bo
);
1480 drm_gem_object_unreference(®_bo
->base
);
1482 mutex_unlock(&dev
->struct_mutex
);
1487 void intel_cleanup_overlay(struct drm_device
*dev
)
1489 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1491 if (!dev_priv
->overlay
)
1494 /* The bo's should be free'd by the generic code already.
1495 * Furthermore modesetting teardown happens beforehand so the
1496 * hardware should be off already */
1497 BUG_ON(dev_priv
->overlay
->active
);
1499 drm_gem_object_unreference_unlocked(&dev_priv
->overlay
->reg_bo
->base
);
1500 kfree(dev_priv
->overlay
);
1503 #ifdef CONFIG_DEBUG_FS
1504 #include <linux/seq_file.h>
1506 struct intel_overlay_error_state
{
1507 struct overlay_registers regs
;
1513 static struct overlay_registers __iomem
*
1514 intel_overlay_map_regs_atomic(struct intel_overlay
*overlay
)
1516 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
1517 struct overlay_registers __iomem
*regs
;
1519 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1520 /* Cast to make sparse happy, but it's wc memory anyway, so
1521 * equivalent to the wc io mapping on X86. */
1522 regs
= (struct overlay_registers __iomem
*)
1523 overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
1525 regs
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
1526 overlay
->reg_bo
->gtt_offset
);
1531 static void intel_overlay_unmap_regs_atomic(struct intel_overlay
*overlay
,
1532 struct overlay_registers __iomem
*regs
)
1534 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1535 io_mapping_unmap_atomic(regs
);
1539 struct intel_overlay_error_state
*
1540 intel_overlay_capture_error_state(struct drm_device
*dev
)
1542 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1543 struct intel_overlay
*overlay
= dev_priv
->overlay
;
1544 struct intel_overlay_error_state
*error
;
1545 struct overlay_registers __iomem
*regs
;
1547 if (!overlay
|| !overlay
->active
)
1550 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
1554 error
->dovsta
= I915_READ(DOVSTA
);
1555 error
->isr
= I915_READ(ISR
);
1556 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1557 error
->base
= (__force
long)overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
1559 error
->base
= overlay
->reg_bo
->gtt_offset
;
1561 regs
= intel_overlay_map_regs_atomic(overlay
);
1565 memcpy_fromio(&error
->regs
, regs
, sizeof(struct overlay_registers
));
1566 intel_overlay_unmap_regs_atomic(overlay
, regs
);
1576 intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
)
1578 seq_printf(m
, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1579 error
->dovsta
, error
->isr
);
1580 seq_printf(m
, " Register file at 0x%08lx:\n",
1583 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)