UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_hdmi.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
37 #include "i915_drv.h"
38
39 static void
40 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
41 {
42 struct drm_device *dev = intel_hdmi->base.base.dev;
43 struct drm_i915_private *dev_priv = dev->dev_private;
44 uint32_t enabled_bits;
45
46 enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
47
48 WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
49 "HDMI port enabled, expecting disabled\n");
50 }
51
52 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
53 {
54 return container_of(encoder, struct intel_hdmi, base.base);
55 }
56
57 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
58 {
59 return container_of(intel_attached_encoder(connector),
60 struct intel_hdmi, base);
61 }
62
63 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
64 {
65 uint8_t *data = (uint8_t *)frame;
66 uint8_t sum = 0;
67 unsigned i;
68
69 frame->checksum = 0;
70 frame->ecc = 0;
71
72 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
73 sum += data[i];
74
75 frame->checksum = 0x100 - sum;
76 }
77
78 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
79 {
80 switch (frame->type) {
81 case DIP_TYPE_AVI:
82 return VIDEO_DIP_SELECT_AVI;
83 case DIP_TYPE_SPD:
84 return VIDEO_DIP_SELECT_SPD;
85 default:
86 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
87 return 0;
88 }
89 }
90
91 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
92 {
93 switch (frame->type) {
94 case DIP_TYPE_AVI:
95 return VIDEO_DIP_ENABLE_AVI;
96 case DIP_TYPE_SPD:
97 return VIDEO_DIP_ENABLE_SPD;
98 default:
99 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
100 return 0;
101 }
102 }
103
104 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
105 {
106 switch (frame->type) {
107 case DIP_TYPE_AVI:
108 return VIDEO_DIP_ENABLE_AVI_HSW;
109 case DIP_TYPE_SPD:
110 return VIDEO_DIP_ENABLE_SPD_HSW;
111 default:
112 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
113 return 0;
114 }
115 }
116
117 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
118 {
119 switch (frame->type) {
120 case DIP_TYPE_AVI:
121 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
122 case DIP_TYPE_SPD:
123 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
124 default:
125 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
126 return 0;
127 }
128 }
129
130 static void g4x_write_infoframe(struct drm_encoder *encoder,
131 struct dip_infoframe *frame)
132 {
133 uint32_t *data = (uint32_t *)frame;
134 struct drm_device *dev = encoder->dev;
135 struct drm_i915_private *dev_priv = dev->dev_private;
136 u32 val = I915_READ(VIDEO_DIP_CTL);
137 unsigned i, len = DIP_HEADER_SIZE + frame->len;
138
139 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
140
141 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
142 val |= g4x_infoframe_index(frame);
143
144 val &= ~g4x_infoframe_enable(frame);
145
146 I915_WRITE(VIDEO_DIP_CTL, val);
147
148 mmiowb();
149 for (i = 0; i < len; i += 4) {
150 I915_WRITE(VIDEO_DIP_DATA, *data);
151 data++;
152 }
153 mmiowb();
154
155 val |= g4x_infoframe_enable(frame);
156 val &= ~VIDEO_DIP_FREQ_MASK;
157 val |= VIDEO_DIP_FREQ_VSYNC;
158
159 I915_WRITE(VIDEO_DIP_CTL, val);
160 POSTING_READ(VIDEO_DIP_CTL);
161 }
162
163 static void ibx_write_infoframe(struct drm_encoder *encoder,
164 struct dip_infoframe *frame)
165 {
166 uint32_t *data = (uint32_t *)frame;
167 struct drm_device *dev = encoder->dev;
168 struct drm_i915_private *dev_priv = dev->dev_private;
169 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
170 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
171 unsigned i, len = DIP_HEADER_SIZE + frame->len;
172 u32 val = I915_READ(reg);
173
174 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
175
176 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
177 val |= g4x_infoframe_index(frame);
178
179 val &= ~g4x_infoframe_enable(frame);
180
181 I915_WRITE(reg, val);
182
183 mmiowb();
184 for (i = 0; i < len; i += 4) {
185 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
186 data++;
187 }
188 mmiowb();
189
190 val |= g4x_infoframe_enable(frame);
191 val &= ~VIDEO_DIP_FREQ_MASK;
192 val |= VIDEO_DIP_FREQ_VSYNC;
193
194 I915_WRITE(reg, val);
195 POSTING_READ(reg);
196 }
197
198 static void cpt_write_infoframe(struct drm_encoder *encoder,
199 struct dip_infoframe *frame)
200 {
201 uint32_t *data = (uint32_t *)frame;
202 struct drm_device *dev = encoder->dev;
203 struct drm_i915_private *dev_priv = dev->dev_private;
204 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
205 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
206 unsigned i, len = DIP_HEADER_SIZE + frame->len;
207 u32 val = I915_READ(reg);
208
209 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
210
211 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
212 val |= g4x_infoframe_index(frame);
213
214 /* The DIP control register spec says that we need to update the AVI
215 * infoframe without clearing its enable bit */
216 if (frame->type != DIP_TYPE_AVI)
217 val &= ~g4x_infoframe_enable(frame);
218
219 I915_WRITE(reg, val);
220
221 mmiowb();
222 for (i = 0; i < len; i += 4) {
223 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
224 data++;
225 }
226 mmiowb();
227
228 val |= g4x_infoframe_enable(frame);
229 val &= ~VIDEO_DIP_FREQ_MASK;
230 val |= VIDEO_DIP_FREQ_VSYNC;
231
232 I915_WRITE(reg, val);
233 POSTING_READ(reg);
234 }
235
236 static void vlv_write_infoframe(struct drm_encoder *encoder,
237 struct dip_infoframe *frame)
238 {
239 uint32_t *data = (uint32_t *)frame;
240 struct drm_device *dev = encoder->dev;
241 struct drm_i915_private *dev_priv = dev->dev_private;
242 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
243 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
244 unsigned i, len = DIP_HEADER_SIZE + frame->len;
245 u32 val = I915_READ(reg);
246
247 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
248
249 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
250 val |= g4x_infoframe_index(frame);
251
252 val &= ~g4x_infoframe_enable(frame);
253
254 I915_WRITE(reg, val);
255
256 mmiowb();
257 for (i = 0; i < len; i += 4) {
258 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
259 data++;
260 }
261 mmiowb();
262
263 val |= g4x_infoframe_enable(frame);
264 val &= ~VIDEO_DIP_FREQ_MASK;
265 val |= VIDEO_DIP_FREQ_VSYNC;
266
267 I915_WRITE(reg, val);
268 POSTING_READ(reg);
269 }
270
271 static void hsw_write_infoframe(struct drm_encoder *encoder,
272 struct dip_infoframe *frame)
273 {
274 uint32_t *data = (uint32_t *)frame;
275 struct drm_device *dev = encoder->dev;
276 struct drm_i915_private *dev_priv = dev->dev_private;
277 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
278 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
279 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
280 unsigned int i, len = DIP_HEADER_SIZE + frame->len;
281 u32 val = I915_READ(ctl_reg);
282
283 if (data_reg == 0)
284 return;
285
286 val &= ~hsw_infoframe_enable(frame);
287 I915_WRITE(ctl_reg, val);
288
289 mmiowb();
290 for (i = 0; i < len; i += 4) {
291 I915_WRITE(data_reg + i, *data);
292 data++;
293 }
294 mmiowb();
295
296 val |= hsw_infoframe_enable(frame);
297 I915_WRITE(ctl_reg, val);
298 POSTING_READ(ctl_reg);
299 }
300
301 static void intel_set_infoframe(struct drm_encoder *encoder,
302 struct dip_infoframe *frame)
303 {
304 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
305
306 intel_dip_infoframe_csum(frame);
307 intel_hdmi->write_infoframe(encoder, frame);
308 }
309
310 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
311 struct drm_display_mode *adjusted_mode)
312 {
313 struct dip_infoframe avi_if = {
314 .type = DIP_TYPE_AVI,
315 .ver = DIP_VERSION_AVI,
316 .len = DIP_LEN_AVI,
317 };
318
319 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
320 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
321
322 intel_set_infoframe(encoder, &avi_if);
323 }
324
325 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
326 {
327 struct dip_infoframe spd_if;
328
329 memset(&spd_if, 0, sizeof(spd_if));
330 spd_if.type = DIP_TYPE_SPD;
331 spd_if.ver = DIP_VERSION_SPD;
332 spd_if.len = DIP_LEN_SPD;
333 strcpy(spd_if.body.spd.vn, "Intel");
334 strcpy(spd_if.body.spd.pd, "Integrated gfx");
335 spd_if.body.spd.sdi = DIP_SPD_PC;
336
337 intel_set_infoframe(encoder, &spd_if);
338 }
339
340 static void g4x_set_infoframes(struct drm_encoder *encoder,
341 struct drm_display_mode *adjusted_mode)
342 {
343 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
344 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
345 u32 reg = VIDEO_DIP_CTL;
346 u32 val = I915_READ(reg);
347 u32 port;
348
349 assert_hdmi_port_disabled(intel_hdmi);
350
351 /* If the registers were not initialized yet, they might be zeroes,
352 * which means we're selecting the AVI DIP and we're setting its
353 * frequency to once. This seems to really confuse the HW and make
354 * things stop working (the register spec says the AVI always needs to
355 * be sent every VSync). So here we avoid writing to the register more
356 * than we need and also explicitly select the AVI DIP and explicitly
357 * set its frequency to every VSync. Avoiding to write it twice seems to
358 * be enough to solve the problem, but being defensive shouldn't hurt us
359 * either. */
360 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
361
362 if (!intel_hdmi->has_hdmi_sink) {
363 if (!(val & VIDEO_DIP_ENABLE))
364 return;
365 val &= ~VIDEO_DIP_ENABLE;
366 I915_WRITE(reg, val);
367 POSTING_READ(reg);
368 return;
369 }
370
371 switch (intel_hdmi->sdvox_reg) {
372 case SDVOB:
373 port = VIDEO_DIP_PORT_B;
374 break;
375 case SDVOC:
376 port = VIDEO_DIP_PORT_C;
377 break;
378 default:
379 return;
380 }
381
382 if (port != (val & VIDEO_DIP_PORT_MASK)) {
383 if (val & VIDEO_DIP_ENABLE) {
384 val &= ~VIDEO_DIP_ENABLE;
385 I915_WRITE(reg, val);
386 POSTING_READ(reg);
387 }
388 val &= ~VIDEO_DIP_PORT_MASK;
389 val |= port;
390 }
391
392 val |= VIDEO_DIP_ENABLE;
393 val &= ~VIDEO_DIP_ENABLE_VENDOR;
394
395 I915_WRITE(reg, val);
396 POSTING_READ(reg);
397
398 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
399 intel_hdmi_set_spd_infoframe(encoder);
400 }
401
402 static void ibx_set_infoframes(struct drm_encoder *encoder,
403 struct drm_display_mode *adjusted_mode)
404 {
405 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
406 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
407 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
408 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
409 u32 val = I915_READ(reg);
410 u32 port;
411
412 assert_hdmi_port_disabled(intel_hdmi);
413
414 /* See the big comment in g4x_set_infoframes() */
415 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
416
417 if (!intel_hdmi->has_hdmi_sink) {
418 if (!(val & VIDEO_DIP_ENABLE))
419 return;
420 val &= ~VIDEO_DIP_ENABLE;
421 I915_WRITE(reg, val);
422 POSTING_READ(reg);
423 return;
424 }
425
426 switch (intel_hdmi->sdvox_reg) {
427 case HDMIB:
428 port = VIDEO_DIP_PORT_B;
429 break;
430 case HDMIC:
431 port = VIDEO_DIP_PORT_C;
432 break;
433 case HDMID:
434 port = VIDEO_DIP_PORT_D;
435 break;
436 default:
437 return;
438 }
439
440 if (port != (val & VIDEO_DIP_PORT_MASK)) {
441 if (val & VIDEO_DIP_ENABLE) {
442 val &= ~VIDEO_DIP_ENABLE;
443 I915_WRITE(reg, val);
444 POSTING_READ(reg);
445 }
446 val &= ~VIDEO_DIP_PORT_MASK;
447 val |= port;
448 }
449
450 val |= VIDEO_DIP_ENABLE;
451 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
452 VIDEO_DIP_ENABLE_GCP);
453
454 I915_WRITE(reg, val);
455 POSTING_READ(reg);
456
457 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
458 intel_hdmi_set_spd_infoframe(encoder);
459 }
460
461 static void cpt_set_infoframes(struct drm_encoder *encoder,
462 struct drm_display_mode *adjusted_mode)
463 {
464 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
465 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
466 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
467 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
468 u32 val = I915_READ(reg);
469
470 assert_hdmi_port_disabled(intel_hdmi);
471
472 /* See the big comment in g4x_set_infoframes() */
473 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
474
475 if (!intel_hdmi->has_hdmi_sink) {
476 if (!(val & VIDEO_DIP_ENABLE))
477 return;
478 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
479 I915_WRITE(reg, val);
480 POSTING_READ(reg);
481 return;
482 }
483
484 /* Set both together, unset both together: see the spec. */
485 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
486 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
487 VIDEO_DIP_ENABLE_GCP);
488
489 I915_WRITE(reg, val);
490 POSTING_READ(reg);
491
492 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
493 intel_hdmi_set_spd_infoframe(encoder);
494 }
495
496 static void vlv_set_infoframes(struct drm_encoder *encoder,
497 struct drm_display_mode *adjusted_mode)
498 {
499 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
500 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
501 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
502 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
503 u32 val = I915_READ(reg);
504
505 assert_hdmi_port_disabled(intel_hdmi);
506
507 /* See the big comment in g4x_set_infoframes() */
508 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
509
510 if (!intel_hdmi->has_hdmi_sink) {
511 if (!(val & VIDEO_DIP_ENABLE))
512 return;
513 val &= ~VIDEO_DIP_ENABLE;
514 I915_WRITE(reg, val);
515 POSTING_READ(reg);
516 return;
517 }
518
519 val |= VIDEO_DIP_ENABLE;
520 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
521 VIDEO_DIP_ENABLE_GCP);
522
523 I915_WRITE(reg, val);
524 POSTING_READ(reg);
525
526 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
527 intel_hdmi_set_spd_infoframe(encoder);
528 }
529
530 static void hsw_set_infoframes(struct drm_encoder *encoder,
531 struct drm_display_mode *adjusted_mode)
532 {
533 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
534 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
535 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
536 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
537 u32 val = I915_READ(reg);
538
539 assert_hdmi_port_disabled(intel_hdmi);
540
541 if (!intel_hdmi->has_hdmi_sink) {
542 I915_WRITE(reg, 0);
543 POSTING_READ(reg);
544 return;
545 }
546
547 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
548 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
549
550 I915_WRITE(reg, val);
551 POSTING_READ(reg);
552
553 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
554 intel_hdmi_set_spd_infoframe(encoder);
555 }
556
557 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
558 struct drm_display_mode *mode,
559 struct drm_display_mode *adjusted_mode)
560 {
561 struct drm_device *dev = encoder->dev;
562 struct drm_i915_private *dev_priv = dev->dev_private;
563 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
564 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
565 u32 sdvox;
566
567 sdvox = SDVO_ENCODING_HDMI;
568 if (!HAS_PCH_SPLIT(dev))
569 sdvox |= intel_hdmi->color_range;
570 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
571 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
572 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
573 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
574
575 if (intel_crtc->bpp > 24)
576 sdvox |= COLOR_FORMAT_12bpc;
577 else
578 sdvox |= COLOR_FORMAT_8bpc;
579
580 /* Required on CPT */
581 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
582 sdvox |= HDMI_MODE_SELECT;
583
584 if (intel_hdmi->has_audio) {
585 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
586 pipe_name(intel_crtc->pipe));
587 sdvox |= SDVO_AUDIO_ENABLE;
588 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
589 intel_write_eld(encoder, adjusted_mode);
590 }
591
592 if (HAS_PCH_CPT(dev))
593 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
594 else if (intel_crtc->pipe == PIPE_B)
595 sdvox |= SDVO_PIPE_B_SELECT;
596
597 I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
598 POSTING_READ(intel_hdmi->sdvox_reg);
599
600 intel_hdmi->set_infoframes(encoder, adjusted_mode);
601 }
602
603 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
604 {
605 struct drm_device *dev = encoder->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
608 u32 temp;
609 u32 enable_bits = SDVO_ENABLE;
610
611 if (intel_hdmi->has_audio || mode != DRM_MODE_DPMS_ON)
612 enable_bits |= SDVO_AUDIO_ENABLE;
613
614 temp = I915_READ(intel_hdmi->sdvox_reg);
615
616 /* HW workaround for IBX, we need to move the port to transcoder A
617 * before disabling it. */
618 if (HAS_PCH_IBX(dev)) {
619 struct drm_crtc *crtc = encoder->crtc;
620 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
621
622 if (mode != DRM_MODE_DPMS_ON) {
623 if (temp & SDVO_PIPE_B_SELECT) {
624 temp &= ~SDVO_PIPE_B_SELECT;
625 I915_WRITE(intel_hdmi->sdvox_reg, temp);
626 POSTING_READ(intel_hdmi->sdvox_reg);
627
628 /* Again we need to write this twice. */
629 I915_WRITE(intel_hdmi->sdvox_reg, temp);
630 POSTING_READ(intel_hdmi->sdvox_reg);
631
632 /* Transcoder selection bits only update
633 * effectively on vblank. */
634 if (crtc)
635 intel_wait_for_vblank(dev, pipe);
636 else
637 msleep(50);
638 }
639 } else {
640 /* Restore the transcoder select bit. */
641 if (pipe == PIPE_B)
642 enable_bits |= SDVO_PIPE_B_SELECT;
643 }
644 }
645
646 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
647 * we do this anyway which shows more stable in testing.
648 */
649 if (HAS_PCH_SPLIT(dev)) {
650 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
651 POSTING_READ(intel_hdmi->sdvox_reg);
652 }
653
654 if (mode != DRM_MODE_DPMS_ON) {
655 temp &= ~enable_bits;
656 } else {
657 temp |= enable_bits;
658 }
659
660 I915_WRITE(intel_hdmi->sdvox_reg, temp);
661 POSTING_READ(intel_hdmi->sdvox_reg);
662
663 /* HW workaround, need to write this twice for issue that may result
664 * in first write getting masked.
665 */
666 if (HAS_PCH_SPLIT(dev)) {
667 I915_WRITE(intel_hdmi->sdvox_reg, temp);
668 POSTING_READ(intel_hdmi->sdvox_reg);
669 }
670 }
671
672 static int intel_hdmi_mode_valid(struct drm_connector *connector,
673 struct drm_display_mode *mode)
674 {
675 if (mode->clock > 165000)
676 return MODE_CLOCK_HIGH;
677 if (mode->clock < 20000)
678 return MODE_CLOCK_LOW;
679
680 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
681 return MODE_NO_DBLESCAN;
682
683 return MODE_OK;
684 }
685
686 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
687 const struct drm_display_mode *mode,
688 struct drm_display_mode *adjusted_mode)
689 {
690 return true;
691 }
692
693 static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
694 {
695 struct drm_device *dev = intel_hdmi->base.base.dev;
696 struct drm_i915_private *dev_priv = dev->dev_private;
697 uint32_t bit;
698
699 switch (intel_hdmi->sdvox_reg) {
700 case SDVOB:
701 bit = HDMIB_HOTPLUG_LIVE_STATUS;
702 break;
703 case SDVOC:
704 bit = HDMIC_HOTPLUG_LIVE_STATUS;
705 break;
706 default:
707 bit = 0;
708 break;
709 }
710
711 return I915_READ(PORT_HOTPLUG_STAT) & bit;
712 }
713
714 static enum drm_connector_status
715 intel_hdmi_detect(struct drm_connector *connector, bool force)
716 {
717 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
718 struct drm_i915_private *dev_priv = connector->dev->dev_private;
719 struct edid *edid;
720 enum drm_connector_status status = connector_status_disconnected;
721
722 if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
723 return status;
724
725 intel_hdmi->has_hdmi_sink = false;
726 intel_hdmi->has_audio = false;
727 edid = drm_get_edid(connector,
728 intel_gmbus_get_adapter(dev_priv,
729 intel_hdmi->ddc_bus));
730
731 if (edid) {
732 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
733 status = connector_status_connected;
734 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
735 intel_hdmi->has_hdmi_sink =
736 drm_detect_hdmi_monitor(edid);
737 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
738 }
739 connector->display_info.raw_edid = NULL;
740 kfree(edid);
741 }
742
743 if (status == connector_status_connected) {
744 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
745 intel_hdmi->has_audio =
746 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
747 }
748
749 return status;
750 }
751
752 static int intel_hdmi_get_modes(struct drm_connector *connector)
753 {
754 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
755 struct drm_i915_private *dev_priv = connector->dev->dev_private;
756
757 /* We should parse the EDID data and find out if it's an HDMI sink so
758 * we can send audio to it.
759 */
760
761 return intel_ddc_get_modes(connector,
762 intel_gmbus_get_adapter(dev_priv,
763 intel_hdmi->ddc_bus));
764 }
765
766 static bool
767 intel_hdmi_detect_audio(struct drm_connector *connector)
768 {
769 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
770 struct drm_i915_private *dev_priv = connector->dev->dev_private;
771 struct edid *edid;
772 bool has_audio = false;
773
774 edid = drm_get_edid(connector,
775 intel_gmbus_get_adapter(dev_priv,
776 intel_hdmi->ddc_bus));
777 if (edid) {
778 if (edid->input & DRM_EDID_INPUT_DIGITAL)
779 has_audio = drm_detect_monitor_audio(edid);
780
781 connector->display_info.raw_edid = NULL;
782 kfree(edid);
783 }
784
785 return has_audio;
786 }
787
788 static int
789 intel_hdmi_set_property(struct drm_connector *connector,
790 struct drm_property *property,
791 uint64_t val)
792 {
793 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
794 struct drm_i915_private *dev_priv = connector->dev->dev_private;
795 int ret;
796
797 ret = drm_connector_property_set_value(connector, property, val);
798 if (ret)
799 return ret;
800
801 if (property == dev_priv->force_audio_property) {
802 enum hdmi_force_audio i = val;
803 bool has_audio;
804
805 if (i == intel_hdmi->force_audio)
806 return 0;
807
808 intel_hdmi->force_audio = i;
809
810 if (i == HDMI_AUDIO_AUTO)
811 has_audio = intel_hdmi_detect_audio(connector);
812 else
813 has_audio = (i == HDMI_AUDIO_ON);
814
815 if (i == HDMI_AUDIO_OFF_DVI)
816 intel_hdmi->has_hdmi_sink = 0;
817
818 intel_hdmi->has_audio = has_audio;
819 goto done;
820 }
821
822 if (property == dev_priv->broadcast_rgb_property) {
823 if (val == !!intel_hdmi->color_range)
824 return 0;
825
826 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
827 goto done;
828 }
829
830 return -EINVAL;
831
832 done:
833 if (intel_hdmi->base.base.crtc) {
834 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
835 drm_crtc_helper_set_mode(crtc, &crtc->mode,
836 crtc->x, crtc->y,
837 crtc->fb);
838 }
839
840 return 0;
841 }
842
843 static void intel_hdmi_destroy(struct drm_connector *connector)
844 {
845 drm_sysfs_connector_remove(connector);
846 drm_connector_cleanup(connector);
847 kfree(connector);
848 }
849
850 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
851 .dpms = intel_ddi_dpms,
852 .mode_fixup = intel_hdmi_mode_fixup,
853 .prepare = intel_encoder_prepare,
854 .mode_set = intel_ddi_mode_set,
855 .commit = intel_encoder_commit,
856 };
857
858 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
859 .dpms = intel_hdmi_dpms,
860 .mode_fixup = intel_hdmi_mode_fixup,
861 .prepare = intel_encoder_prepare,
862 .mode_set = intel_hdmi_mode_set,
863 .commit = intel_encoder_commit,
864 };
865
866 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
867 .dpms = drm_helper_connector_dpms,
868 .detect = intel_hdmi_detect,
869 .fill_modes = drm_helper_probe_single_connector_modes,
870 .set_property = intel_hdmi_set_property,
871 .destroy = intel_hdmi_destroy,
872 };
873
874 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
875 .get_modes = intel_hdmi_get_modes,
876 .mode_valid = intel_hdmi_mode_valid,
877 .best_encoder = intel_best_encoder,
878 };
879
880 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
881 .destroy = intel_encoder_destroy,
882 };
883
884 static void
885 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
886 {
887 intel_attach_force_audio_property(connector);
888 intel_attach_broadcast_rgb_property(connector);
889 }
890
891 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
892 {
893 struct drm_i915_private *dev_priv = dev->dev_private;
894 struct drm_connector *connector;
895 struct intel_encoder *intel_encoder;
896 struct intel_connector *intel_connector;
897 struct intel_hdmi *intel_hdmi;
898
899 intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
900 if (!intel_hdmi)
901 return;
902
903 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
904 if (!intel_connector) {
905 kfree(intel_hdmi);
906 return;
907 }
908
909 intel_encoder = &intel_hdmi->base;
910 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
911 DRM_MODE_ENCODER_TMDS);
912
913 connector = &intel_connector->base;
914 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
915 DRM_MODE_CONNECTOR_HDMIA);
916 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
917
918 intel_encoder->type = INTEL_OUTPUT_HDMI;
919
920 connector->polled = DRM_CONNECTOR_POLL_HPD;
921 connector->interlace_allowed = 1;
922 connector->doublescan_allowed = 0;
923 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
924
925 /* Set up the DDC bus. */
926 if (sdvox_reg == SDVOB) {
927 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
928 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
929 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
930 } else if (sdvox_reg == SDVOC) {
931 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
932 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
933 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
934 } else if (sdvox_reg == HDMIB) {
935 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
936 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
937 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
938 } else if (sdvox_reg == HDMIC) {
939 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
940 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
941 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
942 } else if (sdvox_reg == HDMID) {
943 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
944 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
945 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
946 } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
947 DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
948 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
949 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
950 intel_hdmi->ddi_port = PORT_B;
951 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
952 } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
953 DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
954 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
955 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
956 intel_hdmi->ddi_port = PORT_C;
957 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
958 } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
959 DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
960 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
961 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
962 intel_hdmi->ddi_port = PORT_D;
963 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
964 } else {
965 /* If we got an unknown sdvox_reg, things are pretty much broken
966 * in a way that we should let the kernel know about it */
967 BUG();
968 }
969
970 intel_hdmi->sdvox_reg = sdvox_reg;
971
972 if (!HAS_PCH_SPLIT(dev)) {
973 intel_hdmi->write_infoframe = g4x_write_infoframe;
974 intel_hdmi->set_infoframes = g4x_set_infoframes;
975 } else if (IS_VALLEYVIEW(dev)) {
976 intel_hdmi->write_infoframe = vlv_write_infoframe;
977 intel_hdmi->set_infoframes = vlv_set_infoframes;
978 } else if (IS_HASWELL(dev)) {
979 intel_hdmi->write_infoframe = hsw_write_infoframe;
980 intel_hdmi->set_infoframes = hsw_set_infoframes;
981 } else if (HAS_PCH_IBX(dev)) {
982 intel_hdmi->write_infoframe = ibx_write_infoframe;
983 intel_hdmi->set_infoframes = ibx_set_infoframes;
984 } else {
985 intel_hdmi->write_infoframe = cpt_write_infoframe;
986 intel_hdmi->set_infoframes = cpt_set_infoframes;
987 }
988
989 if (IS_HASWELL(dev))
990 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
991 else
992 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
993
994 intel_hdmi_add_properties(intel_hdmi, connector);
995
996 intel_connector_attach_encoder(intel_connector, intel_encoder);
997 drm_sysfs_connector_add(connector);
998
999 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1000 * 0xd. Failure to do so will result in spurious interrupts being
1001 * generated on the port when a cable is not attached.
1002 */
1003 if (IS_G4X(dev) && !IS_GM45(dev)) {
1004 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1005 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1006 }
1007 }