2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 * DOC: Frame Buffer Compression (FBC)
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
41 #include "intel_drv.h"
44 static inline bool fbc_supported(struct drm_i915_private
*dev_priv
)
46 return HAS_FBC(dev_priv
);
49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private
*dev_priv
)
51 return IS_HASWELL(dev_priv
) || INTEL_GEN(dev_priv
) >= 8;
54 static inline bool fbc_on_plane_a_only(struct drm_i915_private
*dev_priv
)
56 return INTEL_GEN(dev_priv
) < 4;
59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private
*dev_priv
)
61 return INTEL_GEN(dev_priv
) <= 3;
65 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
66 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
67 * origin so the x and y offsets can actually fit the registers. As a
68 * consequence, the fence doesn't really start exactly at the display plane
69 * address we program because it starts at the real start of the buffer, so we
70 * have to take this into consideration here.
72 static unsigned int get_crtc_fence_y_offset(struct intel_crtc
*crtc
)
74 return crtc
->base
.y
- crtc
->adjusted_y
;
78 * For SKL+, the plane source size used by the hardware is based on the value we
79 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
80 * we wrote to PIPESRC.
82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache
*cache
,
83 int *width
, int *height
)
87 if (drm_rotation_90_or_270(cache
->plane
.rotation
)) {
88 w
= cache
->plane
.src_h
;
89 h
= cache
->plane
.src_w
;
91 w
= cache
->plane
.src_w
;
92 h
= cache
->plane
.src_h
;
101 static int intel_fbc_calculate_cfb_size(struct drm_i915_private
*dev_priv
,
102 struct intel_fbc_state_cache
*cache
)
106 intel_fbc_get_plane_source_size(cache
, NULL
, &lines
);
107 if (INTEL_GEN(dev_priv
) == 7)
108 lines
= min(lines
, 2048);
109 else if (INTEL_GEN(dev_priv
) >= 8)
110 lines
= min(lines
, 2560);
112 /* Hardware needs the full buffer stride, not just the active area. */
113 return lines
* cache
->fb
.stride
;
116 static void i8xx_fbc_deactivate(struct drm_i915_private
*dev_priv
)
120 /* Disable compression */
121 fbc_ctl
= I915_READ(FBC_CONTROL
);
122 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
125 fbc_ctl
&= ~FBC_CTL_EN
;
126 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
128 /* Wait for compressing bit to clear */
129 if (intel_wait_for_register(dev_priv
,
130 FBC_STATUS
, FBC_STAT_COMPRESSING
, 0,
132 DRM_DEBUG_KMS("FBC idle timed out\n");
137 static void i8xx_fbc_activate(struct drm_i915_private
*dev_priv
)
139 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
144 /* Note: fbc.threshold == 1 for i8xx */
145 cfb_pitch
= params
->cfb_size
/ FBC_LL_SIZE
;
146 if (params
->fb
.stride
< cfb_pitch
)
147 cfb_pitch
= params
->fb
.stride
;
149 /* FBC_CTL wants 32B or 64B units */
150 if (IS_GEN2(dev_priv
))
151 cfb_pitch
= (cfb_pitch
/ 32) - 1;
153 cfb_pitch
= (cfb_pitch
/ 64) - 1;
156 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
157 I915_WRITE(FBC_TAG(i
), 0);
159 if (IS_GEN4(dev_priv
)) {
163 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
164 fbc_ctl2
|= FBC_CTL_PLANE(params
->crtc
.plane
);
165 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
166 I915_WRITE(FBC_FENCE_OFF
, params
->crtc
.fence_y_offset
);
170 fbc_ctl
= I915_READ(FBC_CONTROL
);
171 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
172 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
173 if (IS_I945GM(dev_priv
))
174 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
175 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
176 fbc_ctl
|= params
->fb
.fence_reg
;
177 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
180 static bool i8xx_fbc_is_active(struct drm_i915_private
*dev_priv
)
182 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
185 static void g4x_fbc_activate(struct drm_i915_private
*dev_priv
)
187 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
190 dpfc_ctl
= DPFC_CTL_PLANE(params
->crtc
.plane
) | DPFC_SR_EN
;
191 if (drm_format_plane_cpp(params
->fb
.pixel_format
, 0) == 2)
192 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
194 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
196 if (params
->fb
.fence_reg
!= I915_FENCE_REG_NONE
) {
197 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| params
->fb
.fence_reg
;
198 I915_WRITE(DPFC_FENCE_YOFF
, params
->crtc
.fence_y_offset
);
200 I915_WRITE(DPFC_FENCE_YOFF
, 0);
204 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
207 static void g4x_fbc_deactivate(struct drm_i915_private
*dev_priv
)
211 /* Disable compression */
212 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
213 if (dpfc_ctl
& DPFC_CTL_EN
) {
214 dpfc_ctl
&= ~DPFC_CTL_EN
;
215 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
219 static bool g4x_fbc_is_active(struct drm_i915_private
*dev_priv
)
221 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
224 /* This function forces a CFB recompression through the nuke operation. */
225 static void intel_fbc_recompress(struct drm_i915_private
*dev_priv
)
227 I915_WRITE(MSG_FBC_REND_STATE
, FBC_REND_NUKE
);
228 POSTING_READ(MSG_FBC_REND_STATE
);
231 static void ilk_fbc_activate(struct drm_i915_private
*dev_priv
)
233 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
235 int threshold
= dev_priv
->fbc
.threshold
;
237 dpfc_ctl
= DPFC_CTL_PLANE(params
->crtc
.plane
);
238 if (drm_format_plane_cpp(params
->fb
.pixel_format
, 0) == 2)
244 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
247 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
250 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
254 if (params
->fb
.fence_reg
!= I915_FENCE_REG_NONE
) {
255 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
256 if (IS_GEN5(dev_priv
))
257 dpfc_ctl
|= params
->fb
.fence_reg
;
258 if (IS_GEN6(dev_priv
)) {
259 I915_WRITE(SNB_DPFC_CTL_SA
,
260 SNB_CPU_FENCE_ENABLE
| params
->fb
.fence_reg
);
261 I915_WRITE(DPFC_CPU_FENCE_OFFSET
,
262 params
->crtc
.fence_y_offset
);
265 if (IS_GEN6(dev_priv
)) {
266 I915_WRITE(SNB_DPFC_CTL_SA
, 0);
267 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, 0);
271 I915_WRITE(ILK_DPFC_FENCE_YOFF
, params
->crtc
.fence_y_offset
);
272 I915_WRITE(ILK_FBC_RT_BASE
, params
->fb
.ggtt_offset
| ILK_FBC_RT_VALID
);
274 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
276 intel_fbc_recompress(dev_priv
);
279 static void ilk_fbc_deactivate(struct drm_i915_private
*dev_priv
)
283 /* Disable compression */
284 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
285 if (dpfc_ctl
& DPFC_CTL_EN
) {
286 dpfc_ctl
&= ~DPFC_CTL_EN
;
287 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
291 static bool ilk_fbc_is_active(struct drm_i915_private
*dev_priv
)
293 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
296 static void gen7_fbc_activate(struct drm_i915_private
*dev_priv
)
298 struct intel_fbc_reg_params
*params
= &dev_priv
->fbc
.params
;
300 int threshold
= dev_priv
->fbc
.threshold
;
303 if (IS_IVYBRIDGE(dev_priv
))
304 dpfc_ctl
|= IVB_DPFC_CTL_PLANE(params
->crtc
.plane
);
306 if (drm_format_plane_cpp(params
->fb
.pixel_format
, 0) == 2)
312 dpfc_ctl
|= DPFC_CTL_LIMIT_4X
;
315 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
318 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
322 if (params
->fb
.fence_reg
!= I915_FENCE_REG_NONE
) {
323 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
324 I915_WRITE(SNB_DPFC_CTL_SA
,
325 SNB_CPU_FENCE_ENABLE
| params
->fb
.fence_reg
);
326 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, params
->crtc
.fence_y_offset
);
328 I915_WRITE(SNB_DPFC_CTL_SA
,0);
329 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, 0);
332 if (dev_priv
->fbc
.false_color
)
333 dpfc_ctl
|= FBC_CTL_FALSE_COLOR
;
335 if (IS_IVYBRIDGE(dev_priv
)) {
336 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
337 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
338 I915_READ(ILK_DISPLAY_CHICKEN1
) |
340 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
341 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
342 I915_WRITE(CHICKEN_PIPESL_1(params
->crtc
.pipe
),
343 I915_READ(CHICKEN_PIPESL_1(params
->crtc
.pipe
)) |
347 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
349 intel_fbc_recompress(dev_priv
);
352 static bool intel_fbc_hw_is_active(struct drm_i915_private
*dev_priv
)
354 if (INTEL_GEN(dev_priv
) >= 5)
355 return ilk_fbc_is_active(dev_priv
);
356 else if (IS_GM45(dev_priv
))
357 return g4x_fbc_is_active(dev_priv
);
359 return i8xx_fbc_is_active(dev_priv
);
362 static void intel_fbc_hw_activate(struct drm_i915_private
*dev_priv
)
364 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
368 if (INTEL_GEN(dev_priv
) >= 7)
369 gen7_fbc_activate(dev_priv
);
370 else if (INTEL_GEN(dev_priv
) >= 5)
371 ilk_fbc_activate(dev_priv
);
372 else if (IS_GM45(dev_priv
))
373 g4x_fbc_activate(dev_priv
);
375 i8xx_fbc_activate(dev_priv
);
378 static void intel_fbc_hw_deactivate(struct drm_i915_private
*dev_priv
)
380 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
384 if (INTEL_GEN(dev_priv
) >= 5)
385 ilk_fbc_deactivate(dev_priv
);
386 else if (IS_GM45(dev_priv
))
387 g4x_fbc_deactivate(dev_priv
);
389 i8xx_fbc_deactivate(dev_priv
);
393 * intel_fbc_is_active - Is FBC active?
394 * @dev_priv: i915 device instance
396 * This function is used to verify the current state of FBC.
398 * FIXME: This should be tracked in the plane config eventually
399 * instead of queried at runtime for most callers.
401 bool intel_fbc_is_active(struct drm_i915_private
*dev_priv
)
403 return dev_priv
->fbc
.active
;
406 static void intel_fbc_work_fn(struct work_struct
*__work
)
408 struct drm_i915_private
*dev_priv
=
409 container_of(__work
, struct drm_i915_private
, fbc
.work
.work
);
410 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
411 struct intel_fbc_work
*work
= &fbc
->work
;
412 struct intel_crtc
*crtc
= fbc
->crtc
;
413 struct drm_vblank_crtc
*vblank
= &dev_priv
->drm
.vblank
[crtc
->pipe
];
415 if (drm_crtc_vblank_get(&crtc
->base
)) {
416 DRM_ERROR("vblank not available for FBC on pipe %c\n",
417 pipe_name(crtc
->pipe
));
419 mutex_lock(&fbc
->lock
);
420 work
->scheduled
= false;
421 mutex_unlock(&fbc
->lock
);
426 /* Delay the actual enabling to let pageflipping cease and the
427 * display to settle before starting the compression. Note that
428 * this delay also serves a second purpose: it allows for a
429 * vblank to pass after disabling the FBC before we attempt
430 * to modify the control registers.
432 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
434 * It is also worth mentioning that since work->scheduled_vblank can be
435 * updated multiple times by the other threads, hitting the timeout is
436 * not an error condition. We'll just end up hitting the "goto retry"
439 wait_event_timeout(vblank
->queue
,
440 drm_crtc_vblank_count(&crtc
->base
) != work
->scheduled_vblank
,
441 msecs_to_jiffies(50));
443 mutex_lock(&fbc
->lock
);
445 /* Were we cancelled? */
446 if (!work
->scheduled
)
449 /* Were we delayed again while this function was sleeping? */
450 if (drm_crtc_vblank_count(&crtc
->base
) == work
->scheduled_vblank
) {
451 mutex_unlock(&fbc
->lock
);
455 intel_fbc_hw_activate(dev_priv
);
457 work
->scheduled
= false;
460 mutex_unlock(&fbc
->lock
);
461 drm_crtc_vblank_put(&crtc
->base
);
464 static void intel_fbc_schedule_activation(struct intel_crtc
*crtc
)
466 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
467 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
468 struct intel_fbc_work
*work
= &fbc
->work
;
470 WARN_ON(!mutex_is_locked(&fbc
->lock
));
472 if (drm_crtc_vblank_get(&crtc
->base
)) {
473 DRM_ERROR("vblank not available for FBC on pipe %c\n",
474 pipe_name(crtc
->pipe
));
478 /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
479 * this function since we're not releasing fbc.lock, so it won't have an
480 * opportunity to grab it to discover that it was cancelled. So we just
481 * update the expected jiffy count. */
482 work
->scheduled
= true;
483 work
->scheduled_vblank
= drm_crtc_vblank_count(&crtc
->base
);
484 drm_crtc_vblank_put(&crtc
->base
);
486 schedule_work(&work
->work
);
489 static void intel_fbc_deactivate(struct drm_i915_private
*dev_priv
)
491 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
493 WARN_ON(!mutex_is_locked(&fbc
->lock
));
495 /* Calling cancel_work() here won't help due to the fact that the work
496 * function grabs fbc->lock. Just set scheduled to false so the work
497 * function can know it was cancelled. */
498 fbc
->work
.scheduled
= false;
501 intel_fbc_hw_deactivate(dev_priv
);
504 static bool multiple_pipes_ok(struct intel_crtc
*crtc
,
505 struct intel_plane_state
*plane_state
)
507 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
508 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
509 enum pipe pipe
= crtc
->pipe
;
511 /* Don't even bother tracking anything we don't need. */
512 if (!no_fbc_on_multiple_pipes(dev_priv
))
515 if (plane_state
->base
.visible
)
516 fbc
->visible_pipes_mask
|= (1 << pipe
);
518 fbc
->visible_pipes_mask
&= ~(1 << pipe
);
520 return (fbc
->visible_pipes_mask
& ~(1 << pipe
)) != 0;
523 static int find_compression_threshold(struct drm_i915_private
*dev_priv
,
524 struct drm_mm_node
*node
,
528 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
529 int compression_threshold
= 1;
533 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
534 * reserved range size, so it always assumes the maximum (8mb) is used.
535 * If we enable FBC using a CFB on that memory range we'll get FIFO
536 * underruns, even if that range is not reserved by the BIOS. */
537 if (IS_BROADWELL(dev_priv
) ||
538 IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
539 end
= ggtt
->stolen_size
- 8 * 1024 * 1024;
541 end
= ggtt
->stolen_usable_size
;
543 /* HACK: This code depends on what we will do in *_enable_fbc. If that
544 * code changes, this code needs to change as well.
546 * The enable_fbc code will attempt to use one of our 2 compression
547 * thresholds, therefore, in that case, we only have 1 resort.
550 /* Try to over-allocate to reduce reallocations and fragmentation. */
551 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
<<= 1,
554 return compression_threshold
;
557 /* HW's ability to limit the CFB is 1:4 */
558 if (compression_threshold
> 4 ||
559 (fb_cpp
== 2 && compression_threshold
== 2))
562 ret
= i915_gem_stolen_insert_node_in_range(dev_priv
, node
, size
>>= 1,
564 if (ret
&& INTEL_GEN(dev_priv
) <= 4) {
567 compression_threshold
<<= 1;
570 return compression_threshold
;
574 static int intel_fbc_alloc_cfb(struct intel_crtc
*crtc
)
576 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
577 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
578 struct drm_mm_node
*uninitialized_var(compressed_llb
);
579 int size
, fb_cpp
, ret
;
581 WARN_ON(drm_mm_node_allocated(&fbc
->compressed_fb
));
583 size
= intel_fbc_calculate_cfb_size(dev_priv
, &fbc
->state_cache
);
584 fb_cpp
= drm_format_plane_cpp(fbc
->state_cache
.fb
.pixel_format
, 0);
586 ret
= find_compression_threshold(dev_priv
, &fbc
->compressed_fb
,
591 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
595 fbc
->threshold
= ret
;
597 if (INTEL_GEN(dev_priv
) >= 5)
598 I915_WRITE(ILK_DPFC_CB_BASE
, fbc
->compressed_fb
.start
);
599 else if (IS_GM45(dev_priv
)) {
600 I915_WRITE(DPFC_CB_BASE
, fbc
->compressed_fb
.start
);
602 compressed_llb
= kzalloc(sizeof(*compressed_llb
), GFP_KERNEL
);
606 ret
= i915_gem_stolen_insert_node(dev_priv
, compressed_llb
,
611 fbc
->compressed_llb
= compressed_llb
;
613 I915_WRITE(FBC_CFB_BASE
,
614 dev_priv
->mm
.stolen_base
+ fbc
->compressed_fb
.start
);
615 I915_WRITE(FBC_LL_BASE
,
616 dev_priv
->mm
.stolen_base
+ compressed_llb
->start
);
619 DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
620 fbc
->compressed_fb
.size
, fbc
->threshold
);
625 kfree(compressed_llb
);
626 i915_gem_stolen_remove_node(dev_priv
, &fbc
->compressed_fb
);
628 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size
);
632 static void __intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
634 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
636 if (drm_mm_node_allocated(&fbc
->compressed_fb
))
637 i915_gem_stolen_remove_node(dev_priv
, &fbc
->compressed_fb
);
639 if (fbc
->compressed_llb
) {
640 i915_gem_stolen_remove_node(dev_priv
, fbc
->compressed_llb
);
641 kfree(fbc
->compressed_llb
);
645 void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv
)
647 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
649 if (!fbc_supported(dev_priv
))
652 mutex_lock(&fbc
->lock
);
653 __intel_fbc_cleanup_cfb(dev_priv
);
654 mutex_unlock(&fbc
->lock
);
657 static bool stride_is_valid(struct drm_i915_private
*dev_priv
,
660 /* These should have been caught earlier. */
661 WARN_ON(stride
< 512);
662 WARN_ON((stride
& (64 - 1)) != 0);
664 /* Below are the additional FBC restrictions. */
666 if (IS_GEN2(dev_priv
) || IS_GEN3(dev_priv
))
667 return stride
== 4096 || stride
== 8192;
669 if (IS_GEN4(dev_priv
) && !IS_G4X(dev_priv
) && stride
< 2048)
678 static bool pixel_format_is_valid(struct drm_i915_private
*dev_priv
,
679 uint32_t pixel_format
)
681 switch (pixel_format
) {
682 case DRM_FORMAT_XRGB8888
:
683 case DRM_FORMAT_XBGR8888
:
685 case DRM_FORMAT_XRGB1555
:
686 case DRM_FORMAT_RGB565
:
687 /* 16bpp not supported on gen2 */
688 if (IS_GEN2(dev_priv
))
690 /* WaFbcOnly1to1Ratio:ctg */
691 if (IS_G4X(dev_priv
))
700 * For some reason, the hardware tracking starts looking at whatever we
701 * programmed as the display plane base address register. It does not look at
702 * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
703 * variables instead of just looking at the pipe/plane size.
705 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc
*crtc
)
707 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
708 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
709 unsigned int effective_w
, effective_h
, max_w
, max_h
;
711 if (INTEL_GEN(dev_priv
) >= 8 || IS_HASWELL(dev_priv
)) {
714 } else if (IS_G4X(dev_priv
) || INTEL_GEN(dev_priv
) >= 5) {
722 intel_fbc_get_plane_source_size(&fbc
->state_cache
, &effective_w
,
724 effective_w
+= crtc
->adjusted_x
;
725 effective_h
+= crtc
->adjusted_y
;
727 return effective_w
<= max_w
&& effective_h
<= max_h
;
730 /* XXX replace me when we have VMA tracking for intel_plane_state */
731 static int get_fence_id(struct drm_framebuffer
*fb
)
733 struct i915_vma
*vma
= i915_gem_object_to_ggtt(intel_fb_obj(fb
), NULL
);
735 return vma
&& vma
->fence
? vma
->fence
->id
: I915_FENCE_REG_NONE
;
738 static void intel_fbc_update_state_cache(struct intel_crtc
*crtc
,
739 struct intel_crtc_state
*crtc_state
,
740 struct intel_plane_state
*plane_state
)
742 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
743 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
744 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
745 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
746 struct drm_i915_gem_object
*obj
;
748 cache
->crtc
.mode_flags
= crtc_state
->base
.adjusted_mode
.flags
;
749 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
750 cache
->crtc
.hsw_bdw_pixel_rate
=
751 ilk_pipe_pixel_rate(crtc_state
);
753 cache
->plane
.rotation
= plane_state
->base
.rotation
;
754 cache
->plane
.src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
755 cache
->plane
.src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
756 cache
->plane
.visible
= plane_state
->base
.visible
;
758 if (!cache
->plane
.visible
)
761 obj
= intel_fb_obj(fb
);
763 /* FIXME: We lack the proper locking here, so only run this on the
764 * platforms that need. */
765 if (IS_GEN(dev_priv
, 5, 6))
766 cache
->fb
.ilk_ggtt_offset
= i915_gem_object_ggtt_offset(obj
, NULL
);
767 cache
->fb
.pixel_format
= fb
->pixel_format
;
768 cache
->fb
.stride
= fb
->pitches
[0];
769 cache
->fb
.fence_reg
= get_fence_id(fb
);
770 cache
->fb
.tiling_mode
= i915_gem_object_get_tiling(obj
);
773 static bool intel_fbc_can_activate(struct intel_crtc
*crtc
)
775 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
776 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
777 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
779 /* We don't need to use a state cache here since this information is
780 * global for all CRTC.
782 if (fbc
->underrun_detected
) {
783 fbc
->no_fbc_reason
= "underrun detected";
787 if (!cache
->plane
.visible
) {
788 fbc
->no_fbc_reason
= "primary plane not visible";
792 if ((cache
->crtc
.mode_flags
& DRM_MODE_FLAG_INTERLACE
) ||
793 (cache
->crtc
.mode_flags
& DRM_MODE_FLAG_DBLSCAN
)) {
794 fbc
->no_fbc_reason
= "incompatible mode";
798 if (!intel_fbc_hw_tracking_covers_screen(crtc
)) {
799 fbc
->no_fbc_reason
= "mode too large for compression";
803 /* The use of a CPU fence is mandatory in order to detect writes
804 * by the CPU to the scanout and trigger updates to the FBC.
806 * Note that is possible for a tiled surface to be unmappable (and
807 * so have no fence associated with it) due to aperture constaints
808 * at the time of pinning.
810 if (cache
->fb
.tiling_mode
!= I915_TILING_X
||
811 cache
->fb
.fence_reg
== I915_FENCE_REG_NONE
) {
812 fbc
->no_fbc_reason
= "framebuffer not tiled or fenced";
815 if (INTEL_GEN(dev_priv
) <= 4 && !IS_G4X(dev_priv
) &&
816 cache
->plane
.rotation
!= DRM_ROTATE_0
) {
817 fbc
->no_fbc_reason
= "rotation unsupported";
821 if (!stride_is_valid(dev_priv
, cache
->fb
.stride
)) {
822 fbc
->no_fbc_reason
= "framebuffer stride not supported";
826 if (!pixel_format_is_valid(dev_priv
, cache
->fb
.pixel_format
)) {
827 fbc
->no_fbc_reason
= "pixel format is invalid";
831 /* WaFbcExceedCdClockThreshold:hsw,bdw */
832 if ((IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) &&
833 cache
->crtc
.hsw_bdw_pixel_rate
>= dev_priv
->cdclk_freq
* 95 / 100) {
834 fbc
->no_fbc_reason
= "pixel rate is too big";
838 /* It is possible for the required CFB size change without a
839 * crtc->disable + crtc->enable since it is possible to change the
840 * stride without triggering a full modeset. Since we try to
841 * over-allocate the CFB, there's a chance we may keep FBC enabled even
842 * if this happens, but if we exceed the current CFB size we'll have to
843 * disable FBC. Notice that it would be possible to disable FBC, wait
844 * for a frame, free the stolen node, then try to reenable FBC in case
845 * we didn't get any invalidate/deactivate calls, but this would require
846 * a lot of tracking just for a specific case. If we conclude it's an
847 * important case, we can implement it later. */
848 if (intel_fbc_calculate_cfb_size(dev_priv
, &fbc
->state_cache
) >
849 fbc
->compressed_fb
.size
* fbc
->threshold
) {
850 fbc
->no_fbc_reason
= "CFB requirements changed";
857 static bool intel_fbc_can_enable(struct drm_i915_private
*dev_priv
)
859 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
861 if (intel_vgpu_active(dev_priv
)) {
862 fbc
->no_fbc_reason
= "VGPU is active";
866 if (!i915
.enable_fbc
) {
867 fbc
->no_fbc_reason
= "disabled per module param or by default";
871 if (fbc
->underrun_detected
) {
872 fbc
->no_fbc_reason
= "underrun detected";
879 static void intel_fbc_get_reg_params(struct intel_crtc
*crtc
,
880 struct intel_fbc_reg_params
*params
)
882 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
883 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
884 struct intel_fbc_state_cache
*cache
= &fbc
->state_cache
;
886 /* Since all our fields are integer types, use memset here so the
887 * comparison function can rely on memcmp because the padding will be
889 memset(params
, 0, sizeof(*params
));
891 params
->crtc
.pipe
= crtc
->pipe
;
892 params
->crtc
.plane
= crtc
->plane
;
893 params
->crtc
.fence_y_offset
= get_crtc_fence_y_offset(crtc
);
895 params
->fb
.pixel_format
= cache
->fb
.pixel_format
;
896 params
->fb
.stride
= cache
->fb
.stride
;
897 params
->fb
.fence_reg
= cache
->fb
.fence_reg
;
899 params
->cfb_size
= intel_fbc_calculate_cfb_size(dev_priv
, cache
);
901 params
->fb
.ggtt_offset
= cache
->fb
.ilk_ggtt_offset
;
904 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params
*params1
,
905 struct intel_fbc_reg_params
*params2
)
907 /* We can use this since intel_fbc_get_reg_params() does a memset. */
908 return memcmp(params1
, params2
, sizeof(*params1
)) == 0;
911 void intel_fbc_pre_update(struct intel_crtc
*crtc
,
912 struct intel_crtc_state
*crtc_state
,
913 struct intel_plane_state
*plane_state
)
915 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
916 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
918 if (!fbc_supported(dev_priv
))
921 mutex_lock(&fbc
->lock
);
923 if (!multiple_pipes_ok(crtc
, plane_state
)) {
924 fbc
->no_fbc_reason
= "more than one pipe active";
928 if (!fbc
->enabled
|| fbc
->crtc
!= crtc
)
931 intel_fbc_update_state_cache(crtc
, crtc_state
, plane_state
);
934 intel_fbc_deactivate(dev_priv
);
936 mutex_unlock(&fbc
->lock
);
939 static void __intel_fbc_post_update(struct intel_crtc
*crtc
)
941 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
942 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
943 struct intel_fbc_reg_params old_params
;
945 WARN_ON(!mutex_is_locked(&fbc
->lock
));
947 if (!fbc
->enabled
|| fbc
->crtc
!= crtc
)
950 if (!intel_fbc_can_activate(crtc
)) {
951 WARN_ON(fbc
->active
);
955 old_params
= fbc
->params
;
956 intel_fbc_get_reg_params(crtc
, &fbc
->params
);
958 /* If the scanout has not changed, don't modify the FBC settings.
959 * Note that we make the fundamental assumption that the fb->obj
960 * cannot be unpinned (and have its GTT offset and fence revoked)
961 * without first being decoupled from the scanout and FBC disabled.
964 intel_fbc_reg_params_equal(&old_params
, &fbc
->params
))
967 intel_fbc_deactivate(dev_priv
);
968 intel_fbc_schedule_activation(crtc
);
969 fbc
->no_fbc_reason
= "FBC enabled (active or scheduled)";
972 void intel_fbc_post_update(struct intel_crtc
*crtc
)
974 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
975 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
977 if (!fbc_supported(dev_priv
))
980 mutex_lock(&fbc
->lock
);
981 __intel_fbc_post_update(crtc
);
982 mutex_unlock(&fbc
->lock
);
985 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc
*fbc
)
988 return to_intel_plane(fbc
->crtc
->base
.primary
)->frontbuffer_bit
;
990 return fbc
->possible_framebuffer_bits
;
993 void intel_fbc_invalidate(struct drm_i915_private
*dev_priv
,
994 unsigned int frontbuffer_bits
,
995 enum fb_op_origin origin
)
997 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
999 if (!fbc_supported(dev_priv
))
1002 if (origin
== ORIGIN_GTT
|| origin
== ORIGIN_FLIP
)
1005 mutex_lock(&fbc
->lock
);
1007 fbc
->busy_bits
|= intel_fbc_get_frontbuffer_bit(fbc
) & frontbuffer_bits
;
1009 if (fbc
->enabled
&& fbc
->busy_bits
)
1010 intel_fbc_deactivate(dev_priv
);
1012 mutex_unlock(&fbc
->lock
);
1015 void intel_fbc_flush(struct drm_i915_private
*dev_priv
,
1016 unsigned int frontbuffer_bits
, enum fb_op_origin origin
)
1018 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1020 if (!fbc_supported(dev_priv
))
1023 mutex_lock(&fbc
->lock
);
1025 fbc
->busy_bits
&= ~frontbuffer_bits
;
1027 if (origin
== ORIGIN_GTT
|| origin
== ORIGIN_FLIP
)
1030 if (!fbc
->busy_bits
&& fbc
->enabled
&&
1031 (frontbuffer_bits
& intel_fbc_get_frontbuffer_bit(fbc
))) {
1033 intel_fbc_recompress(dev_priv
);
1035 __intel_fbc_post_update(fbc
->crtc
);
1039 mutex_unlock(&fbc
->lock
);
1043 * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1044 * @dev_priv: i915 device instance
1045 * @state: the atomic state structure
1047 * This function looks at the proposed state for CRTCs and planes, then chooses
1048 * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1051 * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1052 * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1054 void intel_fbc_choose_crtc(struct drm_i915_private
*dev_priv
,
1055 struct drm_atomic_state
*state
)
1057 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1058 struct drm_plane
*plane
;
1059 struct drm_plane_state
*plane_state
;
1060 bool crtc_chosen
= false;
1063 mutex_lock(&fbc
->lock
);
1065 /* Does this atomic commit involve the CRTC currently tied to FBC? */
1067 !drm_atomic_get_existing_crtc_state(state
, &fbc
->crtc
->base
))
1070 if (!intel_fbc_can_enable(dev_priv
))
1073 /* Simply choose the first CRTC that is compatible and has a visible
1074 * plane. We could go for fancier schemes such as checking the plane
1075 * size, but this would just affect the few platforms that don't tie FBC
1076 * to pipe or plane A. */
1077 for_each_plane_in_state(state
, plane
, plane_state
, i
) {
1078 struct intel_plane_state
*intel_plane_state
=
1079 to_intel_plane_state(plane_state
);
1080 struct intel_crtc_state
*intel_crtc_state
;
1081 struct intel_crtc
*crtc
= to_intel_crtc(plane_state
->crtc
);
1083 if (!intel_plane_state
->base
.visible
)
1086 if (fbc_on_pipe_a_only(dev_priv
) && crtc
->pipe
!= PIPE_A
)
1089 if (fbc_on_plane_a_only(dev_priv
) && crtc
->plane
!= PLANE_A
)
1092 intel_crtc_state
= to_intel_crtc_state(
1093 drm_atomic_get_existing_crtc_state(state
, &crtc
->base
));
1095 intel_crtc_state
->enable_fbc
= true;
1101 fbc
->no_fbc_reason
= "no suitable CRTC for FBC";
1104 mutex_unlock(&fbc
->lock
);
1108 * intel_fbc_enable: tries to enable FBC on the CRTC
1110 * @crtc_state: corresponding &drm_crtc_state for @crtc
1111 * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1113 * This function checks if the given CRTC was chosen for FBC, then enables it if
1114 * possible. Notice that it doesn't activate FBC. It is valid to call
1115 * intel_fbc_enable multiple times for the same pipe without an
1116 * intel_fbc_disable in the middle, as long as it is deactivated.
1118 void intel_fbc_enable(struct intel_crtc
*crtc
,
1119 struct intel_crtc_state
*crtc_state
,
1120 struct intel_plane_state
*plane_state
)
1122 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1123 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1125 if (!fbc_supported(dev_priv
))
1128 mutex_lock(&fbc
->lock
);
1131 WARN_ON(fbc
->crtc
== NULL
);
1132 if (fbc
->crtc
== crtc
) {
1133 WARN_ON(!crtc_state
->enable_fbc
);
1134 WARN_ON(fbc
->active
);
1139 if (!crtc_state
->enable_fbc
)
1142 WARN_ON(fbc
->active
);
1143 WARN_ON(fbc
->crtc
!= NULL
);
1145 intel_fbc_update_state_cache(crtc
, crtc_state
, plane_state
);
1146 if (intel_fbc_alloc_cfb(crtc
)) {
1147 fbc
->no_fbc_reason
= "not enough stolen memory";
1151 DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc
->pipe
));
1152 fbc
->no_fbc_reason
= "FBC enabled but not active yet\n";
1154 fbc
->enabled
= true;
1157 mutex_unlock(&fbc
->lock
);
1161 * __intel_fbc_disable - disable FBC
1162 * @dev_priv: i915 device instance
1164 * This is the low level function that actually disables FBC. Callers should
1165 * grab the FBC lock.
1167 static void __intel_fbc_disable(struct drm_i915_private
*dev_priv
)
1169 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1170 struct intel_crtc
*crtc
= fbc
->crtc
;
1172 WARN_ON(!mutex_is_locked(&fbc
->lock
));
1173 WARN_ON(!fbc
->enabled
);
1174 WARN_ON(fbc
->active
);
1175 WARN_ON(crtc
->active
);
1177 DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc
->pipe
));
1179 __intel_fbc_cleanup_cfb(dev_priv
);
1181 fbc
->enabled
= false;
1186 * intel_fbc_disable - disable FBC if it's associated with crtc
1189 * This function disables FBC if it's associated with the provided CRTC.
1191 void intel_fbc_disable(struct intel_crtc
*crtc
)
1193 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1194 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1196 if (!fbc_supported(dev_priv
))
1199 mutex_lock(&fbc
->lock
);
1200 if (fbc
->crtc
== crtc
)
1201 __intel_fbc_disable(dev_priv
);
1202 mutex_unlock(&fbc
->lock
);
1204 cancel_work_sync(&fbc
->work
.work
);
1208 * intel_fbc_global_disable - globally disable FBC
1209 * @dev_priv: i915 device instance
1211 * This function disables FBC regardless of which CRTC is associated with it.
1213 void intel_fbc_global_disable(struct drm_i915_private
*dev_priv
)
1215 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1217 if (!fbc_supported(dev_priv
))
1220 mutex_lock(&fbc
->lock
);
1222 __intel_fbc_disable(dev_priv
);
1223 mutex_unlock(&fbc
->lock
);
1225 cancel_work_sync(&fbc
->work
.work
);
1228 static void intel_fbc_underrun_work_fn(struct work_struct
*work
)
1230 struct drm_i915_private
*dev_priv
=
1231 container_of(work
, struct drm_i915_private
, fbc
.underrun_work
);
1232 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1234 mutex_lock(&fbc
->lock
);
1236 /* Maybe we were scheduled twice. */
1237 if (fbc
->underrun_detected
)
1240 DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1241 fbc
->underrun_detected
= true;
1243 intel_fbc_deactivate(dev_priv
);
1245 mutex_unlock(&fbc
->lock
);
1249 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1250 * @dev_priv: i915 device instance
1252 * Without FBC, most underruns are harmless and don't really cause too many
1253 * problems, except for an annoying message on dmesg. With FBC, underruns can
1254 * become black screens or even worse, especially when paired with bad
1255 * watermarks. So in order for us to be on the safe side, completely disable FBC
1256 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1257 * already suggests that watermarks may be bad, so try to be as safe as
1260 * This function is called from the IRQ handler.
1262 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private
*dev_priv
)
1264 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1266 if (!fbc_supported(dev_priv
))
1269 /* There's no guarantee that underrun_detected won't be set to true
1270 * right after this check and before the work is scheduled, but that's
1271 * not a problem since we'll check it again under the work function
1272 * while FBC is locked. This check here is just to prevent us from
1273 * unnecessarily scheduling the work, and it relies on the fact that we
1274 * never switch underrun_detect back to false after it's true. */
1275 if (READ_ONCE(fbc
->underrun_detected
))
1278 schedule_work(&fbc
->underrun_work
);
1282 * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1283 * @dev_priv: i915 device instance
1285 * The FBC code needs to track CRTC visibility since the older platforms can't
1286 * have FBC enabled while multiple pipes are used. This function does the
1287 * initial setup at driver load to make sure FBC is matching the real hardware.
1289 void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv
)
1291 struct intel_crtc
*crtc
;
1293 /* Don't even bother tracking anything if we don't need. */
1294 if (!no_fbc_on_multiple_pipes(dev_priv
))
1297 for_each_intel_crtc(&dev_priv
->drm
, crtc
)
1298 if (intel_crtc_active(crtc
) &&
1299 to_intel_plane_state(crtc
->base
.primary
->state
)->base
.visible
)
1300 dev_priv
->fbc
.visible_pipes_mask
|= (1 << crtc
->pipe
);
1304 * The DDX driver changes its behavior depending on the value it reads from
1305 * i915.enable_fbc, so sanitize it by translating the default value into either
1306 * 0 or 1 in order to allow it to know what's going on.
1308 * Notice that this is done at driver initialization and we still allow user
1309 * space to change the value during runtime without sanitizing it again. IGT
1310 * relies on being able to change i915.enable_fbc at runtime.
1312 static int intel_sanitize_fbc_option(struct drm_i915_private
*dev_priv
)
1314 if (i915
.enable_fbc
>= 0)
1315 return !!i915
.enable_fbc
;
1317 if (!HAS_FBC(dev_priv
))
1320 if (IS_BROADWELL(dev_priv
))
1326 static bool need_fbc_vtd_wa(struct drm_i915_private
*dev_priv
)
1328 #ifdef CONFIG_INTEL_IOMMU
1329 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1330 if (intel_iommu_gfx_mapped
&&
1331 (IS_SKYLAKE(dev_priv
) || IS_BROXTON(dev_priv
))) {
1332 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1341 * intel_fbc_init - Initialize FBC
1342 * @dev_priv: the i915 device
1344 * This function might be called during PM init process.
1346 void intel_fbc_init(struct drm_i915_private
*dev_priv
)
1348 struct intel_fbc
*fbc
= &dev_priv
->fbc
;
1351 INIT_WORK(&fbc
->work
.work
, intel_fbc_work_fn
);
1352 INIT_WORK(&fbc
->underrun_work
, intel_fbc_underrun_work_fn
);
1353 mutex_init(&fbc
->lock
);
1354 fbc
->enabled
= false;
1355 fbc
->active
= false;
1356 fbc
->work
.scheduled
= false;
1358 if (need_fbc_vtd_wa(dev_priv
))
1359 mkwrite_device_info(dev_priv
)->has_fbc
= false;
1361 i915
.enable_fbc
= intel_sanitize_fbc_option(dev_priv
);
1362 DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915
.enable_fbc
);
1364 if (!HAS_FBC(dev_priv
)) {
1365 fbc
->no_fbc_reason
= "unsupported by this chipset";
1369 for_each_pipe(dev_priv
, pipe
) {
1370 fbc
->possible_framebuffer_bits
|=
1371 INTEL_FRONTBUFFER_PRIMARY(pipe
);
1373 if (fbc_on_pipe_a_only(dev_priv
))
1377 /* This value was pulled out of someone's hat */
1378 if (INTEL_GEN(dev_priv
) <= 4 && !IS_GM45(dev_priv
))
1379 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
1381 /* We still don't have any sort of hardware state readout for FBC, so
1382 * deactivate it in case the BIOS activated it to make sure software
1383 * matches the hardware state. */
1384 if (intel_fbc_hw_is_active(dev_priv
))
1385 intel_fbc_hw_deactivate(dev_priv
);