drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  *
  51  * TODO: When modesetting has fully transitioned to atomic, the below
  52  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  53  * added.
  54  */
  55 #define _wait_for(COND, US, W) ({ \
  56         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  57         int ret__;                                                      \
  58         for (;;) {                                                      \
  59                 bool expired__ = time_after(jiffies, timeout__);        \
  60                 if (COND) {                                             \
  61                         ret__ = 0;                                      \
  62                         break;                                          \
  63                 }                                                       \
  64                 if (expired__) {                                        \
  65                         ret__ = -ETIMEDOUT;                             \
  66                         break;                                          \
  67                 }                                                       \
  68                 if ((W) && drm_can_sleep()) {                           \
  69                         usleep_range((W), (W)*2);                       \
  70                 } else {                                                \
  71                         cpu_relax();                                    \
  72                 }                                                       \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  78
  79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  82 #else
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  84 #endif
  85
  86 #define _wait_for_atomic(COND, US, ATOMIC) \
  87 ({ \
  88         int cpu, ret, timeout = (US) * 1000; \
  89         u64 base; \
  90         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  91         BUILD_BUG_ON((US) > 50000); \
  92         if (!(ATOMIC)) { \
  93                 preempt_disable(); \
  94                 cpu = smp_processor_id(); \
  95         } \
  96         base = local_clock(); \
  97         for (;;) { \
  98                 u64 now = local_clock(); \
  99                 if (!(ATOMIC)) \
 100                         preempt_enable(); \
 101                 if (COND) { \
 102                         ret = 0; \
 103                         break; \
 104                 } \
 105                 if (now - base >= timeout) { \
 106                         ret = -ETIMEDOUT; \
 107                         break; \
 108                 } \
 109                 cpu_relax(); \
 110                 if (!(ATOMIC)) { \
 111                         preempt_disable(); \
 112                         if (unlikely(cpu != smp_processor_id())) { \
 113                                 timeout -= now - base; \
 114                                 cpu = smp_processor_id(); \
 115                                 base = local_clock(); \
 116                         } \
 117                 } \
 118         } \
 119         ret; \
 120 })
 121
 122 #define wait_for_us(COND, US) \
 123 ({ \
 124         int ret__; \
 125         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 126         if ((US) > 10) \
 127                 ret__ = _wait_for((COND), (US), 10); \
 128         else \
 129                 ret__ = _wait_for_atomic((COND), (US), 0); \
 130         ret__; \
 131 })
 132
 133 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 134 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 135
 136 #define KHz(x) (1000 * (x))
 137 #define MHz(x) KHz(1000 * (x))
 138
 139 /*
 140  * Display related stuff
 141  */
 142
 143 /* store information about an Ixxx DVO */
 144 /* The i830->i865 use multiple DVOs with multiple i2cs */
 145 /* the i915, i945 have a single sDVO i2c bus - which is different */
 146 #define MAX_OUTPUTS 6
 147 /* maximum connectors per crtcs in the mode set */
 148
 149 /* Maximum cursor sizes */
 150 #define GEN2_CURSOR_WIDTH 64
 151 #define GEN2_CURSOR_HEIGHT 64
 152 #define MAX_CURSOR_WIDTH 256
 153 #define MAX_CURSOR_HEIGHT 256
 154
 155 #define INTEL_I2C_BUS_DVO 1
 156 #define INTEL_I2C_BUS_SDVO 2
 157
 158 /* these are outputs from the chip - integrated only
 159    external chips are via DVO or SDVO output */
 160 enum intel_output_type {
 161         INTEL_OUTPUT_UNUSED = 0,
 162         INTEL_OUTPUT_ANALOG = 1,
 163         INTEL_OUTPUT_DVO = 2,
 164         INTEL_OUTPUT_SDVO = 3,
 165         INTEL_OUTPUT_LVDS = 4,
 166         INTEL_OUTPUT_TVOUT = 5,
 167         INTEL_OUTPUT_HDMI = 6,
 168         INTEL_OUTPUT_DP = 7,
 169         INTEL_OUTPUT_EDP = 8,
 170         INTEL_OUTPUT_DSI = 9,
 171         INTEL_OUTPUT_UNKNOWN = 10,
 172         INTEL_OUTPUT_DP_MST = 11,
 173 };
 174
 175 #define INTEL_DVO_CHIP_NONE 0
 176 #define INTEL_DVO_CHIP_LVDS 1
 177 #define INTEL_DVO_CHIP_TMDS 2
 178 #define INTEL_DVO_CHIP_TVOUT 4
 179
 180 #define INTEL_DSI_VIDEO_MODE    0
 181 #define INTEL_DSI_COMMAND_MODE  1
 182
 183 struct intel_framebuffer {
 184         struct drm_framebuffer base;
 185         struct drm_i915_gem_object *obj;
 186         struct intel_rotation_info rot_info;
 187
 188         /* for each plane in the normal GTT view */
 189         struct {
 190                 unsigned int x, y;
 191         } normal[2];
 192         /* for each plane in the rotated GTT view */
 193         struct {
 194                 unsigned int x, y;
 195                 unsigned int pitch; /* pixels */
 196         } rotated[2];
 197 };
 198
 199 struct intel_fbdev {
 200         struct drm_fb_helper helper;
 201         struct intel_framebuffer *fb;
 202         struct i915_vma *vma;
 203         async_cookie_t cookie;
 204         int preferred_bpp;
 205 };
 206
 207 struct intel_encoder {
 208         struct drm_encoder base;
 209
 210         enum intel_output_type type;
 211         enum port port;
 212         unsigned int cloneable;
 213         void (*hot_plug)(struct intel_encoder *);
 214         bool (*compute_config)(struct intel_encoder *,
 215                                struct intel_crtc_state *,
 216                                struct drm_connector_state *);
 217         void (*pre_pll_enable)(struct intel_encoder *,
 218                                struct intel_crtc_state *,
 219                                struct drm_connector_state *);
 220         void (*pre_enable)(struct intel_encoder *,
 221                            struct intel_crtc_state *,
 222                            struct drm_connector_state *);
 223         void (*enable)(struct intel_encoder *,
 224                        struct intel_crtc_state *,
 225                        struct drm_connector_state *);
 226         void (*disable)(struct intel_encoder *,
 227                         struct intel_crtc_state *,
 228                         struct drm_connector_state *);
 229         void (*post_disable)(struct intel_encoder *,
 230                              struct intel_crtc_state *,
 231                              struct drm_connector_state *);
 232         void (*post_pll_disable)(struct intel_encoder *,
 233                                  struct intel_crtc_state *,
 234                                  struct drm_connector_state *);
 235         /* Read out the current hw state of this connector, returning true if
 236          * the encoder is active. If the encoder is enabled it also set the pipe
 237          * it is connected to in the pipe parameter. */
 238         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 239         /* Reconstructs the equivalent mode flags for the current hardware
 240          * state. This must be called _after_ display->get_pipe_config has
 241          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 242          * be set correctly before calling this function. */
 243         void (*get_config)(struct intel_encoder *,
 244                            struct intel_crtc_state *pipe_config);
 245         /*
 246          * Called during system suspend after all pending requests for the
 247          * encoder are flushed (for example for DP AUX transactions) and
 248          * device interrupts are disabled.
 249          */
 250         void (*suspend)(struct intel_encoder *);
 251         int crtc_mask;
 252         enum hpd_pin hpd_pin;
 253         /* for communication with audio component; protected by av_mutex */
 254         const struct drm_connector *audio_connector;
 255 };
 256
 257 struct intel_panel {
 258         struct drm_display_mode *fixed_mode;
 259         struct drm_display_mode *downclock_mode;
 260         int fitting_mode;
 261
 262         /* backlight */
 263         struct {
 264                 bool present;
 265                 u32 level;
 266                 u32 min;
 267                 u32 max;
 268                 bool enabled;
 269                 bool combination_mode;  /* gen 2/4 only */
 270                 bool active_low_pwm;
 271                 bool alternate_pwm_increment;   /* lpt+ */
 272
 273                 /* PWM chip */
 274                 bool util_pin_active_low;       /* bxt+ */
 275                 u8 controller;          /* bxt+ only */
 276                 struct pwm_device *pwm;
 277
 278                 struct backlight_device *device;
 279
 280                 /* Connector and platform specific backlight functions */
 281                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 282                 uint32_t (*get)(struct intel_connector *connector);
 283                 void (*set)(struct intel_connector *connector, uint32_t level);
 284                 void (*disable)(struct intel_connector *connector);
 285                 void (*enable)(struct intel_connector *connector);
 286                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 287                                       uint32_t hz);
 288                 void (*power)(struct intel_connector *, bool enable);
 289         } backlight;
 290 };
 291
 292 struct intel_connector {
 293         struct drm_connector base;
 294         /*
 295          * The fixed encoder this connector is connected to.
 296          */
 297         struct intel_encoder *encoder;
 298
 299         /* ACPI device id for ACPI and driver cooperation */
 300         u32 acpi_device_id;
 301
 302         /* Reads out the current hw, returning true if the connector is enabled
 303          * and active (i.e. dpms ON state). */
 304         bool (*get_hw_state)(struct intel_connector *);
 305
 306         /* Panel info for eDP and LVDS */
 307         struct intel_panel panel;
 308
 309         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 310         struct edid *edid;
 311         struct edid *detect_edid;
 312
 313         /* since POLL and HPD connectors may use the same HPD line keep the native
 314            state of connector->polled in case hotplug storm detection changes it */
 315         u8 polled;
 316
 317         void *port; /* store this opaque as its illegal to dereference it */
 318
 319         struct intel_dp *mst_port;
 320 };
 321
 322 struct dpll {
 323         /* given values */
 324         int n;
 325         int m1, m2;
 326         int p1, p2;
 327         /* derived values */
 328         int     dot;
 329         int     vco;
 330         int     m;
 331         int     p;
 332 };
 333
 334 struct intel_atomic_state {
 335         struct drm_atomic_state base;
 336
 337         unsigned int cdclk;
 338
 339         /*
 340          * Calculated device cdclk, can be different from cdclk
 341          * only when all crtc's are DPMS off.
 342          */
 343         unsigned int dev_cdclk;
 344
 345         bool dpll_set, modeset;
 346
 347         /*
 348          * Does this transaction change the pipes that are active?  This mask
 349          * tracks which CRTC's have changed their active state at the end of
 350          * the transaction (not counting the temporary disable during modesets).
 351          * This mask should only be non-zero when intel_state->modeset is true,
 352          * but the converse is not necessarily true; simply changing a mode may
 353          * not flip the final active status of any CRTC's
 354          */
 355         unsigned int active_pipe_changes;
 356
 357         unsigned int active_crtcs;
 358         unsigned int min_pixclk[I915_MAX_PIPES];
 359
 360         /* SKL/KBL Only */
 361         unsigned int cdclk_pll_vco;
 362
 363         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 364
 365         /*
 366          * Current watermarks can't be trusted during hardware readout, so
 367          * don't bother calculating intermediate watermarks.
 368          */
 369         bool skip_intermediate_wm;
 370
 371         /* Gen9+ only */
 372         struct skl_wm_values wm_results;
 373
 374         struct i915_sw_fence commit_ready;
 375
 376         struct llist_node freed;
 377 };
 378
 379 struct intel_plane_state {
 380         struct drm_plane_state base;
 381         struct drm_rect clip;
 382         struct i915_vma *vma;
 383
 384         struct {
 385                 u32 offset;
 386                 int x, y;
 387         } main;
 388         struct {
 389                 u32 offset;
 390                 int x, y;
 391         } aux;
 392
 393         /*
 394          * scaler_id
 395          *    = -1 : not using a scaler
 396          *    >=  0 : using a scalers
 397          *
 398          * plane requiring a scaler:
 399          *   - During check_plane, its bit is set in
 400          *     crtc_state->scaler_state.scaler_users by calling helper function
 401          *     update_scaler_plane.
 402          *   - scaler_id indicates the scaler it got assigned.
 403          *
 404          * plane doesn't require a scaler:
 405          *   - this can happen when scaling is no more required or plane simply
 406          *     got disabled.
 407          *   - During check_plane, corresponding bit is reset in
 408          *     crtc_state->scaler_state.scaler_users by calling helper function
 409          *     update_scaler_plane.
 410          */
 411         int scaler_id;
 412
 413         struct drm_intel_sprite_colorkey ckey;
 414 };
 415
 416 struct intel_initial_plane_config {
 417         struct intel_framebuffer *fb;
 418         unsigned int tiling;
 419         int size;
 420         u32 base;
 421 };
 422
 423 #define SKL_MIN_SRC_W 8
 424 #define SKL_MAX_SRC_W 4096
 425 #define SKL_MIN_SRC_H 8
 426 #define SKL_MAX_SRC_H 4096
 427 #define SKL_MIN_DST_W 8
 428 #define SKL_MAX_DST_W 4096
 429 #define SKL_MIN_DST_H 8
 430 #define SKL_MAX_DST_H 4096
 431
 432 struct intel_scaler {
 433         int in_use;
 434         uint32_t mode;
 435 };
 436
 437 struct intel_crtc_scaler_state {
 438 #define SKL_NUM_SCALERS 2
 439         struct intel_scaler scalers[SKL_NUM_SCALERS];
 440
 441         /*
 442          * scaler_users: keeps track of users requesting scalers on this crtc.
 443          *
 444          *     If a bit is set, a user is using a scaler.
 445          *     Here user can be a plane or crtc as defined below:
 446          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 447          *       bit 31    - crtc
 448          *
 449          * Instead of creating a new index to cover planes and crtc, using
 450          * existing drm_plane_index for planes which is well less than 31
 451          * planes and bit 31 for crtc. This should be fine to cover all
 452          * our platforms.
 453          *
 454          * intel_atomic_setup_scalers will setup available scalers to users
 455          * requesting scalers. It will gracefully fail if request exceeds
 456          * avilability.
 457          */
 458 #define SKL_CRTC_INDEX 31
 459         unsigned scaler_users;
 460
 461         /* scaler used by crtc for panel fitting purpose */
 462         int scaler_id;
 463 };
 464
 465 /* drm_mode->private_flags */
 466 #define I915_MODE_FLAG_INHERITED 1
 467
 468 struct intel_pipe_wm {
 469         struct intel_wm_level wm[5];
 470         struct intel_wm_level raw_wm[5];
 471         uint32_t linetime;
 472         bool fbc_wm_enabled;
 473         bool pipe_enabled;
 474         bool sprites_enabled;
 475         bool sprites_scaled;
 476 };
 477
 478 struct skl_plane_wm {
 479         struct skl_wm_level wm[8];
 480         struct skl_wm_level trans_wm;
 481 };
 482
 483 struct skl_pipe_wm {
 484         struct skl_plane_wm planes[I915_MAX_PLANES];
 485         uint32_t linetime;
 486 };
 487
 488 struct intel_crtc_wm_state {
 489         union {
 490                 struct {
 491                         /*
 492                          * Intermediate watermarks; these can be
 493                          * programmed immediately since they satisfy
 494                          * both the current configuration we're
 495                          * switching away from and the new
 496                          * configuration we're switching to.
 497                          */
 498                         struct intel_pipe_wm intermediate;
 499
 500                         /*
 501                          * Optimal watermarks, programmed post-vblank
 502                          * when this state is committed.
 503                          */
 504                         struct intel_pipe_wm optimal;
 505                 } ilk;
 506
 507                 struct {
 508                         /* gen9+ only needs 1-step wm programming */
 509                         struct skl_pipe_wm optimal;
 510                         struct skl_ddb_entry ddb;
 511                 } skl;
 512         };
 513
 514         /*
 515          * Platforms with two-step watermark programming will need to
 516          * update watermark programming post-vblank to switch from the
 517          * safe intermediate watermarks to the optimal final
 518          * watermarks.
 519          */
 520         bool need_postvbl_update;
 521 };
 522
 523 struct intel_crtc_state {
 524         struct drm_crtc_state base;
 525
 526         /**
 527          * quirks - bitfield with hw state readout quirks
 528          *
 529          * For various reasons the hw state readout code might not be able to
 530          * completely faithfully read out the current state. These cases are
 531          * tracked with quirk flags so that fastboot and state checker can act
 532          * accordingly.
 533          */
 534 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 535         unsigned long quirks;
 536
 537         unsigned fb_bits; /* framebuffers to flip */
 538         bool update_pipe; /* can a fast modeset be performed? */
 539         bool disable_cxsr;
 540         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 541         bool fb_changed; /* fb on any of the planes is changed */
 542
 543         /* Pipe source size (ie. panel fitter input size)
 544          * All planes will be positioned inside this space,
 545          * and get clipped at the edges. */
 546         int pipe_src_w, pipe_src_h;
 547
 548         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 549          * between pch encoders and cpu encoders. */
 550         bool has_pch_encoder;
 551
 552         /* Are we sending infoframes on the attached port */
 553         bool has_infoframe;
 554
 555         /* CPU Transcoder for the pipe. Currently this can only differ from the
 556          * pipe on Haswell and later (where we have a special eDP transcoder)
 557          * and Broxton (where we have special DSI transcoders). */
 558         enum transcoder cpu_transcoder;
 559
 560         /*
 561          * Use reduced/limited/broadcast rbg range, compressing from the full
 562          * range fed into the crtcs.
 563          */
 564         bool limited_color_range;
 565
 566         /* Bitmask of encoder types (enum intel_output_type)
 567          * driven by the pipe.
 568          */
 569         unsigned int output_types;
 570
 571         /* Whether we should send NULL infoframes. Required for audio. */
 572         bool has_hdmi_sink;
 573
 574         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 575          * has_dp_encoder is set. */
 576         bool has_audio;
 577
 578         /*
 579          * Enable dithering, used when the selected pipe bpp doesn't match the
 580          * plane bpp.
 581          */
 582         bool dither;
 583
 584         /* Controls for the clock computation, to override various stages. */
 585         bool clock_set;
 586
 587         /* SDVO TV has a bunch of special case. To make multifunction encoders
 588          * work correctly, we need to track this at runtime.*/
 589         bool sdvo_tv_clock;
 590
 591         /*
 592          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 593          * required. This is set in the 2nd loop of calling encoder's
 594          * ->compute_config if the first pick doesn't work out.
 595          */
 596         bool bw_constrained;
 597
 598         /* Settings for the intel dpll used on pretty much everything but
 599          * haswell. */
 600         struct dpll dpll;
 601
 602         /* Selected dpll when shared or NULL. */
 603         struct intel_shared_dpll *shared_dpll;
 604
 605         /* Actual register state of the dpll, for shared dpll cross-checking. */
 606         struct intel_dpll_hw_state dpll_hw_state;
 607
 608         /* DSI PLL registers */
 609         struct {
 610                 u32 ctrl, div;
 611         } dsi_pll;
 612
 613         int pipe_bpp;
 614         struct intel_link_m_n dp_m_n;
 615
 616         /* m2_n2 for eDP downclock */
 617         struct intel_link_m_n dp_m2_n2;
 618         bool has_drrs;
 619
 620         /*
 621          * Frequence the dpll for the port should run at. Differs from the
 622          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 623          * already multiplied by pixel_multiplier.
 624          */
 625         int port_clock;
 626
 627         /* Used by SDVO (and if we ever fix it, HDMI). */
 628         unsigned pixel_multiplier;
 629
 630         uint8_t lane_count;
 631
 632         /*
 633          * Used by platforms having DP/HDMI PHY with programmable lane
 634          * latency optimization.
 635          */
 636         uint8_t lane_lat_optim_mask;
 637
 638         /* Panel fitter controls for gen2-gen4 + VLV */
 639         struct {
 640                 u32 control;
 641                 u32 pgm_ratios;
 642                 u32 lvds_border_bits;
 643         } gmch_pfit;
 644
 645         /* Panel fitter placement and size for Ironlake+ */
 646         struct {
 647                 u32 pos;
 648                 u32 size;
 649                 bool enabled;
 650                 bool force_thru;
 651         } pch_pfit;
 652
 653         /* FDI configuration, only valid if has_pch_encoder is set. */
 654         int fdi_lanes;
 655         struct intel_link_m_n fdi_m_n;
 656
 657         bool ips_enabled;
 658
 659         bool enable_fbc;
 660
 661         bool double_wide;
 662
 663         int pbn;
 664
 665         struct intel_crtc_scaler_state scaler_state;
 666
 667         /* w/a for waiting 2 vblanks during crtc enable */
 668         enum pipe hsw_workaround_pipe;
 669
 670         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 671         bool disable_lp_wm;
 672
 673         struct intel_crtc_wm_state wm;
 674
 675         /* Gamma mode programmed on the pipe */
 676         uint32_t gamma_mode;
 677 };
 678
 679 struct vlv_wm_state {
 680         struct vlv_pipe_wm wm[3];
 681         struct vlv_sr_wm sr[3];
 682         uint8_t num_active_planes;
 683         uint8_t num_levels;
 684         uint8_t level;
 685         bool cxsr;
 686 };
 687
 688 struct intel_crtc {
 689         struct drm_crtc base;
 690         enum pipe pipe;
 691         enum plane plane;
 692         u8 lut_r[256], lut_g[256], lut_b[256];
 693         /*
 694          * Whether the crtc and the connected output pipeline is active. Implies
 695          * that crtc->enabled is set, i.e. the current mode configuration has
 696          * some outputs connected to this crtc.
 697          */
 698         bool active;
 699         bool lowfreq_avail;
 700         u8 plane_ids_mask;
 701         unsigned long enabled_power_domains;
 702         struct intel_overlay *overlay;
 703         struct intel_flip_work *flip_work;
 704
 705         atomic_t unpin_work_count;
 706
 707         /* Display surface base address adjustement for pageflips. Note that on
 708          * gen4+ this only adjusts up to a tile, offsets within a tile are
 709          * handled in the hw itself (with the TILEOFF register). */
 710         u32 dspaddr_offset;
 711         int adjusted_x;
 712         int adjusted_y;
 713
 714         uint32_t cursor_addr;
 715         uint32_t cursor_cntl;
 716         uint32_t cursor_size;
 717         uint32_t cursor_base;
 718
 719         struct intel_crtc_state *config;
 720
 721         /* global reset count when the last flip was submitted */
 722         unsigned int reset_count;
 723
 724         /* Access to these should be protected by dev_priv->irq_lock. */
 725         bool cpu_fifo_underrun_disabled;
 726         bool pch_fifo_underrun_disabled;
 727
 728         /* per-pipe watermark state */
 729         struct {
 730                 /* watermarks currently being used  */
 731                 union {
 732                         struct intel_pipe_wm ilk;
 733                 } active;
 734
 735                 /* allow CxSR on this pipe */
 736                 bool cxsr_allowed;
 737         } wm;
 738
 739         int scanline_offset;
 740
 741         struct {
 742                 unsigned start_vbl_count;
 743                 ktime_t start_vbl_time;
 744                 int min_vbl, max_vbl;
 745                 int scanline_start;
 746         } debug;
 747
 748         /* scalers available on this crtc */
 749         int num_scalers;
 750
 751         struct vlv_wm_state wm_state;
 752 };
 753
 754 struct intel_plane_wm_parameters {
 755         uint32_t horiz_pixels;
 756         uint32_t vert_pixels;
 757         /*
 758          *   For packed pixel formats:
 759          *     bytes_per_pixel - holds bytes per pixel
 760          *   For planar pixel formats:
 761          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 762          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 763          */
 764         uint8_t bytes_per_pixel;
 765         uint8_t y_bytes_per_pixel;
 766         bool enabled;
 767         bool scaled;
 768         u64 tiling;
 769         unsigned int rotation;
 770         uint16_t fifo_size;
 771 };
 772
 773 struct intel_plane {
 774         struct drm_plane base;
 775         u8 plane;
 776         enum plane_id id;
 777         enum pipe pipe;
 778         bool can_scale;
 779         int max_downscale;
 780         uint32_t frontbuffer_bit;
 781
 782         /* Since we need to change the watermarks before/after
 783          * enabling/disabling the planes, we need to store the parameters here
 784          * as the other pieces of the struct may not reflect the values we want
 785          * for the watermark calculations. Currently only Haswell uses this.
 786          */
 787         struct intel_plane_wm_parameters wm;
 788
 789         /*
 790          * NOTE: Do not place new plane state fields here (e.g., when adding
 791          * new plane properties).  New runtime state should now be placed in
 792          * the intel_plane_state structure and accessed via plane_state.
 793          */
 794
 795         void (*update_plane)(struct drm_plane *plane,
 796                              const struct intel_crtc_state *crtc_state,
 797                              const struct intel_plane_state *plane_state);
 798         void (*disable_plane)(struct drm_plane *plane,
 799                               struct drm_crtc *crtc);
 800         int (*check_plane)(struct drm_plane *plane,
 801                            struct intel_crtc_state *crtc_state,
 802                            struct intel_plane_state *state);
 803 };
 804
 805 struct intel_watermark_params {
 806         u16 fifo_size;
 807         u16 max_wm;
 808         u8 default_wm;
 809         u8 guard_size;
 810         u8 cacheline_size;
 811 };
 812
 813 struct cxsr_latency {
 814         bool is_desktop : 1;
 815         bool is_ddr3 : 1;
 816         u16 fsb_freq;
 817         u16 mem_freq;
 818         u16 display_sr;
 819         u16 display_hpll_disable;
 820         u16 cursor_sr;
 821         u16 cursor_hpll_disable;
 822 };
 823
 824 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 825 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 826 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 827 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 828 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 829 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 830 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 831 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 832 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 833
 834 struct intel_hdmi {
 835         i915_reg_t hdmi_reg;
 836         int ddc_bus;
 837         struct {
 838                 enum drm_dp_dual_mode_type type;
 839                 int max_tmds_clock;
 840         } dp_dual_mode;
 841         bool limited_color_range;
 842         bool color_range_auto;
 843         bool has_hdmi_sink;
 844         bool has_audio;
 845         enum hdmi_force_audio force_audio;
 846         bool rgb_quant_range_selectable;
 847         enum hdmi_picture_aspect aspect_ratio;
 848         struct intel_connector *attached_connector;
 849         void (*write_infoframe)(struct drm_encoder *encoder,
 850                                 const struct intel_crtc_state *crtc_state,
 851                                 enum hdmi_infoframe_type type,
 852                                 const void *frame, ssize_t len);
 853         void (*set_infoframes)(struct drm_encoder *encoder,
 854                                bool enable,
 855                                const struct intel_crtc_state *crtc_state,
 856                                const struct drm_connector_state *conn_state);
 857         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 858                                   const struct intel_crtc_state *pipe_config);
 859 };
 860
 861 struct intel_dp_mst_encoder;
 862 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 863
 864 /*
 865  * enum link_m_n_set:
 866  *      When platform provides two set of M_N registers for dp, we can
 867  *      program them and switch between them incase of DRRS.
 868  *      But When only one such register is provided, we have to program the
 869  *      required divider value on that registers itself based on the DRRS state.
 870  *
 871  * M1_N1        : Program dp_m_n on M1_N1 registers
 872  *                        dp_m2_n2 on M2_N2 registers (If supported)
 873  *
 874  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 875  *                        M2_N2 registers are not supported
 876  */
 877
 878 enum link_m_n_set {
 879         /* Sets the m1_n1 and m2_n2 */
 880         M1_N1 = 0,
 881         M2_N2
 882 };
 883
 884 struct intel_dp_desc {
 885         u8 oui[3];
 886         u8 device_id[6];
 887         u8 hw_rev;
 888         u8 sw_major_rev;
 889         u8 sw_minor_rev;
 890 } __packed;
 891
 892 struct intel_dp_compliance_data {
 893         unsigned long edid;
 894 };
 895
 896 struct intel_dp_compliance {
 897         unsigned long test_type;
 898         struct intel_dp_compliance_data test_data;
 899         bool test_active;
 900 };
 901
 902 struct intel_dp {
 903         i915_reg_t output_reg;
 904         i915_reg_t aux_ch_ctl_reg;
 905         i915_reg_t aux_ch_data_reg[5];
 906         uint32_t DP;
 907         int link_rate;
 908         uint8_t lane_count;
 909         uint8_t sink_count;
 910         bool link_mst;
 911         bool has_audio;
 912         bool detect_done;
 913         bool channel_eq_status;
 914         enum hdmi_force_audio force_audio;
 915         bool limited_color_range;
 916         bool color_range_auto;
 917         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 918         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 919         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 920         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 921         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 922         uint8_t num_sink_rates;
 923         int sink_rates[DP_MAX_SUPPORTED_RATES];
 924         /* Max lane count for the sink as per DPCD registers */
 925         uint8_t max_sink_lane_count;
 926         /* Max link BW for the sink as per DPCD registers */
 927         int max_sink_link_bw;
 928         /* sink or branch descriptor */
 929         struct intel_dp_desc desc;
 930         struct drm_dp_aux aux;
 931         uint8_t train_set[4];
 932         int panel_power_up_delay;
 933         int panel_power_down_delay;
 934         int panel_power_cycle_delay;
 935         int backlight_on_delay;
 936         int backlight_off_delay;
 937         struct delayed_work panel_vdd_work;
 938         bool want_panel_vdd;
 939         unsigned long last_power_on;
 940         unsigned long last_backlight_off;
 941         ktime_t panel_power_off_time;
 942
 943         struct notifier_block edp_notifier;
 944
 945         /*
 946          * Pipe whose power sequencer is currently locked into
 947          * this port. Only relevant on VLV/CHV.
 948          */
 949         enum pipe pps_pipe;
 950         /*
 951          * Pipe currently driving the port. Used for preventing
 952          * the use of the PPS for any pipe currentrly driving
 953          * external DP as that will mess things up on VLV.
 954          */
 955         enum pipe active_pipe;
 956         /*
 957          * Set if the sequencer may be reset due to a power transition,
 958          * requiring a reinitialization. Only relevant on BXT.
 959          */
 960         bool pps_reset;
 961         struct edp_power_seq pps_delays;
 962
 963         bool can_mst; /* this port supports mst */
 964         bool is_mst;
 965         int active_mst_links;
 966         /* connector directly attached - won't be use for modeset in mst world */
 967         struct intel_connector *attached_connector;
 968
 969         /* mst connector list */
 970         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 971         struct drm_dp_mst_topology_mgr mst_mgr;
 972
 973         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 974         /*
 975          * This function returns the value we have to program the AUX_CTL
 976          * register with to kick off an AUX transaction.
 977          */
 978         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 979                                      bool has_aux_irq,
 980                                      int send_bytes,
 981                                      uint32_t aux_clock_divider);
 982
 983         /* This is called before a link training is starterd */
 984         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 985
 986         /* Displayport compliance testing */
 987         struct intel_dp_compliance compliance;
 988 };
 989
 990 struct intel_lspcon {
 991         bool active;
 992         enum drm_lspcon_mode mode;
 993         bool desc_valid;
 994 };
 995
 996 struct intel_digital_port {
 997         struct intel_encoder base;
 998         enum port port;
 999         u32 saved_port_bits;
1000         struct intel_dp dp;
1001         struct intel_hdmi hdmi;
1002         struct intel_lspcon lspcon;
1003         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1004         bool release_cl2_override;
1005         uint8_t max_lanes;
1006 };
1007
1008 struct intel_dp_mst_encoder {
1009         struct intel_encoder base;
1010         enum pipe pipe;
1011         struct intel_digital_port *primary;
1012         struct intel_connector *connector;
1013 };
1014
1015 static inline enum dpio_channel
1016 vlv_dport_to_channel(struct intel_digital_port *dport)
1017 {
1018         switch (dport->port) {
1019         case PORT_B:
1020         case PORT_D:
1021                 return DPIO_CH0;
1022         case PORT_C:
1023                 return DPIO_CH1;
1024         default:
1025                 BUG();
1026         }
1027 }
1028
1029 static inline enum dpio_phy
1030 vlv_dport_to_phy(struct intel_digital_port *dport)
1031 {
1032         switch (dport->port) {
1033         case PORT_B:
1034         case PORT_C:
1035                 return DPIO_PHY0;
1036         case PORT_D:
1037                 return DPIO_PHY1;
1038         default:
1039                 BUG();
1040         }
1041 }
1042
1043 static inline enum dpio_channel
1044 vlv_pipe_to_channel(enum pipe pipe)
1045 {
1046         switch (pipe) {
1047         case PIPE_A:
1048         case PIPE_C:
1049                 return DPIO_CH0;
1050         case PIPE_B:
1051                 return DPIO_CH1;
1052         default:
1053                 BUG();
1054         }
1055 }
1056
1057 static inline struct intel_crtc *
1058 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1059 {
1060         return dev_priv->pipe_to_crtc_mapping[pipe];
1061 }
1062
1063 static inline struct intel_crtc *
1064 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1065 {
1066         return dev_priv->plane_to_crtc_mapping[plane];
1067 }
1068
1069 struct intel_flip_work {
1070         struct work_struct unpin_work;
1071         struct work_struct mmio_work;
1072
1073         struct drm_crtc *crtc;
1074         struct i915_vma *old_vma;
1075         struct drm_framebuffer *old_fb;
1076         struct drm_i915_gem_object *pending_flip_obj;
1077         struct drm_pending_vblank_event *event;
1078         atomic_t pending;
1079         u32 flip_count;
1080         u32 gtt_offset;
1081         struct drm_i915_gem_request *flip_queued_req;
1082         u32 flip_queued_vblank;
1083         u32 flip_ready_vblank;
1084         unsigned int rotation;
1085 };
1086
1087 struct intel_load_detect_pipe {
1088         struct drm_atomic_state *restore_state;
1089 };
1090
1091 static inline struct intel_encoder *
1092 intel_attached_encoder(struct drm_connector *connector)
1093 {
1094         return to_intel_connector(connector)->encoder;
1095 }
1096
1097 static inline struct intel_digital_port *
1098 enc_to_dig_port(struct drm_encoder *encoder)
1099 {
1100         return container_of(encoder, struct intel_digital_port, base.base);
1101 }
1102
1103 static inline struct intel_dp_mst_encoder *
1104 enc_to_mst(struct drm_encoder *encoder)
1105 {
1106         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1107 }
1108
1109 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1110 {
1111         return &enc_to_dig_port(encoder)->dp;
1112 }
1113
1114 static inline struct intel_digital_port *
1115 dp_to_dig_port(struct intel_dp *intel_dp)
1116 {
1117         return container_of(intel_dp, struct intel_digital_port, dp);
1118 }
1119
1120 static inline struct intel_lspcon *
1121 dp_to_lspcon(struct intel_dp *intel_dp)
1122 {
1123         return &dp_to_dig_port(intel_dp)->lspcon;
1124 }
1125
1126 static inline struct intel_digital_port *
1127 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1128 {
1129         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1130 }
1131
1132 /* intel_fifo_underrun.c */
1133 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1134                                            enum pipe pipe, bool enable);
1135 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1136                                            enum transcoder pch_transcoder,
1137                                            bool enable);
1138 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1139                                          enum pipe pipe);
1140 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1141                                          enum transcoder pch_transcoder);
1142 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1143 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1144
1145 /* i915_irq.c */
1146 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1147 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1148 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1149 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1150 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1151 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1152 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1153 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1154 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1155 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1156 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1157 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1158 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1159 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1160 {
1161         /*
1162          * We only use drm_irq_uninstall() at unload and VT switch, so
1163          * this is the only thing we need to check.
1164          */
1165         return dev_priv->pm.irqs_enabled;
1166 }
1167
1168 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1169 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1170                                      unsigned int pipe_mask);
1171 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1172                                      unsigned int pipe_mask);
1173 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1174 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1175 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1176
1177 /* intel_crt.c */
1178 void intel_crt_init(struct drm_i915_private *dev_priv);
1179 void intel_crt_reset(struct drm_encoder *encoder);
1180
1181 /* intel_ddi.c */
1182 void intel_ddi_clk_select(struct intel_encoder *encoder,
1183                           struct intel_shared_dpll *pll);
1184 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1185                                 struct intel_crtc_state *old_crtc_state,
1186                                 struct drm_connector_state *old_conn_state);
1187 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1188 void hsw_fdi_link_train(struct drm_crtc *crtc);
1189 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1190 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1191 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1192 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1193 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1194                                        enum transcoder cpu_transcoder);
1195 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1196 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1197 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1198                           struct intel_crtc_state *crtc_state);
1199 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1200 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1201 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1202 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1203                                  struct intel_crtc *intel_crtc);
1204 void intel_ddi_get_config(struct intel_encoder *encoder,
1205                           struct intel_crtc_state *pipe_config);
1206 struct intel_encoder *
1207 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1208
1209 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1210 void intel_ddi_clock_get(struct intel_encoder *encoder,
1211                          struct intel_crtc_state *pipe_config);
1212 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1213 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1214 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
1215                                                   int clock);
1216 unsigned int intel_fb_align_height(struct drm_device *dev,
1217                                    unsigned int height,
1218                                    uint32_t pixel_format,
1219                                    uint64_t fb_format_modifier);
1220 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1221                               uint64_t fb_modifier, uint32_t pixel_format);
1222
1223 /* intel_audio.c */
1224 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1225 void intel_audio_codec_enable(struct intel_encoder *encoder,
1226                               const struct intel_crtc_state *crtc_state,
1227                               const struct drm_connector_state *conn_state);
1228 void intel_audio_codec_disable(struct intel_encoder *encoder);
1229 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1230 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1231 void intel_audio_init(struct drm_i915_private *dev_priv);
1232 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1233
1234 /* intel_display.c */
1235 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1236 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1237 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1238 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1239                       const char *name, u32 reg, int ref_freq);
1240 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1241 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1242 extern const struct drm_plane_funcs intel_plane_funcs;
1243 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1244 unsigned int intel_fb_xy_to_linear(int x, int y,
1245                                    const struct intel_plane_state *state,
1246                                    int plane);
1247 void intel_add_fb_offsets(int *x, int *y,
1248                           const struct intel_plane_state *state, int plane);
1249 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1250 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1251 void intel_mark_busy(struct drm_i915_private *dev_priv);
1252 void intel_mark_idle(struct drm_i915_private *dev_priv);
1253 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1254 int intel_display_suspend(struct drm_device *dev);
1255 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1256 void intel_encoder_destroy(struct drm_encoder *encoder);
1257 int intel_connector_init(struct intel_connector *);
1258 struct intel_connector *intel_connector_alloc(void);
1259 bool intel_connector_get_hw_state(struct intel_connector *connector);
1260 void intel_connector_attach_encoder(struct intel_connector *connector,
1261                                     struct intel_encoder *encoder);
1262 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1263                                              struct drm_crtc *crtc);
1264 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1265 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1266                                 struct drm_file *file_priv);
1267 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1268                                              enum pipe pipe);
1269 static inline bool
1270 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1271                     enum intel_output_type type)
1272 {
1273         return crtc_state->output_types & (1 << type);
1274 }
1275 static inline bool
1276 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1277 {
1278         return crtc_state->output_types &
1279                 ((1 << INTEL_OUTPUT_DP) |
1280                  (1 << INTEL_OUTPUT_DP_MST) |
1281                  (1 << INTEL_OUTPUT_EDP));
1282 }
1283 static inline void
1284 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1285 {
1286         drm_wait_one_vblank(&dev_priv->drm, pipe);
1287 }
1288 static inline void
1289 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1290 {
1291         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1292
1293         if (crtc->active)
1294                 intel_wait_for_vblank(dev_priv, pipe);
1295 }
1296
1297 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1298
1299 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1300 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1301                          struct intel_digital_port *dport,
1302                          unsigned int expected_mask);
1303 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1304                                 struct drm_display_mode *mode,
1305                                 struct intel_load_detect_pipe *old,
1306                                 struct drm_modeset_acquire_ctx *ctx);
1307 void intel_release_load_detect_pipe(struct drm_connector *connector,
1308                                     struct intel_load_detect_pipe *old,
1309                                     struct drm_modeset_acquire_ctx *ctx);
1310 struct i915_vma *
1311 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1312 void intel_unpin_fb_vma(struct i915_vma *vma);
1313 struct drm_framebuffer *
1314 __intel_framebuffer_create(struct drm_device *dev,
1315                            struct drm_mode_fb_cmd2 *mode_cmd,
1316                            struct drm_i915_gem_object *obj);
1317 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1318 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1319 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1320 int intel_prepare_plane_fb(struct drm_plane *plane,
1321                            struct drm_plane_state *new_state);
1322 void intel_cleanup_plane_fb(struct drm_plane *plane,
1323                             struct drm_plane_state *old_state);
1324 int intel_plane_atomic_get_property(struct drm_plane *plane,
1325                                     const struct drm_plane_state *state,
1326                                     struct drm_property *property,
1327                                     uint64_t *val);
1328 int intel_plane_atomic_set_property(struct drm_plane *plane,
1329                                     struct drm_plane_state *state,
1330                                     struct drm_property *property,
1331                                     uint64_t val);
1332 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1333                                     struct drm_plane_state *plane_state);
1334
1335 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1336                                uint64_t fb_modifier, unsigned int cpp);
1337
1338 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1339                                     enum pipe pipe);
1340
1341 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1342                      const struct dpll *dpll);
1343 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1344 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1345
1346 /* modesetting asserts */
1347 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1348                            enum pipe pipe);
1349 void assert_pll(struct drm_i915_private *dev_priv,
1350                 enum pipe pipe, bool state);
1351 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1352 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1353 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1354 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1355 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1356 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1357                        enum pipe pipe, bool state);
1358 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1359 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1360 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1361 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1362 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1363 u32 intel_compute_tile_offset(int *x, int *y,
1364                               const struct intel_plane_state *state, int plane);
1365 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1366 void intel_finish_reset(struct drm_i915_private *dev_priv);
1367 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1368 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1369 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1370 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1371 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1372 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1373 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1374 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1375 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1376 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1377 unsigned int skl_cdclk_get_vco(unsigned int freq);
1378 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1379 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1380 void intel_dp_get_m_n(struct intel_crtc *crtc,
1381                       struct intel_crtc_state *pipe_config);
1382 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1383 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1384 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1385                         struct dpll *best_clock);
1386 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1387
1388 bool intel_crtc_active(struct intel_crtc *crtc);
1389 void hsw_enable_ips(struct intel_crtc *crtc);
1390 void hsw_disable_ips(struct intel_crtc *crtc);
1391 enum intel_display_power_domain
1392 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1393 enum intel_display_power_domain
1394 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1395 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1396                                  struct intel_crtc_state *pipe_config);
1397
1398 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1399 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1400
1401 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1402 {
1403         return i915_ggtt_offset(state->vma);
1404 }
1405
1406 u32 skl_plane_ctl_format(uint32_t pixel_format);
1407 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1408 u32 skl_plane_ctl_rotation(unsigned int rotation);
1409 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1410                      unsigned int rotation);
1411 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1412
1413 /* intel_csr.c */
1414 void intel_csr_ucode_init(struct drm_i915_private *);
1415 void intel_csr_load_program(struct drm_i915_private *);
1416 void intel_csr_ucode_fini(struct drm_i915_private *);
1417 void intel_csr_ucode_suspend(struct drm_i915_private *);
1418 void intel_csr_ucode_resume(struct drm_i915_private *);
1419
1420 /* intel_dp.c */
1421 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1422                    enum port port);
1423 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1424                              struct intel_connector *intel_connector);
1425 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1426                               int link_rate, uint8_t lane_count,
1427                               bool link_mst);
1428 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1429                                             int link_rate, uint8_t lane_count);
1430 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1431 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1432 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1433 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1434 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1435 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1436 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1437 bool intel_dp_compute_config(struct intel_encoder *encoder,
1438                              struct intel_crtc_state *pipe_config,
1439                              struct drm_connector_state *conn_state);
1440 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1441 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1442                                   bool long_hpd);
1443 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1444 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1445 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1446 void intel_edp_panel_on(struct intel_dp *intel_dp);
1447 void intel_edp_panel_off(struct intel_dp *intel_dp);
1448 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1449 void intel_dp_mst_suspend(struct drm_device *dev);
1450 void intel_dp_mst_resume(struct drm_device *dev);
1451 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1452 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1453 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1454 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1455 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1456 void intel_plane_destroy(struct drm_plane *plane);
1457 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1458                            struct intel_crtc_state *crtc_state);
1459 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1460                            struct intel_crtc_state *crtc_state);
1461 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1462                                unsigned int frontbuffer_bits);
1463 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1464                           unsigned int frontbuffer_bits);
1465
1466 void
1467 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1468                                        uint8_t dp_train_pat);
1469 void
1470 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1471 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1472 uint8_t
1473 intel_dp_voltage_max(struct intel_dp *intel_dp);
1474 uint8_t
1475 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1476 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1477                            uint8_t *link_bw, uint8_t *rate_select);
1478 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1479 bool
1480 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1481
1482 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1483 {
1484         return ~((1 << lane_count) - 1) & 0xf;
1485 }
1486
1487 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1488 bool __intel_dp_read_desc(struct intel_dp *intel_dp,
1489                           struct intel_dp_desc *desc);
1490 bool intel_dp_read_desc(struct intel_dp *intel_dp);
1491 int intel_dp_link_required(int pixel_clock, int bpp);
1492 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1493 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1494                                   struct intel_digital_port *port);
1495
1496 /* intel_dp_aux_backlight.c */
1497 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1498
1499 /* intel_dp_mst.c */
1500 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1501 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1502 /* intel_dsi.c */
1503 void intel_dsi_init(struct drm_i915_private *dev_priv);
1504
1505 /* intel_dsi_dcs_backlight.c */
1506 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1507
1508 /* intel_dvo.c */
1509 void intel_dvo_init(struct drm_i915_private *dev_priv);
1510 /* intel_hotplug.c */
1511 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1512
1513
1514 /* legacy fbdev emulation in intel_fbdev.c */
1515 #ifdef CONFIG_DRM_FBDEV_EMULATION
1516 extern int intel_fbdev_init(struct drm_device *dev);
1517 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1518 extern void intel_fbdev_fini(struct drm_device *dev);
1519 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1520 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1521 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1522 #else
1523 static inline int intel_fbdev_init(struct drm_device *dev)
1524 {
1525         return 0;
1526 }
1527
1528 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1529 {
1530 }
1531
1532 static inline void intel_fbdev_fini(struct drm_device *dev)
1533 {
1534 }
1535
1536 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1537 {
1538 }
1539
1540 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1541 {
1542 }
1543
1544 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1545 {
1546 }
1547 #endif
1548
1549 /* intel_fbc.c */
1550 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1551                            struct drm_atomic_state *state);
1552 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1553 void intel_fbc_pre_update(struct intel_crtc *crtc,
1554                           struct intel_crtc_state *crtc_state,
1555                           struct intel_plane_state *plane_state);
1556 void intel_fbc_post_update(struct intel_crtc *crtc);
1557 void intel_fbc_init(struct drm_i915_private *dev_priv);
1558 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1559 void intel_fbc_enable(struct intel_crtc *crtc,
1560                       struct intel_crtc_state *crtc_state,
1561                       struct intel_plane_state *plane_state);
1562 void intel_fbc_disable(struct intel_crtc *crtc);
1563 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1564 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1565                           unsigned int frontbuffer_bits,
1566                           enum fb_op_origin origin);
1567 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1568                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1569 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1570 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1571
1572 /* intel_hdmi.c */
1573 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1574                      enum port port);
1575 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1576                                struct intel_connector *intel_connector);
1577 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1578 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1579                                struct intel_crtc_state *pipe_config,
1580                                struct drm_connector_state *conn_state);
1581 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1582
1583
1584 /* intel_lvds.c */
1585 void intel_lvds_init(struct drm_i915_private *dev_priv);
1586 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1587 bool intel_is_dual_link_lvds(struct drm_device *dev);
1588
1589
1590 /* intel_modes.c */
1591 int intel_connector_update_modes(struct drm_connector *connector,
1592                                  struct edid *edid);
1593 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1594 void intel_attach_force_audio_property(struct drm_connector *connector);
1595 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1596 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1597
1598
1599 /* intel_overlay.c */
1600 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1601 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1602 int intel_overlay_switch_off(struct intel_overlay *overlay);
1603 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1604                                   struct drm_file *file_priv);
1605 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1606                               struct drm_file *file_priv);
1607 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1608
1609
1610 /* intel_panel.c */
1611 int intel_panel_init(struct intel_panel *panel,
1612                      struct drm_display_mode *fixed_mode,
1613                      struct drm_display_mode *downclock_mode);
1614 void intel_panel_fini(struct intel_panel *panel);
1615 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1616                             struct drm_display_mode *adjusted_mode);
1617 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1618                              struct intel_crtc_state *pipe_config,
1619                              int fitting_mode);
1620 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1621                               struct intel_crtc_state *pipe_config,
1622                               int fitting_mode);
1623 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1624                                     u32 level, u32 max);
1625 int intel_panel_setup_backlight(struct drm_connector *connector,
1626                                 enum pipe pipe);
1627 void intel_panel_enable_backlight(struct intel_connector *connector);
1628 void intel_panel_disable_backlight(struct intel_connector *connector);
1629 void intel_panel_destroy_backlight(struct drm_connector *connector);
1630 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1631 extern struct drm_display_mode *intel_find_panel_downclock(
1632                                 struct drm_i915_private *dev_priv,
1633                                 struct drm_display_mode *fixed_mode,
1634                                 struct drm_connector *connector);
1635
1636 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1637 int intel_backlight_device_register(struct intel_connector *connector);
1638 void intel_backlight_device_unregister(struct intel_connector *connector);
1639 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1640 static int intel_backlight_device_register(struct intel_connector *connector)
1641 {
1642         return 0;
1643 }
1644 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1645 {
1646 }
1647 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1648
1649
1650 /* intel_psr.c */
1651 void intel_psr_enable(struct intel_dp *intel_dp);
1652 void intel_psr_disable(struct intel_dp *intel_dp);
1653 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1654                           unsigned frontbuffer_bits);
1655 void intel_psr_flush(struct drm_i915_private *dev_priv,
1656                      unsigned frontbuffer_bits,
1657                      enum fb_op_origin origin);
1658 void intel_psr_init(struct drm_i915_private *dev_priv);
1659 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1660                                    unsigned frontbuffer_bits);
1661
1662 /* intel_runtime_pm.c */
1663 int intel_power_domains_init(struct drm_i915_private *);
1664 void intel_power_domains_fini(struct drm_i915_private *);
1665 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1666 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1667 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1668 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1669 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1670 const char *
1671 intel_display_power_domain_str(enum intel_display_power_domain domain);
1672
1673 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1674                                     enum intel_display_power_domain domain);
1675 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1676                                       enum intel_display_power_domain domain);
1677 void intel_display_power_get(struct drm_i915_private *dev_priv,
1678                              enum intel_display_power_domain domain);
1679 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1680                                         enum intel_display_power_domain domain);
1681 void intel_display_power_put(struct drm_i915_private *dev_priv,
1682                              enum intel_display_power_domain domain);
1683
1684 static inline void
1685 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1686 {
1687         WARN_ONCE(dev_priv->pm.suspended,
1688                   "Device suspended during HW access\n");
1689 }
1690
1691 static inline void
1692 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1693 {
1694         assert_rpm_device_not_suspended(dev_priv);
1695         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1696          * too much noise. */
1697         if (!atomic_read(&dev_priv->pm.wakeref_count))
1698                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1699 }
1700
1701 /**
1702  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1703  * @dev_priv: i915 device instance
1704  *
1705  * This function disable asserts that check if we hold an RPM wakelock
1706  * reference, while keeping the device-not-suspended checks still enabled.
1707  * It's meant to be used only in special circumstances where our rule about
1708  * the wakelock refcount wrt. the device power state doesn't hold. According
1709  * to this rule at any point where we access the HW or want to keep the HW in
1710  * an active state we must hold an RPM wakelock reference acquired via one of
1711  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1712  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1713  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1714  * users should avoid using this function.
1715  *
1716  * Any calls to this function must have a symmetric call to
1717  * enable_rpm_wakeref_asserts().
1718  */
1719 static inline void
1720 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1721 {
1722         atomic_inc(&dev_priv->pm.wakeref_count);
1723 }
1724
1725 /**
1726  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1727  * @dev_priv: i915 device instance
1728  *
1729  * This function re-enables the RPM assert checks after disabling them with
1730  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1731  * circumstances otherwise its use should be avoided.
1732  *
1733  * Any calls to this function must have a symmetric call to
1734  * disable_rpm_wakeref_asserts().
1735  */
1736 static inline void
1737 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1738 {
1739         atomic_dec(&dev_priv->pm.wakeref_count);
1740 }
1741
1742 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1743 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1744 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1745 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1746
1747 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1748
1749 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1750                              bool override, unsigned int mask);
1751 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1752                           enum dpio_channel ch, bool override);
1753
1754
1755 /* intel_pm.c */
1756 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1757 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1758 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1759 void intel_update_watermarks(struct intel_crtc *crtc);
1760 void intel_init_pm(struct drm_i915_private *dev_priv);
1761 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1762 void intel_pm_setup(struct drm_i915_private *dev_priv);
1763 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1764 void intel_gpu_ips_teardown(void);
1765 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1766 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1767 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1768 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1769 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1770 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1771 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1772 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1773 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1774 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1775 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1776                     struct intel_rps_client *rps,
1777                     unsigned long submitted);
1778 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1779 void vlv_wm_get_hw_state(struct drm_device *dev);
1780 void ilk_wm_get_hw_state(struct drm_device *dev);
1781 void skl_wm_get_hw_state(struct drm_device *dev);
1782 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1783                           struct skl_ddb_allocation *ddb /* out */);
1784 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1785                               struct skl_pipe_wm *out);
1786 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1787 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1788 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1789 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1790                          const struct skl_wm_level *l2);
1791 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1792                                  const struct skl_ddb_entry *ddb,
1793                                  int ignore);
1794 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1795 bool ilk_disable_lp_wm(struct drm_device *dev);
1796 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1797 static inline int intel_enable_rc6(void)
1798 {
1799         return i915.enable_rc6;
1800 }
1801
1802 /* intel_sdvo.c */
1803 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1804                      i915_reg_t reg, enum port port);
1805
1806
1807 /* intel_sprite.c */
1808 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1809                              int usecs);
1810 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1811                                               enum pipe pipe, int plane);
1812 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1813                               struct drm_file *file_priv);
1814 void intel_pipe_update_start(struct intel_crtc *crtc);
1815 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1816
1817 /* intel_tv.c */
1818 void intel_tv_init(struct drm_i915_private *dev_priv);
1819
1820 /* intel_atomic.c */
1821 int intel_connector_atomic_get_property(struct drm_connector *connector,
1822                                         const struct drm_connector_state *state,
1823                                         struct drm_property *property,
1824                                         uint64_t *val);
1825 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1826 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1827                                struct drm_crtc_state *state);
1828 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1829 void intel_atomic_state_clear(struct drm_atomic_state *);
1830
1831 static inline struct intel_crtc_state *
1832 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1833                             struct intel_crtc *crtc)
1834 {
1835         struct drm_crtc_state *crtc_state;
1836         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1837         if (IS_ERR(crtc_state))
1838                 return ERR_CAST(crtc_state);
1839
1840         return to_intel_crtc_state(crtc_state);
1841 }
1842
1843 static inline struct intel_crtc_state *
1844 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1845                                      struct intel_crtc *crtc)
1846 {
1847         struct drm_crtc_state *crtc_state;
1848
1849         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1850
1851         if (crtc_state)
1852                 return to_intel_crtc_state(crtc_state);
1853         else
1854                 return NULL;
1855 }
1856
1857 static inline struct intel_plane_state *
1858 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1859                                       struct intel_plane *plane)
1860 {
1861         struct drm_plane_state *plane_state;
1862
1863         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1864
1865         return to_intel_plane_state(plane_state);
1866 }
1867
1868 int intel_atomic_setup_scalers(struct drm_device *dev,
1869         struct intel_crtc *intel_crtc,
1870         struct intel_crtc_state *crtc_state);
1871
1872 /* intel_atomic_plane.c */
1873 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1874 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1875 void intel_plane_destroy_state(struct drm_plane *plane,
1876                                struct drm_plane_state *state);
1877 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1878 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1879                                         struct intel_plane_state *intel_state);
1880
1881 /* intel_color.c */
1882 void intel_color_init(struct drm_crtc *crtc);
1883 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1884 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1885 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1886
1887 /* intel_lspcon.c */
1888 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1889 void lspcon_resume(struct intel_lspcon *lspcon);
1890 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1891
1892 /* intel_pipe_crc.c */
1893 int intel_pipe_crc_create(struct drm_minor *minor);
1894 #ifdef CONFIG_DEBUG_FS
1895 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
1896                               size_t *values_cnt);
1897 #else
1898 #define intel_crtc_set_crc_source NULL
1899 #endif
1900 extern const struct file_operations i915_display_crc_ctl_fops;
1901 #endif /* __INTEL_DRV_H__ */