2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
38 #include <drm/drm_dp_helper.h>
40 #define DP_RECEIVER_CAP_SIZE 0xf
41 #define DP_LINK_STATUS_SIZE 6
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 #define DP_LINK_CONFIGURATION_SIZE 9
47 struct intel_encoder base
;
50 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
52 enum hdmi_force_audio force_audio
;
57 uint8_t dpcd
[DP_RECEIVER_CAP_SIZE
];
58 struct i2c_adapter adapter
;
59 struct i2c_algo_dp_aux_data algo
;
62 int panel_power_up_delay
;
63 int panel_power_down_delay
;
64 int panel_power_cycle_delay
;
65 int backlight_on_delay
;
66 int backlight_off_delay
;
67 struct drm_display_mode
*panel_fixed_mode
; /* for eDP */
68 struct delayed_work panel_vdd_work
;
70 struct edid
*edid
; /* cached EDID for eDP */
75 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
76 * @intel_dp: DP struct
78 * If a CPU or PCH DP output is attached to an eDP panel, this function
79 * will return true, and false otherwise.
81 static bool is_edp(struct intel_dp
*intel_dp
)
83 return intel_dp
->base
.type
== INTEL_OUTPUT_EDP
;
87 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
88 * @intel_dp: DP struct
90 * Returns true if the given DP struct corresponds to a PCH DP port attached
91 * to an eDP panel, false otherwise. Helpful for determining whether we
92 * may need FDI resources for a given DP output or not.
94 static bool is_pch_edp(struct intel_dp
*intel_dp
)
96 return intel_dp
->is_pch_edp
;
100 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
101 * @intel_dp: DP struct
103 * Returns true if the given DP struct corresponds to a CPU eDP port.
105 static bool is_cpu_edp(struct intel_dp
*intel_dp
)
107 return is_edp(intel_dp
) && !is_pch_edp(intel_dp
);
110 static struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
112 return container_of(encoder
, struct intel_dp
, base
.base
);
115 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
117 return container_of(intel_attached_encoder(connector
),
118 struct intel_dp
, base
);
122 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
123 * @encoder: DRM encoder
125 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
126 * by intel_display.c.
128 bool intel_encoder_is_pch_edp(struct drm_encoder
*encoder
)
130 struct intel_dp
*intel_dp
;
135 intel_dp
= enc_to_intel_dp(encoder
);
137 return is_pch_edp(intel_dp
);
140 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
141 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
142 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
145 intel_edp_link_config(struct intel_encoder
*intel_encoder
,
146 int *lane_num
, int *link_bw
)
148 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
150 *lane_num
= intel_dp
->lane_count
;
151 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
153 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
158 intel_edp_target_clock(struct intel_encoder
*intel_encoder
,
159 struct drm_display_mode
*mode
)
161 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
163 if (intel_dp
->panel_fixed_mode
)
164 return intel_dp
->panel_fixed_mode
->clock
;
170 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
172 int max_lane_count
= intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & 0x1f;
173 switch (max_lane_count
) {
174 case 1: case 2: case 4:
179 return max_lane_count
;
183 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
185 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
187 switch (max_link_bw
) {
188 case DP_LINK_BW_1_62
:
192 max_link_bw
= DP_LINK_BW_1_62
;
199 intel_dp_link_clock(uint8_t link_bw
)
201 if (link_bw
== DP_LINK_BW_2_7
)
208 * The units on the numbers in the next two are... bizarre. Examples will
209 * make it clearer; this one parallels an example in the eDP spec.
211 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
213 * 270000 * 1 * 8 / 10 == 216000
215 * The actual data capacity of that configuration is 2.16Gbit/s, so the
216 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
217 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
218 * 119000. At 18bpp that's 2142000 kilobits per second.
220 * Thus the strange-looking division by 10 in intel_dp_link_required, to
221 * get the result in decakilobits instead of kilobits.
225 intel_dp_link_required(int pixel_clock
, int bpp
)
227 return (pixel_clock
* bpp
+ 9) / 10;
231 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
233 return (max_link_clock
* max_lanes
* 8) / 10;
237 intel_dp_adjust_dithering(struct intel_dp
*intel_dp
,
238 struct drm_display_mode
*mode
,
241 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
242 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
243 int max_rate
, mode_rate
;
245 mode_rate
= intel_dp_link_required(mode
->clock
, 24);
246 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
248 if (mode_rate
> max_rate
) {
249 mode_rate
= intel_dp_link_required(mode
->clock
, 18);
250 if (mode_rate
> max_rate
)
255 |= INTEL_MODE_DP_FORCE_6BPC
;
264 intel_dp_mode_valid(struct drm_connector
*connector
,
265 struct drm_display_mode
*mode
)
267 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
269 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
270 if (mode
->hdisplay
> intel_dp
->panel_fixed_mode
->hdisplay
)
273 if (mode
->vdisplay
> intel_dp
->panel_fixed_mode
->vdisplay
)
277 if (!intel_dp_adjust_dithering(intel_dp
, mode
, false))
278 return MODE_CLOCK_HIGH
;
280 if (mode
->clock
< 10000)
281 return MODE_CLOCK_LOW
;
283 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
284 return MODE_H_ILLEGAL
;
290 pack_aux(uint8_t *src
, int src_bytes
)
297 for (i
= 0; i
< src_bytes
; i
++)
298 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
303 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
308 for (i
= 0; i
< dst_bytes
; i
++)
309 dst
[i
] = src
>> ((3-i
) * 8);
312 /* hrawclock is 1/4 the FSB frequency */
314 intel_hrawclk(struct drm_device
*dev
)
316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
319 clkcfg
= I915_READ(CLKCFG
);
320 switch (clkcfg
& CLKCFG_FSB_MASK
) {
329 case CLKCFG_FSB_1067
:
331 case CLKCFG_FSB_1333
:
333 /* these two are just a guess; one of them might be right */
334 case CLKCFG_FSB_1600
:
335 case CLKCFG_FSB_1600_ALT
:
342 static bool ironlake_edp_have_panel_power(struct intel_dp
*intel_dp
)
344 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
347 return (I915_READ(PCH_PP_STATUS
) & PP_ON
) != 0;
350 static bool ironlake_edp_have_panel_vdd(struct intel_dp
*intel_dp
)
352 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
355 return (I915_READ(PCH_PP_CONTROL
) & EDP_FORCE_VDD
) != 0;
359 intel_dp_check_edp(struct intel_dp
*intel_dp
)
361 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
364 if (!is_edp(intel_dp
))
366 if (!ironlake_edp_have_panel_power(intel_dp
) && !ironlake_edp_have_panel_vdd(intel_dp
)) {
367 WARN(1, "eDP powered off while attempting aux channel communication.\n");
368 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
369 I915_READ(PCH_PP_STATUS
),
370 I915_READ(PCH_PP_CONTROL
));
375 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
376 uint8_t *send
, int send_bytes
,
377 uint8_t *recv
, int recv_size
)
379 uint32_t output_reg
= intel_dp
->output_reg
;
380 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
382 uint32_t ch_ctl
= output_reg
+ 0x10;
383 uint32_t ch_data
= ch_ctl
+ 4;
387 uint32_t aux_clock_divider
;
390 intel_dp_check_edp(intel_dp
);
391 /* The clock divider is based off the hrawclk,
392 * and would like to run at 2MHz. So, take the
393 * hrawclk value and divide by 2 and use that
395 * Note that PCH attached eDP panels should use a 125MHz input
398 if (is_cpu_edp(intel_dp
)) {
399 if (IS_GEN6(dev
) || IS_GEN7(dev
))
400 aux_clock_divider
= 200; /* SNB & IVB eDP input clock at 400Mhz */
402 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
403 } else if (HAS_PCH_SPLIT(dev
))
404 aux_clock_divider
= 63; /* IRL input clock fixed at 125Mhz */
406 aux_clock_divider
= intel_hrawclk(dev
) / 2;
413 /* Try to wait for any previous AUX channel activity */
414 for (try = 0; try < 3; try++) {
415 status
= I915_READ(ch_ctl
);
416 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
422 WARN(1, "dp_aux_ch not started status 0x%08x\n",
427 /* Must try at least 3 times according to DP spec */
428 for (try = 0; try < 5; try++) {
429 /* Load the send data into the aux channel data registers */
430 for (i
= 0; i
< send_bytes
; i
+= 4)
431 I915_WRITE(ch_data
+ i
,
432 pack_aux(send
+ i
, send_bytes
- i
));
434 /* Send the command and wait for it to complete */
436 DP_AUX_CH_CTL_SEND_BUSY
|
437 DP_AUX_CH_CTL_TIME_OUT_400us
|
438 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
439 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
440 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
442 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
443 DP_AUX_CH_CTL_RECEIVE_ERROR
);
445 status
= I915_READ(ch_ctl
);
446 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
451 /* Clear done status and any errors */
455 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
456 DP_AUX_CH_CTL_RECEIVE_ERROR
);
458 if (status
& (DP_AUX_CH_CTL_TIME_OUT_ERROR
|
459 DP_AUX_CH_CTL_RECEIVE_ERROR
))
461 if (status
& DP_AUX_CH_CTL_DONE
)
465 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
466 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
470 /* Check for timeout or receive error.
471 * Timeouts occur when the sink is not connected
473 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
474 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
478 /* Timeouts occur when the device isn't connected, so they're
479 * "normal" -- don't fill the kernel log with these */
480 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
481 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
485 /* Unload any bytes sent back from the other side */
486 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
487 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
488 if (recv_bytes
> recv_size
)
489 recv_bytes
= recv_size
;
491 for (i
= 0; i
< recv_bytes
; i
+= 4)
492 unpack_aux(I915_READ(ch_data
+ i
),
493 recv
+ i
, recv_bytes
- i
);
498 /* Write data to the aux channel in native mode */
500 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
501 uint16_t address
, uint8_t *send
, int send_bytes
)
508 intel_dp_check_edp(intel_dp
);
511 msg
[0] = AUX_NATIVE_WRITE
<< 4;
512 msg
[1] = address
>> 8;
513 msg
[2] = address
& 0xff;
514 msg
[3] = send_bytes
- 1;
515 memcpy(&msg
[4], send
, send_bytes
);
516 msg_bytes
= send_bytes
+ 4;
518 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
521 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
523 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
531 /* Write a single byte to the aux channel in native mode */
533 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
534 uint16_t address
, uint8_t byte
)
536 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
539 /* read bytes from a native aux channel */
541 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
542 uint16_t address
, uint8_t *recv
, int recv_bytes
)
551 intel_dp_check_edp(intel_dp
);
552 msg
[0] = AUX_NATIVE_READ
<< 4;
553 msg
[1] = address
>> 8;
554 msg
[2] = address
& 0xff;
555 msg
[3] = recv_bytes
- 1;
558 reply_bytes
= recv_bytes
+ 1;
561 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
568 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
569 memcpy(recv
, reply
+ 1, ret
- 1);
572 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
580 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
581 uint8_t write_byte
, uint8_t *read_byte
)
583 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
584 struct intel_dp
*intel_dp
= container_of(adapter
,
587 uint16_t address
= algo_data
->address
;
595 intel_dp_check_edp(intel_dp
);
596 /* Set up the command byte */
597 if (mode
& MODE_I2C_READ
)
598 msg
[0] = AUX_I2C_READ
<< 4;
600 msg
[0] = AUX_I2C_WRITE
<< 4;
602 if (!(mode
& MODE_I2C_STOP
))
603 msg
[0] |= AUX_I2C_MOT
<< 4;
605 msg
[1] = address
>> 8;
626 for (retry
= 0; retry
< 5; retry
++) {
627 ret
= intel_dp_aux_ch(intel_dp
,
631 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
635 switch (reply
[0] & AUX_NATIVE_REPLY_MASK
) {
636 case AUX_NATIVE_REPLY_ACK
:
637 /* I2C-over-AUX Reply field is only valid
638 * when paired with AUX ACK.
641 case AUX_NATIVE_REPLY_NACK
:
642 DRM_DEBUG_KMS("aux_ch native nack\n");
644 case AUX_NATIVE_REPLY_DEFER
:
648 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
653 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
654 case AUX_I2C_REPLY_ACK
:
655 if (mode
== MODE_I2C_READ
) {
656 *read_byte
= reply
[1];
658 return reply_bytes
- 1;
659 case AUX_I2C_REPLY_NACK
:
660 DRM_DEBUG_KMS("aux_i2c nack\n");
662 case AUX_I2C_REPLY_DEFER
:
663 DRM_DEBUG_KMS("aux_i2c defer\n");
667 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply
[0]);
672 DRM_ERROR("too many retries, giving up\n");
676 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
);
677 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
680 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
681 struct intel_connector
*intel_connector
, const char *name
)
685 DRM_DEBUG_KMS("i2c_init %s\n", name
);
686 intel_dp
->algo
.running
= false;
687 intel_dp
->algo
.address
= 0;
688 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
690 memset(&intel_dp
->adapter
, '\0', sizeof(intel_dp
->adapter
));
691 intel_dp
->adapter
.owner
= THIS_MODULE
;
692 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
693 strncpy(intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
694 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
695 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
696 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
698 ironlake_edp_panel_vdd_on(intel_dp
);
699 ret
= i2c_dp_aux_add_bus(&intel_dp
->adapter
);
700 ironlake_edp_panel_vdd_off(intel_dp
, false);
705 intel_dp_mode_fixup(struct drm_encoder
*encoder
,
706 const struct drm_display_mode
*mode
,
707 struct drm_display_mode
*adjusted_mode
)
709 struct drm_device
*dev
= encoder
->dev
;
710 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
711 int lane_count
, clock
;
712 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
713 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
715 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
717 if (is_edp(intel_dp
) && intel_dp
->panel_fixed_mode
) {
718 intel_fixed_panel_mode(intel_dp
->panel_fixed_mode
, adjusted_mode
);
719 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
720 mode
, adjusted_mode
);
723 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
726 DRM_DEBUG_KMS("DP link computation with max lane count %i "
727 "max bw %02x pixel clock %iKHz\n",
728 max_lane_count
, bws
[max_clock
], adjusted_mode
->clock
);
730 if (!intel_dp_adjust_dithering(intel_dp
, adjusted_mode
, true))
733 bpp
= adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
? 18 : 24;
734 mode_rate
= intel_dp_link_required(adjusted_mode
->clock
, bpp
);
736 for (clock
= 0; clock
<= max_clock
; clock
++) {
737 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
738 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
740 if (mode_rate
<= link_avail
) {
741 intel_dp
->link_bw
= bws
[clock
];
742 intel_dp
->lane_count
= lane_count
;
743 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
744 DRM_DEBUG_KMS("DP link bw %02x lane "
745 "count %d clock %d bpp %d\n",
746 intel_dp
->link_bw
, intel_dp
->lane_count
,
747 adjusted_mode
->clock
, bpp
);
748 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
749 mode_rate
, link_avail
);
758 struct intel_dp_m_n
{
767 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
769 while (*num
> 0xffffff || *den
> 0xffffff) {
776 intel_dp_compute_m_n(int bpp
,
780 struct intel_dp_m_n
*m_n
)
783 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
784 m_n
->gmch_n
= link_clock
* nlanes
;
785 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
786 m_n
->link_m
= pixel_clock
;
787 m_n
->link_n
= link_clock
;
788 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
792 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
793 struct drm_display_mode
*adjusted_mode
)
795 struct drm_device
*dev
= crtc
->dev
;
796 struct intel_encoder
*encoder
;
797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
798 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
800 struct intel_dp_m_n m_n
;
801 int pipe
= intel_crtc
->pipe
;
804 * Find the lane count in the intel_encoder private
806 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
807 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
809 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
810 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
812 lane_count
= intel_dp
->lane_count
;
818 * Compute the GMCH and Link ratios. The '3' here is
819 * the number of bytes_per_pixel post-LUT, which we always
820 * set up for 8-bits of R/G/B, or 3 bytes total.
822 intel_dp_compute_m_n(intel_crtc
->bpp
, lane_count
,
823 mode
->clock
, adjusted_mode
->clock
, &m_n
);
825 if (HAS_PCH_SPLIT(dev
)) {
826 I915_WRITE(TRANSDATA_M1(pipe
),
827 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
829 I915_WRITE(TRANSDATA_N1(pipe
), m_n
.gmch_n
);
830 I915_WRITE(TRANSDPLINK_M1(pipe
), m_n
.link_m
);
831 I915_WRITE(TRANSDPLINK_N1(pipe
), m_n
.link_n
);
833 I915_WRITE(PIPE_GMCH_DATA_M(pipe
),
834 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
836 I915_WRITE(PIPE_GMCH_DATA_N(pipe
), m_n
.gmch_n
);
837 I915_WRITE(PIPE_DP_LINK_M(pipe
), m_n
.link_m
);
838 I915_WRITE(PIPE_DP_LINK_N(pipe
), m_n
.link_n
);
842 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
);
843 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
);
846 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
847 struct drm_display_mode
*adjusted_mode
)
849 struct drm_device
*dev
= encoder
->dev
;
850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
851 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
852 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
853 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
855 /* Turn on the eDP PLL if needed */
856 if (is_edp(intel_dp
)) {
857 if (!is_pch_edp(intel_dp
))
858 ironlake_edp_pll_on(encoder
);
860 ironlake_edp_pll_off(encoder
);
864 * There are four kinds of DP registers:
871 * IBX PCH and CPU are the same for almost everything,
872 * except that the CPU DP PLL is configured in this
875 * CPT PCH is quite different, having many bits moved
876 * to the TRANS_DP_CTL register instead. That
877 * configuration happens (oddly) in ironlake_pch_enable
880 /* Preserve the BIOS-computed detected bit. This is
881 * supposed to be read-only.
883 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
884 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
886 /* Handle DP bits in common between all three register formats */
888 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
890 switch (intel_dp
->lane_count
) {
892 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
895 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
898 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
901 if (intel_dp
->has_audio
) {
902 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
903 pipe_name(intel_crtc
->pipe
));
904 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
905 intel_write_eld(encoder
, adjusted_mode
);
907 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
908 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
909 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
910 intel_dp
->link_configuration
[8] = DP_SET_ANSI_8B10B
;
912 * Check for DPCD version > 1.1 and enhanced framing support
914 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
915 (intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_ENHANCED_FRAME_CAP
)) {
916 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
919 /* Split out the IBX/CPU vs CPT settings */
921 if (is_cpu_edp(intel_dp
) && IS_GEN7(dev
)) {
922 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
923 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
924 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
925 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
926 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
928 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
929 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
931 intel_dp
->DP
|= intel_crtc
->pipe
<< 29;
933 /* don't miss out required setting for eDP */
934 intel_dp
->DP
|= DP_PLL_ENABLE
;
935 if (adjusted_mode
->clock
< 200000)
936 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
938 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
939 } else if (!HAS_PCH_CPT(dev
) || is_cpu_edp(intel_dp
)) {
940 intel_dp
->DP
|= intel_dp
->color_range
;
942 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
943 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
944 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
945 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
946 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
948 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
949 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
951 if (intel_crtc
->pipe
== 1)
952 intel_dp
->DP
|= DP_PIPEB_SELECT
;
954 if (is_cpu_edp(intel_dp
)) {
955 /* don't miss out required setting for eDP */
956 intel_dp
->DP
|= DP_PLL_ENABLE
;
957 if (adjusted_mode
->clock
< 200000)
958 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
960 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
963 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
967 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
968 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
970 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
971 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
973 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
974 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
976 static void ironlake_wait_panel_status(struct intel_dp
*intel_dp
,
980 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
983 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
985 I915_READ(PCH_PP_STATUS
),
986 I915_READ(PCH_PP_CONTROL
));
988 if (_wait_for((I915_READ(PCH_PP_STATUS
) & mask
) == value
, 5000, 10)) {
989 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
990 I915_READ(PCH_PP_STATUS
),
991 I915_READ(PCH_PP_CONTROL
));
995 static void ironlake_wait_panel_on(struct intel_dp
*intel_dp
)
997 DRM_DEBUG_KMS("Wait for panel power on\n");
998 ironlake_wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1001 static void ironlake_wait_panel_off(struct intel_dp
*intel_dp
)
1003 DRM_DEBUG_KMS("Wait for panel power off time\n");
1004 ironlake_wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1007 static void ironlake_wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1009 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1010 ironlake_wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1014 /* Read the current pp_control value, unlocking the register if it
1018 static u32
ironlake_get_pp_control(struct drm_i915_private
*dev_priv
)
1020 u32 control
= I915_READ(PCH_PP_CONTROL
);
1022 control
&= ~PANEL_UNLOCK_MASK
;
1023 control
|= PANEL_UNLOCK_REGS
;
1027 static void ironlake_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1029 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1033 if (!is_edp(intel_dp
))
1035 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1037 WARN(intel_dp
->want_panel_vdd
,
1038 "eDP VDD already requested on\n");
1040 intel_dp
->want_panel_vdd
= true;
1042 if (ironlake_edp_have_panel_vdd(intel_dp
)) {
1043 DRM_DEBUG_KMS("eDP VDD already on\n");
1047 if (!ironlake_edp_have_panel_power(intel_dp
))
1048 ironlake_wait_panel_power_cycle(intel_dp
);
1050 pp
= ironlake_get_pp_control(dev_priv
);
1051 pp
|= EDP_FORCE_VDD
;
1052 I915_WRITE(PCH_PP_CONTROL
, pp
);
1053 POSTING_READ(PCH_PP_CONTROL
);
1054 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1055 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1058 * If the panel wasn't on, delay before accessing aux channel
1060 if (!ironlake_edp_have_panel_power(intel_dp
)) {
1061 DRM_DEBUG_KMS("eDP was not running\n");
1062 msleep(intel_dp
->panel_power_up_delay
);
1066 static void ironlake_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1068 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1072 if (!intel_dp
->want_panel_vdd
&& ironlake_edp_have_panel_vdd(intel_dp
)) {
1073 pp
= ironlake_get_pp_control(dev_priv
);
1074 pp
&= ~EDP_FORCE_VDD
;
1075 I915_WRITE(PCH_PP_CONTROL
, pp
);
1076 POSTING_READ(PCH_PP_CONTROL
);
1078 /* Make sure sequencer is idle before allowing subsequent activity */
1079 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1080 I915_READ(PCH_PP_STATUS
), I915_READ(PCH_PP_CONTROL
));
1082 msleep(intel_dp
->panel_power_down_delay
);
1086 static void ironlake_panel_vdd_work(struct work_struct
*__work
)
1088 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1089 struct intel_dp
, panel_vdd_work
);
1090 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1092 mutex_lock(&dev
->mode_config
.mutex
);
1093 ironlake_panel_vdd_off_sync(intel_dp
);
1094 mutex_unlock(&dev
->mode_config
.mutex
);
1097 static void ironlake_edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1099 if (!is_edp(intel_dp
))
1102 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp
->want_panel_vdd
);
1103 WARN(!intel_dp
->want_panel_vdd
, "eDP VDD not forced on");
1105 intel_dp
->want_panel_vdd
= false;
1108 ironlake_panel_vdd_off_sync(intel_dp
);
1111 * Queue the timer to fire a long
1112 * time from now (relative to the power down delay)
1113 * to keep the panel power up across a sequence of operations
1115 schedule_delayed_work(&intel_dp
->panel_vdd_work
,
1116 msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5));
1120 static void ironlake_edp_panel_on(struct intel_dp
*intel_dp
)
1122 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1126 if (!is_edp(intel_dp
))
1129 DRM_DEBUG_KMS("Turn eDP power on\n");
1131 if (ironlake_edp_have_panel_power(intel_dp
)) {
1132 DRM_DEBUG_KMS("eDP power already on\n");
1136 ironlake_wait_panel_power_cycle(intel_dp
);
1138 pp
= ironlake_get_pp_control(dev_priv
);
1140 /* ILK workaround: disable reset around power sequence */
1141 pp
&= ~PANEL_POWER_RESET
;
1142 I915_WRITE(PCH_PP_CONTROL
, pp
);
1143 POSTING_READ(PCH_PP_CONTROL
);
1146 pp
|= POWER_TARGET_ON
;
1148 pp
|= PANEL_POWER_RESET
;
1150 I915_WRITE(PCH_PP_CONTROL
, pp
);
1151 POSTING_READ(PCH_PP_CONTROL
);
1153 ironlake_wait_panel_on(intel_dp
);
1156 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1157 I915_WRITE(PCH_PP_CONTROL
, pp
);
1158 POSTING_READ(PCH_PP_CONTROL
);
1162 static void ironlake_edp_panel_off(struct intel_dp
*intel_dp
)
1164 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1168 if (!is_edp(intel_dp
))
1171 DRM_DEBUG_KMS("Turn eDP power off\n");
1173 WARN(!intel_dp
->want_panel_vdd
, "Need VDD to turn off panel\n");
1175 pp
= ironlake_get_pp_control(dev_priv
);
1176 /* We need to switch off panel power _and_ force vdd, for otherwise some
1177 * panels get very unhappy and cease to work. */
1178 pp
&= ~(POWER_TARGET_ON
| EDP_FORCE_VDD
| PANEL_POWER_RESET
| EDP_BLC_ENABLE
);
1179 I915_WRITE(PCH_PP_CONTROL
, pp
);
1180 POSTING_READ(PCH_PP_CONTROL
);
1182 intel_dp
->want_panel_vdd
= false;
1184 ironlake_wait_panel_off(intel_dp
);
1187 static void ironlake_edp_backlight_on(struct intel_dp
*intel_dp
)
1189 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1193 if (!is_edp(intel_dp
))
1196 DRM_DEBUG_KMS("\n");
1198 * If we enable the backlight right away following a panel power
1199 * on, we may see slight flicker as the panel syncs with the eDP
1200 * link. So delay a bit to make sure the image is solid before
1201 * allowing it to appear.
1203 msleep(intel_dp
->backlight_on_delay
);
1204 pp
= ironlake_get_pp_control(dev_priv
);
1205 pp
|= EDP_BLC_ENABLE
;
1206 I915_WRITE(PCH_PP_CONTROL
, pp
);
1207 POSTING_READ(PCH_PP_CONTROL
);
1210 static void ironlake_edp_backlight_off(struct intel_dp
*intel_dp
)
1212 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1216 if (!is_edp(intel_dp
))
1219 DRM_DEBUG_KMS("\n");
1220 pp
= ironlake_get_pp_control(dev_priv
);
1221 pp
&= ~EDP_BLC_ENABLE
;
1222 I915_WRITE(PCH_PP_CONTROL
, pp
);
1223 POSTING_READ(PCH_PP_CONTROL
);
1224 msleep(intel_dp
->backlight_off_delay
);
1227 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
)
1229 struct drm_device
*dev
= encoder
->dev
;
1230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1233 DRM_DEBUG_KMS("\n");
1234 dpa_ctl
= I915_READ(DP_A
);
1235 dpa_ctl
|= DP_PLL_ENABLE
;
1236 I915_WRITE(DP_A
, dpa_ctl
);
1241 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
)
1243 struct drm_device
*dev
= encoder
->dev
;
1244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1247 dpa_ctl
= I915_READ(DP_A
);
1248 dpa_ctl
&= ~DP_PLL_ENABLE
;
1249 I915_WRITE(DP_A
, dpa_ctl
);
1254 /* If the sink supports it, try to set the power state appropriately */
1255 static void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
1259 /* Should have a valid DPCD by this point */
1260 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
1263 if (mode
!= DRM_MODE_DPMS_ON
) {
1264 ret
= intel_dp_aux_native_write_1(intel_dp
, DP_SET_POWER
,
1267 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1270 * When turning on, we need to retry for 1ms to give the sink
1273 for (i
= 0; i
< 3; i
++) {
1274 ret
= intel_dp_aux_native_write_1(intel_dp
,
1284 static void intel_dp_prepare(struct drm_encoder
*encoder
)
1286 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1289 /* Make sure the panel is off before trying to change the mode. But also
1290 * ensure that we have vdd while we switch off the panel. */
1291 ironlake_edp_panel_vdd_on(intel_dp
);
1292 ironlake_edp_backlight_off(intel_dp
);
1293 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1294 ironlake_edp_panel_off(intel_dp
);
1295 intel_dp_link_down(intel_dp
);
1298 static void intel_dp_commit(struct drm_encoder
*encoder
)
1300 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1301 struct drm_device
*dev
= encoder
->dev
;
1302 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1304 ironlake_edp_panel_vdd_on(intel_dp
);
1305 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1306 intel_dp_start_link_train(intel_dp
);
1307 ironlake_edp_panel_on(intel_dp
);
1308 ironlake_edp_panel_vdd_off(intel_dp
, true);
1309 intel_dp_complete_link_train(intel_dp
);
1310 ironlake_edp_backlight_on(intel_dp
);
1312 intel_dp
->dpms_mode
= DRM_MODE_DPMS_ON
;
1314 if (HAS_PCH_CPT(dev
))
1315 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
1319 intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
1321 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1322 struct drm_device
*dev
= encoder
->dev
;
1323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1324 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
1326 if (mode
!= DRM_MODE_DPMS_ON
) {
1327 /* Switching the panel off requires vdd. */
1328 ironlake_edp_panel_vdd_on(intel_dp
);
1329 ironlake_edp_backlight_off(intel_dp
);
1330 intel_dp_sink_dpms(intel_dp
, mode
);
1331 ironlake_edp_panel_off(intel_dp
);
1332 intel_dp_link_down(intel_dp
);
1334 if (is_cpu_edp(intel_dp
))
1335 ironlake_edp_pll_off(encoder
);
1337 if (is_cpu_edp(intel_dp
))
1338 ironlake_edp_pll_on(encoder
);
1340 ironlake_edp_panel_vdd_on(intel_dp
);
1341 intel_dp_sink_dpms(intel_dp
, mode
);
1342 if (!(dp_reg
& DP_PORT_EN
)) {
1343 intel_dp_start_link_train(intel_dp
);
1344 ironlake_edp_panel_on(intel_dp
);
1345 ironlake_edp_panel_vdd_off(intel_dp
, true);
1346 intel_dp_complete_link_train(intel_dp
);
1348 ironlake_edp_panel_vdd_off(intel_dp
, false);
1349 ironlake_edp_backlight_on(intel_dp
);
1351 intel_dp
->dpms_mode
= mode
;
1355 * Native read with retry for link status and receiver capability reads for
1356 * cases where the sink may still be asleep.
1359 intel_dp_aux_native_read_retry(struct intel_dp
*intel_dp
, uint16_t address
,
1360 uint8_t *recv
, int recv_bytes
)
1365 * Sinks are *supposed* to come up within 1ms from an off state,
1366 * but we're also supposed to retry 3 times per the spec.
1368 for (i
= 0; i
< 3; i
++) {
1369 ret
= intel_dp_aux_native_read(intel_dp
, address
, recv
,
1371 if (ret
== recv_bytes
)
1380 * Fetch AUX CH registers 0x202 - 0x207 which contain
1381 * link status information
1384 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1386 return intel_dp_aux_native_read_retry(intel_dp
,
1389 DP_LINK_STATUS_SIZE
);
1393 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1396 return link_status
[r
- DP_LANE0_1_STATUS
];
1400 intel_get_adjust_request_voltage(uint8_t adjust_request
[2],
1403 int s
= ((lane
& 1) ?
1404 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
1405 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
1406 uint8_t l
= adjust_request
[lane
>>1];
1408 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
1412 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request
[2],
1415 int s
= ((lane
& 1) ?
1416 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
1417 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
1418 uint8_t l
= adjust_request
[lane
>>1];
1420 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1425 static char *voltage_names
[] = {
1426 "0.4V", "0.6V", "0.8V", "1.2V"
1428 static char *pre_emph_names
[] = {
1429 "0dB", "3.5dB", "6dB", "9.5dB"
1431 static char *link_train_names
[] = {
1432 "pattern 1", "pattern 2", "idle", "off"
1437 * These are source-specific values; current Intel hardware supports
1438 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1442 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
1444 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1446 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
))
1447 return DP_TRAIN_VOLTAGE_SWING_800
;
1448 else if (HAS_PCH_CPT(dev
) && !is_cpu_edp(intel_dp
))
1449 return DP_TRAIN_VOLTAGE_SWING_1200
;
1451 return DP_TRAIN_VOLTAGE_SWING_800
;
1455 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
1457 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1459 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1460 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1461 case DP_TRAIN_VOLTAGE_SWING_400
:
1462 return DP_TRAIN_PRE_EMPHASIS_6
;
1463 case DP_TRAIN_VOLTAGE_SWING_600
:
1464 case DP_TRAIN_VOLTAGE_SWING_800
:
1465 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1467 return DP_TRAIN_PRE_EMPHASIS_0
;
1470 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1471 case DP_TRAIN_VOLTAGE_SWING_400
:
1472 return DP_TRAIN_PRE_EMPHASIS_6
;
1473 case DP_TRAIN_VOLTAGE_SWING_600
:
1474 return DP_TRAIN_PRE_EMPHASIS_6
;
1475 case DP_TRAIN_VOLTAGE_SWING_800
:
1476 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1477 case DP_TRAIN_VOLTAGE_SWING_1200
:
1479 return DP_TRAIN_PRE_EMPHASIS_0
;
1485 intel_get_adjust_train(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1490 uint8_t *adjust_request
= link_status
+ (DP_ADJUST_REQUEST_LANE0_1
- DP_LANE0_1_STATUS
);
1491 uint8_t voltage_max
;
1492 uint8_t preemph_max
;
1494 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1495 uint8_t this_v
= intel_get_adjust_request_voltage(adjust_request
, lane
);
1496 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(adjust_request
, lane
);
1504 voltage_max
= intel_dp_voltage_max(intel_dp
);
1505 if (v
>= voltage_max
)
1506 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
1508 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
1509 if (p
>= preemph_max
)
1510 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1512 for (lane
= 0; lane
< 4; lane
++)
1513 intel_dp
->train_set
[lane
] = v
| p
;
1517 intel_dp_signal_levels(uint8_t train_set
)
1519 uint32_t signal_levels
= 0;
1521 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1522 case DP_TRAIN_VOLTAGE_SWING_400
:
1524 signal_levels
|= DP_VOLTAGE_0_4
;
1526 case DP_TRAIN_VOLTAGE_SWING_600
:
1527 signal_levels
|= DP_VOLTAGE_0_6
;
1529 case DP_TRAIN_VOLTAGE_SWING_800
:
1530 signal_levels
|= DP_VOLTAGE_0_8
;
1532 case DP_TRAIN_VOLTAGE_SWING_1200
:
1533 signal_levels
|= DP_VOLTAGE_1_2
;
1536 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1537 case DP_TRAIN_PRE_EMPHASIS_0
:
1539 signal_levels
|= DP_PRE_EMPHASIS_0
;
1541 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1542 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1544 case DP_TRAIN_PRE_EMPHASIS_6
:
1545 signal_levels
|= DP_PRE_EMPHASIS_6
;
1547 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1548 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1551 return signal_levels
;
1554 /* Gen6's DP voltage swing and pre-emphasis control */
1556 intel_gen6_edp_signal_levels(uint8_t train_set
)
1558 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1559 DP_TRAIN_PRE_EMPHASIS_MASK
);
1560 switch (signal_levels
) {
1561 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1562 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1563 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1564 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1565 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
1566 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1567 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_6
:
1568 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
1569 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1570 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1571 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
1572 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1573 case DP_TRAIN_VOLTAGE_SWING_1200
| DP_TRAIN_PRE_EMPHASIS_0
:
1574 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
1576 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1577 "0x%x\n", signal_levels
);
1578 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
1582 /* Gen7's DP voltage swing and pre-emphasis control */
1584 intel_gen7_edp_signal_levels(uint8_t train_set
)
1586 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
1587 DP_TRAIN_PRE_EMPHASIS_MASK
);
1588 switch (signal_levels
) {
1589 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1590 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
1591 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1592 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
1593 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1594 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
1596 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_0
:
1597 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
1598 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1599 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
1601 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1602 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
1603 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1604 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
1607 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1608 "0x%x\n", signal_levels
);
1609 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
1614 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1617 int s
= (lane
& 1) * 4;
1618 uint8_t l
= link_status
[lane
>>1];
1620 return (l
>> s
) & 0xf;
1623 /* Check for clock recovery is done on all channels */
1625 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1628 uint8_t lane_status
;
1630 for (lane
= 0; lane
< lane_count
; lane
++) {
1631 lane_status
= intel_get_lane_status(link_status
, lane
);
1632 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1638 /* Check to see if channel eq is done on all channels */
1639 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1640 DP_LANE_CHANNEL_EQ_DONE|\
1641 DP_LANE_SYMBOL_LOCKED)
1643 intel_channel_eq_ok(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
1646 uint8_t lane_status
;
1649 lane_align
= intel_dp_link_status(link_status
,
1650 DP_LANE_ALIGN_STATUS_UPDATED
);
1651 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1653 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1654 lane_status
= intel_get_lane_status(link_status
, lane
);
1655 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1662 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1663 uint32_t dp_reg_value
,
1664 uint8_t dp_train_pat
)
1666 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1670 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1671 POSTING_READ(intel_dp
->output_reg
);
1673 intel_dp_aux_native_write_1(intel_dp
,
1674 DP_TRAINING_PATTERN_SET
,
1677 ret
= intel_dp_aux_native_write(intel_dp
,
1678 DP_TRAINING_LANE0_SET
,
1679 intel_dp
->train_set
,
1680 intel_dp
->lane_count
);
1681 if (ret
!= intel_dp
->lane_count
)
1687 /* Enable corresponding port and start training pattern 1 */
1689 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1691 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1693 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.base
.crtc
);
1696 bool clock_recovery
= false;
1697 int voltage_tries
, loop_tries
;
1699 uint32_t DP
= intel_dp
->DP
;
1702 * On CPT we have to enable the port in training pattern 1, which
1703 * will happen below in intel_dp_set_link_train. Otherwise, enable
1704 * the port and wait for it to become active.
1706 if (!HAS_PCH_CPT(dev
)) {
1707 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
1708 POSTING_READ(intel_dp
->output_reg
);
1709 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1712 /* Write the link configuration data */
1713 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1714 intel_dp
->link_configuration
,
1715 DP_LINK_CONFIGURATION_SIZE
);
1719 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1720 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1722 DP
&= ~DP_LINK_TRAIN_MASK
;
1723 memset(intel_dp
->train_set
, 0, 4);
1727 clock_recovery
= false;
1729 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1730 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1731 uint32_t signal_levels
;
1734 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1735 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1736 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1737 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1738 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1739 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1741 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1742 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels
);
1743 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1746 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1747 reg
= DP
| DP_LINK_TRAIN_PAT_1_CPT
;
1749 reg
= DP
| DP_LINK_TRAIN_PAT_1
;
1751 if (!intel_dp_set_link_train(intel_dp
, reg
,
1752 DP_TRAINING_PATTERN_1
|
1753 DP_LINK_SCRAMBLING_DISABLE
))
1755 /* Set training pattern 1 */
1758 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
1759 DRM_ERROR("failed to get link status\n");
1763 if (intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1764 DRM_DEBUG_KMS("clock recovery OK\n");
1765 clock_recovery
= true;
1769 /* Check to see if we've tried the max voltage */
1770 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1771 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1773 if (i
== intel_dp
->lane_count
&& voltage_tries
== 5) {
1775 if (loop_tries
== 5) {
1776 DRM_DEBUG_KMS("too many full retries, give up\n");
1779 memset(intel_dp
->train_set
, 0, 4);
1784 /* Check to see if we've tried the same voltage 5 times */
1785 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1787 if (voltage_tries
== 5) {
1788 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1793 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1795 /* Compute new intel_dp->train_set as requested by target */
1796 intel_get_adjust_train(intel_dp
, link_status
);
1803 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1805 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1807 bool channel_eq
= false;
1808 int tries
, cr_tries
;
1810 uint32_t DP
= intel_dp
->DP
;
1812 /* channel equalization */
1817 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1818 uint32_t signal_levels
;
1819 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
1822 DRM_ERROR("failed to train DP, aborting\n");
1823 intel_dp_link_down(intel_dp
);
1827 if (IS_GEN7(dev
) && is_cpu_edp(intel_dp
)) {
1828 signal_levels
= intel_gen7_edp_signal_levels(intel_dp
->train_set
[0]);
1829 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
) | signal_levels
;
1830 } else if (IS_GEN6(dev
) && is_cpu_edp(intel_dp
)) {
1831 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1832 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1834 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0]);
1835 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1838 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1839 reg
= DP
| DP_LINK_TRAIN_PAT_2_CPT
;
1841 reg
= DP
| DP_LINK_TRAIN_PAT_2
;
1843 /* channel eq pattern */
1844 if (!intel_dp_set_link_train(intel_dp
, reg
,
1845 DP_TRAINING_PATTERN_2
|
1846 DP_LINK_SCRAMBLING_DISABLE
))
1850 if (!intel_dp_get_link_status(intel_dp
, link_status
))
1853 /* Make sure clock is still ok */
1854 if (!intel_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
1855 intel_dp_start_link_train(intel_dp
);
1860 if (intel_channel_eq_ok(intel_dp
, link_status
)) {
1865 /* Try 5 times, then try clock recovery if that fails */
1867 intel_dp_link_down(intel_dp
);
1868 intel_dp_start_link_train(intel_dp
);
1874 /* Compute new intel_dp->train_set as requested by target */
1875 intel_get_adjust_train(intel_dp
, link_status
);
1879 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1880 reg
= DP
| DP_LINK_TRAIN_OFF_CPT
;
1882 reg
= DP
| DP_LINK_TRAIN_OFF
;
1884 I915_WRITE(intel_dp
->output_reg
, reg
);
1885 POSTING_READ(intel_dp
->output_reg
);
1886 intel_dp_aux_native_write_1(intel_dp
,
1887 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
1891 intel_dp_link_down(struct intel_dp
*intel_dp
)
1893 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
1894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1895 uint32_t DP
= intel_dp
->DP
;
1897 if ((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0)
1900 DRM_DEBUG_KMS("\n");
1902 if (is_edp(intel_dp
)) {
1903 DP
&= ~DP_PLL_ENABLE
;
1904 I915_WRITE(intel_dp
->output_reg
, DP
);
1905 POSTING_READ(intel_dp
->output_reg
);
1909 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
))) {
1910 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1911 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1913 DP
&= ~DP_LINK_TRAIN_MASK
;
1914 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1916 POSTING_READ(intel_dp
->output_reg
);
1920 if (is_edp(intel_dp
)) {
1921 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || !is_cpu_edp(intel_dp
)))
1922 DP
|= DP_LINK_TRAIN_OFF_CPT
;
1924 DP
|= DP_LINK_TRAIN_OFF
;
1927 if (HAS_PCH_IBX(dev
) &&
1928 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
1929 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
1931 /* Hardware workaround: leaving our transcoder select
1932 * set to transcoder B while it's off will prevent the
1933 * corresponding HDMI output on transcoder A.
1935 * Combine this with another hardware workaround:
1936 * transcoder select bit can only be cleared while the
1939 DP
&= ~DP_PIPEB_SELECT
;
1940 I915_WRITE(intel_dp
->output_reg
, DP
);
1942 /* Changes to enable or select take place the vblank
1943 * after being written.
1946 /* We can arrive here never having been attached
1947 * to a CRTC, for instance, due to inheriting
1948 * random state from the BIOS.
1950 * If the pipe is not running, play safe and
1951 * wait for the clocks to stabilise before
1954 POSTING_READ(intel_dp
->output_reg
);
1957 intel_wait_for_vblank(dev
, to_intel_crtc(crtc
)->pipe
);
1960 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
1961 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1962 POSTING_READ(intel_dp
->output_reg
);
1963 msleep(intel_dp
->panel_power_down_delay
);
1967 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
1969 if (intel_dp_aux_native_read_retry(intel_dp
, 0x000, intel_dp
->dpcd
,
1970 sizeof(intel_dp
->dpcd
)) &&
1971 (intel_dp
->dpcd
[DP_DPCD_REV
] != 0)) {
1979 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
1983 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
1986 ironlake_edp_panel_vdd_on(intel_dp
);
1988 if (intel_dp_aux_native_read_retry(intel_dp
, DP_SINK_OUI
, buf
, 3))
1989 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1990 buf
[0], buf
[1], buf
[2]);
1992 if (intel_dp_aux_native_read_retry(intel_dp
, DP_BRANCH_OUI
, buf
, 3))
1993 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1994 buf
[0], buf
[1], buf
[2]);
1996 ironlake_edp_panel_vdd_off(intel_dp
, false);
2000 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
2004 ret
= intel_dp_aux_native_read_retry(intel_dp
,
2005 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2006 sink_irq_vector
, 1);
2014 intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
2016 /* NAK by default */
2017 intel_dp_aux_native_write_1(intel_dp
, DP_TEST_RESPONSE
, DP_TEST_ACK
);
2021 * According to DP spec
2024 * 2. Configure link according to Receiver Capabilities
2025 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2026 * 4. Check link status on receipt of hot-plug interrupt
2030 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
2033 u8 link_status
[DP_LINK_STATUS_SIZE
];
2035 if (intel_dp
->dpms_mode
!= DRM_MODE_DPMS_ON
)
2038 if (!intel_dp
->base
.base
.crtc
)
2041 /* Try to read receiver status if the link appears to be up */
2042 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
2043 intel_dp_link_down(intel_dp
);
2047 /* Now read the DPCD to see if it's actually running */
2048 if (!intel_dp_get_dpcd(intel_dp
)) {
2049 intel_dp_link_down(intel_dp
);
2053 /* Try to read the source of the interrupt */
2054 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
2055 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
2056 /* Clear interrupt source */
2057 intel_dp_aux_native_write_1(intel_dp
,
2058 DP_DEVICE_SERVICE_IRQ_VECTOR
,
2061 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
2062 intel_dp_handle_test_request(intel_dp
);
2063 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
2064 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2067 if (!intel_channel_eq_ok(intel_dp
, link_status
)) {
2068 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2069 drm_get_encoder_name(&intel_dp
->base
.base
));
2070 intel_dp_start_link_train(intel_dp
);
2071 intel_dp_complete_link_train(intel_dp
);
2075 static enum drm_connector_status
2076 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
2078 if (intel_dp_get_dpcd(intel_dp
))
2079 return connector_status_connected
;
2080 return connector_status_disconnected
;
2083 static enum drm_connector_status
2084 ironlake_dp_detect(struct intel_dp
*intel_dp
)
2086 enum drm_connector_status status
;
2088 /* Can't disconnect eDP, but you can close the lid... */
2089 if (is_edp(intel_dp
)) {
2090 status
= intel_panel_detect(intel_dp
->base
.base
.dev
);
2091 if (status
== connector_status_unknown
)
2092 status
= connector_status_connected
;
2096 return intel_dp_detect_dpcd(intel_dp
);
2099 static enum drm_connector_status
2100 g4x_dp_detect(struct intel_dp
*intel_dp
)
2102 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2106 switch (intel_dp
->output_reg
) {
2108 bit
= DPB_HOTPLUG_LIVE_STATUS
;
2111 bit
= DPC_HOTPLUG_LIVE_STATUS
;
2114 bit
= DPD_HOTPLUG_LIVE_STATUS
;
2117 return connector_status_unknown
;
2120 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
2121 return connector_status_disconnected
;
2123 return intel_dp_detect_dpcd(intel_dp
);
2126 static struct edid
*
2127 intel_dp_get_edid(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2129 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2133 if (is_edp(intel_dp
)) {
2134 if (!intel_dp
->edid
)
2137 size
= (intel_dp
->edid
->extensions
+ 1) * EDID_LENGTH
;
2138 edid
= kmalloc(size
, GFP_KERNEL
);
2142 memcpy(edid
, intel_dp
->edid
, size
);
2146 edid
= drm_get_edid(connector
, adapter
);
2151 intel_dp_get_edid_modes(struct drm_connector
*connector
, struct i2c_adapter
*adapter
)
2153 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2156 if (is_edp(intel_dp
)) {
2157 drm_mode_connector_update_edid_property(connector
,
2159 ret
= drm_add_edid_modes(connector
, intel_dp
->edid
);
2160 drm_edid_to_eld(connector
,
2162 connector
->display_info
.raw_edid
= NULL
;
2163 return intel_dp
->edid_mode_count
;
2166 ret
= intel_ddc_get_modes(connector
, adapter
);
2172 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2174 * \return true if DP port is connected.
2175 * \return false if DP port is disconnected.
2177 static enum drm_connector_status
2178 intel_dp_detect(struct drm_connector
*connector
, bool force
)
2180 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2181 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2182 enum drm_connector_status status
;
2183 struct edid
*edid
= NULL
;
2185 intel_dp
->has_audio
= false;
2187 if (HAS_PCH_SPLIT(dev
))
2188 status
= ironlake_dp_detect(intel_dp
);
2190 status
= g4x_dp_detect(intel_dp
);
2192 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2193 intel_dp
->dpcd
[0], intel_dp
->dpcd
[1], intel_dp
->dpcd
[2],
2194 intel_dp
->dpcd
[3], intel_dp
->dpcd
[4], intel_dp
->dpcd
[5],
2195 intel_dp
->dpcd
[6], intel_dp
->dpcd
[7]);
2197 if (status
!= connector_status_connected
)
2200 intel_dp_probe_oui(intel_dp
);
2202 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
) {
2203 intel_dp
->has_audio
= (intel_dp
->force_audio
== HDMI_AUDIO_ON
);
2205 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2207 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
2208 connector
->display_info
.raw_edid
= NULL
;
2213 return connector_status_connected
;
2216 static int intel_dp_get_modes(struct drm_connector
*connector
)
2218 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2219 struct drm_device
*dev
= intel_dp
->base
.base
.dev
;
2220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2223 /* We should parse the EDID data and find out if it has an audio sink
2226 ret
= intel_dp_get_edid_modes(connector
, &intel_dp
->adapter
);
2228 if (is_edp(intel_dp
) && !intel_dp
->panel_fixed_mode
) {
2229 struct drm_display_mode
*newmode
;
2230 list_for_each_entry(newmode
, &connector
->probed_modes
,
2232 if ((newmode
->type
& DRM_MODE_TYPE_PREFERRED
)) {
2233 intel_dp
->panel_fixed_mode
=
2234 drm_mode_duplicate(dev
, newmode
);
2242 /* if eDP has no EDID, try to use fixed panel mode from VBT */
2243 if (is_edp(intel_dp
)) {
2244 /* initialize panel mode from VBT if available for eDP */
2245 if (intel_dp
->panel_fixed_mode
== NULL
&& dev_priv
->lfp_lvds_vbt_mode
!= NULL
) {
2246 intel_dp
->panel_fixed_mode
=
2247 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
2248 if (intel_dp
->panel_fixed_mode
) {
2249 intel_dp
->panel_fixed_mode
->type
|=
2250 DRM_MODE_TYPE_PREFERRED
;
2253 if (intel_dp
->panel_fixed_mode
) {
2254 struct drm_display_mode
*mode
;
2255 mode
= drm_mode_duplicate(dev
, intel_dp
->panel_fixed_mode
);
2256 drm_mode_probed_add(connector
, mode
);
2264 intel_dp_detect_audio(struct drm_connector
*connector
)
2266 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2268 bool has_audio
= false;
2270 edid
= intel_dp_get_edid(connector
, &intel_dp
->adapter
);
2272 has_audio
= drm_detect_monitor_audio(edid
);
2274 connector
->display_info
.raw_edid
= NULL
;
2282 intel_dp_set_property(struct drm_connector
*connector
,
2283 struct drm_property
*property
,
2286 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
2287 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
2290 ret
= drm_connector_property_set_value(connector
, property
, val
);
2294 if (property
== dev_priv
->force_audio_property
) {
2298 if (i
== intel_dp
->force_audio
)
2301 intel_dp
->force_audio
= i
;
2303 if (i
== HDMI_AUDIO_AUTO
)
2304 has_audio
= intel_dp_detect_audio(connector
);
2306 has_audio
= (i
== HDMI_AUDIO_ON
);
2308 if (has_audio
== intel_dp
->has_audio
)
2311 intel_dp
->has_audio
= has_audio
;
2315 if (property
== dev_priv
->broadcast_rgb_property
) {
2316 if (val
== !!intel_dp
->color_range
)
2319 intel_dp
->color_range
= val
? DP_COLOR_RANGE_16_235
: 0;
2326 if (intel_dp
->base
.base
.crtc
) {
2327 struct drm_crtc
*crtc
= intel_dp
->base
.base
.crtc
;
2328 drm_crtc_helper_set_mode(crtc
, &crtc
->mode
,
2337 intel_dp_destroy(struct drm_connector
*connector
)
2339 struct drm_device
*dev
= connector
->dev
;
2341 if (intel_dpd_is_edp(dev
))
2342 intel_panel_destroy_backlight(dev
);
2344 drm_sysfs_connector_remove(connector
);
2345 drm_connector_cleanup(connector
);
2349 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
2351 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
2353 i2c_del_adapter(&intel_dp
->adapter
);
2354 drm_encoder_cleanup(encoder
);
2355 if (is_edp(intel_dp
)) {
2356 kfree(intel_dp
->edid
);
2357 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
2358 ironlake_panel_vdd_off_sync(intel_dp
);
2363 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
2364 .dpms
= intel_dp_dpms
,
2365 .mode_fixup
= intel_dp_mode_fixup
,
2366 .prepare
= intel_dp_prepare
,
2367 .mode_set
= intel_dp_mode_set
,
2368 .commit
= intel_dp_commit
,
2371 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
2372 .dpms
= drm_helper_connector_dpms
,
2373 .detect
= intel_dp_detect
,
2374 .fill_modes
= drm_helper_probe_single_connector_modes
,
2375 .set_property
= intel_dp_set_property
,
2376 .destroy
= intel_dp_destroy
,
2379 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
2380 .get_modes
= intel_dp_get_modes
,
2381 .mode_valid
= intel_dp_mode_valid
,
2382 .best_encoder
= intel_best_encoder
,
2385 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
2386 .destroy
= intel_dp_encoder_destroy
,
2390 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
2392 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
2394 intel_dp_check_link_status(intel_dp
);
2397 /* Return which DP Port should be selected for Transcoder DP control */
2399 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
2401 struct drm_device
*dev
= crtc
->dev
;
2402 struct intel_encoder
*encoder
;
2404 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
2405 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2407 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
||
2408 intel_dp
->base
.type
== INTEL_OUTPUT_EDP
)
2409 return intel_dp
->output_reg
;
2415 /* check the VBT to see whether the eDP is on DP-D port */
2416 bool intel_dpd_is_edp(struct drm_device
*dev
)
2418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2419 struct child_device_config
*p_child
;
2422 if (!dev_priv
->child_dev_num
)
2425 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
2426 p_child
= dev_priv
->child_dev
+ i
;
2428 if (p_child
->dvo_port
== PORT_IDPD
&&
2429 p_child
->device_type
== DEVICE_TYPE_eDP
)
2436 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
2438 intel_attach_force_audio_property(connector
);
2439 intel_attach_broadcast_rgb_property(connector
);
2443 intel_dp_init(struct drm_device
*dev
, int output_reg
)
2445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2446 struct drm_connector
*connector
;
2447 struct intel_dp
*intel_dp
;
2448 struct intel_encoder
*intel_encoder
;
2449 struct intel_connector
*intel_connector
;
2450 const char *name
= NULL
;
2453 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
2457 intel_dp
->output_reg
= output_reg
;
2458 intel_dp
->dpms_mode
= -1;
2460 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
2461 if (!intel_connector
) {
2465 intel_encoder
= &intel_dp
->base
;
2467 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
2468 if (intel_dpd_is_edp(dev
))
2469 intel_dp
->is_pch_edp
= true;
2471 if (output_reg
== DP_A
|| is_pch_edp(intel_dp
)) {
2472 type
= DRM_MODE_CONNECTOR_eDP
;
2473 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
2475 type
= DRM_MODE_CONNECTOR_DisplayPort
;
2476 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
2479 connector
= &intel_connector
->base
;
2480 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
2481 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
2483 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
2485 if (output_reg
== DP_B
|| output_reg
== PCH_DP_B
)
2486 intel_encoder
->clone_mask
= (1 << INTEL_DP_B_CLONE_BIT
);
2487 else if (output_reg
== DP_C
|| output_reg
== PCH_DP_C
)
2488 intel_encoder
->clone_mask
= (1 << INTEL_DP_C_CLONE_BIT
);
2489 else if (output_reg
== DP_D
|| output_reg
== PCH_DP_D
)
2490 intel_encoder
->clone_mask
= (1 << INTEL_DP_D_CLONE_BIT
);
2492 if (is_edp(intel_dp
)) {
2493 intel_encoder
->clone_mask
= (1 << INTEL_EDP_CLONE_BIT
);
2494 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
2495 ironlake_panel_vdd_work
);
2498 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
2500 connector
->interlace_allowed
= true;
2501 connector
->doublescan_allowed
= 0;
2503 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
2504 DRM_MODE_ENCODER_TMDS
);
2505 drm_encoder_helper_add(&intel_encoder
->base
, &intel_dp_helper_funcs
);
2507 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
2508 drm_sysfs_connector_add(connector
);
2510 /* Set up the DDC bus. */
2511 switch (output_reg
) {
2517 dev_priv
->hotplug_supported_mask
|=
2518 DPB_HOTPLUG_INT_STATUS
;
2523 dev_priv
->hotplug_supported_mask
|=
2524 DPC_HOTPLUG_INT_STATUS
;
2529 dev_priv
->hotplug_supported_mask
|=
2530 DPD_HOTPLUG_INT_STATUS
;
2535 /* Cache some DPCD data in the eDP case */
2536 if (is_edp(intel_dp
)) {
2537 struct edp_power_seq cur
, vbt
;
2538 u32 pp_on
, pp_off
, pp_div
;
2540 pp_on
= I915_READ(PCH_PP_ON_DELAYS
);
2541 pp_off
= I915_READ(PCH_PP_OFF_DELAYS
);
2542 pp_div
= I915_READ(PCH_PP_DIVISOR
);
2544 if (!pp_on
|| !pp_off
|| !pp_div
) {
2545 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2546 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2547 intel_dp_destroy(&intel_connector
->base
);
2551 /* Pull timing values out of registers */
2552 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
2553 PANEL_POWER_UP_DELAY_SHIFT
;
2555 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
2556 PANEL_LIGHT_ON_DELAY_SHIFT
;
2558 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
2559 PANEL_LIGHT_OFF_DELAY_SHIFT
;
2561 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
2562 PANEL_POWER_DOWN_DELAY_SHIFT
;
2564 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
2565 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
2567 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2568 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
2570 vbt
= dev_priv
->edp
.pps
;
2572 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2573 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
2575 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2577 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
2578 intel_dp
->backlight_on_delay
= get_delay(t8
);
2579 intel_dp
->backlight_off_delay
= get_delay(t9
);
2580 intel_dp
->panel_power_down_delay
= get_delay(t10
);
2581 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
2583 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2584 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
2585 intel_dp
->panel_power_cycle_delay
);
2587 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2588 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
2591 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
2593 if (is_edp(intel_dp
)) {
2597 ironlake_edp_panel_vdd_on(intel_dp
);
2598 ret
= intel_dp_get_dpcd(intel_dp
);
2599 ironlake_edp_panel_vdd_off(intel_dp
, false);
2602 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
2603 dev_priv
->no_aux_handshake
=
2604 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
2605 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
2607 /* if this fails, presume the device is a ghost */
2608 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2609 intel_dp_encoder_destroy(&intel_dp
->base
.base
);
2610 intel_dp_destroy(&intel_connector
->base
);
2614 ironlake_edp_panel_vdd_on(intel_dp
);
2615 edid
= drm_get_edid(connector
, &intel_dp
->adapter
);
2617 drm_mode_connector_update_edid_property(connector
,
2619 intel_dp
->edid_mode_count
=
2620 drm_add_edid_modes(connector
, edid
);
2621 drm_edid_to_eld(connector
, edid
);
2622 intel_dp
->edid
= edid
;
2624 ironlake_edp_panel_vdd_off(intel_dp
, false);
2627 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
2629 if (is_edp(intel_dp
)) {
2630 dev_priv
->int_edp_connector
= connector
;
2631 intel_panel_setup_backlight(dev
);
2634 intel_dp_add_properties(intel_dp
, connector
);
2636 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2637 * 0xd. Failure to do so will result in spurious interrupts being
2638 * generated on the port when a cable is not attached.
2640 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
2641 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
2642 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);