2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
49 static const struct dp_link_dpll gen4_dpll
[] = {
51 { .p1
= 2, .p2
= 10, .n
= 2, .m1
= 23, .m2
= 8 } },
53 { .p1
= 1, .p2
= 10, .n
= 1, .m1
= 14, .m2
= 2 } }
56 static const struct dp_link_dpll pch_dpll
[] = {
58 { .p1
= 2, .p2
= 10, .n
= 1, .m1
= 12, .m2
= 9 } },
60 { .p1
= 1, .p2
= 10, .n
= 2, .m1
= 14, .m2
= 8 } }
63 static const struct dp_link_dpll vlv_dpll
[] = {
65 { .p1
= 3, .p2
= 2, .n
= 5, .m1
= 3, .m2
= 81 } },
67 { .p1
= 2, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 27 } }
71 * CHV supports eDP 1.4 that have more link rates.
72 * Below only provides the fixed rate but exclude variable rate.
74 static const struct dp_link_dpll chv_dpll
[] = {
76 * CHV requires to program fractional division for m2.
77 * m2 is stored in fixed point format using formula below
78 * (m2_int << 22) | m2_fraction
80 { DP_LINK_BW_1_62
, /* m2_int = 32, m2_fraction = 1677722 */
81 { .p1
= 4, .p2
= 2, .n
= 1, .m1
= 2, .m2
= 0x819999a } },
82 { DP_LINK_BW_2_7
, /* m2_int = 27, m2_fraction = 0 */
83 { .p1
= 4, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } },
84 { DP_LINK_BW_5_4
, /* m2_int = 27, m2_fraction = 0 */
85 { .p1
= 2, .p2
= 1, .n
= 1, .m1
= 2, .m2
= 0x6c00000 } }
87 /* Skylake supports following rates */
88 static const int gen9_rates
[] = { 162000, 216000, 270000,
89 324000, 432000, 540000 };
90 static const int chv_rates
[] = { 162000, 202500, 210000, 216000,
91 243000, 270000, 324000, 405000,
92 420000, 432000, 540000 };
93 static const int default_rates
[] = { 162000, 270000, 540000 };
96 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
97 * @intel_dp: DP struct
99 * If a CPU or PCH DP output is attached to an eDP panel, this function
100 * will return true, and false otherwise.
102 static bool is_edp(struct intel_dp
*intel_dp
)
104 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
106 return intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
;
109 static struct drm_device
*intel_dp_to_dev(struct intel_dp
*intel_dp
)
111 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
113 return intel_dig_port
->base
.base
.dev
;
116 static struct intel_dp
*intel_attached_dp(struct drm_connector
*connector
)
118 return enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
121 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
122 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
);
123 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
);
124 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
);
125 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
129 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
131 int max_link_bw
= intel_dp
->dpcd
[DP_MAX_LINK_RATE
];
133 switch (max_link_bw
) {
134 case DP_LINK_BW_1_62
:
139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
141 max_link_bw
= DP_LINK_BW_1_62
;
147 static u8
intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
149 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
150 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
151 u8 source_max
, sink_max
;
154 if (HAS_DDI(dev
) && intel_dig_port
->port
== PORT_A
&&
155 (intel_dig_port
->saved_port_bits
& DDI_A_4_LANES
) == 0)
158 sink_max
= drm_dp_max_lane_count(intel_dp
->dpcd
);
160 return min(source_max
, sink_max
);
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 * 270000 * 1 * 8 / 10 == 216000
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
181 intel_dp_link_required(int pixel_clock
, int bpp
)
183 return (pixel_clock
* bpp
+ 9) / 10;
187 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
189 return (max_link_clock
* max_lanes
* 8) / 10;
192 static enum drm_mode_status
193 intel_dp_mode_valid(struct drm_connector
*connector
,
194 struct drm_display_mode
*mode
)
196 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
197 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
198 struct drm_display_mode
*fixed_mode
= intel_connector
->panel
.fixed_mode
;
199 int target_clock
= mode
->clock
;
200 int max_rate
, mode_rate
, max_lanes
, max_link_clock
;
202 if (is_edp(intel_dp
) && fixed_mode
) {
203 if (mode
->hdisplay
> fixed_mode
->hdisplay
)
206 if (mode
->vdisplay
> fixed_mode
->vdisplay
)
209 target_clock
= fixed_mode
->clock
;
212 max_link_clock
= intel_dp_max_link_rate(intel_dp
);
213 max_lanes
= intel_dp_max_lane_count(intel_dp
);
215 max_rate
= intel_dp_max_data_rate(max_link_clock
, max_lanes
);
216 mode_rate
= intel_dp_link_required(target_clock
, 18);
218 if (mode_rate
> max_rate
)
219 return MODE_CLOCK_HIGH
;
221 if (mode
->clock
< 10000)
222 return MODE_CLOCK_LOW
;
224 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
225 return MODE_H_ILLEGAL
;
230 uint32_t intel_dp_pack_aux(const uint8_t *src
, int src_bytes
)
237 for (i
= 0; i
< src_bytes
; i
++)
238 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
242 static void intel_dp_unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
247 for (i
= 0; i
< dst_bytes
; i
++)
248 dst
[i
] = src
>> ((3-i
) * 8);
251 /* hrawclock is 1/4 the FSB frequency */
253 intel_hrawclk(struct drm_device
*dev
)
255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev
))
262 clkcfg
= I915_READ(CLKCFG
);
263 switch (clkcfg
& CLKCFG_FSB_MASK
) {
272 case CLKCFG_FSB_1067
:
274 case CLKCFG_FSB_1333
:
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600
:
278 case CLKCFG_FSB_1600_ALT
:
286 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
287 struct intel_dp
*intel_dp
);
289 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
290 struct intel_dp
*intel_dp
);
292 static void pps_lock(struct intel_dp
*intel_dp
)
294 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
295 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
296 struct drm_device
*dev
= encoder
->base
.dev
;
297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
298 enum intel_display_power_domain power_domain
;
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
304 power_domain
= intel_display_port_power_domain(encoder
);
305 intel_display_power_get(dev_priv
, power_domain
);
307 mutex_lock(&dev_priv
->pps_mutex
);
310 static void pps_unlock(struct intel_dp
*intel_dp
)
312 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
313 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
314 struct drm_device
*dev
= encoder
->base
.dev
;
315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
316 enum intel_display_power_domain power_domain
;
318 mutex_unlock(&dev_priv
->pps_mutex
);
320 power_domain
= intel_display_port_power_domain(encoder
);
321 intel_display_power_put(dev_priv
, power_domain
);
325 vlv_power_sequencer_kick(struct intel_dp
*intel_dp
)
327 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
328 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
330 enum pipe pipe
= intel_dp
->pps_pipe
;
334 if (WARN(I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
,
335 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
336 pipe_name(pipe
), port_name(intel_dig_port
->port
)))
339 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
340 pipe_name(pipe
), port_name(intel_dig_port
->port
));
342 /* Preserve the BIOS-computed detected bit. This is
343 * supposed to be read-only.
345 DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
346 DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
347 DP
|= DP_PORT_WIDTH(1);
348 DP
|= DP_LINK_TRAIN_PAT_1
;
350 if (IS_CHERRYVIEW(dev
))
351 DP
|= DP_PIPE_SELECT_CHV(pipe
);
352 else if (pipe
== PIPE_B
)
353 DP
|= DP_PIPEB_SELECT
;
355 pll_enabled
= I915_READ(DPLL(pipe
)) & DPLL_VCO_ENABLE
;
358 * The DPLL for the pipe must be enabled for this to work.
359 * So enable temporarily it if it's not already enabled.
362 vlv_force_pll_on(dev
, pipe
, IS_CHERRYVIEW(dev
) ?
363 &chv_dpll
[0].dpll
: &vlv_dpll
[0].dpll
);
366 * Similar magic as in intel_dp_enable_port().
367 * We _must_ do this port enable + disable trick
368 * to make this power seqeuencer lock onto the port.
369 * Otherwise even VDD force bit won't work.
371 I915_WRITE(intel_dp
->output_reg
, DP
);
372 POSTING_READ(intel_dp
->output_reg
);
374 I915_WRITE(intel_dp
->output_reg
, DP
| DP_PORT_EN
);
375 POSTING_READ(intel_dp
->output_reg
);
377 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
378 POSTING_READ(intel_dp
->output_reg
);
381 vlv_force_pll_off(dev
, pipe
);
385 vlv_power_sequencer_pipe(struct intel_dp
*intel_dp
)
387 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
388 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
390 struct intel_encoder
*encoder
;
391 unsigned int pipes
= (1 << PIPE_A
) | (1 << PIPE_B
);
394 lockdep_assert_held(&dev_priv
->pps_mutex
);
396 /* We should never land here with regular DP ports */
397 WARN_ON(!is_edp(intel_dp
));
399 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
400 return intel_dp
->pps_pipe
;
403 * We don't have power sequencer currently.
404 * Pick one that's not used by other ports.
406 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
408 struct intel_dp
*tmp
;
410 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
413 tmp
= enc_to_intel_dp(&encoder
->base
);
415 if (tmp
->pps_pipe
!= INVALID_PIPE
)
416 pipes
&= ~(1 << tmp
->pps_pipe
);
420 * Didn't find one. This should not happen since there
421 * are two power sequencers and up to two eDP ports.
423 if (WARN_ON(pipes
== 0))
426 pipe
= ffs(pipes
) - 1;
428 vlv_steal_power_sequencer(dev
, pipe
);
429 intel_dp
->pps_pipe
= pipe
;
431 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
432 pipe_name(intel_dp
->pps_pipe
),
433 port_name(intel_dig_port
->port
));
435 /* init power sequencer on this pipe and port */
436 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
437 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
440 * Even vdd force doesn't work until we've made
441 * the power sequencer lock in on the port.
443 vlv_power_sequencer_kick(intel_dp
);
445 return intel_dp
->pps_pipe
;
448 typedef bool (*vlv_pipe_check
)(struct drm_i915_private
*dev_priv
,
451 static bool vlv_pipe_has_pp_on(struct drm_i915_private
*dev_priv
,
454 return I915_READ(VLV_PIPE_PP_STATUS(pipe
)) & PP_ON
;
457 static bool vlv_pipe_has_vdd_on(struct drm_i915_private
*dev_priv
,
460 return I915_READ(VLV_PIPE_PP_CONTROL(pipe
)) & EDP_FORCE_VDD
;
463 static bool vlv_pipe_any(struct drm_i915_private
*dev_priv
,
470 vlv_initial_pps_pipe(struct drm_i915_private
*dev_priv
,
472 vlv_pipe_check pipe_check
)
476 for (pipe
= PIPE_A
; pipe
<= PIPE_B
; pipe
++) {
477 u32 port_sel
= I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe
)) &
478 PANEL_PORT_SELECT_MASK
;
480 if (port_sel
!= PANEL_PORT_SELECT_VLV(port
))
483 if (!pipe_check(dev_priv
, pipe
))
493 vlv_initial_power_sequencer_setup(struct intel_dp
*intel_dp
)
495 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
496 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
498 enum port port
= intel_dig_port
->port
;
500 lockdep_assert_held(&dev_priv
->pps_mutex
);
502 /* try to find a pipe with this port selected */
503 /* first pick one where the panel is on */
504 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
506 /* didn't find one? pick one where vdd is on */
507 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
508 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
509 vlv_pipe_has_vdd_on
);
510 /* didn't find one? pick one with just the correct port */
511 if (intel_dp
->pps_pipe
== INVALID_PIPE
)
512 intel_dp
->pps_pipe
= vlv_initial_pps_pipe(dev_priv
, port
,
515 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
516 if (intel_dp
->pps_pipe
== INVALID_PIPE
) {
517 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
522 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
523 port_name(port
), pipe_name(intel_dp
->pps_pipe
));
525 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
526 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
529 void vlv_power_sequencer_reset(struct drm_i915_private
*dev_priv
)
531 struct drm_device
*dev
= dev_priv
->dev
;
532 struct intel_encoder
*encoder
;
534 if (WARN_ON(!IS_VALLEYVIEW(dev
)))
538 * We can't grab pps_mutex here due to deadlock with power_domain
539 * mutex when power_domain functions are called while holding pps_mutex.
540 * That also means that in order to use pps_pipe the code needs to
541 * hold both a power domain reference and pps_mutex, and the power domain
542 * reference get/put must be done while _not_ holding pps_mutex.
543 * pps_{lock,unlock}() do these steps in the correct order, so one
544 * should use them always.
547 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
548 struct intel_dp
*intel_dp
;
550 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
553 intel_dp
= enc_to_intel_dp(&encoder
->base
);
554 intel_dp
->pps_pipe
= INVALID_PIPE
;
558 static u32
_pp_ctrl_reg(struct intel_dp
*intel_dp
)
560 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
562 if (HAS_PCH_SPLIT(dev
))
563 return PCH_PP_CONTROL
;
565 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp
));
568 static u32
_pp_stat_reg(struct intel_dp
*intel_dp
)
570 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
572 if (HAS_PCH_SPLIT(dev
))
573 return PCH_PP_STATUS
;
575 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp
));
578 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
579 This function only applicable when panel PM state is not to be tracked */
580 static int edp_notify_handler(struct notifier_block
*this, unsigned long code
,
583 struct intel_dp
*intel_dp
= container_of(this, typeof(* intel_dp
),
585 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
588 u32 pp_ctrl_reg
, pp_div_reg
;
590 if (!is_edp(intel_dp
) || code
!= SYS_RESTART
)
595 if (IS_VALLEYVIEW(dev
)) {
596 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
598 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
599 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
600 pp_div
= I915_READ(pp_div_reg
);
601 pp_div
&= PP_REFERENCE_DIVIDER_MASK
;
603 /* 0x1F write to PP_DIV_REG sets max cycle delay */
604 I915_WRITE(pp_div_reg
, pp_div
| 0x1F);
605 I915_WRITE(pp_ctrl_reg
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
606 msleep(intel_dp
->panel_power_cycle_delay
);
609 pps_unlock(intel_dp
);
614 static bool edp_have_panel_power(struct intel_dp
*intel_dp
)
616 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
619 lockdep_assert_held(&dev_priv
->pps_mutex
);
621 if (IS_VALLEYVIEW(dev
) &&
622 intel_dp
->pps_pipe
== INVALID_PIPE
)
625 return (I915_READ(_pp_stat_reg(intel_dp
)) & PP_ON
) != 0;
628 static bool edp_have_panel_vdd(struct intel_dp
*intel_dp
)
630 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
633 lockdep_assert_held(&dev_priv
->pps_mutex
);
635 if (IS_VALLEYVIEW(dev
) &&
636 intel_dp
->pps_pipe
== INVALID_PIPE
)
639 return I915_READ(_pp_ctrl_reg(intel_dp
)) & EDP_FORCE_VDD
;
643 intel_dp_check_edp(struct intel_dp
*intel_dp
)
645 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
648 if (!is_edp(intel_dp
))
651 if (!edp_have_panel_power(intel_dp
) && !edp_have_panel_vdd(intel_dp
)) {
652 WARN(1, "eDP powered off while attempting aux channel communication.\n");
653 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
654 I915_READ(_pp_stat_reg(intel_dp
)),
655 I915_READ(_pp_ctrl_reg(intel_dp
)));
660 intel_dp_aux_wait_done(struct intel_dp
*intel_dp
, bool has_aux_irq
)
662 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
663 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
665 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
669 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
671 done
= wait_event_timeout(dev_priv
->gmbus_wait_queue
, C
,
672 msecs_to_jiffies_timeout(10));
674 done
= wait_for_atomic(C
, 10) == 0;
676 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
683 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
685 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
686 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
689 * The clock divider is based off the hrawclk, and would like to run at
690 * 2MHz. So, take the hrawclk value and divide by 2 and use that
692 return index
? 0 : intel_hrawclk(dev
) / 2;
695 static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
697 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
698 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
704 if (intel_dig_port
->port
== PORT_A
) {
705 return DIV_ROUND_UP(dev_priv
->display
.get_display_clock_speed(dev
), 2000);
707 return DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
711 static uint32_t hsw_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
713 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
714 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
717 if (intel_dig_port
->port
== PORT_A
) {
720 return DIV_ROUND_CLOSEST(dev_priv
->display
.get_display_clock_speed(dev
), 2000);
721 } else if (dev_priv
->pch_id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
722 /* Workaround for non-ULT HSW */
729 return index
? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev
), 2);
733 static uint32_t vlv_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
735 return index
? 0 : 100;
738 static uint32_t skl_get_aux_clock_divider(struct intel_dp
*intel_dp
, int index
)
741 * SKL doesn't need us to program the AUX clock divider (Hardware will
742 * derive the clock from CDCLK automatically). We still implement the
743 * get_aux_clock_divider vfunc to plug-in into the existing code.
745 return index
? 0 : 1;
748 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
*intel_dp
,
751 uint32_t aux_clock_divider
)
753 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
754 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
755 uint32_t precharge
, timeout
;
762 if (IS_BROADWELL(dev
) && intel_dp
->aux_ch_ctl_reg
== DPA_AUX_CH_CTL
)
763 timeout
= DP_AUX_CH_CTL_TIME_OUT_600us
;
765 timeout
= DP_AUX_CH_CTL_TIME_OUT_400us
;
767 return DP_AUX_CH_CTL_SEND_BUSY
|
769 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
770 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
772 DP_AUX_CH_CTL_RECEIVE_ERROR
|
773 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
774 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
775 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
);
778 static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp
,
783 return DP_AUX_CH_CTL_SEND_BUSY
|
785 (has_aux_irq
? DP_AUX_CH_CTL_INTERRUPT
: 0) |
786 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
787 DP_AUX_CH_CTL_TIME_OUT_1600us
|
788 DP_AUX_CH_CTL_RECEIVE_ERROR
|
789 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
790 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
794 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
795 const uint8_t *send
, int send_bytes
,
796 uint8_t *recv
, int recv_size
)
798 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
799 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
801 uint32_t ch_ctl
= intel_dp
->aux_ch_ctl_reg
;
802 uint32_t ch_data
= ch_ctl
+ 4;
803 uint32_t aux_clock_divider
;
804 int i
, ret
, recv_bytes
;
807 bool has_aux_irq
= HAS_AUX_IRQ(dev
);
813 * We will be called with VDD already enabled for dpcd/edid/oui reads.
814 * In such cases we want to leave VDD enabled and it's up to upper layers
815 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
818 vdd
= edp_panel_vdd_on(intel_dp
);
820 /* dp aux is extremely sensitive to irq latency, hence request the
821 * lowest possible wakeup latency and so prevent the cpu from going into
824 pm_qos_update_request(&dev_priv
->pm_qos
, 0);
826 intel_dp_check_edp(intel_dp
);
828 intel_aux_display_runtime_get(dev_priv
);
830 /* Try to wait for any previous AUX channel activity */
831 for (try = 0; try < 3; try++) {
832 status
= I915_READ_NOTRACE(ch_ctl
);
833 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
839 WARN(1, "dp_aux_ch not started status 0x%08x\n",
845 /* Only 5 data registers! */
846 if (WARN_ON(send_bytes
> 20 || recv_size
> 20)) {
851 while ((aux_clock_divider
= intel_dp
->get_aux_clock_divider(intel_dp
, clock
++))) {
852 u32 send_ctl
= intel_dp
->get_aux_send_ctl(intel_dp
,
857 /* Must try at least 3 times according to DP spec */
858 for (try = 0; try < 5; try++) {
859 /* Load the send data into the aux channel data registers */
860 for (i
= 0; i
< send_bytes
; i
+= 4)
861 I915_WRITE(ch_data
+ i
,
862 intel_dp_pack_aux(send
+ i
,
865 /* Send the command and wait for it to complete */
866 I915_WRITE(ch_ctl
, send_ctl
);
868 status
= intel_dp_aux_wait_done(intel_dp
, has_aux_irq
);
870 /* Clear done status and any errors */
874 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
875 DP_AUX_CH_CTL_RECEIVE_ERROR
);
877 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
)
880 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
881 * 400us delay required for errors and timeouts
882 * Timeout errors from the HW already meet this
883 * requirement so skip to next iteration
885 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
886 usleep_range(400, 500);
889 if (status
& DP_AUX_CH_CTL_DONE
)
892 if (status
& DP_AUX_CH_CTL_DONE
)
896 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
897 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
902 /* Check for timeout or receive error.
903 * Timeouts occur when the sink is not connected
905 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
906 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
911 /* Timeouts occur when the device isn't connected, so they're
912 * "normal" -- don't fill the kernel log with these */
913 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
914 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
919 /* Unload any bytes sent back from the other side */
920 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
921 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
922 if (recv_bytes
> recv_size
)
923 recv_bytes
= recv_size
;
925 for (i
= 0; i
< recv_bytes
; i
+= 4)
926 intel_dp_unpack_aux(I915_READ(ch_data
+ i
),
927 recv
+ i
, recv_bytes
- i
);
931 pm_qos_update_request(&dev_priv
->pm_qos
, PM_QOS_DEFAULT_VALUE
);
932 intel_aux_display_runtime_put(dev_priv
);
935 edp_panel_vdd_off(intel_dp
, false);
937 pps_unlock(intel_dp
);
942 #define BARE_ADDRESS_SIZE 3
943 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
945 intel_dp_aux_transfer(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
947 struct intel_dp
*intel_dp
= container_of(aux
, struct intel_dp
, aux
);
948 uint8_t txbuf
[20], rxbuf
[20];
949 size_t txsize
, rxsize
;
952 txbuf
[0] = (msg
->request
<< 4) |
953 ((msg
->address
>> 16) & 0xf);
954 txbuf
[1] = (msg
->address
>> 8) & 0xff;
955 txbuf
[2] = msg
->address
& 0xff;
956 txbuf
[3] = msg
->size
- 1;
958 switch (msg
->request
& ~DP_AUX_I2C_MOT
) {
959 case DP_AUX_NATIVE_WRITE
:
960 case DP_AUX_I2C_WRITE
:
961 txsize
= msg
->size
? HEADER_SIZE
+ msg
->size
: BARE_ADDRESS_SIZE
;
962 rxsize
= 2; /* 0 or 1 data bytes */
964 if (WARN_ON(txsize
> 20))
967 memcpy(txbuf
+ HEADER_SIZE
, msg
->buffer
, msg
->size
);
969 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
971 msg
->reply
= rxbuf
[0] >> 4;
974 /* Number of bytes written in a short write. */
975 ret
= clamp_t(int, rxbuf
[1], 0, msg
->size
);
977 /* Return payload size. */
983 case DP_AUX_NATIVE_READ
:
984 case DP_AUX_I2C_READ
:
985 txsize
= msg
->size
? HEADER_SIZE
: BARE_ADDRESS_SIZE
;
986 rxsize
= msg
->size
+ 1;
988 if (WARN_ON(rxsize
> 20))
991 ret
= intel_dp_aux_ch(intel_dp
, txbuf
, txsize
, rxbuf
, rxsize
);
993 msg
->reply
= rxbuf
[0] >> 4;
995 * Assume happy day, and copy the data. The caller is
996 * expected to check msg->reply before touching it.
998 * Return payload size.
1001 memcpy(msg
->buffer
, rxbuf
+ 1, ret
);
1014 intel_dp_aux_init(struct intel_dp
*intel_dp
, struct intel_connector
*connector
)
1016 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1017 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1018 enum port port
= intel_dig_port
->port
;
1019 const char *name
= NULL
;
1024 intel_dp
->aux_ch_ctl_reg
= DPA_AUX_CH_CTL
;
1028 intel_dp
->aux_ch_ctl_reg
= PCH_DPB_AUX_CH_CTL
;
1032 intel_dp
->aux_ch_ctl_reg
= PCH_DPC_AUX_CH_CTL
;
1036 intel_dp
->aux_ch_ctl_reg
= PCH_DPD_AUX_CH_CTL
;
1044 * The AUX_CTL register is usually DP_CTL + 0x10.
1046 * On Haswell and Broadwell though:
1047 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1048 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1050 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1052 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
1053 intel_dp
->aux_ch_ctl_reg
= intel_dp
->output_reg
+ 0x10;
1055 intel_dp
->aux
.name
= name
;
1056 intel_dp
->aux
.dev
= dev
->dev
;
1057 intel_dp
->aux
.transfer
= intel_dp_aux_transfer
;
1059 DRM_DEBUG_KMS("registering %s bus for %s\n", name
,
1060 connector
->base
.kdev
->kobj
.name
);
1062 ret
= drm_dp_aux_register(&intel_dp
->aux
);
1064 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1069 ret
= sysfs_create_link(&connector
->base
.kdev
->kobj
,
1070 &intel_dp
->aux
.ddc
.dev
.kobj
,
1071 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1073 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name
, ret
);
1074 drm_dp_aux_unregister(&intel_dp
->aux
);
1079 intel_dp_connector_unregister(struct intel_connector
*intel_connector
)
1081 struct intel_dp
*intel_dp
= intel_attached_dp(&intel_connector
->base
);
1083 if (!intel_connector
->mst_port
)
1084 sysfs_remove_link(&intel_connector
->base
.kdev
->kobj
,
1085 intel_dp
->aux
.ddc
.dev
.kobj
.name
);
1086 intel_connector_unregister(intel_connector
);
1090 skl_edp_set_pll_config(struct intel_crtc_state
*pipe_config
, int link_clock
)
1094 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
1095 pipe_config
->dpll_hw_state
.cfgcr1
= 0;
1096 pipe_config
->dpll_hw_state
.cfgcr2
= 0;
1098 ctrl1
= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
1099 switch (link_clock
/ 2) {
1101 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810
,
1105 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350
,
1109 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700
,
1113 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620
,
1116 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1117 results in CDCLK change. Need to handle the change of CDCLK by
1118 disabling pipes and re-enabling them */
1120 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080
,
1124 ctrl1
|= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160
,
1129 pipe_config
->dpll_hw_state
.ctrl1
= ctrl1
;
1133 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state
*pipe_config
, int link_bw
)
1136 case DP_LINK_BW_1_62
:
1137 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
1139 case DP_LINK_BW_2_7
:
1140 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
1142 case DP_LINK_BW_5_4
:
1143 pipe_config
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
1149 intel_dp_sink_rates(struct intel_dp
*intel_dp
, const int **sink_rates
)
1151 if (intel_dp
->num_sink_rates
) {
1152 *sink_rates
= intel_dp
->sink_rates
;
1153 return intel_dp
->num_sink_rates
;
1156 *sink_rates
= default_rates
;
1158 return (intel_dp_max_link_bw(intel_dp
) >> 3) + 1;
1162 intel_dp_source_rates(struct drm_device
*dev
, const int **source_rates
)
1164 if (INTEL_INFO(dev
)->gen
>= 9) {
1165 *source_rates
= gen9_rates
;
1166 return ARRAY_SIZE(gen9_rates
);
1167 } else if (IS_CHERRYVIEW(dev
)) {
1168 *source_rates
= chv_rates
;
1169 return ARRAY_SIZE(chv_rates
);
1172 *source_rates
= default_rates
;
1174 if (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
)
1175 /* WaDisableHBR2:skl */
1176 return (DP_LINK_BW_2_7
>> 3) + 1;
1177 else if (INTEL_INFO(dev
)->gen
>= 8 ||
1178 (IS_HASWELL(dev
) && !IS_HSW_ULX(dev
)))
1179 return (DP_LINK_BW_5_4
>> 3) + 1;
1181 return (DP_LINK_BW_2_7
>> 3) + 1;
1185 intel_dp_set_clock(struct intel_encoder
*encoder
,
1186 struct intel_crtc_state
*pipe_config
, int link_bw
)
1188 struct drm_device
*dev
= encoder
->base
.dev
;
1189 const struct dp_link_dpll
*divisor
= NULL
;
1193 divisor
= gen4_dpll
;
1194 count
= ARRAY_SIZE(gen4_dpll
);
1195 } else if (HAS_PCH_SPLIT(dev
)) {
1197 count
= ARRAY_SIZE(pch_dpll
);
1198 } else if (IS_CHERRYVIEW(dev
)) {
1200 count
= ARRAY_SIZE(chv_dpll
);
1201 } else if (IS_VALLEYVIEW(dev
)) {
1203 count
= ARRAY_SIZE(vlv_dpll
);
1206 if (divisor
&& count
) {
1207 for (i
= 0; i
< count
; i
++) {
1208 if (link_bw
== divisor
[i
].link_bw
) {
1209 pipe_config
->dpll
= divisor
[i
].dpll
;
1210 pipe_config
->clock_set
= true;
1217 static int intersect_rates(const int *source_rates
, int source_len
,
1218 const int *sink_rates
, int sink_len
,
1221 int i
= 0, j
= 0, k
= 0;
1223 while (i
< source_len
&& j
< sink_len
) {
1224 if (source_rates
[i
] == sink_rates
[j
]) {
1225 if (WARN_ON(k
>= DP_MAX_SUPPORTED_RATES
))
1227 common_rates
[k
] = source_rates
[i
];
1231 } else if (source_rates
[i
] < sink_rates
[j
]) {
1240 static int intel_dp_common_rates(struct intel_dp
*intel_dp
,
1243 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1244 const int *source_rates
, *sink_rates
;
1245 int source_len
, sink_len
;
1247 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1248 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1250 return intersect_rates(source_rates
, source_len
,
1251 sink_rates
, sink_len
,
1255 static void snprintf_int_array(char *str
, size_t len
,
1256 const int *array
, int nelem
)
1262 for (i
= 0; i
< nelem
; i
++) {
1263 int r
= snprintf(str
, len
, "%d,", array
[i
]);
1271 static void intel_dp_print_rates(struct intel_dp
*intel_dp
)
1273 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1274 const int *source_rates
, *sink_rates
;
1275 int source_len
, sink_len
, common_len
;
1276 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1277 char str
[128]; /* FIXME: too big for stack? */
1279 if ((drm_debug
& DRM_UT_KMS
) == 0)
1282 source_len
= intel_dp_source_rates(dev
, &source_rates
);
1283 snprintf_int_array(str
, sizeof(str
), source_rates
, source_len
);
1284 DRM_DEBUG_KMS("source rates: %s\n", str
);
1286 sink_len
= intel_dp_sink_rates(intel_dp
, &sink_rates
);
1287 snprintf_int_array(str
, sizeof(str
), sink_rates
, sink_len
);
1288 DRM_DEBUG_KMS("sink rates: %s\n", str
);
1290 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1291 snprintf_int_array(str
, sizeof(str
), common_rates
, common_len
);
1292 DRM_DEBUG_KMS("common rates: %s\n", str
);
1295 static int rate_to_index(int find
, const int *rates
)
1299 for (i
= 0; i
< DP_MAX_SUPPORTED_RATES
; ++i
)
1300 if (find
== rates
[i
])
1307 intel_dp_max_link_rate(struct intel_dp
*intel_dp
)
1309 int rates
[DP_MAX_SUPPORTED_RATES
] = {};
1312 len
= intel_dp_common_rates(intel_dp
, rates
);
1313 if (WARN_ON(len
<= 0))
1316 return rates
[rate_to_index(0, rates
) - 1];
1319 int intel_dp_rate_select(struct intel_dp
*intel_dp
, int rate
)
1321 return rate_to_index(rate
, intel_dp
->sink_rates
);
1325 intel_dp_compute_config(struct intel_encoder
*encoder
,
1326 struct intel_crtc_state
*pipe_config
)
1328 struct drm_device
*dev
= encoder
->base
.dev
;
1329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1330 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
1331 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1332 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1333 struct intel_crtc
*intel_crtc
= to_intel_crtc(pipe_config
->base
.crtc
);
1334 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
1335 int lane_count
, clock
;
1336 int min_lane_count
= 1;
1337 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
1338 /* Conveniently, the link BW constants become indices with a shift...*/
1342 int link_avail
, link_clock
;
1343 int common_rates
[DP_MAX_SUPPORTED_RATES
] = {};
1346 common_len
= intel_dp_common_rates(intel_dp
, common_rates
);
1348 /* No common link rates between source and sink */
1349 WARN_ON(common_len
<= 0);
1351 max_clock
= common_len
- 1;
1353 if (HAS_PCH_SPLIT(dev
) && !HAS_DDI(dev
) && port
!= PORT_A
)
1354 pipe_config
->has_pch_encoder
= true;
1356 pipe_config
->has_dp_encoder
= true;
1357 pipe_config
->has_drrs
= false;
1358 pipe_config
->has_audio
= intel_dp
->has_audio
;
1360 if (is_edp(intel_dp
) && intel_connector
->panel
.fixed_mode
) {
1361 intel_fixed_panel_mode(intel_connector
->panel
.fixed_mode
,
1364 if (INTEL_INFO(dev
)->gen
>= 9) {
1366 ret
= skl_update_scaler_users(intel_crtc
, pipe_config
, NULL
, NULL
, 0);
1371 if (!HAS_PCH_SPLIT(dev
))
1372 intel_gmch_panel_fitting(intel_crtc
, pipe_config
,
1373 intel_connector
->panel
.fitting_mode
);
1375 intel_pch_panel_fitting(intel_crtc
, pipe_config
,
1376 intel_connector
->panel
.fitting_mode
);
1379 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
1382 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1383 "max bw %d pixel clock %iKHz\n",
1384 max_lane_count
, common_rates
[max_clock
],
1385 adjusted_mode
->crtc_clock
);
1387 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1388 * bpc in between. */
1389 bpp
= pipe_config
->pipe_bpp
;
1390 if (is_edp(intel_dp
)) {
1391 if (dev_priv
->vbt
.edp_bpp
&& dev_priv
->vbt
.edp_bpp
< bpp
) {
1392 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1393 dev_priv
->vbt
.edp_bpp
);
1394 bpp
= dev_priv
->vbt
.edp_bpp
;
1398 * Use the maximum clock and number of lanes the eDP panel
1399 * advertizes being capable of. The panels are generally
1400 * designed to support only a single clock and lane
1401 * configuration, and typically these values correspond to the
1402 * native resolution of the panel.
1404 min_lane_count
= max_lane_count
;
1405 min_clock
= max_clock
;
1408 for (; bpp
>= 6*3; bpp
-= 2*3) {
1409 mode_rate
= intel_dp_link_required(adjusted_mode
->crtc_clock
,
1412 for (clock
= min_clock
; clock
<= max_clock
; clock
++) {
1413 for (lane_count
= min_lane_count
;
1414 lane_count
<= max_lane_count
;
1417 link_clock
= common_rates
[clock
];
1418 link_avail
= intel_dp_max_data_rate(link_clock
,
1421 if (mode_rate
<= link_avail
) {
1431 if (intel_dp
->color_range_auto
) {
1434 * CEA-861-E - 5.1 Default Encoding Parameters
1435 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1437 if (bpp
!= 18 && drm_match_cea_mode(adjusted_mode
) > 1)
1438 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
1440 intel_dp
->color_range
= 0;
1443 if (intel_dp
->color_range
)
1444 pipe_config
->limited_color_range
= true;
1446 intel_dp
->lane_count
= lane_count
;
1448 if (intel_dp
->num_sink_rates
) {
1449 intel_dp
->link_bw
= 0;
1450 intel_dp
->rate_select
=
1451 intel_dp_rate_select(intel_dp
, common_rates
[clock
]);
1454 drm_dp_link_rate_to_bw_code(common_rates
[clock
]);
1455 intel_dp
->rate_select
= 0;
1458 pipe_config
->pipe_bpp
= bpp
;
1459 pipe_config
->port_clock
= common_rates
[clock
];
1461 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1462 intel_dp
->link_bw
, intel_dp
->lane_count
,
1463 pipe_config
->port_clock
, bpp
);
1464 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1465 mode_rate
, link_avail
);
1467 intel_link_compute_m_n(bpp
, lane_count
,
1468 adjusted_mode
->crtc_clock
,
1469 pipe_config
->port_clock
,
1470 &pipe_config
->dp_m_n
);
1472 if (intel_connector
->panel
.downclock_mode
!= NULL
&&
1473 dev_priv
->drrs
.type
== SEAMLESS_DRRS_SUPPORT
) {
1474 pipe_config
->has_drrs
= true;
1475 intel_link_compute_m_n(bpp
, lane_count
,
1476 intel_connector
->panel
.downclock_mode
->clock
,
1477 pipe_config
->port_clock
,
1478 &pipe_config
->dp_m2_n2
);
1481 if (IS_SKYLAKE(dev
) && is_edp(intel_dp
))
1482 skl_edp_set_pll_config(pipe_config
, common_rates
[clock
]);
1483 else if (IS_BROXTON(dev
))
1484 /* handled in ddi */;
1485 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1486 hsw_dp_set_ddi_pll_sel(pipe_config
, intel_dp
->link_bw
);
1488 intel_dp_set_clock(encoder
, pipe_config
, intel_dp
->link_bw
);
1493 static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp
)
1495 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
1496 struct intel_crtc
*crtc
= to_intel_crtc(dig_port
->base
.base
.crtc
);
1497 struct drm_device
*dev
= crtc
->base
.dev
;
1498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1501 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1502 crtc
->config
->port_clock
);
1503 dpa_ctl
= I915_READ(DP_A
);
1504 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1506 if (crtc
->config
->port_clock
== 162000) {
1507 /* For a long time we've carried around a ILK-DevA w/a for the
1508 * 160MHz clock. If we're really unlucky, it's still required.
1510 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1511 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1512 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
1514 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1515 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
1518 I915_WRITE(DP_A
, dpa_ctl
);
1524 static void intel_dp_prepare(struct intel_encoder
*encoder
)
1526 struct drm_device
*dev
= encoder
->base
.dev
;
1527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1528 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
1529 enum port port
= dp_to_dig_port(intel_dp
)->port
;
1530 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
1531 struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1534 * There are four kinds of DP registers:
1541 * IBX PCH and CPU are the same for almost everything,
1542 * except that the CPU DP PLL is configured in this
1545 * CPT PCH is quite different, having many bits moved
1546 * to the TRANS_DP_CTL register instead. That
1547 * configuration happens (oddly) in ironlake_pch_enable
1550 /* Preserve the BIOS-computed detected bit. This is
1551 * supposed to be read-only.
1553 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
) & DP_DETECTED
;
1555 /* Handle DP bits in common between all three register formats */
1556 intel_dp
->DP
|= DP_VOLTAGE_0_4
| DP_PRE_EMPHASIS_0
;
1557 intel_dp
->DP
|= DP_PORT_WIDTH(intel_dp
->lane_count
);
1559 if (crtc
->config
->has_audio
)
1560 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
1562 /* Split out the IBX/CPU vs CPT settings */
1564 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
1565 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1566 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1567 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1568 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1569 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1571 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1572 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1574 intel_dp
->DP
|= crtc
->pipe
<< 29;
1575 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
1576 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
))
1577 intel_dp
->DP
|= intel_dp
->color_range
;
1579 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1580 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
1581 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1582 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
1583 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
1585 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
1586 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
1588 if (!IS_CHERRYVIEW(dev
)) {
1589 if (crtc
->pipe
== 1)
1590 intel_dp
->DP
|= DP_PIPEB_SELECT
;
1592 intel_dp
->DP
|= DP_PIPE_SELECT_CHV(crtc
->pipe
);
1595 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
1599 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1600 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1602 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1603 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1605 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1606 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1608 static void wait_panel_status(struct intel_dp
*intel_dp
,
1612 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1614 u32 pp_stat_reg
, pp_ctrl_reg
;
1616 lockdep_assert_held(&dev_priv
->pps_mutex
);
1618 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1619 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1621 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1623 I915_READ(pp_stat_reg
),
1624 I915_READ(pp_ctrl_reg
));
1626 if (_wait_for((I915_READ(pp_stat_reg
) & mask
) == value
, 5000, 10)) {
1627 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1628 I915_READ(pp_stat_reg
),
1629 I915_READ(pp_ctrl_reg
));
1632 DRM_DEBUG_KMS("Wait complete\n");
1635 static void wait_panel_on(struct intel_dp
*intel_dp
)
1637 DRM_DEBUG_KMS("Wait for panel power on\n");
1638 wait_panel_status(intel_dp
, IDLE_ON_MASK
, IDLE_ON_VALUE
);
1641 static void wait_panel_off(struct intel_dp
*intel_dp
)
1643 DRM_DEBUG_KMS("Wait for panel power off time\n");
1644 wait_panel_status(intel_dp
, IDLE_OFF_MASK
, IDLE_OFF_VALUE
);
1647 static void wait_panel_power_cycle(struct intel_dp
*intel_dp
)
1649 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1651 /* When we disable the VDD override bit last we have to do the manual
1653 wait_remaining_ms_from_jiffies(intel_dp
->last_power_cycle
,
1654 intel_dp
->panel_power_cycle_delay
);
1656 wait_panel_status(intel_dp
, IDLE_CYCLE_MASK
, IDLE_CYCLE_VALUE
);
1659 static void wait_backlight_on(struct intel_dp
*intel_dp
)
1661 wait_remaining_ms_from_jiffies(intel_dp
->last_power_on
,
1662 intel_dp
->backlight_on_delay
);
1665 static void edp_wait_backlight_off(struct intel_dp
*intel_dp
)
1667 wait_remaining_ms_from_jiffies(intel_dp
->last_backlight_off
,
1668 intel_dp
->backlight_off_delay
);
1671 /* Read the current pp_control value, unlocking the register if it
1675 static u32
ironlake_get_pp_control(struct intel_dp
*intel_dp
)
1677 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1681 lockdep_assert_held(&dev_priv
->pps_mutex
);
1683 control
= I915_READ(_pp_ctrl_reg(intel_dp
));
1684 control
&= ~PANEL_UNLOCK_MASK
;
1685 control
|= PANEL_UNLOCK_REGS
;
1690 * Must be paired with edp_panel_vdd_off().
1691 * Must hold pps_mutex around the whole on/off sequence.
1692 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1694 static bool edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1696 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1697 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1698 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1700 enum intel_display_power_domain power_domain
;
1702 u32 pp_stat_reg
, pp_ctrl_reg
;
1703 bool need_to_disable
= !intel_dp
->want_panel_vdd
;
1705 lockdep_assert_held(&dev_priv
->pps_mutex
);
1707 if (!is_edp(intel_dp
))
1710 cancel_delayed_work(&intel_dp
->panel_vdd_work
);
1711 intel_dp
->want_panel_vdd
= true;
1713 if (edp_have_panel_vdd(intel_dp
))
1714 return need_to_disable
;
1716 power_domain
= intel_display_port_power_domain(intel_encoder
);
1717 intel_display_power_get(dev_priv
, power_domain
);
1719 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1720 port_name(intel_dig_port
->port
));
1722 if (!edp_have_panel_power(intel_dp
))
1723 wait_panel_power_cycle(intel_dp
);
1725 pp
= ironlake_get_pp_control(intel_dp
);
1726 pp
|= EDP_FORCE_VDD
;
1728 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1729 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1731 I915_WRITE(pp_ctrl_reg
, pp
);
1732 POSTING_READ(pp_ctrl_reg
);
1733 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1734 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1736 * If the panel wasn't on, delay before accessing aux channel
1738 if (!edp_have_panel_power(intel_dp
)) {
1739 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1740 port_name(intel_dig_port
->port
));
1741 msleep(intel_dp
->panel_power_up_delay
);
1744 return need_to_disable
;
1748 * Must be paired with intel_edp_panel_vdd_off() or
1749 * intel_edp_panel_off().
1750 * Nested calls to these functions are not allowed since
1751 * we drop the lock. Caller must use some higher level
1752 * locking to prevent nested calls from other threads.
1754 void intel_edp_panel_vdd_on(struct intel_dp
*intel_dp
)
1758 if (!is_edp(intel_dp
))
1762 vdd
= edp_panel_vdd_on(intel_dp
);
1763 pps_unlock(intel_dp
);
1765 I915_STATE_WARN(!vdd
, "eDP port %c VDD already requested on\n",
1766 port_name(dp_to_dig_port(intel_dp
)->port
));
1769 static void edp_panel_vdd_off_sync(struct intel_dp
*intel_dp
)
1771 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1773 struct intel_digital_port
*intel_dig_port
=
1774 dp_to_dig_port(intel_dp
);
1775 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1776 enum intel_display_power_domain power_domain
;
1778 u32 pp_stat_reg
, pp_ctrl_reg
;
1780 lockdep_assert_held(&dev_priv
->pps_mutex
);
1782 WARN_ON(intel_dp
->want_panel_vdd
);
1784 if (!edp_have_panel_vdd(intel_dp
))
1787 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1788 port_name(intel_dig_port
->port
));
1790 pp
= ironlake_get_pp_control(intel_dp
);
1791 pp
&= ~EDP_FORCE_VDD
;
1793 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1794 pp_stat_reg
= _pp_stat_reg(intel_dp
);
1796 I915_WRITE(pp_ctrl_reg
, pp
);
1797 POSTING_READ(pp_ctrl_reg
);
1799 /* Make sure sequencer is idle before allowing subsequent activity */
1800 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1801 I915_READ(pp_stat_reg
), I915_READ(pp_ctrl_reg
));
1803 if ((pp
& POWER_TARGET_ON
) == 0)
1804 intel_dp
->last_power_cycle
= jiffies
;
1806 power_domain
= intel_display_port_power_domain(intel_encoder
);
1807 intel_display_power_put(dev_priv
, power_domain
);
1810 static void edp_panel_vdd_work(struct work_struct
*__work
)
1812 struct intel_dp
*intel_dp
= container_of(to_delayed_work(__work
),
1813 struct intel_dp
, panel_vdd_work
);
1816 if (!intel_dp
->want_panel_vdd
)
1817 edp_panel_vdd_off_sync(intel_dp
);
1818 pps_unlock(intel_dp
);
1821 static void edp_panel_vdd_schedule_off(struct intel_dp
*intel_dp
)
1823 unsigned long delay
;
1826 * Queue the timer to fire a long time from now (relative to the power
1827 * down delay) to keep the panel power up across a sequence of
1830 delay
= msecs_to_jiffies(intel_dp
->panel_power_cycle_delay
* 5);
1831 schedule_delayed_work(&intel_dp
->panel_vdd_work
, delay
);
1835 * Must be paired with edp_panel_vdd_on().
1836 * Must hold pps_mutex around the whole on/off sequence.
1837 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1839 static void edp_panel_vdd_off(struct intel_dp
*intel_dp
, bool sync
)
1841 struct drm_i915_private
*dev_priv
=
1842 intel_dp_to_dev(intel_dp
)->dev_private
;
1844 lockdep_assert_held(&dev_priv
->pps_mutex
);
1846 if (!is_edp(intel_dp
))
1849 I915_STATE_WARN(!intel_dp
->want_panel_vdd
, "eDP port %c VDD not forced on",
1850 port_name(dp_to_dig_port(intel_dp
)->port
));
1852 intel_dp
->want_panel_vdd
= false;
1855 edp_panel_vdd_off_sync(intel_dp
);
1857 edp_panel_vdd_schedule_off(intel_dp
);
1860 static void edp_panel_on(struct intel_dp
*intel_dp
)
1862 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1867 lockdep_assert_held(&dev_priv
->pps_mutex
);
1869 if (!is_edp(intel_dp
))
1872 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1873 port_name(dp_to_dig_port(intel_dp
)->port
));
1875 if (WARN(edp_have_panel_power(intel_dp
),
1876 "eDP port %c panel power already on\n",
1877 port_name(dp_to_dig_port(intel_dp
)->port
)))
1880 wait_panel_power_cycle(intel_dp
);
1882 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1883 pp
= ironlake_get_pp_control(intel_dp
);
1885 /* ILK workaround: disable reset around power sequence */
1886 pp
&= ~PANEL_POWER_RESET
;
1887 I915_WRITE(pp_ctrl_reg
, pp
);
1888 POSTING_READ(pp_ctrl_reg
);
1891 pp
|= POWER_TARGET_ON
;
1893 pp
|= PANEL_POWER_RESET
;
1895 I915_WRITE(pp_ctrl_reg
, pp
);
1896 POSTING_READ(pp_ctrl_reg
);
1898 wait_panel_on(intel_dp
);
1899 intel_dp
->last_power_on
= jiffies
;
1902 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
1903 I915_WRITE(pp_ctrl_reg
, pp
);
1904 POSTING_READ(pp_ctrl_reg
);
1908 void intel_edp_panel_on(struct intel_dp
*intel_dp
)
1910 if (!is_edp(intel_dp
))
1914 edp_panel_on(intel_dp
);
1915 pps_unlock(intel_dp
);
1919 static void edp_panel_off(struct intel_dp
*intel_dp
)
1921 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1922 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
1923 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
1924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1925 enum intel_display_power_domain power_domain
;
1929 lockdep_assert_held(&dev_priv
->pps_mutex
);
1931 if (!is_edp(intel_dp
))
1934 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1935 port_name(dp_to_dig_port(intel_dp
)->port
));
1937 WARN(!intel_dp
->want_panel_vdd
, "Need eDP port %c VDD to turn off panel\n",
1938 port_name(dp_to_dig_port(intel_dp
)->port
));
1940 pp
= ironlake_get_pp_control(intel_dp
);
1941 /* We need to switch off panel power _and_ force vdd, for otherwise some
1942 * panels get very unhappy and cease to work. */
1943 pp
&= ~(POWER_TARGET_ON
| PANEL_POWER_RESET
| EDP_FORCE_VDD
|
1946 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1948 intel_dp
->want_panel_vdd
= false;
1950 I915_WRITE(pp_ctrl_reg
, pp
);
1951 POSTING_READ(pp_ctrl_reg
);
1953 intel_dp
->last_power_cycle
= jiffies
;
1954 wait_panel_off(intel_dp
);
1956 /* We got a reference when we enabled the VDD. */
1957 power_domain
= intel_display_port_power_domain(intel_encoder
);
1958 intel_display_power_put(dev_priv
, power_domain
);
1961 void intel_edp_panel_off(struct intel_dp
*intel_dp
)
1963 if (!is_edp(intel_dp
))
1967 edp_panel_off(intel_dp
);
1968 pps_unlock(intel_dp
);
1971 /* Enable backlight in the panel power control. */
1972 static void _intel_edp_backlight_on(struct intel_dp
*intel_dp
)
1974 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
1975 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
1976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1981 * If we enable the backlight right away following a panel power
1982 * on, we may see slight flicker as the panel syncs with the eDP
1983 * link. So delay a bit to make sure the image is solid before
1984 * allowing it to appear.
1986 wait_backlight_on(intel_dp
);
1990 pp
= ironlake_get_pp_control(intel_dp
);
1991 pp
|= EDP_BLC_ENABLE
;
1993 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
1995 I915_WRITE(pp_ctrl_reg
, pp
);
1996 POSTING_READ(pp_ctrl_reg
);
1998 pps_unlock(intel_dp
);
2001 /* Enable backlight PWM and backlight PP control. */
2002 void intel_edp_backlight_on(struct intel_dp
*intel_dp
)
2004 if (!is_edp(intel_dp
))
2007 DRM_DEBUG_KMS("\n");
2009 intel_panel_enable_backlight(intel_dp
->attached_connector
);
2010 _intel_edp_backlight_on(intel_dp
);
2013 /* Disable backlight in the panel power control. */
2014 static void _intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2016 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2021 if (!is_edp(intel_dp
))
2026 pp
= ironlake_get_pp_control(intel_dp
);
2027 pp
&= ~EDP_BLC_ENABLE
;
2029 pp_ctrl_reg
= _pp_ctrl_reg(intel_dp
);
2031 I915_WRITE(pp_ctrl_reg
, pp
);
2032 POSTING_READ(pp_ctrl_reg
);
2034 pps_unlock(intel_dp
);
2036 intel_dp
->last_backlight_off
= jiffies
;
2037 edp_wait_backlight_off(intel_dp
);
2040 /* Disable backlight PP control and backlight PWM. */
2041 void intel_edp_backlight_off(struct intel_dp
*intel_dp
)
2043 if (!is_edp(intel_dp
))
2046 DRM_DEBUG_KMS("\n");
2048 _intel_edp_backlight_off(intel_dp
);
2049 intel_panel_disable_backlight(intel_dp
->attached_connector
);
2053 * Hook for controlling the panel power control backlight through the bl_power
2054 * sysfs attribute. Take care to handle multiple calls.
2056 static void intel_edp_backlight_power(struct intel_connector
*connector
,
2059 struct intel_dp
*intel_dp
= intel_attached_dp(&connector
->base
);
2063 is_enabled
= ironlake_get_pp_control(intel_dp
) & EDP_BLC_ENABLE
;
2064 pps_unlock(intel_dp
);
2066 if (is_enabled
== enable
)
2069 DRM_DEBUG_KMS("panel power control backlight %s\n",
2070 enable
? "enable" : "disable");
2073 _intel_edp_backlight_on(intel_dp
);
2075 _intel_edp_backlight_off(intel_dp
);
2078 static void ironlake_edp_pll_on(struct intel_dp
*intel_dp
)
2080 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2081 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2082 struct drm_device
*dev
= crtc
->dev
;
2083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2086 assert_pipe_disabled(dev_priv
,
2087 to_intel_crtc(crtc
)->pipe
);
2089 DRM_DEBUG_KMS("\n");
2090 dpa_ctl
= I915_READ(DP_A
);
2091 WARN(dpa_ctl
& DP_PLL_ENABLE
, "dp pll on, should be off\n");
2092 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2094 /* We don't adjust intel_dp->DP while tearing down the link, to
2095 * facilitate link retraining (e.g. after hotplug). Hence clear all
2096 * enable bits here to ensure that we don't enable too much. */
2097 intel_dp
->DP
&= ~(DP_PORT_EN
| DP_AUDIO_OUTPUT_ENABLE
);
2098 intel_dp
->DP
|= DP_PLL_ENABLE
;
2099 I915_WRITE(DP_A
, intel_dp
->DP
);
2104 static void ironlake_edp_pll_off(struct intel_dp
*intel_dp
)
2106 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2107 struct drm_crtc
*crtc
= intel_dig_port
->base
.base
.crtc
;
2108 struct drm_device
*dev
= crtc
->dev
;
2109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2112 assert_pipe_disabled(dev_priv
,
2113 to_intel_crtc(crtc
)->pipe
);
2115 dpa_ctl
= I915_READ(DP_A
);
2116 WARN((dpa_ctl
& DP_PLL_ENABLE
) == 0,
2117 "dp pll off, should be on\n");
2118 WARN(dpa_ctl
& DP_PORT_EN
, "dp port still on, should be off\n");
2120 /* We can't rely on the value tracked for the DP register in
2121 * intel_dp->DP because link_down must not change that (otherwise link
2122 * re-training will fail. */
2123 dpa_ctl
&= ~DP_PLL_ENABLE
;
2124 I915_WRITE(DP_A
, dpa_ctl
);
2129 /* If the sink supports it, try to set the power state appropriately */
2130 void intel_dp_sink_dpms(struct intel_dp
*intel_dp
, int mode
)
2134 /* Should have a valid DPCD by this point */
2135 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x11)
2138 if (mode
!= DRM_MODE_DPMS_ON
) {
2139 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2143 * When turning on, we need to retry for 1ms to give the sink
2146 for (i
= 0; i
< 3; i
++) {
2147 ret
= drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_SET_POWER
,
2156 DRM_DEBUG_KMS("failed to %s sink power state\n",
2157 mode
== DRM_MODE_DPMS_ON
? "enable" : "disable");
2160 static bool intel_dp_get_hw_state(struct intel_encoder
*encoder
,
2163 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2164 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2165 struct drm_device
*dev
= encoder
->base
.dev
;
2166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2167 enum intel_display_power_domain power_domain
;
2170 power_domain
= intel_display_port_power_domain(encoder
);
2171 if (!intel_display_power_is_enabled(dev_priv
, power_domain
))
2174 tmp
= I915_READ(intel_dp
->output_reg
);
2176 if (!(tmp
& DP_PORT_EN
))
2179 if (port
== PORT_A
&& IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) {
2180 *pipe
= PORT_TO_PIPE_CPT(tmp
);
2181 } else if (IS_CHERRYVIEW(dev
)) {
2182 *pipe
= DP_PORT_TO_PIPE_CHV(tmp
);
2183 } else if (!HAS_PCH_CPT(dev
) || port
== PORT_A
) {
2184 *pipe
= PORT_TO_PIPE(tmp
);
2190 switch (intel_dp
->output_reg
) {
2192 trans_sel
= TRANS_DP_PORT_SEL_B
;
2195 trans_sel
= TRANS_DP_PORT_SEL_C
;
2198 trans_sel
= TRANS_DP_PORT_SEL_D
;
2204 for_each_pipe(dev_priv
, i
) {
2205 trans_dp
= I915_READ(TRANS_DP_CTL(i
));
2206 if ((trans_dp
& TRANS_DP_PORT_SEL_MASK
) == trans_sel
) {
2212 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2213 intel_dp
->output_reg
);
2219 static void intel_dp_get_config(struct intel_encoder
*encoder
,
2220 struct intel_crtc_state
*pipe_config
)
2222 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2224 struct drm_device
*dev
= encoder
->base
.dev
;
2225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2226 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2227 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2230 tmp
= I915_READ(intel_dp
->output_reg
);
2231 if (tmp
& DP_AUDIO_OUTPUT_ENABLE
)
2232 pipe_config
->has_audio
= true;
2234 if ((port
== PORT_A
) || !HAS_PCH_CPT(dev
)) {
2235 if (tmp
& DP_SYNC_HS_HIGH
)
2236 flags
|= DRM_MODE_FLAG_PHSYNC
;
2238 flags
|= DRM_MODE_FLAG_NHSYNC
;
2240 if (tmp
& DP_SYNC_VS_HIGH
)
2241 flags
|= DRM_MODE_FLAG_PVSYNC
;
2243 flags
|= DRM_MODE_FLAG_NVSYNC
;
2245 tmp
= I915_READ(TRANS_DP_CTL(crtc
->pipe
));
2246 if (tmp
& TRANS_DP_HSYNC_ACTIVE_HIGH
)
2247 flags
|= DRM_MODE_FLAG_PHSYNC
;
2249 flags
|= DRM_MODE_FLAG_NHSYNC
;
2251 if (tmp
& TRANS_DP_VSYNC_ACTIVE_HIGH
)
2252 flags
|= DRM_MODE_FLAG_PVSYNC
;
2254 flags
|= DRM_MODE_FLAG_NVSYNC
;
2257 pipe_config
->base
.adjusted_mode
.flags
|= flags
;
2259 if (!HAS_PCH_SPLIT(dev
) && !IS_VALLEYVIEW(dev
) &&
2260 tmp
& DP_COLOR_RANGE_16_235
)
2261 pipe_config
->limited_color_range
= true;
2263 pipe_config
->has_dp_encoder
= true;
2265 intel_dp_get_m_n(crtc
, pipe_config
);
2267 if (port
== PORT_A
) {
2268 if ((I915_READ(DP_A
) & DP_PLL_FREQ_MASK
) == DP_PLL_FREQ_160MHZ
)
2269 pipe_config
->port_clock
= 162000;
2271 pipe_config
->port_clock
= 270000;
2274 dotclock
= intel_dotclock_calculate(pipe_config
->port_clock
,
2275 &pipe_config
->dp_m_n
);
2277 if (HAS_PCH_SPLIT(dev_priv
->dev
) && port
!= PORT_A
)
2278 ironlake_check_encoder_dotclock(pipe_config
, dotclock
);
2280 pipe_config
->base
.adjusted_mode
.crtc_clock
= dotclock
;
2282 if (is_edp(intel_dp
) && dev_priv
->vbt
.edp_bpp
&&
2283 pipe_config
->pipe_bpp
> dev_priv
->vbt
.edp_bpp
) {
2285 * This is a big fat ugly hack.
2287 * Some machines in UEFI boot mode provide us a VBT that has 18
2288 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2289 * unknown we fail to light up. Yet the same BIOS boots up with
2290 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2291 * max, not what it tells us to use.
2293 * Note: This will still be broken if the eDP panel is not lit
2294 * up by the BIOS, and thus we can't get the mode at module
2297 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2298 pipe_config
->pipe_bpp
, dev_priv
->vbt
.edp_bpp
);
2299 dev_priv
->vbt
.edp_bpp
= pipe_config
->pipe_bpp
;
2303 static void intel_disable_dp(struct intel_encoder
*encoder
)
2305 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2306 struct drm_device
*dev
= encoder
->base
.dev
;
2307 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2309 if (crtc
->config
->has_audio
)
2310 intel_audio_codec_disable(encoder
);
2312 if (HAS_PSR(dev
) && !HAS_DDI(dev
))
2313 intel_psr_disable(intel_dp
);
2315 /* Make sure the panel is off before trying to change the mode. But also
2316 * ensure that we have vdd while we switch off the panel. */
2317 intel_edp_panel_vdd_on(intel_dp
);
2318 intel_edp_backlight_off(intel_dp
);
2319 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_OFF
);
2320 intel_edp_panel_off(intel_dp
);
2322 /* disable the port before the pipe on g4x */
2323 if (INTEL_INFO(dev
)->gen
< 5)
2324 intel_dp_link_down(intel_dp
);
2327 static void ilk_post_disable_dp(struct intel_encoder
*encoder
)
2329 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2330 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2332 intel_dp_link_down(intel_dp
);
2334 ironlake_edp_pll_off(intel_dp
);
2337 static void vlv_post_disable_dp(struct intel_encoder
*encoder
)
2339 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2341 intel_dp_link_down(intel_dp
);
2344 static void chv_post_disable_dp(struct intel_encoder
*encoder
)
2346 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2347 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2348 struct drm_device
*dev
= encoder
->base
.dev
;
2349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2350 struct intel_crtc
*intel_crtc
=
2351 to_intel_crtc(encoder
->base
.crtc
);
2352 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2353 enum pipe pipe
= intel_crtc
->pipe
;
2356 intel_dp_link_down(intel_dp
);
2358 mutex_lock(&dev_priv
->dpio_lock
);
2360 /* Propagate soft reset to data lane reset */
2361 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2362 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2363 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2365 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2366 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2367 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2369 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2370 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2371 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2373 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2374 val
&= ~(DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2375 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2377 mutex_unlock(&dev_priv
->dpio_lock
);
2381 _intel_dp_set_link_train(struct intel_dp
*intel_dp
,
2383 uint8_t dp_train_pat
)
2385 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2386 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
2387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2388 enum port port
= intel_dig_port
->port
;
2391 uint32_t temp
= I915_READ(DP_TP_CTL(port
));
2393 if (dp_train_pat
& DP_LINK_SCRAMBLING_DISABLE
)
2394 temp
|= DP_TP_CTL_SCRAMBLE_DISABLE
;
2396 temp
&= ~DP_TP_CTL_SCRAMBLE_DISABLE
;
2398 temp
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
2399 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2400 case DP_TRAINING_PATTERN_DISABLE
:
2401 temp
|= DP_TP_CTL_LINK_TRAIN_NORMAL
;
2404 case DP_TRAINING_PATTERN_1
:
2405 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
2407 case DP_TRAINING_PATTERN_2
:
2408 temp
|= DP_TP_CTL_LINK_TRAIN_PAT2
;
2410 case DP_TRAINING_PATTERN_3
:
2411 temp
|= DP_TP_CTL_LINK_TRAIN_PAT3
;
2414 I915_WRITE(DP_TP_CTL(port
), temp
);
2416 } else if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
2417 *DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
2419 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2420 case DP_TRAINING_PATTERN_DISABLE
:
2421 *DP
|= DP_LINK_TRAIN_OFF_CPT
;
2423 case DP_TRAINING_PATTERN_1
:
2424 *DP
|= DP_LINK_TRAIN_PAT_1_CPT
;
2426 case DP_TRAINING_PATTERN_2
:
2427 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2429 case DP_TRAINING_PATTERN_3
:
2430 DRM_ERROR("DP training pattern 3 not supported\n");
2431 *DP
|= DP_LINK_TRAIN_PAT_2_CPT
;
2436 if (IS_CHERRYVIEW(dev
))
2437 *DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
2439 *DP
&= ~DP_LINK_TRAIN_MASK
;
2441 switch (dp_train_pat
& DP_TRAINING_PATTERN_MASK
) {
2442 case DP_TRAINING_PATTERN_DISABLE
:
2443 *DP
|= DP_LINK_TRAIN_OFF
;
2445 case DP_TRAINING_PATTERN_1
:
2446 *DP
|= DP_LINK_TRAIN_PAT_1
;
2448 case DP_TRAINING_PATTERN_2
:
2449 *DP
|= DP_LINK_TRAIN_PAT_2
;
2451 case DP_TRAINING_PATTERN_3
:
2452 if (IS_CHERRYVIEW(dev
)) {
2453 *DP
|= DP_LINK_TRAIN_PAT_3_CHV
;
2455 DRM_ERROR("DP training pattern 3 not supported\n");
2456 *DP
|= DP_LINK_TRAIN_PAT_2
;
2463 static void intel_dp_enable_port(struct intel_dp
*intel_dp
)
2465 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2468 /* enable with pattern 1 (as per spec) */
2469 _intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
2470 DP_TRAINING_PATTERN_1
);
2472 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2473 POSTING_READ(intel_dp
->output_reg
);
2476 * Magic for VLV/CHV. We _must_ first set up the register
2477 * without actually enabling the port, and then do another
2478 * write to enable the port. Otherwise link training will
2479 * fail when the power sequencer is freshly used for this port.
2481 intel_dp
->DP
|= DP_PORT_EN
;
2483 I915_WRITE(intel_dp
->output_reg
, intel_dp
->DP
);
2484 POSTING_READ(intel_dp
->output_reg
);
2487 static void intel_enable_dp(struct intel_encoder
*encoder
)
2489 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2490 struct drm_device
*dev
= encoder
->base
.dev
;
2491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2492 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2493 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
2495 if (WARN_ON(dp_reg
& DP_PORT_EN
))
2500 if (IS_VALLEYVIEW(dev
))
2501 vlv_init_panel_power_sequencer(intel_dp
);
2503 intel_dp_enable_port(intel_dp
);
2505 edp_panel_vdd_on(intel_dp
);
2506 edp_panel_on(intel_dp
);
2507 edp_panel_vdd_off(intel_dp
, true);
2509 pps_unlock(intel_dp
);
2511 if (IS_VALLEYVIEW(dev
))
2512 vlv_wait_port_ready(dev_priv
, dp_to_dig_port(intel_dp
));
2514 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
2515 intel_dp_start_link_train(intel_dp
);
2516 intel_dp_complete_link_train(intel_dp
);
2517 intel_dp_stop_link_train(intel_dp
);
2519 if (crtc
->config
->has_audio
) {
2520 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2521 pipe_name(crtc
->pipe
));
2522 intel_audio_codec_enable(encoder
);
2526 static void g4x_enable_dp(struct intel_encoder
*encoder
)
2528 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2530 intel_enable_dp(encoder
);
2531 intel_edp_backlight_on(intel_dp
);
2534 static void vlv_enable_dp(struct intel_encoder
*encoder
)
2536 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2538 intel_edp_backlight_on(intel_dp
);
2539 intel_psr_enable(intel_dp
);
2542 static void g4x_pre_enable_dp(struct intel_encoder
*encoder
)
2544 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2545 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2547 intel_dp_prepare(encoder
);
2549 /* Only ilk+ has port A */
2550 if (dport
->port
== PORT_A
) {
2551 ironlake_set_pll_cpu_edp(intel_dp
);
2552 ironlake_edp_pll_on(intel_dp
);
2556 static void vlv_detach_power_sequencer(struct intel_dp
*intel_dp
)
2558 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2559 struct drm_i915_private
*dev_priv
= intel_dig_port
->base
.base
.dev
->dev_private
;
2560 enum pipe pipe
= intel_dp
->pps_pipe
;
2561 int pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
2563 edp_panel_vdd_off_sync(intel_dp
);
2566 * VLV seems to get confused when multiple power seqeuencers
2567 * have the same port selected (even if only one has power/vdd
2568 * enabled). The failure manifests as vlv_wait_port_ready() failing
2569 * CHV on the other hand doesn't seem to mind having the same port
2570 * selected in multiple power seqeuencers, but let's clear the
2571 * port select always when logically disconnecting a power sequencer
2574 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2575 pipe_name(pipe
), port_name(intel_dig_port
->port
));
2576 I915_WRITE(pp_on_reg
, 0);
2577 POSTING_READ(pp_on_reg
);
2579 intel_dp
->pps_pipe
= INVALID_PIPE
;
2582 static void vlv_steal_power_sequencer(struct drm_device
*dev
,
2585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2586 struct intel_encoder
*encoder
;
2588 lockdep_assert_held(&dev_priv
->pps_mutex
);
2590 if (WARN_ON(pipe
!= PIPE_A
&& pipe
!= PIPE_B
))
2593 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2595 struct intel_dp
*intel_dp
;
2598 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2601 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2602 port
= dp_to_dig_port(intel_dp
)->port
;
2604 if (intel_dp
->pps_pipe
!= pipe
)
2607 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2608 pipe_name(pipe
), port_name(port
));
2610 WARN(encoder
->connectors_active
,
2611 "stealing pipe %c power sequencer from active eDP port %c\n",
2612 pipe_name(pipe
), port_name(port
));
2614 /* make sure vdd is off before we steal it */
2615 vlv_detach_power_sequencer(intel_dp
);
2619 static void vlv_init_panel_power_sequencer(struct intel_dp
*intel_dp
)
2621 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
2622 struct intel_encoder
*encoder
= &intel_dig_port
->base
;
2623 struct drm_device
*dev
= encoder
->base
.dev
;
2624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2625 struct intel_crtc
*crtc
= to_intel_crtc(encoder
->base
.crtc
);
2627 lockdep_assert_held(&dev_priv
->pps_mutex
);
2629 if (!is_edp(intel_dp
))
2632 if (intel_dp
->pps_pipe
== crtc
->pipe
)
2636 * If another power sequencer was being used on this
2637 * port previously make sure to turn off vdd there while
2638 * we still have control of it.
2640 if (intel_dp
->pps_pipe
!= INVALID_PIPE
)
2641 vlv_detach_power_sequencer(intel_dp
);
2644 * We may be stealing the power
2645 * sequencer from another port.
2647 vlv_steal_power_sequencer(dev
, crtc
->pipe
);
2649 /* now it's all ours */
2650 intel_dp
->pps_pipe
= crtc
->pipe
;
2652 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2653 pipe_name(intel_dp
->pps_pipe
), port_name(intel_dig_port
->port
));
2655 /* init power sequencer on this pipe and port */
2656 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
2657 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
2660 static void vlv_pre_enable_dp(struct intel_encoder
*encoder
)
2662 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2663 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2664 struct drm_device
*dev
= encoder
->base
.dev
;
2665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2666 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
2667 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2668 int pipe
= intel_crtc
->pipe
;
2671 mutex_lock(&dev_priv
->dpio_lock
);
2673 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(port
));
2680 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW8(port
), val
);
2681 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW14(port
), 0x00760018);
2682 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW23(port
), 0x00400888);
2684 mutex_unlock(&dev_priv
->dpio_lock
);
2686 intel_enable_dp(encoder
);
2689 static void vlv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2691 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2692 struct drm_device
*dev
= encoder
->base
.dev
;
2693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2694 struct intel_crtc
*intel_crtc
=
2695 to_intel_crtc(encoder
->base
.crtc
);
2696 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2697 int pipe
= intel_crtc
->pipe
;
2699 intel_dp_prepare(encoder
);
2701 /* Program Tx lane resets to default */
2702 mutex_lock(&dev_priv
->dpio_lock
);
2703 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW0(port
),
2704 DPIO_PCS_TX_LANE2_RESET
|
2705 DPIO_PCS_TX_LANE1_RESET
);
2706 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW1(port
),
2707 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN
|
2708 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN
|
2709 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT
) |
2710 DPIO_PCS_CLK_SOFT_RESET
);
2712 /* Fix up inter-pair skew failure */
2713 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW12(port
), 0x00750f00);
2714 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW11(port
), 0x00001500);
2715 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW14(port
), 0x40400000);
2716 mutex_unlock(&dev_priv
->dpio_lock
);
2719 static void chv_pre_enable_dp(struct intel_encoder
*encoder
)
2721 struct intel_dp
*intel_dp
= enc_to_intel_dp(&encoder
->base
);
2722 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2723 struct drm_device
*dev
= encoder
->base
.dev
;
2724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2725 struct intel_crtc
*intel_crtc
=
2726 to_intel_crtc(encoder
->base
.crtc
);
2727 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2728 int pipe
= intel_crtc
->pipe
;
2732 mutex_lock(&dev_priv
->dpio_lock
);
2734 /* allow hardware to manage TX FIFO reset source */
2735 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW11(ch
));
2736 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2737 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW11(ch
), val
);
2739 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW11(ch
));
2740 val
&= ~DPIO_LANEDESKEW_STRAP_OVRD
;
2741 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW11(ch
), val
);
2743 /* Deassert soft data lane reset*/
2744 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW1(ch
));
2745 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2746 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW1(ch
), val
);
2748 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW1(ch
));
2749 val
|= CHV_PCS_REQ_SOFTRESET_EN
;
2750 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW1(ch
), val
);
2752 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW0(ch
));
2753 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2754 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW0(ch
), val
);
2756 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW0(ch
));
2757 val
|= (DPIO_PCS_TX_LANE2_RESET
| DPIO_PCS_TX_LANE1_RESET
);
2758 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW0(ch
), val
);
2760 /* Program Tx lane latency optimal setting*/
2761 for (i
= 0; i
< 4; i
++) {
2762 /* Set the upar bit */
2763 data
= (i
== 1) ? 0x0 : 0x1;
2764 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW14(ch
, i
),
2765 data
<< DPIO_UPAR_SHIFT
);
2768 /* Data lane stagger programming */
2769 /* FIXME: Fix up value only after power analysis */
2771 mutex_unlock(&dev_priv
->dpio_lock
);
2773 intel_enable_dp(encoder
);
2776 static void chv_dp_pre_pll_enable(struct intel_encoder
*encoder
)
2778 struct intel_digital_port
*dport
= enc_to_dig_port(&encoder
->base
);
2779 struct drm_device
*dev
= encoder
->base
.dev
;
2780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2781 struct intel_crtc
*intel_crtc
=
2782 to_intel_crtc(encoder
->base
.crtc
);
2783 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
2784 enum pipe pipe
= intel_crtc
->pipe
;
2787 intel_dp_prepare(encoder
);
2789 mutex_lock(&dev_priv
->dpio_lock
);
2791 /* program left/right clock distribution */
2792 if (pipe
!= PIPE_B
) {
2793 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
2794 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
2796 val
|= CHV_BUFLEFTENA1_FORCE
;
2798 val
|= CHV_BUFRIGHTENA1_FORCE
;
2799 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
2801 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
2802 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
2804 val
|= CHV_BUFLEFTENA2_FORCE
;
2806 val
|= CHV_BUFRIGHTENA2_FORCE
;
2807 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
2810 /* program clock channel usage */
2811 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW8(ch
));
2812 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2814 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2816 val
|= CHV_PCS_USEDCLKCHANNEL
;
2817 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW8(ch
), val
);
2819 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW8(ch
));
2820 val
|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE
;
2822 val
&= ~CHV_PCS_USEDCLKCHANNEL
;
2824 val
|= CHV_PCS_USEDCLKCHANNEL
;
2825 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW8(ch
), val
);
2828 * This a a bit weird since generally CL
2829 * matches the pipe, but here we need to
2830 * pick the CL based on the port.
2832 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW19(ch
));
2834 val
&= ~CHV_CMN_USEDCLKCHANNEL
;
2836 val
|= CHV_CMN_USEDCLKCHANNEL
;
2837 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW19(ch
), val
);
2839 mutex_unlock(&dev_priv
->dpio_lock
);
2843 * Native read with retry for link status and receiver capability reads for
2844 * cases where the sink may still be asleep.
2846 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2847 * supposed to retry 3 times per the spec.
2850 intel_dp_dpcd_read_wake(struct drm_dp_aux
*aux
, unsigned int offset
,
2851 void *buffer
, size_t size
)
2857 * Sometime we just get the same incorrect byte repeated
2858 * over the entire buffer. Doing just one throw away read
2859 * initially seems to "solve" it.
2861 drm_dp_dpcd_read(aux
, DP_DPCD_REV
, buffer
, 1);
2863 for (i
= 0; i
< 3; i
++) {
2864 ret
= drm_dp_dpcd_read(aux
, offset
, buffer
, size
);
2874 * Fetch AUX CH registers 0x202 - 0x207 which contain
2875 * link status information
2878 intel_dp_get_link_status(struct intel_dp
*intel_dp
, uint8_t link_status
[DP_LINK_STATUS_SIZE
])
2880 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
2883 DP_LINK_STATUS_SIZE
) == DP_LINK_STATUS_SIZE
;
2886 /* These are source-specific values. */
2888 intel_dp_voltage_max(struct intel_dp
*intel_dp
)
2890 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2892 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2894 if (IS_BROXTON(dev
))
2895 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2896 else if (INTEL_INFO(dev
)->gen
>= 9) {
2897 if (dev_priv
->vbt
.edp_low_vswing
&& port
== PORT_A
)
2898 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2899 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2900 } else if (IS_VALLEYVIEW(dev
))
2901 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2902 else if (IS_GEN7(dev
) && port
== PORT_A
)
2903 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2904 else if (HAS_PCH_CPT(dev
) && port
!= PORT_A
)
2905 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3
;
2907 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2
;
2911 intel_dp_pre_emphasis_max(struct intel_dp
*intel_dp
, uint8_t voltage_swing
)
2913 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2914 enum port port
= dp_to_dig_port(intel_dp
)->port
;
2916 if (INTEL_INFO(dev
)->gen
>= 9) {
2917 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2919 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2921 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2922 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2923 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2924 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2925 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2927 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2929 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2930 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2932 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2934 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2939 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2941 } else if (IS_VALLEYVIEW(dev
)) {
2942 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2944 return DP_TRAIN_PRE_EMPH_LEVEL_3
;
2945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2946 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2948 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2951 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2953 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
2954 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2956 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2959 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2961 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2964 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2966 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
2968 return DP_TRAIN_PRE_EMPH_LEVEL_2
;
2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
2970 return DP_TRAIN_PRE_EMPH_LEVEL_1
;
2971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
2973 return DP_TRAIN_PRE_EMPH_LEVEL_0
;
2978 static uint32_t vlv_signal_levels(struct intel_dp
*intel_dp
)
2980 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
2981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2982 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
2983 struct intel_crtc
*intel_crtc
=
2984 to_intel_crtc(dport
->base
.base
.crtc
);
2985 unsigned long demph_reg_value
, preemph_reg_value
,
2986 uniqtranscale_reg_value
;
2987 uint8_t train_set
= intel_dp
->train_set
[0];
2988 enum dpio_channel port
= vlv_dport_to_channel(dport
);
2989 int pipe
= intel_crtc
->pipe
;
2991 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
2992 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
2993 preemph_reg_value
= 0x0004000;
2994 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
2996 demph_reg_value
= 0x2B405555;
2997 uniqtranscale_reg_value
= 0x552AB83A;
2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3000 demph_reg_value
= 0x2B404040;
3001 uniqtranscale_reg_value
= 0x5548B83A;
3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3004 demph_reg_value
= 0x2B245555;
3005 uniqtranscale_reg_value
= 0x5560B83A;
3007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3008 demph_reg_value
= 0x2B405555;
3009 uniqtranscale_reg_value
= 0x5598DA3A;
3015 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3016 preemph_reg_value
= 0x0002000;
3017 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3019 demph_reg_value
= 0x2B404040;
3020 uniqtranscale_reg_value
= 0x5552B83A;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3023 demph_reg_value
= 0x2B404848;
3024 uniqtranscale_reg_value
= 0x5580B83A;
3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3027 demph_reg_value
= 0x2B404040;
3028 uniqtranscale_reg_value
= 0x55ADDA3A;
3034 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3035 preemph_reg_value
= 0x0000000;
3036 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3038 demph_reg_value
= 0x2B305555;
3039 uniqtranscale_reg_value
= 0x5570B83A;
3041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3042 demph_reg_value
= 0x2B2B4040;
3043 uniqtranscale_reg_value
= 0x55ADDA3A;
3049 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3050 preemph_reg_value
= 0x0006000;
3051 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3052 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3053 demph_reg_value
= 0x1B405555;
3054 uniqtranscale_reg_value
= 0x55ADDA3A;
3064 mutex_lock(&dev_priv
->dpio_lock
);
3065 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x00000000);
3066 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW4(port
), demph_reg_value
);
3067 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW2(port
),
3068 uniqtranscale_reg_value
);
3069 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW3(port
), 0x0C782040);
3070 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW11(port
), 0x00030000);
3071 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS_DW9(port
), preemph_reg_value
);
3072 vlv_dpio_write(dev_priv
, pipe
, VLV_TX_DW5(port
), 0x80000000);
3073 mutex_unlock(&dev_priv
->dpio_lock
);
3078 static uint32_t chv_signal_levels(struct intel_dp
*intel_dp
)
3080 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
3081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3082 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3083 struct intel_crtc
*intel_crtc
= to_intel_crtc(dport
->base
.base
.crtc
);
3084 u32 deemph_reg_value
, margin_reg_value
, val
;
3085 uint8_t train_set
= intel_dp
->train_set
[0];
3086 enum dpio_channel ch
= vlv_dport_to_channel(dport
);
3087 enum pipe pipe
= intel_crtc
->pipe
;
3090 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3091 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3092 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3094 deemph_reg_value
= 128;
3095 margin_reg_value
= 52;
3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3098 deemph_reg_value
= 128;
3099 margin_reg_value
= 77;
3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3102 deemph_reg_value
= 128;
3103 margin_reg_value
= 102;
3105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3106 deemph_reg_value
= 128;
3107 margin_reg_value
= 154;
3108 /* FIXME extra to set for 1200 */
3114 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3115 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3117 deemph_reg_value
= 85;
3118 margin_reg_value
= 78;
3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3121 deemph_reg_value
= 85;
3122 margin_reg_value
= 116;
3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3125 deemph_reg_value
= 85;
3126 margin_reg_value
= 154;
3132 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3133 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3135 deemph_reg_value
= 64;
3136 margin_reg_value
= 104;
3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3139 deemph_reg_value
= 64;
3140 margin_reg_value
= 154;
3146 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3147 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3148 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3149 deemph_reg_value
= 43;
3150 margin_reg_value
= 154;
3160 mutex_lock(&dev_priv
->dpio_lock
);
3162 /* Clear calc init */
3163 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3164 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3165 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3166 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3167 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3169 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3170 val
&= ~(DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
);
3171 val
&= ~(DPIO_PCS_TX1DEEMP_MASK
| DPIO_PCS_TX2DEEMP_MASK
);
3172 val
|= DPIO_PCS_TX1DEEMP_9P5
| DPIO_PCS_TX2DEEMP_9P5
;
3173 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3175 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW9(ch
));
3176 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3177 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3178 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW9(ch
), val
);
3180 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW9(ch
));
3181 val
&= ~(DPIO_PCS_TX1MARGIN_MASK
| DPIO_PCS_TX2MARGIN_MASK
);
3182 val
|= DPIO_PCS_TX1MARGIN_000
| DPIO_PCS_TX2MARGIN_000
;
3183 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW9(ch
), val
);
3185 /* Program swing deemph */
3186 for (i
= 0; i
< 4; i
++) {
3187 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
));
3188 val
&= ~DPIO_SWING_DEEMPH9P5_MASK
;
3189 val
|= deemph_reg_value
<< DPIO_SWING_DEEMPH9P5_SHIFT
;
3190 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW4(ch
, i
), val
);
3193 /* Program swing margin */
3194 for (i
= 0; i
< 4; i
++) {
3195 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3196 val
&= ~DPIO_SWING_MARGIN000_MASK
;
3197 val
|= margin_reg_value
<< DPIO_SWING_MARGIN000_SHIFT
;
3198 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3201 /* Disable unique transition scale */
3202 for (i
= 0; i
< 4; i
++) {
3203 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3204 val
&= ~DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3205 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3208 if (((train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
)
3209 == DP_TRAIN_PRE_EMPH_LEVEL_0
) &&
3210 ((train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
)
3211 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3
)) {
3214 * The document said it needs to set bit 27 for ch0 and bit 26
3215 * for ch1. Might be a typo in the doc.
3216 * For now, for this unique transition scale selection, set bit
3217 * 27 for ch0 and ch1.
3219 for (i
= 0; i
< 4; i
++) {
3220 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
));
3221 val
|= DPIO_TX_UNIQ_TRANS_SCALE_EN
;
3222 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW3(ch
, i
), val
);
3225 for (i
= 0; i
< 4; i
++) {
3226 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
));
3227 val
&= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3228 val
|= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT
);
3229 vlv_dpio_write(dev_priv
, pipe
, CHV_TX_DW2(ch
, i
), val
);
3233 /* Start swing calculation */
3234 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS01_DW10(ch
));
3235 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3236 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS01_DW10(ch
), val
);
3238 val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PCS23_DW10(ch
));
3239 val
|= DPIO_PCS_SWING_CALC_TX0_TX2
| DPIO_PCS_SWING_CALC_TX1_TX3
;
3240 vlv_dpio_write(dev_priv
, pipe
, VLV_PCS23_DW10(ch
), val
);
3243 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
3244 val
|= DPIO_LRC_BYPASS
;
3245 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, val
);
3247 mutex_unlock(&dev_priv
->dpio_lock
);
3253 intel_get_adjust_train(struct intel_dp
*intel_dp
,
3254 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3259 uint8_t voltage_max
;
3260 uint8_t preemph_max
;
3262 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
3263 uint8_t this_v
= drm_dp_get_adjust_request_voltage(link_status
, lane
);
3264 uint8_t this_p
= drm_dp_get_adjust_request_pre_emphasis(link_status
, lane
);
3272 voltage_max
= intel_dp_voltage_max(intel_dp
);
3273 if (v
>= voltage_max
)
3274 v
= voltage_max
| DP_TRAIN_MAX_SWING_REACHED
;
3276 preemph_max
= intel_dp_pre_emphasis_max(intel_dp
, v
);
3277 if (p
>= preemph_max
)
3278 p
= preemph_max
| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
3280 for (lane
= 0; lane
< 4; lane
++)
3281 intel_dp
->train_set
[lane
] = v
| p
;
3285 gen4_signal_levels(uint8_t train_set
)
3287 uint32_t signal_levels
= 0;
3289 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
:
3292 signal_levels
|= DP_VOLTAGE_0_4
;
3294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
:
3295 signal_levels
|= DP_VOLTAGE_0_6
;
3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
:
3298 signal_levels
|= DP_VOLTAGE_0_8
;
3300 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
:
3301 signal_levels
|= DP_VOLTAGE_1_2
;
3304 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
3305 case DP_TRAIN_PRE_EMPH_LEVEL_0
:
3307 signal_levels
|= DP_PRE_EMPHASIS_0
;
3309 case DP_TRAIN_PRE_EMPH_LEVEL_1
:
3310 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
3312 case DP_TRAIN_PRE_EMPH_LEVEL_2
:
3313 signal_levels
|= DP_PRE_EMPHASIS_6
;
3315 case DP_TRAIN_PRE_EMPH_LEVEL_3
:
3316 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
3319 return signal_levels
;
3322 /* Gen6's DP voltage swing and pre-emphasis control */
3324 gen6_edp_signal_levels(uint8_t train_set
)
3326 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3327 DP_TRAIN_PRE_EMPHASIS_MASK
);
3328 switch (signal_levels
) {
3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3331 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3333 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B
;
3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3336 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B
;
3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3338 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3339 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B
;
3340 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3342 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B
;
3344 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3345 "0x%x\n", signal_levels
);
3346 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B
;
3350 /* Gen7's DP voltage swing and pre-emphasis control */
3352 gen7_edp_signal_levels(uint8_t train_set
)
3354 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3355 DP_TRAIN_PRE_EMPHASIS_MASK
);
3356 switch (signal_levels
) {
3357 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3358 return EDP_LINK_TRAIN_400MV_0DB_IVB
;
3359 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3360 return EDP_LINK_TRAIN_400MV_3_5DB_IVB
;
3361 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3362 return EDP_LINK_TRAIN_400MV_6DB_IVB
;
3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3365 return EDP_LINK_TRAIN_600MV_0DB_IVB
;
3366 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3367 return EDP_LINK_TRAIN_600MV_3_5DB_IVB
;
3369 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3370 return EDP_LINK_TRAIN_800MV_0DB_IVB
;
3371 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3372 return EDP_LINK_TRAIN_800MV_3_5DB_IVB
;
3375 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3376 "0x%x\n", signal_levels
);
3377 return EDP_LINK_TRAIN_500MV_0DB_IVB
;
3381 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3383 hsw_signal_levels(uint8_t train_set
)
3385 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3386 DP_TRAIN_PRE_EMPHASIS_MASK
);
3387 switch (signal_levels
) {
3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3389 return DDI_BUF_TRANS_SELECT(0);
3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3391 return DDI_BUF_TRANS_SELECT(1);
3392 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3393 return DDI_BUF_TRANS_SELECT(2);
3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3395 return DDI_BUF_TRANS_SELECT(3);
3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3398 return DDI_BUF_TRANS_SELECT(4);
3399 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3400 return DDI_BUF_TRANS_SELECT(5);
3401 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3402 return DDI_BUF_TRANS_SELECT(6);
3404 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3405 return DDI_BUF_TRANS_SELECT(7);
3406 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3407 return DDI_BUF_TRANS_SELECT(8);
3409 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3410 return DDI_BUF_TRANS_SELECT(9);
3412 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3413 "0x%x\n", signal_levels
);
3414 return DDI_BUF_TRANS_SELECT(0);
3418 static void bxt_signal_levels(struct intel_dp
*intel_dp
)
3420 struct intel_digital_port
*dport
= dp_to_dig_port(intel_dp
);
3421 enum port port
= dport
->port
;
3422 struct drm_device
*dev
= dport
->base
.base
.dev
;
3423 struct intel_encoder
*encoder
= &dport
->base
;
3424 uint8_t train_set
= intel_dp
->train_set
[0];
3427 int signal_levels
= train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|
3428 DP_TRAIN_PRE_EMPHASIS_MASK
);
3429 switch (signal_levels
) {
3431 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n");
3432 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3435 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3438 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3441 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0
| DP_TRAIN_PRE_EMPH_LEVEL_3
:
3444 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3450 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1
| DP_TRAIN_PRE_EMPH_LEVEL_2
:
3453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2
| DP_TRAIN_PRE_EMPH_LEVEL_1
:
3459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3
| DP_TRAIN_PRE_EMPH_LEVEL_0
:
3464 bxt_ddi_vswing_sequence(dev
, level
, port
, encoder
->type
);
3467 /* Properly updates "DP" with the correct signal levels. */
3469 intel_dp_set_signal_levels(struct intel_dp
*intel_dp
, uint32_t *DP
)
3471 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3472 enum port port
= intel_dig_port
->port
;
3473 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3474 uint32_t signal_levels
, mask
;
3475 uint8_t train_set
= intel_dp
->train_set
[0];
3477 if (IS_BROXTON(dev
)) {
3479 bxt_signal_levels(intel_dp
);
3481 } else if (HAS_DDI(dev
)) {
3482 signal_levels
= hsw_signal_levels(train_set
);
3483 mask
= DDI_BUF_EMP_MASK
;
3484 } else if (IS_CHERRYVIEW(dev
)) {
3485 signal_levels
= chv_signal_levels(intel_dp
);
3487 } else if (IS_VALLEYVIEW(dev
)) {
3488 signal_levels
= vlv_signal_levels(intel_dp
);
3490 } else if (IS_GEN7(dev
) && port
== PORT_A
) {
3491 signal_levels
= gen7_edp_signal_levels(train_set
);
3492 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_IVB
;
3493 } else if (IS_GEN6(dev
) && port
== PORT_A
) {
3494 signal_levels
= gen6_edp_signal_levels(train_set
);
3495 mask
= EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
;
3497 signal_levels
= gen4_signal_levels(train_set
);
3498 mask
= DP_VOLTAGE_MASK
| DP_PRE_EMPHASIS_MASK
;
3502 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels
);
3504 DRM_DEBUG_KMS("Using vswing level %d\n",
3505 train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
);
3506 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3507 (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) >>
3508 DP_TRAIN_PRE_EMPHASIS_SHIFT
);
3510 *DP
= (*DP
& ~mask
) | signal_levels
;
3514 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
3516 uint8_t dp_train_pat
)
3518 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3519 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3521 uint8_t buf
[sizeof(intel_dp
->train_set
) + 1];
3524 _intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3526 I915_WRITE(intel_dp
->output_reg
, *DP
);
3527 POSTING_READ(intel_dp
->output_reg
);
3529 buf
[0] = dp_train_pat
;
3530 if ((dp_train_pat
& DP_TRAINING_PATTERN_MASK
) ==
3531 DP_TRAINING_PATTERN_DISABLE
) {
3532 /* don't write DP_TRAINING_LANEx_SET on disable */
3535 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3536 memcpy(buf
+ 1, intel_dp
->train_set
, intel_dp
->lane_count
);
3537 len
= intel_dp
->lane_count
+ 1;
3540 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_PATTERN_SET
,
3547 intel_dp_reset_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3548 uint8_t dp_train_pat
)
3550 memset(intel_dp
->train_set
, 0, sizeof(intel_dp
->train_set
));
3551 intel_dp_set_signal_levels(intel_dp
, DP
);
3552 return intel_dp_set_link_train(intel_dp
, DP
, dp_train_pat
);
3556 intel_dp_update_link_train(struct intel_dp
*intel_dp
, uint32_t *DP
,
3557 const uint8_t link_status
[DP_LINK_STATUS_SIZE
])
3559 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3560 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3564 intel_get_adjust_train(intel_dp
, link_status
);
3565 intel_dp_set_signal_levels(intel_dp
, DP
);
3567 I915_WRITE(intel_dp
->output_reg
, *DP
);
3568 POSTING_READ(intel_dp
->output_reg
);
3570 ret
= drm_dp_dpcd_write(&intel_dp
->aux
, DP_TRAINING_LANE0_SET
,
3571 intel_dp
->train_set
, intel_dp
->lane_count
);
3573 return ret
== intel_dp
->lane_count
;
3576 static void intel_dp_set_idle_link_train(struct intel_dp
*intel_dp
)
3578 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3579 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3581 enum port port
= intel_dig_port
->port
;
3587 val
= I915_READ(DP_TP_CTL(port
));
3588 val
&= ~DP_TP_CTL_LINK_TRAIN_MASK
;
3589 val
|= DP_TP_CTL_LINK_TRAIN_IDLE
;
3590 I915_WRITE(DP_TP_CTL(port
), val
);
3593 * On PORT_A we can have only eDP in SST mode. There the only reason
3594 * we need to set idle transmission mode is to work around a HW issue
3595 * where we enable the pipe while not in idle link-training mode.
3596 * In this case there is requirement to wait for a minimum number of
3597 * idle patterns to be sent.
3602 if (wait_for((I915_READ(DP_TP_STATUS(port
)) & DP_TP_STATUS_IDLE_DONE
),
3604 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3607 /* Enable corresponding port and start training pattern 1 */
3609 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
3611 struct drm_encoder
*encoder
= &dp_to_dig_port(intel_dp
)->base
.base
;
3612 struct drm_device
*dev
= encoder
->dev
;
3615 int voltage_tries
, loop_tries
;
3616 uint32_t DP
= intel_dp
->DP
;
3617 uint8_t link_config
[2];
3620 intel_ddi_prepare_link_retrain(encoder
);
3622 /* Write the link configuration data */
3623 link_config
[0] = intel_dp
->link_bw
;
3624 link_config
[1] = intel_dp
->lane_count
;
3625 if (drm_dp_enhanced_frame_cap(intel_dp
->dpcd
))
3626 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
3627 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_BW_SET
, link_config
, 2);
3628 if (intel_dp
->num_sink_rates
)
3629 drm_dp_dpcd_write(&intel_dp
->aux
, DP_LINK_RATE_SET
,
3630 &intel_dp
->rate_select
, 1);
3633 link_config
[1] = DP_SET_ANSI_8B10B
;
3634 drm_dp_dpcd_write(&intel_dp
->aux
, DP_DOWNSPREAD_CTRL
, link_config
, 2);
3638 /* clock recovery */
3639 if (!intel_dp_reset_link_train(intel_dp
, &DP
,
3640 DP_TRAINING_PATTERN_1
|
3641 DP_LINK_SCRAMBLING_DISABLE
)) {
3642 DRM_ERROR("failed to enable link training\n");
3650 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3652 drm_dp_link_train_clock_recovery_delay(intel_dp
->dpcd
);
3653 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3654 DRM_ERROR("failed to get link status\n");
3658 if (drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3659 DRM_DEBUG_KMS("clock recovery OK\n");
3663 /* Check to see if we've tried the max voltage */
3664 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
3665 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
3667 if (i
== intel_dp
->lane_count
) {
3669 if (loop_tries
== 5) {
3670 DRM_ERROR("too many full retries, give up\n");
3673 intel_dp_reset_link_train(intel_dp
, &DP
,
3674 DP_TRAINING_PATTERN_1
|
3675 DP_LINK_SCRAMBLING_DISABLE
);
3680 /* Check to see if we've tried the same voltage 5 times */
3681 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
3683 if (voltage_tries
== 5) {
3684 DRM_ERROR("too many voltage retries, give up\n");
3689 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
3691 /* Update training set as requested by target */
3692 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3693 DRM_ERROR("failed to update link training\n");
3702 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
3704 bool channel_eq
= false;
3705 int tries
, cr_tries
;
3706 uint32_t DP
= intel_dp
->DP
;
3707 uint32_t training_pattern
= DP_TRAINING_PATTERN_2
;
3709 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3710 if (intel_dp
->link_bw
== DP_LINK_BW_5_4
|| intel_dp
->use_tps3
)
3711 training_pattern
= DP_TRAINING_PATTERN_3
;
3713 /* channel equalization */
3714 if (!intel_dp_set_link_train(intel_dp
, &DP
,
3716 DP_LINK_SCRAMBLING_DISABLE
)) {
3717 DRM_ERROR("failed to start channel equalization\n");
3725 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
3728 DRM_ERROR("failed to train DP, aborting\n");
3732 drm_dp_link_train_channel_eq_delay(intel_dp
->dpcd
);
3733 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
3734 DRM_ERROR("failed to get link status\n");
3738 /* Make sure clock is still ok */
3739 if (!drm_dp_clock_recovery_ok(link_status
, intel_dp
->lane_count
)) {
3740 intel_dp_start_link_train(intel_dp
);
3741 intel_dp_set_link_train(intel_dp
, &DP
,
3743 DP_LINK_SCRAMBLING_DISABLE
);
3748 if (drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
3753 /* Try 5 times, then try clock recovery if that fails */
3755 intel_dp_start_link_train(intel_dp
);
3756 intel_dp_set_link_train(intel_dp
, &DP
,
3758 DP_LINK_SCRAMBLING_DISABLE
);
3764 /* Update training set as requested by target */
3765 if (!intel_dp_update_link_train(intel_dp
, &DP
, link_status
)) {
3766 DRM_ERROR("failed to update link training\n");
3772 intel_dp_set_idle_link_train(intel_dp
);
3777 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3781 void intel_dp_stop_link_train(struct intel_dp
*intel_dp
)
3783 intel_dp_set_link_train(intel_dp
, &intel_dp
->DP
,
3784 DP_TRAINING_PATTERN_DISABLE
);
3788 intel_dp_link_down(struct intel_dp
*intel_dp
)
3790 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3791 enum port port
= intel_dig_port
->port
;
3792 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3794 uint32_t DP
= intel_dp
->DP
;
3796 if (WARN_ON(HAS_DDI(dev
)))
3799 if (WARN_ON((I915_READ(intel_dp
->output_reg
) & DP_PORT_EN
) == 0))
3802 DRM_DEBUG_KMS("\n");
3804 if (HAS_PCH_CPT(dev
) && (IS_GEN7(dev
) || port
!= PORT_A
)) {
3805 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
3806 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
3808 if (IS_CHERRYVIEW(dev
))
3809 DP
&= ~DP_LINK_TRAIN_MASK_CHV
;
3811 DP
&= ~DP_LINK_TRAIN_MASK
;
3812 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
3814 POSTING_READ(intel_dp
->output_reg
);
3816 if (HAS_PCH_IBX(dev
) &&
3817 I915_READ(intel_dp
->output_reg
) & DP_PIPEB_SELECT
) {
3818 /* Hardware workaround: leaving our transcoder select
3819 * set to transcoder B while it's off will prevent the
3820 * corresponding HDMI output on transcoder A.
3822 * Combine this with another hardware workaround:
3823 * transcoder select bit can only be cleared while the
3826 DP
&= ~DP_PIPEB_SELECT
;
3827 I915_WRITE(intel_dp
->output_reg
, DP
);
3828 POSTING_READ(intel_dp
->output_reg
);
3831 DP
&= ~DP_AUDIO_OUTPUT_ENABLE
;
3832 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
3833 POSTING_READ(intel_dp
->output_reg
);
3834 msleep(intel_dp
->panel_power_down_delay
);
3838 intel_dp_get_dpcd(struct intel_dp
*intel_dp
)
3840 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
3841 struct drm_device
*dev
= dig_port
->base
.base
.dev
;
3842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3845 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, 0x000, intel_dp
->dpcd
,
3846 sizeof(intel_dp
->dpcd
)) < 0)
3847 return false; /* aux transfer failed */
3849 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp
->dpcd
), intel_dp
->dpcd
);
3851 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0)
3852 return false; /* DPCD not present */
3854 /* Check if the panel supports PSR */
3855 memset(intel_dp
->psr_dpcd
, 0, sizeof(intel_dp
->psr_dpcd
));
3856 if (is_edp(intel_dp
)) {
3857 intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_PSR_SUPPORT
,
3859 sizeof(intel_dp
->psr_dpcd
));
3860 if (intel_dp
->psr_dpcd
[0] & DP_PSR_IS_SUPPORTED
) {
3861 dev_priv
->psr
.sink_support
= true;
3862 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3865 if (INTEL_INFO(dev
)->gen
>= 9 &&
3866 (intel_dp
->psr_dpcd
[0] & DP_PSR2_IS_SUPPORTED
)) {
3867 uint8_t frame_sync_cap
;
3869 dev_priv
->psr
.sink_support
= true;
3870 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3871 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP
,
3872 &frame_sync_cap
, 1);
3873 dev_priv
->psr
.aux_frame_sync
= frame_sync_cap
? true : false;
3874 /* PSR2 needs frame sync as well */
3875 dev_priv
->psr
.psr2_support
= dev_priv
->psr
.aux_frame_sync
;
3876 DRM_DEBUG_KMS("PSR2 %s on sink",
3877 dev_priv
->psr
.psr2_support
? "supported" : "not supported");
3881 /* Training Pattern 3 support, both source and sink */
3882 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x12 &&
3883 intel_dp
->dpcd
[DP_MAX_LANE_COUNT
] & DP_TPS3_SUPPORTED
&&
3884 (IS_HASWELL(dev_priv
) || INTEL_INFO(dev_priv
)->gen
>= 8)) {
3885 intel_dp
->use_tps3
= true;
3886 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3888 intel_dp
->use_tps3
= false;
3890 /* Intermediate frequency support */
3891 if (is_edp(intel_dp
) &&
3892 (intel_dp
->dpcd
[DP_EDP_CONFIGURATION_CAP
] & DP_DPCD_DISPLAY_CONTROL_CAPABLE
) &&
3893 (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_EDP_DPCD_REV
, &rev
, 1) == 1) &&
3894 (rev
>= 0x03)) { /* eDp v1.4 or higher */
3895 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
3898 intel_dp_dpcd_read_wake(&intel_dp
->aux
,
3899 DP_SUPPORTED_LINK_RATES
,
3901 sizeof(sink_rates
));
3903 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
3904 int val
= le16_to_cpu(sink_rates
[i
]);
3909 intel_dp
->sink_rates
[i
] = val
* 200;
3911 intel_dp
->num_sink_rates
= i
;
3914 intel_dp_print_rates(intel_dp
);
3916 if (!(intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
3917 DP_DWN_STRM_PORT_PRESENT
))
3918 return true; /* native DP sink */
3920 if (intel_dp
->dpcd
[DP_DPCD_REV
] == 0x10)
3921 return true; /* no per-port downstream info */
3923 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_DOWNSTREAM_PORT_0
,
3924 intel_dp
->downstream_ports
,
3925 DP_MAX_DOWNSTREAM_PORTS
) < 0)
3926 return false; /* downstream port status fetch failed */
3932 intel_dp_probe_oui(struct intel_dp
*intel_dp
)
3936 if (!(intel_dp
->dpcd
[DP_DOWN_STREAM_PORT_COUNT
] & DP_OUI_SUPPORT
))
3939 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_OUI
, buf
, 3) == 3)
3940 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3941 buf
[0], buf
[1], buf
[2]);
3943 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_BRANCH_OUI
, buf
, 3) == 3)
3944 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3945 buf
[0], buf
[1], buf
[2]);
3949 intel_dp_probe_mst(struct intel_dp
*intel_dp
)
3953 if (!intel_dp
->can_mst
)
3956 if (intel_dp
->dpcd
[DP_DPCD_REV
] < 0x12)
3959 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_MSTM_CAP
, buf
, 1)) {
3960 if (buf
[0] & DP_MST_CAP
) {
3961 DRM_DEBUG_KMS("Sink is MST capable\n");
3962 intel_dp
->is_mst
= true;
3964 DRM_DEBUG_KMS("Sink is not MST capable\n");
3965 intel_dp
->is_mst
= false;
3969 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
3970 return intel_dp
->is_mst
;
3973 int intel_dp_sink_crc(struct intel_dp
*intel_dp
, u8
*crc
)
3975 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
3976 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
3977 struct intel_crtc
*intel_crtc
=
3978 to_intel_crtc(intel_dig_port
->base
.base
.crtc
);
3983 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3986 if (!(buf
& DP_TEST_CRC_SUPPORTED
))
3989 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
3992 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
3993 buf
| DP_TEST_SINK_START
) < 0)
3996 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK_MISC
, &buf
) < 0)
3998 test_crc_count
= buf
& DP_TEST_COUNT_MASK
;
4001 if (drm_dp_dpcd_readb(&intel_dp
->aux
,
4002 DP_TEST_SINK_MISC
, &buf
) < 0)
4004 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
4005 } while (--attempts
&& (buf
& DP_TEST_COUNT_MASK
) == test_crc_count
);
4007 if (attempts
== 0) {
4008 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4012 if (drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_CRC_R_CR
, crc
, 6) < 0)
4015 if (drm_dp_dpcd_readb(&intel_dp
->aux
, DP_TEST_SINK
, &buf
) < 0)
4017 if (drm_dp_dpcd_writeb(&intel_dp
->aux
, DP_TEST_SINK
,
4018 buf
& ~DP_TEST_SINK_START
) < 0)
4025 intel_dp_get_sink_irq(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4027 return intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4028 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4029 sink_irq_vector
, 1) == 1;
4033 intel_dp_get_sink_irq_esi(struct intel_dp
*intel_dp
, u8
*sink_irq_vector
)
4037 ret
= intel_dp_dpcd_read_wake(&intel_dp
->aux
,
4039 sink_irq_vector
, 14);
4046 static uint8_t intel_dp_autotest_link_training(struct intel_dp
*intel_dp
)
4048 uint8_t test_result
= DP_TEST_ACK
;
4052 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp
*intel_dp
)
4054 uint8_t test_result
= DP_TEST_NAK
;
4058 static uint8_t intel_dp_autotest_edid(struct intel_dp
*intel_dp
)
4060 uint8_t test_result
= DP_TEST_NAK
;
4064 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp
*intel_dp
)
4066 uint8_t test_result
= DP_TEST_NAK
;
4070 static void intel_dp_handle_test_request(struct intel_dp
*intel_dp
)
4072 uint8_t response
= DP_TEST_NAK
;
4076 intel_dp
->compliance_test_type
= 0;
4077 intel_dp
->aux
.i2c_nack_count
= 0;
4078 intel_dp
->aux
.i2c_defer_count
= 0;
4080 status
= drm_dp_dpcd_read(&intel_dp
->aux
, DP_TEST_REQUEST
, &rxdata
, 1);
4082 DRM_DEBUG_KMS("Could not read test request from sink\n");
4087 case DP_TEST_LINK_TRAINING
:
4088 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4089 intel_dp
->compliance_test_type
= DP_TEST_LINK_TRAINING
;
4090 response
= intel_dp_autotest_link_training(intel_dp
);
4092 case DP_TEST_LINK_VIDEO_PATTERN
:
4093 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4094 intel_dp
->compliance_test_type
= DP_TEST_LINK_VIDEO_PATTERN
;
4095 response
= intel_dp_autotest_video_pattern(intel_dp
);
4097 case DP_TEST_LINK_EDID_READ
:
4098 DRM_DEBUG_KMS("EDID test requested\n");
4099 intel_dp
->compliance_test_type
= DP_TEST_LINK_EDID_READ
;
4100 response
= intel_dp_autotest_edid(intel_dp
);
4102 case DP_TEST_LINK_PHY_TEST_PATTERN
:
4103 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4104 intel_dp
->compliance_test_type
= DP_TEST_LINK_PHY_TEST_PATTERN
;
4105 response
= intel_dp_autotest_phy_pattern(intel_dp
);
4108 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata
);
4113 status
= drm_dp_dpcd_write(&intel_dp
->aux
,
4117 DRM_DEBUG_KMS("Could not write test response to sink\n");
4121 intel_dp_check_mst_status(struct intel_dp
*intel_dp
)
4125 if (intel_dp
->is_mst
) {
4130 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4134 /* check link status - esi[10] = 0x200c */
4135 if (intel_dp
->active_mst_links
&& !drm_dp_channel_eq_ok(&esi
[10], intel_dp
->lane_count
)) {
4136 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4137 intel_dp_start_link_train(intel_dp
);
4138 intel_dp_complete_link_train(intel_dp
);
4139 intel_dp_stop_link_train(intel_dp
);
4142 DRM_DEBUG_KMS("got esi %3ph\n", esi
);
4143 ret
= drm_dp_mst_hpd_irq(&intel_dp
->mst_mgr
, esi
, &handled
);
4146 for (retry
= 0; retry
< 3; retry
++) {
4148 wret
= drm_dp_dpcd_write(&intel_dp
->aux
,
4149 DP_SINK_COUNT_ESI
+1,
4156 bret
= intel_dp_get_sink_irq_esi(intel_dp
, esi
);
4158 DRM_DEBUG_KMS("got esi2 %3ph\n", esi
);
4166 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4167 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4168 intel_dp
->is_mst
= false;
4169 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4170 /* send a hotplug event */
4171 drm_kms_helper_hotplug_event(intel_dig_port
->base
.base
.dev
);
4178 * According to DP spec
4181 * 2. Configure link according to Receiver Capabilities
4182 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4183 * 4. Check link status on receipt of hot-plug interrupt
4186 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
4188 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4189 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4191 u8 link_status
[DP_LINK_STATUS_SIZE
];
4193 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
4195 if (!intel_encoder
->connectors_active
)
4198 if (WARN_ON(!intel_encoder
->base
.crtc
))
4201 if (!to_intel_crtc(intel_encoder
->base
.crtc
)->active
)
4204 /* Try to read receiver status if the link appears to be up */
4205 if (!intel_dp_get_link_status(intel_dp
, link_status
)) {
4209 /* Now read the DPCD to see if it's actually running */
4210 if (!intel_dp_get_dpcd(intel_dp
)) {
4214 /* Try to read the source of the interrupt */
4215 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4216 intel_dp_get_sink_irq(intel_dp
, &sink_irq_vector
)) {
4217 /* Clear interrupt source */
4218 drm_dp_dpcd_writeb(&intel_dp
->aux
,
4219 DP_DEVICE_SERVICE_IRQ_VECTOR
,
4222 if (sink_irq_vector
& DP_AUTOMATED_TEST_REQUEST
)
4223 intel_dp_handle_test_request(intel_dp
);
4224 if (sink_irq_vector
& (DP_CP_IRQ
| DP_SINK_SPECIFIC_IRQ
))
4225 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4228 if (!drm_dp_channel_eq_ok(link_status
, intel_dp
->lane_count
)) {
4229 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4230 intel_encoder
->base
.name
);
4231 intel_dp_start_link_train(intel_dp
);
4232 intel_dp_complete_link_train(intel_dp
);
4233 intel_dp_stop_link_train(intel_dp
);
4237 /* XXX this is probably wrong for multiple downstream ports */
4238 static enum drm_connector_status
4239 intel_dp_detect_dpcd(struct intel_dp
*intel_dp
)
4241 uint8_t *dpcd
= intel_dp
->dpcd
;
4244 if (!intel_dp_get_dpcd(intel_dp
))
4245 return connector_status_disconnected
;
4247 /* if there's no downstream port, we're done */
4248 if (!(dpcd
[DP_DOWNSTREAMPORT_PRESENT
] & DP_DWN_STRM_PORT_PRESENT
))
4249 return connector_status_connected
;
4251 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4252 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11 &&
4253 intel_dp
->downstream_ports
[0] & DP_DS_PORT_HPD
) {
4256 if (intel_dp_dpcd_read_wake(&intel_dp
->aux
, DP_SINK_COUNT
,
4258 return connector_status_unknown
;
4260 return DP_GET_SINK_COUNT(reg
) ? connector_status_connected
4261 : connector_status_disconnected
;
4264 /* If no HPD, poke DDC gently */
4265 if (drm_probe_ddc(&intel_dp
->aux
.ddc
))
4266 return connector_status_connected
;
4268 /* Well we tried, say unknown for unreliable port types */
4269 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11) {
4270 type
= intel_dp
->downstream_ports
[0] & DP_DS_PORT_TYPE_MASK
;
4271 if (type
== DP_DS_PORT_TYPE_VGA
||
4272 type
== DP_DS_PORT_TYPE_NON_EDID
)
4273 return connector_status_unknown
;
4275 type
= intel_dp
->dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
4276 DP_DWN_STRM_PORT_TYPE_MASK
;
4277 if (type
== DP_DWN_STRM_PORT_TYPE_ANALOG
||
4278 type
== DP_DWN_STRM_PORT_TYPE_OTHER
)
4279 return connector_status_unknown
;
4282 /* Anything else is out of spec, warn and ignore */
4283 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4284 return connector_status_disconnected
;
4287 static enum drm_connector_status
4288 edp_detect(struct intel_dp
*intel_dp
)
4290 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4291 enum drm_connector_status status
;
4293 status
= intel_panel_detect(dev
);
4294 if (status
== connector_status_unknown
)
4295 status
= connector_status_connected
;
4300 static enum drm_connector_status
4301 ironlake_dp_detect(struct intel_dp
*intel_dp
)
4303 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4305 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4307 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4308 return connector_status_disconnected
;
4310 return intel_dp_detect_dpcd(intel_dp
);
4313 static int g4x_digital_port_connected(struct drm_device
*dev
,
4314 struct intel_digital_port
*intel_dig_port
)
4316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4319 if (IS_VALLEYVIEW(dev
)) {
4320 switch (intel_dig_port
->port
) {
4322 bit
= PORTB_HOTPLUG_LIVE_STATUS_VLV
;
4325 bit
= PORTC_HOTPLUG_LIVE_STATUS_VLV
;
4328 bit
= PORTD_HOTPLUG_LIVE_STATUS_VLV
;
4334 switch (intel_dig_port
->port
) {
4336 bit
= PORTB_HOTPLUG_LIVE_STATUS_G4X
;
4339 bit
= PORTC_HOTPLUG_LIVE_STATUS_G4X
;
4342 bit
= PORTD_HOTPLUG_LIVE_STATUS_G4X
;
4349 if ((I915_READ(PORT_HOTPLUG_STAT
) & bit
) == 0)
4354 static enum drm_connector_status
4355 g4x_dp_detect(struct intel_dp
*intel_dp
)
4357 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
4358 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4361 /* Can't disconnect eDP, but you can close the lid... */
4362 if (is_edp(intel_dp
)) {
4363 enum drm_connector_status status
;
4365 status
= intel_panel_detect(dev
);
4366 if (status
== connector_status_unknown
)
4367 status
= connector_status_connected
;
4371 ret
= g4x_digital_port_connected(dev
, intel_dig_port
);
4373 return connector_status_unknown
;
4375 return connector_status_disconnected
;
4377 return intel_dp_detect_dpcd(intel_dp
);
4380 static struct edid
*
4381 intel_dp_get_edid(struct intel_dp
*intel_dp
)
4383 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4385 /* use cached edid if we have one */
4386 if (intel_connector
->edid
) {
4388 if (IS_ERR(intel_connector
->edid
))
4391 return drm_edid_duplicate(intel_connector
->edid
);
4393 return drm_get_edid(&intel_connector
->base
,
4394 &intel_dp
->aux
.ddc
);
4398 intel_dp_set_edid(struct intel_dp
*intel_dp
)
4400 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4403 edid
= intel_dp_get_edid(intel_dp
);
4404 intel_connector
->detect_edid
= edid
;
4406 if (intel_dp
->force_audio
!= HDMI_AUDIO_AUTO
)
4407 intel_dp
->has_audio
= intel_dp
->force_audio
== HDMI_AUDIO_ON
;
4409 intel_dp
->has_audio
= drm_detect_monitor_audio(edid
);
4413 intel_dp_unset_edid(struct intel_dp
*intel_dp
)
4415 struct intel_connector
*intel_connector
= intel_dp
->attached_connector
;
4417 kfree(intel_connector
->detect_edid
);
4418 intel_connector
->detect_edid
= NULL
;
4420 intel_dp
->has_audio
= false;
4423 static enum intel_display_power_domain
4424 intel_dp_power_get(struct intel_dp
*dp
)
4426 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4427 enum intel_display_power_domain power_domain
;
4429 power_domain
= intel_display_port_power_domain(encoder
);
4430 intel_display_power_get(to_i915(encoder
->base
.dev
), power_domain
);
4432 return power_domain
;
4436 intel_dp_power_put(struct intel_dp
*dp
,
4437 enum intel_display_power_domain power_domain
)
4439 struct intel_encoder
*encoder
= &dp_to_dig_port(dp
)->base
;
4440 intel_display_power_put(to_i915(encoder
->base
.dev
), power_domain
);
4443 static enum drm_connector_status
4444 intel_dp_detect(struct drm_connector
*connector
, bool force
)
4446 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4447 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4448 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4449 struct drm_device
*dev
= connector
->dev
;
4450 enum drm_connector_status status
;
4451 enum intel_display_power_domain power_domain
;
4454 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4455 connector
->base
.id
, connector
->name
);
4456 intel_dp_unset_edid(intel_dp
);
4458 if (intel_dp
->is_mst
) {
4459 /* MST devices are disconnected from a monitor POV */
4460 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4461 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4462 return connector_status_disconnected
;
4465 power_domain
= intel_dp_power_get(intel_dp
);
4467 /* Can't disconnect eDP, but you can close the lid... */
4468 if (is_edp(intel_dp
))
4469 status
= edp_detect(intel_dp
);
4470 else if (HAS_PCH_SPLIT(dev
))
4471 status
= ironlake_dp_detect(intel_dp
);
4473 status
= g4x_dp_detect(intel_dp
);
4474 if (status
!= connector_status_connected
)
4477 intel_dp_probe_oui(intel_dp
);
4479 ret
= intel_dp_probe_mst(intel_dp
);
4481 /* if we are in MST mode then this connector
4482 won't appear connected or have anything with EDID on it */
4483 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4484 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4485 status
= connector_status_disconnected
;
4489 intel_dp_set_edid(intel_dp
);
4491 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4492 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4493 status
= connector_status_connected
;
4496 intel_dp_power_put(intel_dp
, power_domain
);
4501 intel_dp_force(struct drm_connector
*connector
)
4503 struct intel_dp
*intel_dp
= intel_attached_dp(connector
);
4504 struct intel_encoder
*intel_encoder
= &dp_to_dig_port(intel_dp
)->base
;
4505 enum intel_display_power_domain power_domain
;
4507 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4508 connector
->base
.id
, connector
->name
);
4509 intel_dp_unset_edid(intel_dp
);
4511 if (connector
->status
!= connector_status_connected
)
4514 power_domain
= intel_dp_power_get(intel_dp
);
4516 intel_dp_set_edid(intel_dp
);
4518 intel_dp_power_put(intel_dp
, power_domain
);
4520 if (intel_encoder
->type
!= INTEL_OUTPUT_EDP
)
4521 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
4524 static int intel_dp_get_modes(struct drm_connector
*connector
)
4526 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4529 edid
= intel_connector
->detect_edid
;
4531 int ret
= intel_connector_update_modes(connector
, edid
);
4536 /* if eDP has no EDID, fall back to fixed mode */
4537 if (is_edp(intel_attached_dp(connector
)) &&
4538 intel_connector
->panel
.fixed_mode
) {
4539 struct drm_display_mode
*mode
;
4541 mode
= drm_mode_duplicate(connector
->dev
,
4542 intel_connector
->panel
.fixed_mode
);
4544 drm_mode_probed_add(connector
, mode
);
4553 intel_dp_detect_audio(struct drm_connector
*connector
)
4555 bool has_audio
= false;
4558 edid
= to_intel_connector(connector
)->detect_edid
;
4560 has_audio
= drm_detect_monitor_audio(edid
);
4566 intel_dp_set_property(struct drm_connector
*connector
,
4567 struct drm_property
*property
,
4570 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4571 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4572 struct intel_encoder
*intel_encoder
= intel_attached_encoder(connector
);
4573 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4576 ret
= drm_object_property_set_value(&connector
->base
, property
, val
);
4580 if (property
== dev_priv
->force_audio_property
) {
4584 if (i
== intel_dp
->force_audio
)
4587 intel_dp
->force_audio
= i
;
4589 if (i
== HDMI_AUDIO_AUTO
)
4590 has_audio
= intel_dp_detect_audio(connector
);
4592 has_audio
= (i
== HDMI_AUDIO_ON
);
4594 if (has_audio
== intel_dp
->has_audio
)
4597 intel_dp
->has_audio
= has_audio
;
4601 if (property
== dev_priv
->broadcast_rgb_property
) {
4602 bool old_auto
= intel_dp
->color_range_auto
;
4603 uint32_t old_range
= intel_dp
->color_range
;
4606 case INTEL_BROADCAST_RGB_AUTO
:
4607 intel_dp
->color_range_auto
= true;
4609 case INTEL_BROADCAST_RGB_FULL
:
4610 intel_dp
->color_range_auto
= false;
4611 intel_dp
->color_range
= 0;
4613 case INTEL_BROADCAST_RGB_LIMITED
:
4614 intel_dp
->color_range_auto
= false;
4615 intel_dp
->color_range
= DP_COLOR_RANGE_16_235
;
4621 if (old_auto
== intel_dp
->color_range_auto
&&
4622 old_range
== intel_dp
->color_range
)
4628 if (is_edp(intel_dp
) &&
4629 property
== connector
->dev
->mode_config
.scaling_mode_property
) {
4630 if (val
== DRM_MODE_SCALE_NONE
) {
4631 DRM_DEBUG_KMS("no scaling not supported\n");
4635 if (intel_connector
->panel
.fitting_mode
== val
) {
4636 /* the eDP scaling property is not changed */
4639 intel_connector
->panel
.fitting_mode
= val
;
4647 if (intel_encoder
->base
.crtc
)
4648 intel_crtc_restore_mode(intel_encoder
->base
.crtc
);
4654 intel_dp_connector_destroy(struct drm_connector
*connector
)
4656 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4658 kfree(intel_connector
->detect_edid
);
4660 if (!IS_ERR_OR_NULL(intel_connector
->edid
))
4661 kfree(intel_connector
->edid
);
4663 /* Can't call is_edp() since the encoder may have been destroyed
4665 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4666 intel_panel_fini(&intel_connector
->panel
);
4668 drm_connector_cleanup(connector
);
4672 void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
4674 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
4675 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4677 drm_dp_aux_unregister(&intel_dp
->aux
);
4678 intel_dp_mst_encoder_cleanup(intel_dig_port
);
4679 if (is_edp(intel_dp
)) {
4680 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4682 * vdd might still be enabled do to the delayed vdd off.
4683 * Make sure vdd is actually turned off here.
4686 edp_panel_vdd_off_sync(intel_dp
);
4687 pps_unlock(intel_dp
);
4689 if (intel_dp
->edp_notifier
.notifier_call
) {
4690 unregister_reboot_notifier(&intel_dp
->edp_notifier
);
4691 intel_dp
->edp_notifier
.notifier_call
= NULL
;
4694 drm_encoder_cleanup(encoder
);
4695 kfree(intel_dig_port
);
4698 static void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder
)
4700 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4702 if (!is_edp(intel_dp
))
4706 * vdd might still be enabled do to the delayed vdd off.
4707 * Make sure vdd is actually turned off here.
4709 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
4711 edp_panel_vdd_off_sync(intel_dp
);
4712 pps_unlock(intel_dp
);
4715 static void intel_edp_panel_vdd_sanitize(struct intel_dp
*intel_dp
)
4717 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
4718 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4720 enum intel_display_power_domain power_domain
;
4722 lockdep_assert_held(&dev_priv
->pps_mutex
);
4724 if (!edp_have_panel_vdd(intel_dp
))
4728 * The VDD bit needs a power domain reference, so if the bit is
4729 * already enabled when we boot or resume, grab this reference and
4730 * schedule a vdd off, so we don't hold on to the reference
4733 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4734 power_domain
= intel_display_port_power_domain(&intel_dig_port
->base
);
4735 intel_display_power_get(dev_priv
, power_domain
);
4737 edp_panel_vdd_schedule_off(intel_dp
);
4740 static void intel_dp_encoder_reset(struct drm_encoder
*encoder
)
4742 struct intel_dp
*intel_dp
;
4744 if (to_intel_encoder(encoder
)->type
!= INTEL_OUTPUT_EDP
)
4747 intel_dp
= enc_to_intel_dp(encoder
);
4752 * Read out the current power sequencer assignment,
4753 * in case the BIOS did something with it.
4755 if (IS_VALLEYVIEW(encoder
->dev
))
4756 vlv_initial_power_sequencer_setup(intel_dp
);
4758 intel_edp_panel_vdd_sanitize(intel_dp
);
4760 pps_unlock(intel_dp
);
4763 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
4764 .dpms
= intel_connector_dpms
,
4765 .detect
= intel_dp_detect
,
4766 .force
= intel_dp_force
,
4767 .fill_modes
= drm_helper_probe_single_connector_modes
,
4768 .set_property
= intel_dp_set_property
,
4769 .atomic_get_property
= intel_connector_atomic_get_property
,
4770 .destroy
= intel_dp_connector_destroy
,
4771 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
4772 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
4775 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
4776 .get_modes
= intel_dp_get_modes
,
4777 .mode_valid
= intel_dp_mode_valid
,
4778 .best_encoder
= intel_best_encoder
,
4781 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
4782 .reset
= intel_dp_encoder_reset
,
4783 .destroy
= intel_dp_encoder_destroy
,
4787 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
4793 intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port
, bool long_hpd
)
4795 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
4796 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
4797 struct drm_device
*dev
= intel_dig_port
->base
.base
.dev
;
4798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4799 enum intel_display_power_domain power_domain
;
4800 enum irqreturn ret
= IRQ_NONE
;
4802 if (intel_dig_port
->base
.type
!= INTEL_OUTPUT_EDP
)
4803 intel_dig_port
->base
.type
= INTEL_OUTPUT_DISPLAYPORT
;
4805 if (long_hpd
&& intel_dig_port
->base
.type
== INTEL_OUTPUT_EDP
) {
4807 * vdd off can generate a long pulse on eDP which
4808 * would require vdd on to handle it, and thus we
4809 * would end up in an endless cycle of
4810 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4812 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4813 port_name(intel_dig_port
->port
));
4817 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4818 port_name(intel_dig_port
->port
),
4819 long_hpd
? "long" : "short");
4821 power_domain
= intel_display_port_power_domain(intel_encoder
);
4822 intel_display_power_get(dev_priv
, power_domain
);
4826 if (HAS_PCH_SPLIT(dev
)) {
4827 if (!ibx_digital_port_connected(dev_priv
, intel_dig_port
))
4830 if (g4x_digital_port_connected(dev
, intel_dig_port
) != 1)
4834 if (!intel_dp_get_dpcd(intel_dp
)) {
4838 intel_dp_probe_oui(intel_dp
);
4840 if (!intel_dp_probe_mst(intel_dp
))
4844 if (intel_dp
->is_mst
) {
4845 if (intel_dp_check_mst_status(intel_dp
) == -EINVAL
)
4849 if (!intel_dp
->is_mst
) {
4851 * we'll check the link status via the normal hot plug path later -
4852 * but for short hpds we should check it now
4854 drm_modeset_lock(&dev
->mode_config
.connection_mutex
, NULL
);
4855 intel_dp_check_link_status(intel_dp
);
4856 drm_modeset_unlock(&dev
->mode_config
.connection_mutex
);
4864 /* if we were in MST mode, and device is not there get out of MST mode */
4865 if (intel_dp
->is_mst
) {
4866 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp
->is_mst
, intel_dp
->mst_mgr
.mst_state
);
4867 intel_dp
->is_mst
= false;
4868 drm_dp_mst_topology_mgr_set_mst(&intel_dp
->mst_mgr
, intel_dp
->is_mst
);
4871 intel_display_power_put(dev_priv
, power_domain
);
4876 /* Return which DP Port should be selected for Transcoder DP control */
4878 intel_trans_dp_port_sel(struct drm_crtc
*crtc
)
4880 struct drm_device
*dev
= crtc
->dev
;
4881 struct intel_encoder
*intel_encoder
;
4882 struct intel_dp
*intel_dp
;
4884 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4885 intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
4887 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
4888 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
4889 return intel_dp
->output_reg
;
4895 /* check the VBT to see whether the eDP is on DP-D port */
4896 bool intel_dp_is_edp(struct drm_device
*dev
, enum port port
)
4898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4899 union child_device_config
*p_child
;
4901 static const short port_mapping
[] = {
4902 [PORT_B
] = PORT_IDPB
,
4903 [PORT_C
] = PORT_IDPC
,
4904 [PORT_D
] = PORT_IDPD
,
4910 if (!dev_priv
->vbt
.child_dev_num
)
4913 for (i
= 0; i
< dev_priv
->vbt
.child_dev_num
; i
++) {
4914 p_child
= dev_priv
->vbt
.child_dev
+ i
;
4916 if (p_child
->common
.dvo_port
== port_mapping
[port
] &&
4917 (p_child
->common
.device_type
& DEVICE_TYPE_eDP_BITS
) ==
4918 (DEVICE_TYPE_eDP
& DEVICE_TYPE_eDP_BITS
))
4925 intel_dp_add_properties(struct intel_dp
*intel_dp
, struct drm_connector
*connector
)
4927 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
4929 intel_attach_force_audio_property(connector
);
4930 intel_attach_broadcast_rgb_property(connector
);
4931 intel_dp
->color_range_auto
= true;
4933 if (is_edp(intel_dp
)) {
4934 drm_mode_create_scaling_mode_property(connector
->dev
);
4935 drm_object_attach_property(
4937 connector
->dev
->mode_config
.scaling_mode_property
,
4938 DRM_MODE_SCALE_ASPECT
);
4939 intel_connector
->panel
.fitting_mode
= DRM_MODE_SCALE_ASPECT
;
4943 static void intel_dp_init_panel_power_timestamps(struct intel_dp
*intel_dp
)
4945 intel_dp
->last_power_cycle
= jiffies
;
4946 intel_dp
->last_power_on
= jiffies
;
4947 intel_dp
->last_backlight_off
= jiffies
;
4951 intel_dp_init_panel_power_sequencer(struct drm_device
*dev
,
4952 struct intel_dp
*intel_dp
)
4954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4955 struct edp_power_seq cur
, vbt
, spec
,
4956 *final
= &intel_dp
->pps_delays
;
4957 u32 pp_on
, pp_off
, pp_div
, pp
;
4958 int pp_ctrl_reg
, pp_on_reg
, pp_off_reg
, pp_div_reg
;
4960 lockdep_assert_held(&dev_priv
->pps_mutex
);
4962 /* already initialized? */
4963 if (final
->t11_t12
!= 0)
4966 if (HAS_PCH_SPLIT(dev
)) {
4967 pp_ctrl_reg
= PCH_PP_CONTROL
;
4968 pp_on_reg
= PCH_PP_ON_DELAYS
;
4969 pp_off_reg
= PCH_PP_OFF_DELAYS
;
4970 pp_div_reg
= PCH_PP_DIVISOR
;
4972 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
4974 pp_ctrl_reg
= VLV_PIPE_PP_CONTROL(pipe
);
4975 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
4976 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
4977 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
4980 /* Workaround: Need to write PP_CONTROL with the unlock key as
4981 * the very first thing. */
4982 pp
= ironlake_get_pp_control(intel_dp
);
4983 I915_WRITE(pp_ctrl_reg
, pp
);
4985 pp_on
= I915_READ(pp_on_reg
);
4986 pp_off
= I915_READ(pp_off_reg
);
4987 pp_div
= I915_READ(pp_div_reg
);
4989 /* Pull timing values out of registers */
4990 cur
.t1_t3
= (pp_on
& PANEL_POWER_UP_DELAY_MASK
) >>
4991 PANEL_POWER_UP_DELAY_SHIFT
;
4993 cur
.t8
= (pp_on
& PANEL_LIGHT_ON_DELAY_MASK
) >>
4994 PANEL_LIGHT_ON_DELAY_SHIFT
;
4996 cur
.t9
= (pp_off
& PANEL_LIGHT_OFF_DELAY_MASK
) >>
4997 PANEL_LIGHT_OFF_DELAY_SHIFT
;
4999 cur
.t10
= (pp_off
& PANEL_POWER_DOWN_DELAY_MASK
) >>
5000 PANEL_POWER_DOWN_DELAY_SHIFT
;
5002 cur
.t11_t12
= ((pp_div
& PANEL_POWER_CYCLE_DELAY_MASK
) >>
5003 PANEL_POWER_CYCLE_DELAY_SHIFT
) * 1000;
5005 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5006 cur
.t1_t3
, cur
.t8
, cur
.t9
, cur
.t10
, cur
.t11_t12
);
5008 vbt
= dev_priv
->vbt
.edp_pps
;
5010 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5011 * our hw here, which are all in 100usec. */
5012 spec
.t1_t3
= 210 * 10;
5013 spec
.t8
= 50 * 10; /* no limit for t8, use t7 instead */
5014 spec
.t9
= 50 * 10; /* no limit for t9, make it symmetric with t8 */
5015 spec
.t10
= 500 * 10;
5016 /* This one is special and actually in units of 100ms, but zero
5017 * based in the hw (so we need to add 100 ms). But the sw vbt
5018 * table multiplies it with 1000 to make it in units of 100usec,
5020 spec
.t11_t12
= (510 + 100) * 10;
5022 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5023 vbt
.t1_t3
, vbt
.t8
, vbt
.t9
, vbt
.t10
, vbt
.t11_t12
);
5025 /* Use the max of the register settings and vbt. If both are
5026 * unset, fall back to the spec limits. */
5027 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5029 max(cur.field, vbt.field))
5030 assign_final(t1_t3
);
5034 assign_final(t11_t12
);
5037 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5038 intel_dp
->panel_power_up_delay
= get_delay(t1_t3
);
5039 intel_dp
->backlight_on_delay
= get_delay(t8
);
5040 intel_dp
->backlight_off_delay
= get_delay(t9
);
5041 intel_dp
->panel_power_down_delay
= get_delay(t10
);
5042 intel_dp
->panel_power_cycle_delay
= get_delay(t11_t12
);
5045 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5046 intel_dp
->panel_power_up_delay
, intel_dp
->panel_power_down_delay
,
5047 intel_dp
->panel_power_cycle_delay
);
5049 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5050 intel_dp
->backlight_on_delay
, intel_dp
->backlight_off_delay
);
5054 intel_dp_init_panel_power_sequencer_registers(struct drm_device
*dev
,
5055 struct intel_dp
*intel_dp
)
5057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5058 u32 pp_on
, pp_off
, pp_div
, port_sel
= 0;
5059 int div
= HAS_PCH_SPLIT(dev
) ? intel_pch_rawclk(dev
) : intel_hrawclk(dev
);
5060 int pp_on_reg
, pp_off_reg
, pp_div_reg
;
5061 enum port port
= dp_to_dig_port(intel_dp
)->port
;
5062 const struct edp_power_seq
*seq
= &intel_dp
->pps_delays
;
5064 lockdep_assert_held(&dev_priv
->pps_mutex
);
5066 if (HAS_PCH_SPLIT(dev
)) {
5067 pp_on_reg
= PCH_PP_ON_DELAYS
;
5068 pp_off_reg
= PCH_PP_OFF_DELAYS
;
5069 pp_div_reg
= PCH_PP_DIVISOR
;
5071 enum pipe pipe
= vlv_power_sequencer_pipe(intel_dp
);
5073 pp_on_reg
= VLV_PIPE_PP_ON_DELAYS(pipe
);
5074 pp_off_reg
= VLV_PIPE_PP_OFF_DELAYS(pipe
);
5075 pp_div_reg
= VLV_PIPE_PP_DIVISOR(pipe
);
5079 * And finally store the new values in the power sequencer. The
5080 * backlight delays are set to 1 because we do manual waits on them. For
5081 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5082 * we'll end up waiting for the backlight off delay twice: once when we
5083 * do the manual sleep, and once when we disable the panel and wait for
5084 * the PP_STATUS bit to become zero.
5086 pp_on
= (seq
->t1_t3
<< PANEL_POWER_UP_DELAY_SHIFT
) |
5087 (1 << PANEL_LIGHT_ON_DELAY_SHIFT
);
5088 pp_off
= (1 << PANEL_LIGHT_OFF_DELAY_SHIFT
) |
5089 (seq
->t10
<< PANEL_POWER_DOWN_DELAY_SHIFT
);
5090 /* Compute the divisor for the pp clock, simply match the Bspec
5092 pp_div
= ((100 * div
)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT
;
5093 pp_div
|= (DIV_ROUND_UP(seq
->t11_t12
, 1000)
5094 << PANEL_POWER_CYCLE_DELAY_SHIFT
);
5096 /* Haswell doesn't have any port selection bits for the panel
5097 * power sequencer any more. */
5098 if (IS_VALLEYVIEW(dev
)) {
5099 port_sel
= PANEL_PORT_SELECT_VLV(port
);
5100 } else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5102 port_sel
= PANEL_PORT_SELECT_DPA
;
5104 port_sel
= PANEL_PORT_SELECT_DPD
;
5109 I915_WRITE(pp_on_reg
, pp_on
);
5110 I915_WRITE(pp_off_reg
, pp_off
);
5111 I915_WRITE(pp_div_reg
, pp_div
);
5113 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5114 I915_READ(pp_on_reg
),
5115 I915_READ(pp_off_reg
),
5116 I915_READ(pp_div_reg
));
5120 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5122 * @refresh_rate: RR to be programmed
5124 * This function gets called when refresh rate (RR) has to be changed from
5125 * one frequency to another. Switches can be between high and low RR
5126 * supported by the panel or to any other RR based on media playback (in
5127 * this case, RR value needs to be passed from user space).
5129 * The caller of this function needs to take a lock on dev_priv->drrs.
5131 static void intel_dp_set_drrs_state(struct drm_device
*dev
, int refresh_rate
)
5133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5134 struct intel_encoder
*encoder
;
5135 struct intel_digital_port
*dig_port
= NULL
;
5136 struct intel_dp
*intel_dp
= dev_priv
->drrs
.dp
;
5137 struct intel_crtc_state
*config
= NULL
;
5138 struct intel_crtc
*intel_crtc
= NULL
;
5140 enum drrs_refresh_rate_type index
= DRRS_HIGH_RR
;
5142 if (refresh_rate
<= 0) {
5143 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5147 if (intel_dp
== NULL
) {
5148 DRM_DEBUG_KMS("DRRS not supported.\n");
5153 * FIXME: This needs proper synchronization with psr state for some
5154 * platforms that cannot have PSR and DRRS enabled at the same time.
5157 dig_port
= dp_to_dig_port(intel_dp
);
5158 encoder
= &dig_port
->base
;
5159 intel_crtc
= to_intel_crtc(encoder
->base
.crtc
);
5162 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5166 config
= intel_crtc
->config
;
5168 if (dev_priv
->drrs
.type
< SEAMLESS_DRRS_SUPPORT
) {
5169 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5173 if (intel_dp
->attached_connector
->panel
.downclock_mode
->vrefresh
==
5175 index
= DRRS_LOW_RR
;
5177 if (index
== dev_priv
->drrs
.refresh_rate_type
) {
5179 "DRRS requested for previously set RR...ignoring\n");
5183 if (!intel_crtc
->active
) {
5184 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5188 if (INTEL_INFO(dev
)->gen
>= 8 && !IS_CHERRYVIEW(dev
)) {
5191 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5194 intel_dp_set_m_n(intel_crtc
, M2_N2
);
5198 DRM_ERROR("Unsupported refreshrate type\n");
5200 } else if (INTEL_INFO(dev
)->gen
> 6) {
5201 reg
= PIPECONF(intel_crtc
->config
->cpu_transcoder
);
5202 val
= I915_READ(reg
);
5204 if (index
> DRRS_HIGH_RR
) {
5205 if (IS_VALLEYVIEW(dev
))
5206 val
|= PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5208 val
|= PIPECONF_EDP_RR_MODE_SWITCH
;
5210 if (IS_VALLEYVIEW(dev
))
5211 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV
;
5213 val
&= ~PIPECONF_EDP_RR_MODE_SWITCH
;
5215 I915_WRITE(reg
, val
);
5218 dev_priv
->drrs
.refresh_rate_type
= index
;
5220 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate
);
5224 * intel_edp_drrs_enable - init drrs struct if supported
5225 * @intel_dp: DP struct
5227 * Initializes frontbuffer_bits and drrs.dp
5229 void intel_edp_drrs_enable(struct intel_dp
*intel_dp
)
5231 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5233 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5234 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5235 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5237 if (!intel_crtc
->config
->has_drrs
) {
5238 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5242 mutex_lock(&dev_priv
->drrs
.mutex
);
5243 if (WARN_ON(dev_priv
->drrs
.dp
)) {
5244 DRM_ERROR("DRRS already enabled\n");
5248 dev_priv
->drrs
.busy_frontbuffer_bits
= 0;
5250 dev_priv
->drrs
.dp
= intel_dp
;
5253 mutex_unlock(&dev_priv
->drrs
.mutex
);
5257 * intel_edp_drrs_disable - Disable DRRS
5258 * @intel_dp: DP struct
5261 void intel_edp_drrs_disable(struct intel_dp
*intel_dp
)
5263 struct drm_device
*dev
= intel_dp_to_dev(intel_dp
);
5264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5265 struct intel_digital_port
*dig_port
= dp_to_dig_port(intel_dp
);
5266 struct drm_crtc
*crtc
= dig_port
->base
.base
.crtc
;
5267 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5269 if (!intel_crtc
->config
->has_drrs
)
5272 mutex_lock(&dev_priv
->drrs
.mutex
);
5273 if (!dev_priv
->drrs
.dp
) {
5274 mutex_unlock(&dev_priv
->drrs
.mutex
);
5278 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
)
5279 intel_dp_set_drrs_state(dev_priv
->dev
,
5280 intel_dp
->attached_connector
->panel
.
5281 fixed_mode
->vrefresh
);
5283 dev_priv
->drrs
.dp
= NULL
;
5284 mutex_unlock(&dev_priv
->drrs
.mutex
);
5286 cancel_delayed_work_sync(&dev_priv
->drrs
.work
);
5289 static void intel_edp_drrs_downclock_work(struct work_struct
*work
)
5291 struct drm_i915_private
*dev_priv
=
5292 container_of(work
, typeof(*dev_priv
), drrs
.work
.work
);
5293 struct intel_dp
*intel_dp
;
5295 mutex_lock(&dev_priv
->drrs
.mutex
);
5297 intel_dp
= dev_priv
->drrs
.dp
;
5303 * The delayed work can race with an invalidate hence we need to
5307 if (dev_priv
->drrs
.busy_frontbuffer_bits
)
5310 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
)
5311 intel_dp_set_drrs_state(dev_priv
->dev
,
5312 intel_dp
->attached_connector
->panel
.
5313 downclock_mode
->vrefresh
);
5316 mutex_unlock(&dev_priv
->drrs
.mutex
);
5320 * intel_edp_drrs_invalidate - Invalidate DRRS
5322 * @frontbuffer_bits: frontbuffer plane tracking bits
5324 * When there is a disturbance on screen (due to cursor movement/time
5325 * update etc), DRRS needs to be invalidated, i.e. need to switch to
5328 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5330 void intel_edp_drrs_invalidate(struct drm_device
*dev
,
5331 unsigned frontbuffer_bits
)
5333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5334 struct drm_crtc
*crtc
;
5337 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5340 cancel_delayed_work(&dev_priv
->drrs
.work
);
5342 mutex_lock(&dev_priv
->drrs
.mutex
);
5343 if (!dev_priv
->drrs
.dp
) {
5344 mutex_unlock(&dev_priv
->drrs
.mutex
);
5348 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5349 pipe
= to_intel_crtc(crtc
)->pipe
;
5351 if (dev_priv
->drrs
.refresh_rate_type
== DRRS_LOW_RR
) {
5352 intel_dp_set_drrs_state(dev_priv
->dev
,
5353 dev_priv
->drrs
.dp
->attached_connector
->panel
.
5354 fixed_mode
->vrefresh
);
5357 frontbuffer_bits
&= INTEL_FRONTBUFFER_ALL_MASK(pipe
);
5359 dev_priv
->drrs
.busy_frontbuffer_bits
|= frontbuffer_bits
;
5360 mutex_unlock(&dev_priv
->drrs
.mutex
);
5364 * intel_edp_drrs_flush - Flush DRRS
5366 * @frontbuffer_bits: frontbuffer plane tracking bits
5368 * When there is no movement on screen, DRRS work can be scheduled.
5369 * This DRRS work is responsible for setting relevant registers after a
5370 * timeout of 1 second.
5372 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5374 void intel_edp_drrs_flush(struct drm_device
*dev
,
5375 unsigned frontbuffer_bits
)
5377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5378 struct drm_crtc
*crtc
;
5381 if (dev_priv
->drrs
.type
== DRRS_NOT_SUPPORTED
)
5384 cancel_delayed_work(&dev_priv
->drrs
.work
);
5386 mutex_lock(&dev_priv
->drrs
.mutex
);
5387 if (!dev_priv
->drrs
.dp
) {
5388 mutex_unlock(&dev_priv
->drrs
.mutex
);
5392 crtc
= dp_to_dig_port(dev_priv
->drrs
.dp
)->base
.base
.crtc
;
5393 pipe
= to_intel_crtc(crtc
)->pipe
;
5394 dev_priv
->drrs
.busy_frontbuffer_bits
&= ~frontbuffer_bits
;
5396 if (dev_priv
->drrs
.refresh_rate_type
!= DRRS_LOW_RR
&&
5397 !dev_priv
->drrs
.busy_frontbuffer_bits
)
5398 schedule_delayed_work(&dev_priv
->drrs
.work
,
5399 msecs_to_jiffies(1000));
5400 mutex_unlock(&dev_priv
->drrs
.mutex
);
5404 * DOC: Display Refresh Rate Switching (DRRS)
5406 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5407 * which enables swtching between low and high refresh rates,
5408 * dynamically, based on the usage scenario. This feature is applicable
5409 * for internal panels.
5411 * Indication that the panel supports DRRS is given by the panel EDID, which
5412 * would list multiple refresh rates for one resolution.
5414 * DRRS is of 2 types - static and seamless.
5415 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5416 * (may appear as a blink on screen) and is used in dock-undock scenario.
5417 * Seamless DRRS involves changing RR without any visual effect to the user
5418 * and can be used during normal system usage. This is done by programming
5419 * certain registers.
5421 * Support for static/seamless DRRS may be indicated in the VBT based on
5422 * inputs from the panel spec.
5424 * DRRS saves power by switching to low RR based on usage scenarios.
5427 * The implementation is based on frontbuffer tracking implementation.
5428 * When there is a disturbance on the screen triggered by user activity or a
5429 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5430 * When there is no movement on screen, after a timeout of 1 second, a switch
5431 * to low RR is made.
5432 * For integration with frontbuffer tracking code,
5433 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5435 * DRRS can be further extended to support other internal panels and also
5436 * the scenario of video playback wherein RR is set based on the rate
5437 * requested by userspace.
5441 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5442 * @intel_connector: eDP connector
5443 * @fixed_mode: preferred mode of panel
5445 * This function is called only once at driver load to initialize basic
5449 * Downclock mode if panel supports it, else return NULL.
5450 * DRRS support is determined by the presence of downclock mode (apart
5451 * from VBT setting).
5453 static struct drm_display_mode
*
5454 intel_dp_drrs_init(struct intel_connector
*intel_connector
,
5455 struct drm_display_mode
*fixed_mode
)
5457 struct drm_connector
*connector
= &intel_connector
->base
;
5458 struct drm_device
*dev
= connector
->dev
;
5459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5460 struct drm_display_mode
*downclock_mode
= NULL
;
5462 INIT_DELAYED_WORK(&dev_priv
->drrs
.work
, intel_edp_drrs_downclock_work
);
5463 mutex_init(&dev_priv
->drrs
.mutex
);
5465 if (INTEL_INFO(dev
)->gen
<= 6) {
5466 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5470 if (dev_priv
->vbt
.drrs_type
!= SEAMLESS_DRRS_SUPPORT
) {
5471 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5475 downclock_mode
= intel_find_panel_downclock
5476 (dev
, fixed_mode
, connector
);
5478 if (!downclock_mode
) {
5479 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5483 dev_priv
->drrs
.type
= dev_priv
->vbt
.drrs_type
;
5485 dev_priv
->drrs
.refresh_rate_type
= DRRS_HIGH_RR
;
5486 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5487 return downclock_mode
;
5490 static bool intel_edp_init_connector(struct intel_dp
*intel_dp
,
5491 struct intel_connector
*intel_connector
)
5493 struct drm_connector
*connector
= &intel_connector
->base
;
5494 struct intel_digital_port
*intel_dig_port
= dp_to_dig_port(intel_dp
);
5495 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5496 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5498 struct drm_display_mode
*fixed_mode
= NULL
;
5499 struct drm_display_mode
*downclock_mode
= NULL
;
5501 struct drm_display_mode
*scan
;
5503 enum pipe pipe
= INVALID_PIPE
;
5505 if (!is_edp(intel_dp
))
5509 intel_edp_panel_vdd_sanitize(intel_dp
);
5510 pps_unlock(intel_dp
);
5512 /* Cache DPCD and EDID for edp. */
5513 has_dpcd
= intel_dp_get_dpcd(intel_dp
);
5516 if (intel_dp
->dpcd
[DP_DPCD_REV
] >= 0x11)
5517 dev_priv
->no_aux_handshake
=
5518 intel_dp
->dpcd
[DP_MAX_DOWNSPREAD
] &
5519 DP_NO_AUX_HANDSHAKE_LINK_TRAINING
;
5521 /* if this fails, presume the device is a ghost */
5522 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5526 /* We now know it's not a ghost, init power sequence regs. */
5528 intel_dp_init_panel_power_sequencer_registers(dev
, intel_dp
);
5529 pps_unlock(intel_dp
);
5531 mutex_lock(&dev
->mode_config
.mutex
);
5532 edid
= drm_get_edid(connector
, &intel_dp
->aux
.ddc
);
5534 if (drm_add_edid_modes(connector
, edid
)) {
5535 drm_mode_connector_update_edid_property(connector
,
5537 drm_edid_to_eld(connector
, edid
);
5540 edid
= ERR_PTR(-EINVAL
);
5543 edid
= ERR_PTR(-ENOENT
);
5545 intel_connector
->edid
= edid
;
5547 /* prefer fixed mode from EDID if available */
5548 list_for_each_entry(scan
, &connector
->probed_modes
, head
) {
5549 if ((scan
->type
& DRM_MODE_TYPE_PREFERRED
)) {
5550 fixed_mode
= drm_mode_duplicate(dev
, scan
);
5551 downclock_mode
= intel_dp_drrs_init(
5552 intel_connector
, fixed_mode
);
5557 /* fallback to VBT if available for eDP */
5558 if (!fixed_mode
&& dev_priv
->vbt
.lfp_lvds_vbt_mode
) {
5559 fixed_mode
= drm_mode_duplicate(dev
,
5560 dev_priv
->vbt
.lfp_lvds_vbt_mode
);
5562 fixed_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
5564 mutex_unlock(&dev
->mode_config
.mutex
);
5566 if (IS_VALLEYVIEW(dev
)) {
5567 intel_dp
->edp_notifier
.notifier_call
= edp_notify_handler
;
5568 register_reboot_notifier(&intel_dp
->edp_notifier
);
5571 * Figure out the current pipe for the initial backlight setup.
5572 * If the current pipe isn't valid, try the PPS pipe, and if that
5573 * fails just assume pipe A.
5575 if (IS_CHERRYVIEW(dev
))
5576 pipe
= DP_PORT_TO_PIPE_CHV(intel_dp
->DP
);
5578 pipe
= PORT_TO_PIPE(intel_dp
->DP
);
5580 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5581 pipe
= intel_dp
->pps_pipe
;
5583 if (pipe
!= PIPE_A
&& pipe
!= PIPE_B
)
5586 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5590 intel_panel_init(&intel_connector
->panel
, fixed_mode
, downclock_mode
);
5591 intel_connector
->panel
.backlight_power
= intel_edp_backlight_power
;
5592 intel_panel_setup_backlight(connector
, pipe
);
5598 intel_dp_init_connector(struct intel_digital_port
*intel_dig_port
,
5599 struct intel_connector
*intel_connector
)
5601 struct drm_connector
*connector
= &intel_connector
->base
;
5602 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
5603 struct intel_encoder
*intel_encoder
= &intel_dig_port
->base
;
5604 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5606 enum port port
= intel_dig_port
->port
;
5609 intel_dp
->pps_pipe
= INVALID_PIPE
;
5611 /* intel_dp vfuncs */
5612 if (INTEL_INFO(dev
)->gen
>= 9)
5613 intel_dp
->get_aux_clock_divider
= skl_get_aux_clock_divider
;
5614 else if (IS_VALLEYVIEW(dev
))
5615 intel_dp
->get_aux_clock_divider
= vlv_get_aux_clock_divider
;
5616 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
5617 intel_dp
->get_aux_clock_divider
= hsw_get_aux_clock_divider
;
5618 else if (HAS_PCH_SPLIT(dev
))
5619 intel_dp
->get_aux_clock_divider
= ilk_get_aux_clock_divider
;
5621 intel_dp
->get_aux_clock_divider
= i9xx_get_aux_clock_divider
;
5623 if (INTEL_INFO(dev
)->gen
>= 9)
5624 intel_dp
->get_aux_send_ctl
= skl_get_aux_send_ctl
;
5626 intel_dp
->get_aux_send_ctl
= i9xx_get_aux_send_ctl
;
5628 /* Preserve the current hw state. */
5629 intel_dp
->DP
= I915_READ(intel_dp
->output_reg
);
5630 intel_dp
->attached_connector
= intel_connector
;
5632 if (intel_dp_is_edp(dev
, port
))
5633 type
= DRM_MODE_CONNECTOR_eDP
;
5635 type
= DRM_MODE_CONNECTOR_DisplayPort
;
5638 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5639 * for DP the encoder type can be set by the caller to
5640 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5642 if (type
== DRM_MODE_CONNECTOR_eDP
)
5643 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
5645 /* eDP only on port B and/or C on vlv/chv */
5646 if (WARN_ON(IS_VALLEYVIEW(dev
) && is_edp(intel_dp
) &&
5647 port
!= PORT_B
&& port
!= PORT_C
))
5650 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5651 type
== DRM_MODE_CONNECTOR_eDP
? "eDP" : "DP",
5654 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
5655 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
5657 connector
->interlace_allowed
= true;
5658 connector
->doublescan_allowed
= 0;
5660 INIT_DELAYED_WORK(&intel_dp
->panel_vdd_work
,
5661 edp_panel_vdd_work
);
5663 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
5664 drm_connector_register(connector
);
5667 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
5669 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
5670 intel_connector
->unregister
= intel_dp_connector_unregister
;
5672 /* Set up the hotplug pin. */
5675 intel_encoder
->hpd_pin
= HPD_PORT_A
;
5678 intel_encoder
->hpd_pin
= HPD_PORT_B
;
5681 intel_encoder
->hpd_pin
= HPD_PORT_C
;
5684 intel_encoder
->hpd_pin
= HPD_PORT_D
;
5690 if (is_edp(intel_dp
)) {
5692 intel_dp_init_panel_power_timestamps(intel_dp
);
5693 if (IS_VALLEYVIEW(dev
))
5694 vlv_initial_power_sequencer_setup(intel_dp
);
5696 intel_dp_init_panel_power_sequencer(dev
, intel_dp
);
5697 pps_unlock(intel_dp
);
5700 intel_dp_aux_init(intel_dp
, intel_connector
);
5702 /* init MST on ports that can support it */
5703 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
5704 if (port
== PORT_B
|| port
== PORT_C
|| port
== PORT_D
) {
5705 intel_dp_mst_encoder_init(intel_dig_port
,
5706 intel_connector
->base
.base
.id
);
5710 if (!intel_edp_init_connector(intel_dp
, intel_connector
)) {
5711 drm_dp_aux_unregister(&intel_dp
->aux
);
5712 if (is_edp(intel_dp
)) {
5713 cancel_delayed_work_sync(&intel_dp
->panel_vdd_work
);
5715 * vdd might still be enabled do to the delayed vdd off.
5716 * Make sure vdd is actually turned off here.
5719 edp_panel_vdd_off_sync(intel_dp
);
5720 pps_unlock(intel_dp
);
5722 drm_connector_unregister(connector
);
5723 drm_connector_cleanup(connector
);
5727 intel_dp_add_properties(intel_dp
, connector
);
5729 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5730 * 0xd. Failure to do so will result in spurious interrupts being
5731 * generated on the port when a cable is not attached.
5733 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
5734 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
5735 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);
5738 i915_debugfs_connector_add(connector
);
5744 intel_dp_init(struct drm_device
*dev
, int output_reg
, enum port port
)
5746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5747 struct intel_digital_port
*intel_dig_port
;
5748 struct intel_encoder
*intel_encoder
;
5749 struct drm_encoder
*encoder
;
5750 struct intel_connector
*intel_connector
;
5752 intel_dig_port
= kzalloc(sizeof(*intel_dig_port
), GFP_KERNEL
);
5753 if (!intel_dig_port
)
5756 intel_connector
= intel_connector_alloc();
5757 if (!intel_connector
) {
5758 kfree(intel_dig_port
);
5762 intel_encoder
= &intel_dig_port
->base
;
5763 encoder
= &intel_encoder
->base
;
5765 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_dp_enc_funcs
,
5766 DRM_MODE_ENCODER_TMDS
);
5768 intel_encoder
->compute_config
= intel_dp_compute_config
;
5769 intel_encoder
->disable
= intel_disable_dp
;
5770 intel_encoder
->get_hw_state
= intel_dp_get_hw_state
;
5771 intel_encoder
->get_config
= intel_dp_get_config
;
5772 intel_encoder
->suspend
= intel_dp_encoder_suspend
;
5773 if (IS_CHERRYVIEW(dev
)) {
5774 intel_encoder
->pre_pll_enable
= chv_dp_pre_pll_enable
;
5775 intel_encoder
->pre_enable
= chv_pre_enable_dp
;
5776 intel_encoder
->enable
= vlv_enable_dp
;
5777 intel_encoder
->post_disable
= chv_post_disable_dp
;
5778 } else if (IS_VALLEYVIEW(dev
)) {
5779 intel_encoder
->pre_pll_enable
= vlv_dp_pre_pll_enable
;
5780 intel_encoder
->pre_enable
= vlv_pre_enable_dp
;
5781 intel_encoder
->enable
= vlv_enable_dp
;
5782 intel_encoder
->post_disable
= vlv_post_disable_dp
;
5784 intel_encoder
->pre_enable
= g4x_pre_enable_dp
;
5785 intel_encoder
->enable
= g4x_enable_dp
;
5786 if (INTEL_INFO(dev
)->gen
>= 5)
5787 intel_encoder
->post_disable
= ilk_post_disable_dp
;
5790 intel_dig_port
->port
= port
;
5791 intel_dig_port
->dp
.output_reg
= output_reg
;
5793 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
5794 if (IS_CHERRYVIEW(dev
)) {
5796 intel_encoder
->crtc_mask
= 1 << 2;
5798 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
5800 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
5802 intel_encoder
->cloneable
= 0;
5803 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
5805 intel_dig_port
->hpd_pulse
= intel_dp_hpd_pulse
;
5806 dev_priv
->hpd_irq_port
[port
] = intel_dig_port
;
5808 if (!intel_dp_init_connector(intel_dig_port
, intel_connector
)) {
5809 drm_encoder_cleanup(encoder
);
5810 kfree(intel_dig_port
);
5811 kfree(intel_connector
);
5815 void intel_dp_mst_suspend(struct drm_device
*dev
)
5817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5821 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5822 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5823 if (!intel_dig_port
)
5826 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5827 if (!intel_dig_port
->dp
.can_mst
)
5829 if (intel_dig_port
->dp
.is_mst
)
5830 drm_dp_mst_topology_mgr_suspend(&intel_dig_port
->dp
.mst_mgr
);
5835 void intel_dp_mst_resume(struct drm_device
*dev
)
5837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5840 for (i
= 0; i
< I915_MAX_PORTS
; i
++) {
5841 struct intel_digital_port
*intel_dig_port
= dev_priv
->hpd_irq_port
[i
];
5842 if (!intel_dig_port
)
5844 if (intel_dig_port
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
5847 if (!intel_dig_port
->dp
.can_mst
)
5850 ret
= drm_dp_mst_topology_mgr_resume(&intel_dig_port
->dp
.mst_mgr
);
5852 intel_dp_check_mst_status(&intel_dig_port
->dp
);