2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
47 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
48 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t
;
74 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
76 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
77 int, int, intel_clock_t
*, intel_clock_t
*);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
85 int target
, int refclk
, intel_clock_t
*match_clock
,
86 intel_clock_t
*best_clock
);
88 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
89 int target
, int refclk
, intel_clock_t
*match_clock
,
90 intel_clock_t
*best_clock
);
93 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
94 int target
, int refclk
, intel_clock_t
*match_clock
,
95 intel_clock_t
*best_clock
);
97 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
98 int target
, int refclk
, intel_clock_t
*match_clock
,
99 intel_clock_t
*best_clock
);
102 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
103 int target
, int refclk
, intel_clock_t
*match_clock
,
104 intel_clock_t
*best_clock
);
106 static inline u32
/* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
111 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
116 static const intel_limit_t intel_limits_i8xx_dvo
= {
117 .dot
= { .min
= 25000, .max
= 350000 },
118 .vco
= { .min
= 930000, .max
= 1400000 },
119 .n
= { .min
= 3, .max
= 16 },
120 .m
= { .min
= 96, .max
= 140 },
121 .m1
= { .min
= 18, .max
= 26 },
122 .m2
= { .min
= 6, .max
= 16 },
123 .p
= { .min
= 4, .max
= 128 },
124 .p1
= { .min
= 2, .max
= 33 },
125 .p2
= { .dot_limit
= 165000,
126 .p2_slow
= 4, .p2_fast
= 2 },
127 .find_pll
= intel_find_best_PLL
,
130 static const intel_limit_t intel_limits_i8xx_lvds
= {
131 .dot
= { .min
= 25000, .max
= 350000 },
132 .vco
= { .min
= 930000, .max
= 1400000 },
133 .n
= { .min
= 3, .max
= 16 },
134 .m
= { .min
= 96, .max
= 140 },
135 .m1
= { .min
= 18, .max
= 26 },
136 .m2
= { .min
= 6, .max
= 16 },
137 .p
= { .min
= 4, .max
= 128 },
138 .p1
= { .min
= 1, .max
= 6 },
139 .p2
= { .dot_limit
= 165000,
140 .p2_slow
= 14, .p2_fast
= 7 },
141 .find_pll
= intel_find_best_PLL
,
144 static const intel_limit_t intel_limits_i9xx_sdvo
= {
145 .dot
= { .min
= 20000, .max
= 400000 },
146 .vco
= { .min
= 1400000, .max
= 2800000 },
147 .n
= { .min
= 1, .max
= 6 },
148 .m
= { .min
= 70, .max
= 120 },
149 .m1
= { .min
= 10, .max
= 22 },
150 .m2
= { .min
= 5, .max
= 9 },
151 .p
= { .min
= 5, .max
= 80 },
152 .p1
= { .min
= 1, .max
= 8 },
153 .p2
= { .dot_limit
= 200000,
154 .p2_slow
= 10, .p2_fast
= 5 },
155 .find_pll
= intel_find_best_PLL
,
158 static const intel_limit_t intel_limits_i9xx_lvds
= {
159 .dot
= { .min
= 20000, .max
= 400000 },
160 .vco
= { .min
= 1400000, .max
= 2800000 },
161 .n
= { .min
= 1, .max
= 6 },
162 .m
= { .min
= 70, .max
= 120 },
163 .m1
= { .min
= 10, .max
= 22 },
164 .m2
= { .min
= 5, .max
= 9 },
165 .p
= { .min
= 7, .max
= 98 },
166 .p1
= { .min
= 1, .max
= 8 },
167 .p2
= { .dot_limit
= 112000,
168 .p2_slow
= 14, .p2_fast
= 7 },
169 .find_pll
= intel_find_best_PLL
,
173 static const intel_limit_t intel_limits_g4x_sdvo
= {
174 .dot
= { .min
= 25000, .max
= 270000 },
175 .vco
= { .min
= 1750000, .max
= 3500000},
176 .n
= { .min
= 1, .max
= 4 },
177 .m
= { .min
= 104, .max
= 138 },
178 .m1
= { .min
= 17, .max
= 23 },
179 .m2
= { .min
= 5, .max
= 11 },
180 .p
= { .min
= 10, .max
= 30 },
181 .p1
= { .min
= 1, .max
= 3},
182 .p2
= { .dot_limit
= 270000,
186 .find_pll
= intel_g4x_find_best_PLL
,
189 static const intel_limit_t intel_limits_g4x_hdmi
= {
190 .dot
= { .min
= 22000, .max
= 400000 },
191 .vco
= { .min
= 1750000, .max
= 3500000},
192 .n
= { .min
= 1, .max
= 4 },
193 .m
= { .min
= 104, .max
= 138 },
194 .m1
= { .min
= 16, .max
= 23 },
195 .m2
= { .min
= 5, .max
= 11 },
196 .p
= { .min
= 5, .max
= 80 },
197 .p1
= { .min
= 1, .max
= 8},
198 .p2
= { .dot_limit
= 165000,
199 .p2_slow
= 10, .p2_fast
= 5 },
200 .find_pll
= intel_g4x_find_best_PLL
,
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
204 .dot
= { .min
= 20000, .max
= 115000 },
205 .vco
= { .min
= 1750000, .max
= 3500000 },
206 .n
= { .min
= 1, .max
= 3 },
207 .m
= { .min
= 104, .max
= 138 },
208 .m1
= { .min
= 17, .max
= 23 },
209 .m2
= { .min
= 5, .max
= 11 },
210 .p
= { .min
= 28, .max
= 112 },
211 .p1
= { .min
= 2, .max
= 8 },
212 .p2
= { .dot_limit
= 0,
213 .p2_slow
= 14, .p2_fast
= 14
215 .find_pll
= intel_g4x_find_best_PLL
,
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
219 .dot
= { .min
= 80000, .max
= 224000 },
220 .vco
= { .min
= 1750000, .max
= 3500000 },
221 .n
= { .min
= 1, .max
= 3 },
222 .m
= { .min
= 104, .max
= 138 },
223 .m1
= { .min
= 17, .max
= 23 },
224 .m2
= { .min
= 5, .max
= 11 },
225 .p
= { .min
= 14, .max
= 42 },
226 .p1
= { .min
= 2, .max
= 6 },
227 .p2
= { .dot_limit
= 0,
228 .p2_slow
= 7, .p2_fast
= 7
230 .find_pll
= intel_g4x_find_best_PLL
,
233 static const intel_limit_t intel_limits_g4x_display_port
= {
234 .dot
= { .min
= 161670, .max
= 227000 },
235 .vco
= { .min
= 1750000, .max
= 3500000},
236 .n
= { .min
= 1, .max
= 2 },
237 .m
= { .min
= 97, .max
= 108 },
238 .m1
= { .min
= 0x10, .max
= 0x12 },
239 .m2
= { .min
= 0x05, .max
= 0x06 },
240 .p
= { .min
= 10, .max
= 20 },
241 .p1
= { .min
= 1, .max
= 2},
242 .p2
= { .dot_limit
= 0,
243 .p2_slow
= 10, .p2_fast
= 10 },
244 .find_pll
= intel_find_pll_g4x_dp
,
247 static const intel_limit_t intel_limits_pineview_sdvo
= {
248 .dot
= { .min
= 20000, .max
= 400000},
249 .vco
= { .min
= 1700000, .max
= 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n
= { .min
= 3, .max
= 6 },
252 .m
= { .min
= 2, .max
= 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1
= { .min
= 0, .max
= 0 },
255 .m2
= { .min
= 0, .max
= 254 },
256 .p
= { .min
= 5, .max
= 80 },
257 .p1
= { .min
= 1, .max
= 8 },
258 .p2
= { .dot_limit
= 200000,
259 .p2_slow
= 10, .p2_fast
= 5 },
260 .find_pll
= intel_find_best_PLL
,
263 static const intel_limit_t intel_limits_pineview_lvds
= {
264 .dot
= { .min
= 20000, .max
= 400000 },
265 .vco
= { .min
= 1700000, .max
= 3500000 },
266 .n
= { .min
= 3, .max
= 6 },
267 .m
= { .min
= 2, .max
= 256 },
268 .m1
= { .min
= 0, .max
= 0 },
269 .m2
= { .min
= 0, .max
= 254 },
270 .p
= { .min
= 7, .max
= 112 },
271 .p1
= { .min
= 1, .max
= 8 },
272 .p2
= { .dot_limit
= 112000,
273 .p2_slow
= 14, .p2_fast
= 14 },
274 .find_pll
= intel_find_best_PLL
,
277 /* Ironlake / Sandybridge
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
282 static const intel_limit_t intel_limits_ironlake_dac
= {
283 .dot
= { .min
= 25000, .max
= 350000 },
284 .vco
= { .min
= 1760000, .max
= 3510000 },
285 .n
= { .min
= 1, .max
= 5 },
286 .m
= { .min
= 79, .max
= 127 },
287 .m1
= { .min
= 12, .max
= 22 },
288 .m2
= { .min
= 5, .max
= 9 },
289 .p
= { .min
= 5, .max
= 80 },
290 .p1
= { .min
= 1, .max
= 8 },
291 .p2
= { .dot_limit
= 225000,
292 .p2_slow
= 10, .p2_fast
= 5 },
293 .find_pll
= intel_g4x_find_best_PLL
,
296 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
297 .dot
= { .min
= 25000, .max
= 350000 },
298 .vco
= { .min
= 1760000, .max
= 3510000 },
299 .n
= { .min
= 1, .max
= 3 },
300 .m
= { .min
= 79, .max
= 118 },
301 .m1
= { .min
= 12, .max
= 22 },
302 .m2
= { .min
= 5, .max
= 9 },
303 .p
= { .min
= 28, .max
= 112 },
304 .p1
= { .min
= 2, .max
= 8 },
305 .p2
= { .dot_limit
= 225000,
306 .p2_slow
= 14, .p2_fast
= 14 },
307 .find_pll
= intel_g4x_find_best_PLL
,
310 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
311 .dot
= { .min
= 25000, .max
= 350000 },
312 .vco
= { .min
= 1760000, .max
= 3510000 },
313 .n
= { .min
= 1, .max
= 3 },
314 .m
= { .min
= 79, .max
= 127 },
315 .m1
= { .min
= 12, .max
= 22 },
316 .m2
= { .min
= 5, .max
= 9 },
317 .p
= { .min
= 14, .max
= 56 },
318 .p1
= { .min
= 2, .max
= 8 },
319 .p2
= { .dot_limit
= 225000,
320 .p2_slow
= 7, .p2_fast
= 7 },
321 .find_pll
= intel_g4x_find_best_PLL
,
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
326 .dot
= { .min
= 25000, .max
= 350000 },
327 .vco
= { .min
= 1760000, .max
= 3510000 },
328 .n
= { .min
= 1, .max
= 2 },
329 .m
= { .min
= 79, .max
= 126 },
330 .m1
= { .min
= 12, .max
= 22 },
331 .m2
= { .min
= 5, .max
= 9 },
332 .p
= { .min
= 28, .max
= 112 },
333 .p1
= { .min
= 2, .max
= 8 },
334 .p2
= { .dot_limit
= 225000,
335 .p2_slow
= 14, .p2_fast
= 14 },
336 .find_pll
= intel_g4x_find_best_PLL
,
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
340 .dot
= { .min
= 25000, .max
= 350000 },
341 .vco
= { .min
= 1760000, .max
= 3510000 },
342 .n
= { .min
= 1, .max
= 3 },
343 .m
= { .min
= 79, .max
= 126 },
344 .m1
= { .min
= 12, .max
= 22 },
345 .m2
= { .min
= 5, .max
= 9 },
346 .p
= { .min
= 14, .max
= 42 },
347 .p1
= { .min
= 2, .max
= 6 },
348 .p2
= { .dot_limit
= 225000,
349 .p2_slow
= 7, .p2_fast
= 7 },
350 .find_pll
= intel_g4x_find_best_PLL
,
353 static const intel_limit_t intel_limits_ironlake_display_port
= {
354 .dot
= { .min
= 25000, .max
= 350000 },
355 .vco
= { .min
= 1760000, .max
= 3510000},
356 .n
= { .min
= 1, .max
= 2 },
357 .m
= { .min
= 81, .max
= 90 },
358 .m1
= { .min
= 12, .max
= 22 },
359 .m2
= { .min
= 5, .max
= 9 },
360 .p
= { .min
= 10, .max
= 20 },
361 .p1
= { .min
= 1, .max
= 2},
362 .p2
= { .dot_limit
= 0,
363 .p2_slow
= 10, .p2_fast
= 10 },
364 .find_pll
= intel_find_pll_ironlake_dp
,
367 static const intel_limit_t intel_limits_vlv_dac
= {
368 .dot
= { .min
= 25000, .max
= 270000 },
369 .vco
= { .min
= 4000000, .max
= 6000000 },
370 .n
= { .min
= 1, .max
= 7 },
371 .m
= { .min
= 22, .max
= 450 }, /* guess */
372 .m1
= { .min
= 2, .max
= 3 },
373 .m2
= { .min
= 11, .max
= 156 },
374 .p
= { .min
= 10, .max
= 30 },
375 .p1
= { .min
= 2, .max
= 3 },
376 .p2
= { .dot_limit
= 270000,
377 .p2_slow
= 2, .p2_fast
= 20 },
378 .find_pll
= intel_vlv_find_best_pll
,
381 static const intel_limit_t intel_limits_vlv_hdmi
= {
382 .dot
= { .min
= 20000, .max
= 165000 },
383 .vco
= { .min
= 5994000, .max
= 4000000 },
384 .n
= { .min
= 1, .max
= 7 },
385 .m
= { .min
= 60, .max
= 300 }, /* guess */
386 .m1
= { .min
= 2, .max
= 3 },
387 .m2
= { .min
= 11, .max
= 156 },
388 .p
= { .min
= 10, .max
= 30 },
389 .p1
= { .min
= 2, .max
= 3 },
390 .p2
= { .dot_limit
= 270000,
391 .p2_slow
= 2, .p2_fast
= 20 },
392 .find_pll
= intel_vlv_find_best_pll
,
395 static const intel_limit_t intel_limits_vlv_dp
= {
396 .dot
= { .min
= 162000, .max
= 270000 },
397 .vco
= { .min
= 5994000, .max
= 4000000 },
398 .n
= { .min
= 1, .max
= 7 },
399 .m
= { .min
= 60, .max
= 300 }, /* guess */
400 .m1
= { .min
= 2, .max
= 3 },
401 .m2
= { .min
= 11, .max
= 156 },
402 .p
= { .min
= 10, .max
= 30 },
403 .p1
= { .min
= 2, .max
= 3 },
404 .p2
= { .dot_limit
= 270000,
405 .p2_slow
= 2, .p2_fast
= 20 },
406 .find_pll
= intel_vlv_find_best_pll
,
409 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
414 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
420 I915_WRITE(DPIO_REG
, reg
);
421 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
427 val
= I915_READ(DPIO_DATA
);
430 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
434 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
439 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
445 I915_WRITE(DPIO_DATA
, val
);
446 I915_WRITE(DPIO_REG
, reg
);
447 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
453 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
456 static void vlv_init_dpio(struct drm_device
*dev
)
458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL
, 0);
462 POSTING_READ(DPIO_CTL
);
463 I915_WRITE(DPIO_CTL
, 1);
464 POSTING_READ(DPIO_CTL
);
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id
*id
)
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id
->ident
);
473 static const struct dmi_system_id intel_dual_link_lvds
[] = {
475 .callback
= intel_dual_link_lvds_callback
,
476 .ident
= "Apple MacBook Pro (Core i5/i7 Series)",
478 DMI_MATCH(DMI_SYS_VENDOR
, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME
, "MacBookPro8,2"),
482 { } /* terminating entry */
485 static bool is_dual_link_lvds(struct drm_i915_private
*dev_priv
,
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode
> 0)
492 return i915_lvds_channel_mode
== 2;
494 if (dmi_check_system(intel_dual_link_lvds
))
497 if (dev_priv
->lvds_val
)
498 val
= dev_priv
->lvds_val
;
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
505 val
= I915_READ(reg
);
506 if (!(val
& ~(LVDS_PIPE_MASK
| LVDS_DETECTED
)))
507 val
= dev_priv
->bios_lvds_val
;
508 dev_priv
->lvds_val
= val
;
510 return (val
& LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
;
513 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
516 struct drm_device
*dev
= crtc
->dev
;
517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
518 const intel_limit_t
*limit
;
520 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
521 if (is_dual_link_lvds(dev_priv
, PCH_LVDS
)) {
522 /* LVDS dual channel */
523 if (refclk
== 100000)
524 limit
= &intel_limits_ironlake_dual_lvds_100m
;
526 limit
= &intel_limits_ironlake_dual_lvds
;
528 if (refclk
== 100000)
529 limit
= &intel_limits_ironlake_single_lvds_100m
;
531 limit
= &intel_limits_ironlake_single_lvds
;
533 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
535 limit
= &intel_limits_ironlake_display_port
;
537 limit
= &intel_limits_ironlake_dac
;
542 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
544 struct drm_device
*dev
= crtc
->dev
;
545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
546 const intel_limit_t
*limit
;
548 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
549 if (is_dual_link_lvds(dev_priv
, LVDS
))
550 /* LVDS with dual channel */
551 limit
= &intel_limits_g4x_dual_channel_lvds
;
553 /* LVDS with dual channel */
554 limit
= &intel_limits_g4x_single_channel_lvds
;
555 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
556 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
557 limit
= &intel_limits_g4x_hdmi
;
558 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
559 limit
= &intel_limits_g4x_sdvo
;
560 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
561 limit
= &intel_limits_g4x_display_port
;
562 } else /* The option is for other outputs */
563 limit
= &intel_limits_i9xx_sdvo
;
568 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
570 struct drm_device
*dev
= crtc
->dev
;
571 const intel_limit_t
*limit
;
573 if (HAS_PCH_SPLIT(dev
))
574 limit
= intel_ironlake_limit(crtc
, refclk
);
575 else if (IS_G4X(dev
)) {
576 limit
= intel_g4x_limit(crtc
);
577 } else if (IS_PINEVIEW(dev
)) {
578 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
579 limit
= &intel_limits_pineview_lvds
;
581 limit
= &intel_limits_pineview_sdvo
;
582 } else if (IS_VALLEYVIEW(dev
)) {
583 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
584 limit
= &intel_limits_vlv_dac
;
585 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
586 limit
= &intel_limits_vlv_hdmi
;
588 limit
= &intel_limits_vlv_dp
;
589 } else if (!IS_GEN2(dev
)) {
590 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
591 limit
= &intel_limits_i9xx_lvds
;
593 limit
= &intel_limits_i9xx_sdvo
;
595 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
596 limit
= &intel_limits_i8xx_lvds
;
598 limit
= &intel_limits_i8xx_dvo
;
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
606 clock
->m
= clock
->m2
+ 2;
607 clock
->p
= clock
->p1
* clock
->p2
;
608 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
609 clock
->dot
= clock
->vco
/ clock
->p
;
612 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
614 if (IS_PINEVIEW(dev
)) {
615 pineview_clock(refclk
, clock
);
618 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
619 clock
->p
= clock
->p1
* clock
->p2
;
620 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
621 clock
->dot
= clock
->vco
/ clock
->p
;
625 * Returns whether any output on the specified pipe is of the specified type
627 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
629 struct drm_device
*dev
= crtc
->dev
;
630 struct intel_encoder
*encoder
;
632 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
633 if (encoder
->type
== type
)
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
645 static bool intel_PLL_is_valid(struct drm_device
*dev
,
646 const intel_limit_t
*limit
,
647 const intel_clock_t
*clock
)
649 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
652 INTELPllInvalid("p out of range\n");
653 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
660 INTELPllInvalid("m out of range\n");
661 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
662 INTELPllInvalid("n out of range\n");
663 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
668 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
669 INTELPllInvalid("dot out of range\n");
675 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
676 int target
, int refclk
, intel_clock_t
*match_clock
,
677 intel_clock_t
*best_clock
)
680 struct drm_device
*dev
= crtc
->dev
;
681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
685 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
686 (I915_READ(LVDS
)) != 0) {
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
693 if (is_dual_link_lvds(dev_priv
, LVDS
))
694 clock
.p2
= limit
->p2
.p2_fast
;
696 clock
.p2
= limit
->p2
.p2_slow
;
698 if (target
< limit
->p2
.dot_limit
)
699 clock
.p2
= limit
->p2
.p2_slow
;
701 clock
.p2
= limit
->p2
.p2_fast
;
704 memset(best_clock
, 0, sizeof(*best_clock
));
706 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
708 for (clock
.m2
= limit
->m2
.min
;
709 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
710 /* m1 is always 0 in Pineview */
711 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
713 for (clock
.n
= limit
->n
.min
;
714 clock
.n
<= limit
->n
.max
; clock
.n
++) {
715 for (clock
.p1
= limit
->p1
.min
;
716 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
719 intel_clock(dev
, refclk
, &clock
);
720 if (!intel_PLL_is_valid(dev
, limit
,
724 clock
.p
!= match_clock
->p
)
727 this_err
= abs(clock
.dot
- target
);
728 if (this_err
< err
) {
737 return (err
!= target
);
741 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
742 int target
, int refclk
, intel_clock_t
*match_clock
,
743 intel_clock_t
*best_clock
)
745 struct drm_device
*dev
= crtc
->dev
;
746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
750 /* approximately equals target * 0.00585 */
751 int err_most
= (target
>> 8) + (target
>> 9);
754 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
757 if (HAS_PCH_SPLIT(dev
))
761 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
763 clock
.p2
= limit
->p2
.p2_fast
;
765 clock
.p2
= limit
->p2
.p2_slow
;
767 if (target
< limit
->p2
.dot_limit
)
768 clock
.p2
= limit
->p2
.p2_slow
;
770 clock
.p2
= limit
->p2
.p2_fast
;
773 memset(best_clock
, 0, sizeof(*best_clock
));
774 max_n
= limit
->n
.max
;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock
.m1
= limit
->m1
.max
;
779 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
780 for (clock
.m2
= limit
->m2
.max
;
781 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
782 for (clock
.p1
= limit
->p1
.max
;
783 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
786 intel_clock(dev
, refclk
, &clock
);
787 if (!intel_PLL_is_valid(dev
, limit
,
791 clock
.p
!= match_clock
->p
)
794 this_err
= abs(clock
.dot
- target
);
795 if (this_err
< err_most
) {
809 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
810 int target
, int refclk
, intel_clock_t
*match_clock
,
811 intel_clock_t
*best_clock
)
813 struct drm_device
*dev
= crtc
->dev
;
816 if (target
< 200000) {
829 intel_clock(dev
, refclk
, &clock
);
830 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
836 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
837 int target
, int refclk
, intel_clock_t
*match_clock
,
838 intel_clock_t
*best_clock
)
841 if (target
< 200000) {
854 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
855 clock
.p
= (clock
.p1
* clock
.p2
);
856 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
858 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
862 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
863 int target
, int refclk
, intel_clock_t
*match_clock
,
864 intel_clock_t
*best_clock
)
866 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
868 u32 updrate
, minupdate
, fracbits
, p
;
869 unsigned long bestppm
, ppm
, absppm
;
872 dotclk
= target
* 1000;
875 fastclk
= dotclk
/ (2*100);
879 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
880 bestm1
= bestm2
= bestp1
= bestp2
= 0;
882 /* based on hardware requirement, prefer smaller n to precision */
883 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
884 updrate
= refclk
/ n
;
885 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
886 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
890 /* based on hardware requirement, prefer bigger m1,m2 values */
891 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
892 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
893 refclk
) / (2*refclk
));
896 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
897 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
898 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
899 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
903 if (absppm
< bestppm
- 10) {
920 best_clock
->n
= bestn
;
921 best_clock
->m1
= bestm1
;
922 best_clock
->m2
= bestm2
;
923 best_clock
->p1
= bestp1
;
924 best_clock
->p2
= bestp2
;
929 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
932 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
934 frame
= I915_READ(frame_reg
);
936 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
937 DRM_DEBUG_KMS("vblank wait timed out\n");
941 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @pipe: pipe to wait for
945 * Wait for vblank to occur on a given pipe. Needed for various bits of
948 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
951 int pipestat_reg
= PIPESTAT(pipe
);
953 if (INTEL_INFO(dev
)->gen
>= 5) {
954 ironlake_wait_for_vblank(dev
, pipe
);
958 /* Clear existing vblank status. Note this will clear any other
959 * sticky status fields as well.
961 * This races with i915_driver_irq_handler() with the result
962 * that either function could miss a vblank event. Here it is not
963 * fatal, as we will either wait upon the next vblank interrupt or
964 * timeout. Generally speaking intel_wait_for_vblank() is only
965 * called during modeset at which time the GPU should be idle and
966 * should *not* be performing page flips and thus not waiting on
968 * Currently, the result of us stealing a vblank from the irq
969 * handler is that a single frame will be skipped during swapbuffers.
971 I915_WRITE(pipestat_reg
,
972 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
974 /* Wait for vblank interrupt bit to set */
975 if (wait_for(I915_READ(pipestat_reg
) &
976 PIPE_VBLANK_INTERRUPT_STATUS
,
978 DRM_DEBUG_KMS("vblank wait timed out\n");
982 * intel_wait_for_pipe_off - wait for pipe to turn off
984 * @pipe: pipe to wait for
986 * After disabling a pipe, we can't wait for vblank in the usual way,
987 * spinning on the vblank interrupt status bit, since we won't actually
988 * see an interrupt when the pipe is disabled.
991 * wait for the pipe register state bit to turn off
994 * wait for the display line value to settle (it usually
995 * ends up stopping at the start of the next frame).
998 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
1000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1002 if (INTEL_INFO(dev
)->gen
>= 4) {
1003 int reg
= PIPECONF(pipe
);
1005 /* Wait for the Pipe State to go off */
1006 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1008 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 u32 last_line
, line_mask
;
1011 int reg
= PIPEDSL(pipe
);
1012 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1015 line_mask
= DSL_LINEMASK_GEN2
;
1017 line_mask
= DSL_LINEMASK_GEN3
;
1019 /* Wait for the display line to settle */
1021 last_line
= I915_READ(reg
) & line_mask
;
1023 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
1024 time_after(timeout
, jiffies
));
1025 if (time_after(jiffies
, timeout
))
1026 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1030 static const char *state_string(bool enabled
)
1032 return enabled
? "on" : "off";
1035 /* Only for pre-ILK configs */
1036 static void assert_pll(struct drm_i915_private
*dev_priv
,
1037 enum pipe pipe
, bool state
)
1044 val
= I915_READ(reg
);
1045 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1046 WARN(cur_state
!= state
,
1047 "PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state
), state_string(cur_state
));
1050 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1051 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1054 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1055 struct intel_pch_pll
*pll
,
1056 struct intel_crtc
*crtc
,
1062 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1063 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1068 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1071 val
= I915_READ(pll
->pll_reg
);
1072 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1073 WARN(cur_state
!= state
,
1074 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1075 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1077 /* Make sure the selected PLL is correctly attached to the transcoder */
1078 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1081 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1082 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1083 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1084 "PLL[%d] not attached to this transcoder %d: %08x\n",
1085 cur_state
, crtc
->pipe
, pch_dpll
)) {
1086 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1087 WARN(cur_state
!= state
,
1088 "PLL[%d] not %s on this transcoder %d: %08x\n",
1089 pll
->pll_reg
== _PCH_DPLL_B
,
1090 state_string(state
),
1096 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1097 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1100 enum pipe pipe
, bool state
)
1106 if (IS_HASWELL(dev_priv
->dev
)) {
1107 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1108 reg
= DDI_FUNC_CTL(pipe
);
1109 val
= I915_READ(reg
);
1110 cur_state
= !!(val
& PIPE_DDI_FUNC_ENABLE
);
1112 reg
= FDI_TX_CTL(pipe
);
1113 val
= I915_READ(reg
);
1114 cur_state
= !!(val
& FDI_TX_ENABLE
);
1116 WARN(cur_state
!= state
,
1117 "FDI TX state assertion failure (expected %s, current %s)\n",
1118 state_string(state
), state_string(cur_state
));
1120 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1121 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1124 enum pipe pipe
, bool state
)
1130 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1131 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1134 reg
= FDI_RX_CTL(pipe
);
1135 val
= I915_READ(reg
);
1136 cur_state
= !!(val
& FDI_RX_ENABLE
);
1138 WARN(cur_state
!= state
,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state
), state_string(cur_state
));
1142 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv
->info
->gen
== 5)
1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1156 if (IS_HASWELL(dev_priv
->dev
))
1159 reg
= FDI_TX_CTL(pipe
);
1160 val
= I915_READ(reg
);
1161 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1164 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1170 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1171 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1174 reg
= FDI_RX_CTL(pipe
);
1175 val
= I915_READ(reg
);
1176 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1179 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1182 int pp_reg
, lvds_reg
;
1184 enum pipe panel_pipe
= PIPE_A
;
1187 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1188 pp_reg
= PCH_PP_CONTROL
;
1189 lvds_reg
= PCH_LVDS
;
1191 pp_reg
= PP_CONTROL
;
1195 val
= I915_READ(pp_reg
);
1196 if (!(val
& PANEL_POWER_ON
) ||
1197 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1200 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1201 panel_pipe
= PIPE_B
;
1203 WARN(panel_pipe
== pipe
&& locked
,
1204 "panel assertion failure, pipe %c regs locked\n",
1208 void assert_pipe(struct drm_i915_private
*dev_priv
,
1209 enum pipe pipe
, bool state
)
1215 /* if we need the pipe A quirk it must be always on */
1216 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1219 reg
= PIPECONF(pipe
);
1220 val
= I915_READ(reg
);
1221 cur_state
= !!(val
& PIPECONF_ENABLE
);
1222 WARN(cur_state
!= state
,
1223 "pipe %c assertion failure (expected %s, current %s)\n",
1224 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1227 static void assert_plane(struct drm_i915_private
*dev_priv
,
1228 enum plane plane
, bool state
)
1234 reg
= DSPCNTR(plane
);
1235 val
= I915_READ(reg
);
1236 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1237 WARN(cur_state
!= state
,
1238 "plane %c assertion failure (expected %s, current %s)\n",
1239 plane_name(plane
), state_string(state
), state_string(cur_state
));
1242 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1243 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1252 /* Planes are fixed to pipes on ILK+ */
1253 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1254 reg
= DSPCNTR(pipe
);
1255 val
= I915_READ(reg
);
1256 WARN((val
& DISPLAY_PLANE_ENABLE
),
1257 "plane %c assertion failure, should be disabled but not\n",
1262 /* Need to check both planes against the pipe */
1263 for (i
= 0; i
< 2; i
++) {
1265 val
= I915_READ(reg
);
1266 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1267 DISPPLANE_SEL_PIPE_SHIFT
;
1268 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1269 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1270 plane_name(i
), pipe_name(pipe
));
1274 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1279 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1280 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1284 val
= I915_READ(PCH_DREF_CONTROL
);
1285 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1286 DREF_SUPERSPREAD_SOURCE_MASK
));
1287 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1290 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1297 reg
= TRANSCONF(pipe
);
1298 val
= I915_READ(reg
);
1299 enabled
= !!(val
& TRANS_ENABLE
);
1301 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1305 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1306 enum pipe pipe
, u32 port_sel
, u32 val
)
1308 if ((val
& DP_PORT_EN
) == 0)
1311 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1312 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1313 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1314 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1317 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1323 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1324 enum pipe pipe
, u32 val
)
1326 if ((val
& PORT_ENABLE
) == 0)
1329 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1330 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1333 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1339 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1340 enum pipe pipe
, u32 val
)
1342 if ((val
& LVDS_PORT_EN
) == 0)
1345 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1346 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1349 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1355 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1356 enum pipe pipe
, u32 val
)
1358 if ((val
& ADPA_DAC_ENABLE
) == 0)
1360 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1361 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1364 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1370 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1371 enum pipe pipe
, int reg
, u32 port_sel
)
1373 u32 val
= I915_READ(reg
);
1374 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1375 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1376 reg
, pipe_name(pipe
));
1378 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_PIPE_B_SELECT
),
1379 "IBX PCH dp port still using transcoder B\n");
1382 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1383 enum pipe pipe
, int reg
)
1385 u32 val
= I915_READ(reg
);
1386 WARN(hdmi_pipe_enabled(dev_priv
, val
, pipe
),
1387 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1388 reg
, pipe_name(pipe
));
1390 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_PIPE_B_SELECT
),
1391 "IBX PCH hdmi port still using transcoder B\n");
1394 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1400 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1401 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1402 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1405 val
= I915_READ(reg
);
1406 WARN(adpa_pipe_enabled(dev_priv
, val
, pipe
),
1407 "PCH VGA enabled on transcoder %c, should be disabled\n",
1411 val
= I915_READ(reg
);
1412 WARN(lvds_pipe_enabled(dev_priv
, val
, pipe
),
1413 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1416 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1417 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1418 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1422 * intel_enable_pll - enable a PLL
1423 * @dev_priv: i915 private structure
1424 * @pipe: pipe PLL to enable
1426 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1427 * make sure the PLL reg is writable first though, since the panel write
1428 * protect mechanism may be enabled.
1430 * Note! This is for pre-ILK only.
1432 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1437 /* No really, not for ILK+ */
1438 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1440 /* PLL is protected by panel, make sure we can write it */
1441 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1442 assert_panel_unlocked(dev_priv
, pipe
);
1445 val
= I915_READ(reg
);
1446 val
|= DPLL_VCO_ENABLE
;
1448 /* We do this three times for luck */
1449 I915_WRITE(reg
, val
);
1451 udelay(150); /* wait for warmup */
1452 I915_WRITE(reg
, val
);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg
, val
);
1457 udelay(150); /* wait for warmup */
1461 * intel_disable_pll - disable a PLL
1462 * @dev_priv: i915 private structure
1463 * @pipe: pipe PLL to disable
1465 * Disable the PLL for @pipe, making sure the pipe is off first.
1467 * Note! This is for pre-ILK only.
1469 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1474 /* Don't disable pipe A or pipe A PLLs if needed */
1475 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1478 /* Make sure the pipe isn't still relying on us */
1479 assert_pipe_disabled(dev_priv
, pipe
);
1482 val
= I915_READ(reg
);
1483 val
&= ~DPLL_VCO_ENABLE
;
1484 I915_WRITE(reg
, val
);
1490 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
)
1492 unsigned long flags
;
1494 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1495 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1497 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 I915_WRITE(SBI_ADDR
,
1503 I915_WRITE(SBI_DATA
,
1505 I915_WRITE(SBI_CTL_STAT
,
1509 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1511 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1516 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1520 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
)
1522 unsigned long flags
;
1525 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1526 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1528 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 I915_WRITE(SBI_ADDR
,
1534 I915_WRITE(SBI_CTL_STAT
,
1538 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1540 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 value
= I915_READ(SBI_DATA
);
1547 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1552 * intel_enable_pch_pll - enable PCH PLL
1553 * @dev_priv: i915 private structure
1554 * @pipe: pipe PLL to enable
1556 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1557 * drives the transcoder clock.
1559 static void intel_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1561 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1562 struct intel_pch_pll
*pll
;
1566 /* PCH PLLs only available on ILK, SNB and IVB */
1567 BUG_ON(dev_priv
->info
->gen
< 5);
1568 pll
= intel_crtc
->pch_pll
;
1572 if (WARN_ON(pll
->refcount
== 0))
1575 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1576 pll
->pll_reg
, pll
->active
, pll
->on
,
1577 intel_crtc
->base
.base
.id
);
1579 /* PCH refclock must be enabled first */
1580 assert_pch_refclk_enabled(dev_priv
);
1582 if (pll
->active
++ && pll
->on
) {
1583 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1587 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1590 val
= I915_READ(reg
);
1591 val
|= DPLL_VCO_ENABLE
;
1592 I915_WRITE(reg
, val
);
1599 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1601 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1602 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1606 /* PCH only available on ILK+ */
1607 BUG_ON(dev_priv
->info
->gen
< 5);
1611 if (WARN_ON(pll
->refcount
== 0))
1614 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1615 pll
->pll_reg
, pll
->active
, pll
->on
,
1616 intel_crtc
->base
.base
.id
);
1618 if (WARN_ON(pll
->active
== 0)) {
1619 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1623 if (--pll
->active
) {
1624 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1628 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1630 /* Make sure transcoder isn't still depending on us */
1631 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1634 val
= I915_READ(reg
);
1635 val
&= ~DPLL_VCO_ENABLE
;
1636 I915_WRITE(reg
, val
);
1643 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1647 u32 val
, pipeconf_val
;
1648 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1650 /* PCH only available on ILK+ */
1651 BUG_ON(dev_priv
->info
->gen
< 5);
1653 /* Make sure PCH DPLL is enabled */
1654 assert_pch_pll_enabled(dev_priv
,
1655 to_intel_crtc(crtc
)->pch_pll
,
1656 to_intel_crtc(crtc
));
1658 /* FDI must be feeding us bits for PCH ports */
1659 assert_fdi_tx_enabled(dev_priv
, pipe
);
1660 assert_fdi_rx_enabled(dev_priv
, pipe
);
1662 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1663 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1666 reg
= TRANSCONF(pipe
);
1667 val
= I915_READ(reg
);
1668 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1670 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1672 * make the BPC in transcoder be consistent with
1673 * that in pipeconf reg.
1675 val
&= ~PIPE_BPC_MASK
;
1676 val
|= pipeconf_val
& PIPE_BPC_MASK
;
1679 val
&= ~TRANS_INTERLACE_MASK
;
1680 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1681 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1682 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1683 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1685 val
|= TRANS_INTERLACED
;
1687 val
|= TRANS_PROGRESSIVE
;
1689 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1690 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1691 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1694 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1700 /* FDI relies on the transcoder */
1701 assert_fdi_tx_disabled(dev_priv
, pipe
);
1702 assert_fdi_rx_disabled(dev_priv
, pipe
);
1704 /* Ports must be off as well */
1705 assert_pch_ports_disabled(dev_priv
, pipe
);
1707 reg
= TRANSCONF(pipe
);
1708 val
= I915_READ(reg
);
1709 val
&= ~TRANS_ENABLE
;
1710 I915_WRITE(reg
, val
);
1711 /* wait for PCH transcoder off, transcoder state */
1712 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1713 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1717 * intel_enable_pipe - enable a pipe, asserting requirements
1718 * @dev_priv: i915 private structure
1719 * @pipe: pipe to enable
1720 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1722 * Enable @pipe, making sure that various hardware specific requirements
1723 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1725 * @pipe should be %PIPE_A or %PIPE_B.
1727 * Will wait until the pipe is actually running (i.e. first vblank) before
1730 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1737 * A pipe without a PLL won't actually be able to drive bits from
1738 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1741 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1742 assert_pll_enabled(dev_priv
, pipe
);
1745 /* if driving the PCH, we need FDI enabled */
1746 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1747 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1749 /* FIXME: assert CPU port conditions for SNB+ */
1752 reg
= PIPECONF(pipe
);
1753 val
= I915_READ(reg
);
1754 if (val
& PIPECONF_ENABLE
)
1757 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1758 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1762 * intel_disable_pipe - disable a pipe, asserting requirements
1763 * @dev_priv: i915 private structure
1764 * @pipe: pipe to disable
1766 * Disable @pipe, making sure that various hardware specific requirements
1767 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1769 * @pipe should be %PIPE_A or %PIPE_B.
1771 * Will wait until the pipe has shut down before returning.
1773 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1780 * Make sure planes won't keep trying to pump pixels to us,
1781 * or we might hang the display.
1783 assert_planes_disabled(dev_priv
, pipe
);
1785 /* Don't disable pipe A or pipe A PLLs if needed */
1786 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1789 reg
= PIPECONF(pipe
);
1790 val
= I915_READ(reg
);
1791 if ((val
& PIPECONF_ENABLE
) == 0)
1794 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1795 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1799 * Plane regs are double buffered, going from enabled->disabled needs a
1800 * trigger in order to latch. The display address reg provides this.
1802 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1805 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1806 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1810 * intel_enable_plane - enable a display plane on a given pipe
1811 * @dev_priv: i915 private structure
1812 * @plane: plane to enable
1813 * @pipe: pipe being fed
1815 * Enable @plane on @pipe, making sure that @pipe is running first.
1817 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1818 enum plane plane
, enum pipe pipe
)
1823 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1824 assert_pipe_enabled(dev_priv
, pipe
);
1826 reg
= DSPCNTR(plane
);
1827 val
= I915_READ(reg
);
1828 if (val
& DISPLAY_PLANE_ENABLE
)
1831 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1832 intel_flush_display_plane(dev_priv
, plane
);
1833 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1837 * intel_disable_plane - disable a display plane
1838 * @dev_priv: i915 private structure
1839 * @plane: plane to disable
1840 * @pipe: pipe consuming the data
1842 * Disable @plane; should be an independent operation.
1844 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1845 enum plane plane
, enum pipe pipe
)
1850 reg
= DSPCNTR(plane
);
1851 val
= I915_READ(reg
);
1852 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1855 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1856 intel_flush_display_plane(dev_priv
, plane
);
1857 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1860 static void disable_pch_dp(struct drm_i915_private
*dev_priv
,
1861 enum pipe pipe
, int reg
, u32 port_sel
)
1863 u32 val
= I915_READ(reg
);
1864 if (dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
)) {
1865 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg
, pipe
);
1866 I915_WRITE(reg
, val
& ~DP_PORT_EN
);
1870 static void disable_pch_hdmi(struct drm_i915_private
*dev_priv
,
1871 enum pipe pipe
, int reg
)
1873 u32 val
= I915_READ(reg
);
1874 if (hdmi_pipe_enabled(dev_priv
, val
, pipe
)) {
1875 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1877 I915_WRITE(reg
, val
& ~PORT_ENABLE
);
1881 /* Disable any ports connected to this transcoder */
1882 static void intel_disable_pch_ports(struct drm_i915_private
*dev_priv
,
1887 val
= I915_READ(PCH_PP_CONTROL
);
1888 I915_WRITE(PCH_PP_CONTROL
, val
| PANEL_UNLOCK_REGS
);
1890 disable_pch_dp(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1891 disable_pch_dp(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1892 disable_pch_dp(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1895 val
= I915_READ(reg
);
1896 if (adpa_pipe_enabled(dev_priv
, val
, pipe
))
1897 I915_WRITE(reg
, val
& ~ADPA_DAC_ENABLE
);
1900 val
= I915_READ(reg
);
1901 if (lvds_pipe_enabled(dev_priv
, val
, pipe
)) {
1902 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe
, val
);
1903 I915_WRITE(reg
, val
& ~LVDS_PORT_EN
);
1908 disable_pch_hdmi(dev_priv
, pipe
, HDMIB
);
1909 disable_pch_hdmi(dev_priv
, pipe
, HDMIC
);
1910 disable_pch_hdmi(dev_priv
, pipe
, HDMID
);
1914 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1915 struct drm_i915_gem_object
*obj
,
1916 struct intel_ring_buffer
*pipelined
)
1918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1922 switch (obj
->tiling_mode
) {
1923 case I915_TILING_NONE
:
1924 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1925 alignment
= 128 * 1024;
1926 else if (INTEL_INFO(dev
)->gen
>= 4)
1927 alignment
= 4 * 1024;
1929 alignment
= 64 * 1024;
1932 /* pin() will align the object as required by fence */
1936 /* FIXME: Is this true? */
1937 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1943 dev_priv
->mm
.interruptible
= false;
1944 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1946 goto err_interruptible
;
1948 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1949 * fence, whereas 965+ only requires a fence if using
1950 * framebuffer compression. For simplicity, we always install
1951 * a fence as the cost is not that onerous.
1953 ret
= i915_gem_object_get_fence(obj
);
1957 i915_gem_object_pin_fence(obj
);
1959 dev_priv
->mm
.interruptible
= true;
1963 i915_gem_object_unpin(obj
);
1965 dev_priv
->mm
.interruptible
= true;
1969 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1971 i915_gem_object_unpin_fence(obj
);
1972 i915_gem_object_unpin(obj
);
1975 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1976 * is assumed to be a power-of-two. */
1977 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x
, int *y
,
1981 int tile_rows
, tiles
;
1985 tiles
= *x
/ (512/bpp
);
1988 return tile_rows
* pitch
* 8 + tiles
* 4096;
1991 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1994 struct drm_device
*dev
= crtc
->dev
;
1995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1996 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1997 struct intel_framebuffer
*intel_fb
;
1998 struct drm_i915_gem_object
*obj
;
1999 int plane
= intel_crtc
->plane
;
2000 unsigned long linear_offset
;
2009 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2013 intel_fb
= to_intel_framebuffer(fb
);
2014 obj
= intel_fb
->obj
;
2016 reg
= DSPCNTR(plane
);
2017 dspcntr
= I915_READ(reg
);
2018 /* Mask out pixel format bits in case we change it */
2019 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2020 switch (fb
->bits_per_pixel
) {
2022 dspcntr
|= DISPPLANE_8BPP
;
2025 if (fb
->depth
== 15)
2026 dspcntr
|= DISPPLANE_15_16BPP
;
2028 dspcntr
|= DISPPLANE_16BPP
;
2032 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2035 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2038 if (INTEL_INFO(dev
)->gen
>= 4) {
2039 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2040 dspcntr
|= DISPPLANE_TILED
;
2042 dspcntr
&= ~DISPPLANE_TILED
;
2045 I915_WRITE(reg
, dspcntr
);
2047 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2049 if (INTEL_INFO(dev
)->gen
>= 4) {
2050 intel_crtc
->dspaddr_offset
=
2051 gen4_compute_dspaddr_offset_xtiled(&x
, &y
,
2052 fb
->bits_per_pixel
/ 8,
2054 linear_offset
-= intel_crtc
->dspaddr_offset
;
2056 intel_crtc
->dspaddr_offset
= linear_offset
;
2059 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2060 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2061 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2062 if (INTEL_INFO(dev
)->gen
>= 4) {
2063 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2064 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2065 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2066 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2068 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2074 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2075 struct drm_framebuffer
*fb
, int x
, int y
)
2077 struct drm_device
*dev
= crtc
->dev
;
2078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2079 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2080 struct intel_framebuffer
*intel_fb
;
2081 struct drm_i915_gem_object
*obj
;
2082 int plane
= intel_crtc
->plane
;
2083 unsigned long linear_offset
;
2093 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2097 intel_fb
= to_intel_framebuffer(fb
);
2098 obj
= intel_fb
->obj
;
2100 reg
= DSPCNTR(plane
);
2101 dspcntr
= I915_READ(reg
);
2102 /* Mask out pixel format bits in case we change it */
2103 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2104 switch (fb
->bits_per_pixel
) {
2106 dspcntr
|= DISPPLANE_8BPP
;
2109 if (fb
->depth
!= 16)
2112 dspcntr
|= DISPPLANE_16BPP
;
2116 if (fb
->depth
== 24)
2117 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2118 else if (fb
->depth
== 30)
2119 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
2124 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2128 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2129 dspcntr
|= DISPPLANE_TILED
;
2131 dspcntr
&= ~DISPPLANE_TILED
;
2134 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2136 I915_WRITE(reg
, dspcntr
);
2138 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2139 intel_crtc
->dspaddr_offset
=
2140 gen4_compute_dspaddr_offset_xtiled(&x
, &y
,
2141 fb
->bits_per_pixel
/ 8,
2143 linear_offset
-= intel_crtc
->dspaddr_offset
;
2145 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2146 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2147 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2148 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2149 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2150 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2151 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2157 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2159 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2160 int x
, int y
, enum mode_set_atomic state
)
2162 struct drm_device
*dev
= crtc
->dev
;
2163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2165 if (dev_priv
->display
.disable_fbc
)
2166 dev_priv
->display
.disable_fbc(dev
);
2167 intel_increase_pllclock(crtc
);
2169 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2173 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2175 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2176 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2177 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2180 wait_event(dev_priv
->pending_flip_queue
,
2181 atomic_read(&dev_priv
->mm
.wedged
) ||
2182 atomic_read(&obj
->pending_flip
) == 0);
2184 /* Big Hammer, we also need to ensure that any pending
2185 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2186 * current scanout is retired before unpinning the old
2189 * This should only fail upon a hung GPU, in which case we
2190 * can safely continue.
2192 dev_priv
->mm
.interruptible
= false;
2193 ret
= i915_gem_object_finish_gpu(obj
);
2194 dev_priv
->mm
.interruptible
= was_interruptible
;
2200 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2201 struct drm_framebuffer
*old_fb
)
2203 struct drm_device
*dev
= crtc
->dev
;
2204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2205 struct drm_i915_master_private
*master_priv
;
2206 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2211 DRM_ERROR("No FB bound\n");
2215 if(intel_crtc
->plane
> dev_priv
->num_pipe
) {
2216 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2218 dev_priv
->num_pipe
);
2222 mutex_lock(&dev
->struct_mutex
);
2223 ret
= intel_pin_and_fence_fb_obj(dev
,
2224 to_intel_framebuffer(crtc
->fb
)->obj
,
2227 mutex_unlock(&dev
->struct_mutex
);
2228 DRM_ERROR("pin & fence failed\n");
2233 intel_finish_fb(old_fb
);
2235 ret
= dev_priv
->display
.update_plane(crtc
, crtc
->fb
, x
, y
);
2237 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
2238 mutex_unlock(&dev
->struct_mutex
);
2239 DRM_ERROR("failed to update base address\n");
2244 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2245 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2248 intel_update_fbc(dev
);
2249 mutex_unlock(&dev
->struct_mutex
);
2251 if (!dev
->primary
->master
)
2254 master_priv
= dev
->primary
->master
->driver_priv
;
2255 if (!master_priv
->sarea_priv
)
2258 if (intel_crtc
->pipe
) {
2259 master_priv
->sarea_priv
->pipeB_x
= x
;
2260 master_priv
->sarea_priv
->pipeB_y
= y
;
2262 master_priv
->sarea_priv
->pipeA_x
= x
;
2263 master_priv
->sarea_priv
->pipeA_y
= y
;
2269 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2271 struct drm_device
*dev
= crtc
->dev
;
2272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2275 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2276 dpa_ctl
= I915_READ(DP_A
);
2277 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2279 if (clock
< 200000) {
2281 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2282 /* workaround for 160Mhz:
2283 1) program 0x4600c bits 15:0 = 0x8124
2284 2) program 0x46010 bit 0 = 1
2285 3) program 0x46034 bit 24 = 1
2286 4) program 0x64000 bit 14 = 1
2288 temp
= I915_READ(0x4600c);
2290 I915_WRITE(0x4600c, temp
| 0x8124);
2292 temp
= I915_READ(0x46010);
2293 I915_WRITE(0x46010, temp
| 1);
2295 temp
= I915_READ(0x46034);
2296 I915_WRITE(0x46034, temp
| (1 << 24));
2298 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2300 I915_WRITE(DP_A
, dpa_ctl
);
2306 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2308 struct drm_device
*dev
= crtc
->dev
;
2309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2311 int pipe
= intel_crtc
->pipe
;
2314 /* enable normal train */
2315 reg
= FDI_TX_CTL(pipe
);
2316 temp
= I915_READ(reg
);
2317 if (IS_IVYBRIDGE(dev
)) {
2318 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2319 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2321 temp
&= ~FDI_LINK_TRAIN_NONE
;
2322 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2324 I915_WRITE(reg
, temp
);
2326 reg
= FDI_RX_CTL(pipe
);
2327 temp
= I915_READ(reg
);
2328 if (HAS_PCH_CPT(dev
)) {
2329 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2330 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2332 temp
&= ~FDI_LINK_TRAIN_NONE
;
2333 temp
|= FDI_LINK_TRAIN_NONE
;
2335 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2337 /* wait one idle pattern time */
2341 /* IVB wants error correction enabled */
2342 if (IS_IVYBRIDGE(dev
))
2343 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2344 FDI_FE_ERRC_ENABLE
);
2347 static void cpt_phase_pointer_enable(struct drm_device
*dev
, int pipe
)
2349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2350 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2352 flags
|= FDI_PHASE_SYNC_OVR(pipe
);
2353 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to unlock... */
2354 flags
|= FDI_PHASE_SYNC_EN(pipe
);
2355 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to enable */
2356 POSTING_READ(SOUTH_CHICKEN1
);
2359 /* The FDI link training functions for ILK/Ibexpeak. */
2360 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2362 struct drm_device
*dev
= crtc
->dev
;
2363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2364 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2365 int pipe
= intel_crtc
->pipe
;
2366 int plane
= intel_crtc
->plane
;
2367 u32 reg
, temp
, tries
;
2369 /* FDI needs bits from pipe & plane first */
2370 assert_pipe_enabled(dev_priv
, pipe
);
2371 assert_plane_enabled(dev_priv
, plane
);
2373 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2375 reg
= FDI_RX_IMR(pipe
);
2376 temp
= I915_READ(reg
);
2377 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2378 temp
&= ~FDI_RX_BIT_LOCK
;
2379 I915_WRITE(reg
, temp
);
2383 /* enable CPU FDI TX and PCH FDI RX */
2384 reg
= FDI_TX_CTL(pipe
);
2385 temp
= I915_READ(reg
);
2387 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2388 temp
&= ~FDI_LINK_TRAIN_NONE
;
2389 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2390 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2392 reg
= FDI_RX_CTL(pipe
);
2393 temp
= I915_READ(reg
);
2394 temp
&= ~FDI_LINK_TRAIN_NONE
;
2395 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2396 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2401 /* Ironlake workaround, enable clock pointer after FDI enable*/
2402 if (HAS_PCH_IBX(dev
)) {
2403 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2404 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2405 FDI_RX_PHASE_SYNC_POINTER_EN
);
2408 reg
= FDI_RX_IIR(pipe
);
2409 for (tries
= 0; tries
< 5; tries
++) {
2410 temp
= I915_READ(reg
);
2411 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2413 if ((temp
& FDI_RX_BIT_LOCK
)) {
2414 DRM_DEBUG_KMS("FDI train 1 done.\n");
2415 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2420 DRM_ERROR("FDI train 1 fail!\n");
2423 reg
= FDI_TX_CTL(pipe
);
2424 temp
= I915_READ(reg
);
2425 temp
&= ~FDI_LINK_TRAIN_NONE
;
2426 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2427 I915_WRITE(reg
, temp
);
2429 reg
= FDI_RX_CTL(pipe
);
2430 temp
= I915_READ(reg
);
2431 temp
&= ~FDI_LINK_TRAIN_NONE
;
2432 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2433 I915_WRITE(reg
, temp
);
2438 reg
= FDI_RX_IIR(pipe
);
2439 for (tries
= 0; tries
< 5; tries
++) {
2440 temp
= I915_READ(reg
);
2441 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2443 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2444 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2445 DRM_DEBUG_KMS("FDI train 2 done.\n");
2450 DRM_ERROR("FDI train 2 fail!\n");
2452 DRM_DEBUG_KMS("FDI train done\n");
2456 static const int snb_b_fdi_train_param
[] = {
2457 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2458 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2459 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2460 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2463 /* The FDI link training functions for SNB/Cougarpoint. */
2464 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2466 struct drm_device
*dev
= crtc
->dev
;
2467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2468 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2469 int pipe
= intel_crtc
->pipe
;
2470 u32 reg
, temp
, i
, retry
;
2472 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2474 reg
= FDI_RX_IMR(pipe
);
2475 temp
= I915_READ(reg
);
2476 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2477 temp
&= ~FDI_RX_BIT_LOCK
;
2478 I915_WRITE(reg
, temp
);
2483 /* enable CPU FDI TX and PCH FDI RX */
2484 reg
= FDI_TX_CTL(pipe
);
2485 temp
= I915_READ(reg
);
2487 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2488 temp
&= ~FDI_LINK_TRAIN_NONE
;
2489 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2490 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2492 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2493 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2495 reg
= FDI_RX_CTL(pipe
);
2496 temp
= I915_READ(reg
);
2497 if (HAS_PCH_CPT(dev
)) {
2498 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2499 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2501 temp
&= ~FDI_LINK_TRAIN_NONE
;
2502 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2504 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2509 if (HAS_PCH_CPT(dev
))
2510 cpt_phase_pointer_enable(dev
, pipe
);
2512 for (i
= 0; i
< 4; i
++) {
2513 reg
= FDI_TX_CTL(pipe
);
2514 temp
= I915_READ(reg
);
2515 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2516 temp
|= snb_b_fdi_train_param
[i
];
2517 I915_WRITE(reg
, temp
);
2522 for (retry
= 0; retry
< 5; retry
++) {
2523 reg
= FDI_RX_IIR(pipe
);
2524 temp
= I915_READ(reg
);
2525 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2526 if (temp
& FDI_RX_BIT_LOCK
) {
2527 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2528 DRM_DEBUG_KMS("FDI train 1 done.\n");
2537 DRM_ERROR("FDI train 1 fail!\n");
2540 reg
= FDI_TX_CTL(pipe
);
2541 temp
= I915_READ(reg
);
2542 temp
&= ~FDI_LINK_TRAIN_NONE
;
2543 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2545 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2547 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2549 I915_WRITE(reg
, temp
);
2551 reg
= FDI_RX_CTL(pipe
);
2552 temp
= I915_READ(reg
);
2553 if (HAS_PCH_CPT(dev
)) {
2554 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2555 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2557 temp
&= ~FDI_LINK_TRAIN_NONE
;
2558 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2560 I915_WRITE(reg
, temp
);
2565 for (i
= 0; i
< 4; i
++) {
2566 reg
= FDI_TX_CTL(pipe
);
2567 temp
= I915_READ(reg
);
2568 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2569 temp
|= snb_b_fdi_train_param
[i
];
2570 I915_WRITE(reg
, temp
);
2575 for (retry
= 0; retry
< 5; retry
++) {
2576 reg
= FDI_RX_IIR(pipe
);
2577 temp
= I915_READ(reg
);
2578 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2579 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2580 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2581 DRM_DEBUG_KMS("FDI train 2 done.\n");
2590 DRM_ERROR("FDI train 2 fail!\n");
2592 DRM_DEBUG_KMS("FDI train done.\n");
2595 /* Manual link training for Ivy Bridge A0 parts */
2596 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2598 struct drm_device
*dev
= crtc
->dev
;
2599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2600 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2601 int pipe
= intel_crtc
->pipe
;
2604 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2606 reg
= FDI_RX_IMR(pipe
);
2607 temp
= I915_READ(reg
);
2608 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2609 temp
&= ~FDI_RX_BIT_LOCK
;
2610 I915_WRITE(reg
, temp
);
2615 /* enable CPU FDI TX and PCH FDI RX */
2616 reg
= FDI_TX_CTL(pipe
);
2617 temp
= I915_READ(reg
);
2619 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2620 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2621 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2622 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2623 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2624 temp
|= FDI_COMPOSITE_SYNC
;
2625 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2627 reg
= FDI_RX_CTL(pipe
);
2628 temp
= I915_READ(reg
);
2629 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2630 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2631 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2632 temp
|= FDI_COMPOSITE_SYNC
;
2633 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2638 if (HAS_PCH_CPT(dev
))
2639 cpt_phase_pointer_enable(dev
, pipe
);
2641 for (i
= 0; i
< 4; i
++) {
2642 reg
= FDI_TX_CTL(pipe
);
2643 temp
= I915_READ(reg
);
2644 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2645 temp
|= snb_b_fdi_train_param
[i
];
2646 I915_WRITE(reg
, temp
);
2651 reg
= FDI_RX_IIR(pipe
);
2652 temp
= I915_READ(reg
);
2653 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2655 if (temp
& FDI_RX_BIT_LOCK
||
2656 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2657 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2658 DRM_DEBUG_KMS("FDI train 1 done.\n");
2663 DRM_ERROR("FDI train 1 fail!\n");
2666 reg
= FDI_TX_CTL(pipe
);
2667 temp
= I915_READ(reg
);
2668 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2669 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2670 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2671 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2672 I915_WRITE(reg
, temp
);
2674 reg
= FDI_RX_CTL(pipe
);
2675 temp
= I915_READ(reg
);
2676 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2677 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2678 I915_WRITE(reg
, temp
);
2683 for (i
= 0; i
< 4; i
++) {
2684 reg
= FDI_TX_CTL(pipe
);
2685 temp
= I915_READ(reg
);
2686 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2687 temp
|= snb_b_fdi_train_param
[i
];
2688 I915_WRITE(reg
, temp
);
2693 reg
= FDI_RX_IIR(pipe
);
2694 temp
= I915_READ(reg
);
2695 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2697 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2698 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2699 DRM_DEBUG_KMS("FDI train 2 done.\n");
2704 DRM_ERROR("FDI train 2 fail!\n");
2706 DRM_DEBUG_KMS("FDI train done.\n");
2709 static void ironlake_fdi_pll_enable(struct drm_crtc
*crtc
)
2711 struct drm_device
*dev
= crtc
->dev
;
2712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2713 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2714 int pipe
= intel_crtc
->pipe
;
2717 /* Write the TU size bits so error detection works */
2718 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2719 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2721 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2722 reg
= FDI_RX_CTL(pipe
);
2723 temp
= I915_READ(reg
);
2724 temp
&= ~((0x7 << 19) | (0x7 << 16));
2725 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2726 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2727 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2732 /* Switch from Rawclk to PCDclk */
2733 temp
= I915_READ(reg
);
2734 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2739 /* On Haswell, the PLL configuration for ports and pipes is handled
2740 * separately, as part of DDI setup */
2741 if (!IS_HASWELL(dev
)) {
2742 /* Enable CPU FDI TX PLL, always on for Ironlake */
2743 reg
= FDI_TX_CTL(pipe
);
2744 temp
= I915_READ(reg
);
2745 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2746 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2754 static void cpt_phase_pointer_disable(struct drm_device
*dev
, int pipe
)
2756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2757 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2759 flags
&= ~(FDI_PHASE_SYNC_EN(pipe
));
2760 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to disable... */
2761 flags
&= ~(FDI_PHASE_SYNC_OVR(pipe
));
2762 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to lock */
2763 POSTING_READ(SOUTH_CHICKEN1
);
2765 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2767 struct drm_device
*dev
= crtc
->dev
;
2768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2769 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2770 int pipe
= intel_crtc
->pipe
;
2773 /* disable CPU FDI tx and PCH FDI rx */
2774 reg
= FDI_TX_CTL(pipe
);
2775 temp
= I915_READ(reg
);
2776 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2779 reg
= FDI_RX_CTL(pipe
);
2780 temp
= I915_READ(reg
);
2781 temp
&= ~(0x7 << 16);
2782 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2783 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2788 /* Ironlake workaround, disable clock pointer after downing FDI */
2789 if (HAS_PCH_IBX(dev
)) {
2790 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2791 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2792 I915_READ(FDI_RX_CHICKEN(pipe
) &
2793 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2794 } else if (HAS_PCH_CPT(dev
)) {
2795 cpt_phase_pointer_disable(dev
, pipe
);
2798 /* still set train pattern 1 */
2799 reg
= FDI_TX_CTL(pipe
);
2800 temp
= I915_READ(reg
);
2801 temp
&= ~FDI_LINK_TRAIN_NONE
;
2802 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2803 I915_WRITE(reg
, temp
);
2805 reg
= FDI_RX_CTL(pipe
);
2806 temp
= I915_READ(reg
);
2807 if (HAS_PCH_CPT(dev
)) {
2808 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2809 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2811 temp
&= ~FDI_LINK_TRAIN_NONE
;
2812 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2814 /* BPC in FDI rx is consistent with that in PIPECONF */
2815 temp
&= ~(0x07 << 16);
2816 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2817 I915_WRITE(reg
, temp
);
2823 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2825 struct drm_device
*dev
= crtc
->dev
;
2827 if (crtc
->fb
== NULL
)
2830 mutex_lock(&dev
->struct_mutex
);
2831 intel_finish_fb(crtc
->fb
);
2832 mutex_unlock(&dev
->struct_mutex
);
2835 static bool intel_crtc_driving_pch(struct drm_crtc
*crtc
)
2837 struct drm_device
*dev
= crtc
->dev
;
2838 struct intel_encoder
*encoder
;
2841 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2842 * must be driven by its own crtc; no sharing is possible.
2844 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
2846 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2847 * CPU handles all others */
2848 if (IS_HASWELL(dev
)) {
2849 /* It is still unclear how this will work on PPT, so throw up a warning */
2850 WARN_ON(!HAS_PCH_LPT(dev
));
2852 if (encoder
->type
== DRM_MODE_ENCODER_DAC
) {
2853 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2856 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2862 switch (encoder
->type
) {
2863 case INTEL_OUTPUT_EDP
:
2864 if (!intel_encoder_is_pch_edp(&encoder
->base
))
2873 /* Program iCLKIP clock to the desired frequency */
2874 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2876 struct drm_device
*dev
= crtc
->dev
;
2877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2878 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2881 /* It is necessary to ungate the pixclk gate prior to programming
2882 * the divisors, and gate it back when it is done.
2884 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2886 /* Disable SSCCTL */
2887 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2888 intel_sbi_read(dev_priv
, SBI_SSCCTL6
) |
2889 SBI_SSCCTL_DISABLE
);
2891 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2892 if (crtc
->mode
.clock
== 20000) {
2897 /* The iCLK virtual clock root frequency is in MHz,
2898 * but the crtc->mode.clock in in KHz. To get the divisors,
2899 * it is necessary to divide one by another, so we
2900 * convert the virtual clock precision to KHz here for higher
2903 u32 iclk_virtual_root_freq
= 172800 * 1000;
2904 u32 iclk_pi_range
= 64;
2905 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2907 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2908 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2909 pi_value
= desired_divisor
% iclk_pi_range
;
2912 divsel
= msb_divisor_value
- 2;
2913 phaseinc
= pi_value
;
2916 /* This should not happen with any sane values */
2917 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2918 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2919 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2920 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2922 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2929 /* Program SSCDIVINTPHASE6 */
2930 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
);
2931 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2932 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2933 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2934 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2935 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2936 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2938 intel_sbi_write(dev_priv
,
2939 SBI_SSCDIVINTPHASE6
,
2942 /* Program SSCAUXDIV */
2943 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
);
2944 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2945 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2946 intel_sbi_write(dev_priv
,
2951 /* Enable modulator and associated divider */
2952 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
);
2953 temp
&= ~SBI_SSCCTL_DISABLE
;
2954 intel_sbi_write(dev_priv
,
2958 /* Wait for initialization time */
2961 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2965 * Enable PCH resources required for PCH ports:
2967 * - FDI training & RX/TX
2968 * - update transcoder timings
2969 * - DP transcoding bits
2972 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2974 struct drm_device
*dev
= crtc
->dev
;
2975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2976 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2977 int pipe
= intel_crtc
->pipe
;
2980 assert_transcoder_disabled(dev_priv
, pipe
);
2982 /* For PCH output, training FDI link */
2983 dev_priv
->display
.fdi_link_train(crtc
);
2985 intel_enable_pch_pll(intel_crtc
);
2987 if (HAS_PCH_LPT(dev
)) {
2988 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2989 lpt_program_iclkip(crtc
);
2990 } else if (HAS_PCH_CPT(dev
)) {
2993 temp
= I915_READ(PCH_DPLL_SEL
);
2997 temp
|= TRANSA_DPLL_ENABLE
;
2998 sel
= TRANSA_DPLLB_SEL
;
3001 temp
|= TRANSB_DPLL_ENABLE
;
3002 sel
= TRANSB_DPLLB_SEL
;
3005 temp
|= TRANSC_DPLL_ENABLE
;
3006 sel
= TRANSC_DPLLB_SEL
;
3009 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3013 I915_WRITE(PCH_DPLL_SEL
, temp
);
3016 /* set transcoder timing, panel must allow it */
3017 assert_panel_unlocked(dev_priv
, pipe
);
3018 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3019 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3020 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3022 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3023 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3024 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3025 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3027 if (!IS_HASWELL(dev
))
3028 intel_fdi_normal_train(crtc
);
3030 /* For PCH DP, enable TRANS_DP_CTL */
3031 if (HAS_PCH_CPT(dev
) &&
3032 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3033 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3034 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) >> 5;
3035 reg
= TRANS_DP_CTL(pipe
);
3036 temp
= I915_READ(reg
);
3037 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3038 TRANS_DP_SYNC_MASK
|
3040 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3041 TRANS_DP_ENH_FRAMING
);
3042 temp
|= bpc
<< 9; /* same format but at 11:9 */
3044 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3045 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3046 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3047 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3049 switch (intel_trans_dp_port_sel(crtc
)) {
3051 temp
|= TRANS_DP_PORT_SEL_B
;
3054 temp
|= TRANS_DP_PORT_SEL_C
;
3057 temp
|= TRANS_DP_PORT_SEL_D
;
3060 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3061 temp
|= TRANS_DP_PORT_SEL_B
;
3065 I915_WRITE(reg
, temp
);
3068 intel_enable_transcoder(dev_priv
, pipe
);
3071 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3073 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3078 if (pll
->refcount
== 0) {
3079 WARN(1, "bad PCH PLL refcount\n");
3084 intel_crtc
->pch_pll
= NULL
;
3087 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3089 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3090 struct intel_pch_pll
*pll
;
3093 pll
= intel_crtc
->pch_pll
;
3095 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3096 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3100 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3101 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3102 i
= intel_crtc
->pipe
;
3103 pll
= &dev_priv
->pch_plls
[i
];
3105 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3106 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3111 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3112 pll
= &dev_priv
->pch_plls
[i
];
3114 /* Only want to check enabled timings first */
3115 if (pll
->refcount
== 0)
3118 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3119 fp
== I915_READ(pll
->fp0_reg
)) {
3120 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3121 intel_crtc
->base
.base
.id
,
3122 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3128 /* Ok no matching timings, maybe there's a free one? */
3129 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3130 pll
= &dev_priv
->pch_plls
[i
];
3131 if (pll
->refcount
== 0) {
3132 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3133 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3141 intel_crtc
->pch_pll
= pll
;
3143 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3144 prepare
: /* separate function? */
3145 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3147 /* Wait for the clocks to stabilize before rewriting the regs */
3148 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3149 POSTING_READ(pll
->pll_reg
);
3152 I915_WRITE(pll
->fp0_reg
, fp
);
3153 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3158 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3161 int dslreg
= PIPEDSL(pipe
), tc2reg
= TRANS_CHICKEN2(pipe
);
3164 temp
= I915_READ(dslreg
);
3166 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3167 /* Without this, mode sets may fail silently on FDI */
3168 I915_WRITE(tc2reg
, TRANS_AUTOTRAIN_GEN_STALL_DIS
);
3170 I915_WRITE(tc2reg
, 0);
3171 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3172 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3176 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3178 struct drm_device
*dev
= crtc
->dev
;
3179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3180 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3181 int pipe
= intel_crtc
->pipe
;
3182 int plane
= intel_crtc
->plane
;
3186 if (intel_crtc
->active
)
3189 intel_crtc
->active
= true;
3190 intel_update_watermarks(dev
);
3192 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3193 temp
= I915_READ(PCH_LVDS
);
3194 if ((temp
& LVDS_PORT_EN
) == 0)
3195 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3198 is_pch_port
= intel_crtc_driving_pch(crtc
);
3201 ironlake_fdi_pll_enable(crtc
);
3203 ironlake_fdi_disable(crtc
);
3205 /* Enable panel fitting for LVDS */
3206 if (dev_priv
->pch_pf_size
&&
3207 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
3208 /* Force use of hard-coded filter coefficients
3209 * as some pre-programmed values are broken,
3212 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3213 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3214 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3218 * On ILK+ LUT must be loaded before the pipe is running but with
3221 intel_crtc_load_lut(crtc
);
3223 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3224 intel_enable_plane(dev_priv
, plane
, pipe
);
3227 ironlake_pch_enable(crtc
);
3229 mutex_lock(&dev
->struct_mutex
);
3230 intel_update_fbc(dev
);
3231 mutex_unlock(&dev
->struct_mutex
);
3233 intel_crtc_update_cursor(crtc
, true);
3236 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3238 struct drm_device
*dev
= crtc
->dev
;
3239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3240 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3241 int pipe
= intel_crtc
->pipe
;
3242 int plane
= intel_crtc
->plane
;
3245 if (!intel_crtc
->active
)
3248 intel_crtc_wait_for_pending_flips(crtc
);
3249 drm_vblank_off(dev
, pipe
);
3250 intel_crtc_update_cursor(crtc
, false);
3252 intel_disable_plane(dev_priv
, plane
, pipe
);
3254 if (dev_priv
->cfb_plane
== plane
)
3255 intel_disable_fbc(dev
);
3257 intel_disable_pipe(dev_priv
, pipe
);
3260 I915_WRITE(PF_CTL(pipe
), 0);
3261 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3263 ironlake_fdi_disable(crtc
);
3265 /* This is a horrible layering violation; we should be doing this in
3266 * the connector/encoder ->prepare instead, but we don't always have
3267 * enough information there about the config to know whether it will
3268 * actually be necessary or just cause undesired flicker.
3270 intel_disable_pch_ports(dev_priv
, pipe
);
3272 intel_disable_transcoder(dev_priv
, pipe
);
3274 if (HAS_PCH_CPT(dev
)) {
3275 /* disable TRANS_DP_CTL */
3276 reg
= TRANS_DP_CTL(pipe
);
3277 temp
= I915_READ(reg
);
3278 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3279 temp
|= TRANS_DP_PORT_SEL_NONE
;
3280 I915_WRITE(reg
, temp
);
3282 /* disable DPLL_SEL */
3283 temp
= I915_READ(PCH_DPLL_SEL
);
3286 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3289 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3292 /* C shares PLL A or B */
3293 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3298 I915_WRITE(PCH_DPLL_SEL
, temp
);
3301 /* disable PCH DPLL */
3302 intel_disable_pch_pll(intel_crtc
);
3304 /* Switch from PCDclk to Rawclk */
3305 reg
= FDI_RX_CTL(pipe
);
3306 temp
= I915_READ(reg
);
3307 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3309 /* Disable CPU FDI TX PLL */
3310 reg
= FDI_TX_CTL(pipe
);
3311 temp
= I915_READ(reg
);
3312 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3317 reg
= FDI_RX_CTL(pipe
);
3318 temp
= I915_READ(reg
);
3319 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3321 /* Wait for the clocks to turn off. */
3325 intel_crtc
->active
= false;
3326 intel_update_watermarks(dev
);
3328 mutex_lock(&dev
->struct_mutex
);
3329 intel_update_fbc(dev
);
3330 mutex_unlock(&dev
->struct_mutex
);
3333 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3335 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3336 int pipe
= intel_crtc
->pipe
;
3337 int plane
= intel_crtc
->plane
;
3339 /* XXX: When our outputs are all unaware of DPMS modes other than off
3340 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3343 case DRM_MODE_DPMS_ON
:
3344 case DRM_MODE_DPMS_STANDBY
:
3345 case DRM_MODE_DPMS_SUSPEND
:
3346 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
3347 ironlake_crtc_enable(crtc
);
3350 case DRM_MODE_DPMS_OFF
:
3351 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
3352 ironlake_crtc_disable(crtc
);
3357 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3359 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3360 intel_put_pch_pll(intel_crtc
);
3363 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3365 if (!enable
&& intel_crtc
->overlay
) {
3366 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3369 mutex_lock(&dev
->struct_mutex
);
3370 dev_priv
->mm
.interruptible
= false;
3371 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3372 dev_priv
->mm
.interruptible
= true;
3373 mutex_unlock(&dev
->struct_mutex
);
3376 /* Let userspace switch the overlay on again. In most cases userspace
3377 * has to recompute where to put it anyway.
3381 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3383 struct drm_device
*dev
= crtc
->dev
;
3384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3385 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3386 int pipe
= intel_crtc
->pipe
;
3387 int plane
= intel_crtc
->plane
;
3389 if (intel_crtc
->active
)
3392 intel_crtc
->active
= true;
3393 intel_update_watermarks(dev
);
3395 intel_enable_pll(dev_priv
, pipe
);
3396 intel_enable_pipe(dev_priv
, pipe
, false);
3397 intel_enable_plane(dev_priv
, plane
, pipe
);
3399 intel_crtc_load_lut(crtc
);
3400 intel_update_fbc(dev
);
3402 /* Give the overlay scaler a chance to enable if it's on this pipe */
3403 intel_crtc_dpms_overlay(intel_crtc
, true);
3404 intel_crtc_update_cursor(crtc
, true);
3407 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3409 struct drm_device
*dev
= crtc
->dev
;
3410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3411 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3412 int pipe
= intel_crtc
->pipe
;
3413 int plane
= intel_crtc
->plane
;
3415 if (!intel_crtc
->active
)
3418 /* Give the overlay scaler a chance to disable if it's on this pipe */
3419 intel_crtc_wait_for_pending_flips(crtc
);
3420 drm_vblank_off(dev
, pipe
);
3421 intel_crtc_dpms_overlay(intel_crtc
, false);
3422 intel_crtc_update_cursor(crtc
, false);
3424 if (dev_priv
->cfb_plane
== plane
)
3425 intel_disable_fbc(dev
);
3427 intel_disable_plane(dev_priv
, plane
, pipe
);
3428 intel_disable_pipe(dev_priv
, pipe
);
3429 intel_disable_pll(dev_priv
, pipe
);
3431 intel_crtc
->active
= false;
3432 intel_update_fbc(dev
);
3433 intel_update_watermarks(dev
);
3436 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3438 /* XXX: When our outputs are all unaware of DPMS modes other than off
3439 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3442 case DRM_MODE_DPMS_ON
:
3443 case DRM_MODE_DPMS_STANDBY
:
3444 case DRM_MODE_DPMS_SUSPEND
:
3445 i9xx_crtc_enable(crtc
);
3447 case DRM_MODE_DPMS_OFF
:
3448 i9xx_crtc_disable(crtc
);
3453 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3458 * Sets the power management mode of the pipe and plane.
3460 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3462 struct drm_device
*dev
= crtc
->dev
;
3463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3464 struct drm_i915_master_private
*master_priv
;
3465 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3466 int pipe
= intel_crtc
->pipe
;
3469 if (intel_crtc
->dpms_mode
== mode
)
3472 intel_crtc
->dpms_mode
= mode
;
3474 dev_priv
->display
.dpms(crtc
, mode
);
3476 if (!dev
->primary
->master
)
3479 master_priv
= dev
->primary
->master
->driver_priv
;
3480 if (!master_priv
->sarea_priv
)
3483 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
3487 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3488 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3491 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3492 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3495 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3500 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3502 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3503 struct drm_device
*dev
= crtc
->dev
;
3504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3506 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
3507 dev_priv
->display
.off(crtc
);
3509 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3510 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3513 mutex_lock(&dev
->struct_mutex
);
3514 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3515 mutex_unlock(&dev
->struct_mutex
);
3519 /* Prepare for a mode set.
3521 * Note we could be a lot smarter here. We need to figure out which outputs
3522 * will be enabled, which disabled (in short, how the config will changes)
3523 * and perform the minimum necessary steps to accomplish that, e.g. updating
3524 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3525 * panel fitting is in the proper state, etc.
3527 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
3529 i9xx_crtc_disable(crtc
);
3532 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
3534 i9xx_crtc_enable(crtc
);
3537 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
3539 ironlake_crtc_disable(crtc
);
3542 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
3544 ironlake_crtc_enable(crtc
);
3547 void intel_encoder_prepare(struct drm_encoder
*encoder
)
3549 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3550 /* lvds has its own version of prepare see intel_lvds_prepare */
3551 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
3554 void intel_encoder_commit(struct drm_encoder
*encoder
)
3556 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3557 struct drm_device
*dev
= encoder
->dev
;
3558 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
3560 /* lvds has its own version of commit see intel_lvds_commit */
3561 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3563 if (HAS_PCH_CPT(dev
))
3564 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3567 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3569 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3571 drm_encoder_cleanup(encoder
);
3572 kfree(intel_encoder
);
3575 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3576 const struct drm_display_mode
*mode
,
3577 struct drm_display_mode
*adjusted_mode
)
3579 struct drm_device
*dev
= crtc
->dev
;
3581 if (HAS_PCH_SPLIT(dev
)) {
3582 /* FDI link clock is fixed at 2.7G */
3583 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3587 /* All interlaced capable intel hw wants timings in frames. Note though
3588 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3589 * timings, so we need to be careful not to clobber these.*/
3590 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3591 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3596 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3598 return 400000; /* FIXME */
3601 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3606 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3611 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3616 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3620 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3622 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3625 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3626 case GC_DISPLAY_CLOCK_333_MHZ
:
3629 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3635 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3640 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3643 /* Assume that the hardware is in the high speed state. This
3644 * should be the default.
3646 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3647 case GC_CLOCK_133_200
:
3648 case GC_CLOCK_100_200
:
3650 case GC_CLOCK_166_250
:
3652 case GC_CLOCK_100_133
:
3656 /* Shouldn't happen */
3660 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3674 fdi_reduce_ratio(u32
*num
, u32
*den
)
3676 while (*num
> 0xffffff || *den
> 0xffffff) {
3683 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3684 int link_clock
, struct fdi_m_n
*m_n
)
3686 m_n
->tu
= 64; /* default size */
3688 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3689 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3690 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3691 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3693 m_n
->link_m
= pixel_clock
;
3694 m_n
->link_n
= link_clock
;
3695 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3698 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
3700 if (i915_panel_use_ssc
>= 0)
3701 return i915_panel_use_ssc
!= 0;
3702 return dev_priv
->lvds_use_ssc
3703 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
3707 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3708 * @crtc: CRTC structure
3709 * @mode: requested mode
3711 * A pipe may be connected to one or more outputs. Based on the depth of the
3712 * attached framebuffer, choose a good color depth to use on the pipe.
3714 * If possible, match the pipe depth to the fb depth. In some cases, this
3715 * isn't ideal, because the connected output supports a lesser or restricted
3716 * set of depths. Resolve that here:
3717 * LVDS typically supports only 6bpc, so clamp down in that case
3718 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3719 * Displays may support a restricted set as well, check EDID and clamp as
3721 * DP may want to dither down to 6bpc to fit larger modes
3724 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3725 * true if they don't match).
3727 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
3728 unsigned int *pipe_bpp
,
3729 struct drm_display_mode
*mode
)
3731 struct drm_device
*dev
= crtc
->dev
;
3732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3733 struct drm_connector
*connector
;
3734 struct intel_encoder
*intel_encoder
;
3735 unsigned int display_bpc
= UINT_MAX
, bpc
;
3737 /* Walk the encoders & connectors on this crtc, get min bpc */
3738 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3740 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
3741 unsigned int lvds_bpc
;
3743 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
3749 if (lvds_bpc
< display_bpc
) {
3750 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
3751 display_bpc
= lvds_bpc
;
3756 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
3757 /* Use VBT settings if we have an eDP panel */
3758 unsigned int edp_bpc
= dev_priv
->edp
.bpp
/ 3;
3760 if (edp_bpc
< display_bpc
) {
3761 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc
, edp_bpc
);
3762 display_bpc
= edp_bpc
;
3767 /* Not one of the known troublemakers, check the EDID */
3768 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
3770 if (connector
->encoder
!= &intel_encoder
->base
)
3773 /* Don't use an invalid EDID bpc value */
3774 if (connector
->display_info
.bpc
&&
3775 connector
->display_info
.bpc
< display_bpc
) {
3776 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
3777 display_bpc
= connector
->display_info
.bpc
;
3782 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3783 * through, clamp it down. (Note: >12bpc will be caught below.)
3785 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
3786 if (display_bpc
> 8 && display_bpc
< 12) {
3787 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3790 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3796 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
3797 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3802 * We could just drive the pipe at the highest bpc all the time and
3803 * enable dithering as needed, but that costs bandwidth. So choose
3804 * the minimum value that expresses the full color range of the fb but
3805 * also stays within the max display bpc discovered above.
3808 switch (crtc
->fb
->depth
) {
3810 bpc
= 8; /* since we go through a colormap */
3814 bpc
= 6; /* min is 18bpp */
3826 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3827 bpc
= min((unsigned int)8, display_bpc
);
3831 display_bpc
= min(display_bpc
, bpc
);
3833 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3836 *pipe_bpp
= display_bpc
* 3;
3838 return display_bpc
!= bpc
;
3841 static int vlv_get_refclk(struct drm_crtc
*crtc
)
3843 struct drm_device
*dev
= crtc
->dev
;
3844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3845 int refclk
= 27000; /* for DP & HDMI */
3847 return 100000; /* only one validated so far */
3849 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
3851 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3852 if (intel_panel_use_ssc(dev_priv
))
3856 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3863 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
3865 struct drm_device
*dev
= crtc
->dev
;
3866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3869 if (IS_VALLEYVIEW(dev
)) {
3870 refclk
= vlv_get_refclk(crtc
);
3871 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3872 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
3873 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3874 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3876 } else if (!IS_GEN2(dev
)) {
3885 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
3886 intel_clock_t
*clock
)
3888 /* SDVO TV has fixed PLL values depend on its clock range,
3889 this mirrors vbios setting. */
3890 if (adjusted_mode
->clock
>= 100000
3891 && adjusted_mode
->clock
< 140500) {
3897 } else if (adjusted_mode
->clock
>= 140500
3898 && adjusted_mode
->clock
<= 200000) {
3907 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
3908 intel_clock_t
*clock
,
3909 intel_clock_t
*reduced_clock
)
3911 struct drm_device
*dev
= crtc
->dev
;
3912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3913 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3914 int pipe
= intel_crtc
->pipe
;
3917 if (IS_PINEVIEW(dev
)) {
3918 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
3920 fp2
= (1 << reduced_clock
->n
) << 16 |
3921 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
3923 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
3925 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
3929 I915_WRITE(FP0(pipe
), fp
);
3931 intel_crtc
->lowfreq_avail
= false;
3932 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3933 reduced_clock
&& i915_powersave
) {
3934 I915_WRITE(FP1(pipe
), fp2
);
3935 intel_crtc
->lowfreq_avail
= true;
3937 I915_WRITE(FP1(pipe
), fp
);
3941 static void intel_update_lvds(struct drm_crtc
*crtc
, intel_clock_t
*clock
,
3942 struct drm_display_mode
*adjusted_mode
)
3944 struct drm_device
*dev
= crtc
->dev
;
3945 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3946 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3947 int pipe
= intel_crtc
->pipe
;
3950 temp
= I915_READ(LVDS
);
3951 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
3953 temp
|= LVDS_PIPEB_SELECT
;
3955 temp
&= ~LVDS_PIPEB_SELECT
;
3957 /* set the corresponsding LVDS_BORDER bit */
3958 temp
|= dev_priv
->lvds_border_bits
;
3959 /* Set the B0-B3 data pairs corresponding to whether we're going to
3960 * set the DPLLs for dual-channel mode or not.
3963 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3965 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3967 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3968 * appropriately here, but we need to look more thoroughly into how
3969 * panels behave in the two modes.
3971 /* set the dithering flag on LVDS as needed */
3972 if (INTEL_INFO(dev
)->gen
>= 4) {
3973 if (dev_priv
->lvds_dither
)
3974 temp
|= LVDS_ENABLE_DITHER
;
3976 temp
&= ~LVDS_ENABLE_DITHER
;
3978 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
3979 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
3980 temp
|= LVDS_HSYNC_POLARITY
;
3981 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
3982 temp
|= LVDS_VSYNC_POLARITY
;
3983 I915_WRITE(LVDS
, temp
);
3986 static void vlv_update_pll(struct drm_crtc
*crtc
,
3987 struct drm_display_mode
*mode
,
3988 struct drm_display_mode
*adjusted_mode
,
3989 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
3990 int refclk
, int num_connectors
)
3992 struct drm_device
*dev
= crtc
->dev
;
3993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3994 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3995 int pipe
= intel_crtc
->pipe
;
3996 u32 dpll
, mdiv
, pdiv
;
3997 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4000 is_hdmi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4008 /* Enable DPIO clock input */
4009 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4010 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4011 I915_WRITE(DPLL(pipe
), dpll
);
4012 POSTING_READ(DPLL(pipe
));
4014 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4015 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4016 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4017 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4018 mdiv
|= (1 << DPIO_K_SHIFT
);
4019 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4020 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4022 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4024 pdiv
= DPIO_REFSEL_OVERRIDE
| (5 << DPIO_PLL_MODESEL_SHIFT
) |
4025 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4026 (8 << DPIO_DRIVER_CTL_SHIFT
) | (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4027 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4029 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x009f0051);
4031 dpll
|= DPLL_VCO_ENABLE
;
4032 I915_WRITE(DPLL(pipe
), dpll
);
4033 POSTING_READ(DPLL(pipe
));
4034 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4035 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4038 u32 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4041 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4045 I915_WRITE(DPLL_MD(pipe
), temp
);
4046 POSTING_READ(DPLL_MD(pipe
));
4049 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x641); /* ??? */
4052 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4053 struct drm_display_mode
*mode
,
4054 struct drm_display_mode
*adjusted_mode
,
4055 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4058 struct drm_device
*dev
= crtc
->dev
;
4059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4060 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4061 int pipe
= intel_crtc
->pipe
;
4065 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4066 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4068 dpll
= DPLL_VGA_MODE_DIS
;
4070 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4071 dpll
|= DPLLB_MODE_LVDS
;
4073 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4075 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4076 if (pixel_multiplier
> 1) {
4077 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4078 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4080 dpll
|= DPLL_DVO_HIGH_SPEED
;
4082 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4083 dpll
|= DPLL_DVO_HIGH_SPEED
;
4085 /* compute bitmask from p1 value */
4086 if (IS_PINEVIEW(dev
))
4087 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4089 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4090 if (IS_G4X(dev
) && reduced_clock
)
4091 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4093 switch (clock
->p2
) {
4095 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4098 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4101 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4104 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4107 if (INTEL_INFO(dev
)->gen
>= 4)
4108 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4110 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4111 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4112 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4113 /* XXX: just matching BIOS for now */
4114 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4116 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4117 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4118 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4120 dpll
|= PLL_REF_INPUT_DREFCLK
;
4122 dpll
|= DPLL_VCO_ENABLE
;
4123 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4124 POSTING_READ(DPLL(pipe
));
4127 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4128 * This is an exception to the general rule that mode_set doesn't turn
4131 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4132 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4134 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4135 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4137 I915_WRITE(DPLL(pipe
), dpll
);
4139 /* Wait for the clocks to stabilize. */
4140 POSTING_READ(DPLL(pipe
));
4143 if (INTEL_INFO(dev
)->gen
>= 4) {
4146 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4148 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4152 I915_WRITE(DPLL_MD(pipe
), temp
);
4154 /* The pixel multiplier can only be updated once the
4155 * DPLL is enabled and the clocks are stable.
4157 * So write it again.
4159 I915_WRITE(DPLL(pipe
), dpll
);
4163 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4164 struct drm_display_mode
*adjusted_mode
,
4165 intel_clock_t
*clock
,
4168 struct drm_device
*dev
= crtc
->dev
;
4169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4170 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4171 int pipe
= intel_crtc
->pipe
;
4174 dpll
= DPLL_VGA_MODE_DIS
;
4176 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4177 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4180 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4182 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4184 dpll
|= PLL_P2_DIVIDE_BY_4
;
4187 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4188 /* XXX: just matching BIOS for now */
4189 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4191 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4192 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4193 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4195 dpll
|= PLL_REF_INPUT_DREFCLK
;
4197 dpll
|= DPLL_VCO_ENABLE
;
4198 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4199 POSTING_READ(DPLL(pipe
));
4202 I915_WRITE(DPLL(pipe
), dpll
);
4204 /* Wait for the clocks to stabilize. */
4205 POSTING_READ(DPLL(pipe
));
4208 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4209 * This is an exception to the general rule that mode_set doesn't turn
4212 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4213 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4215 /* The pixel multiplier can only be updated once the
4216 * DPLL is enabled and the clocks are stable.
4218 * So write it again.
4220 I915_WRITE(DPLL(pipe
), dpll
);
4223 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4224 struct drm_display_mode
*mode
,
4225 struct drm_display_mode
*adjusted_mode
,
4227 struct drm_framebuffer
*old_fb
)
4229 struct drm_device
*dev
= crtc
->dev
;
4230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4231 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4232 int pipe
= intel_crtc
->pipe
;
4233 int plane
= intel_crtc
->plane
;
4234 int refclk
, num_connectors
= 0;
4235 intel_clock_t clock
, reduced_clock
;
4236 u32 dspcntr
, pipeconf
, vsyncshift
;
4237 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4238 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4239 struct intel_encoder
*encoder
;
4240 const intel_limit_t
*limit
;
4243 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4244 switch (encoder
->type
) {
4245 case INTEL_OUTPUT_LVDS
:
4248 case INTEL_OUTPUT_SDVO
:
4249 case INTEL_OUTPUT_HDMI
:
4251 if (encoder
->needs_tv_clock
)
4254 case INTEL_OUTPUT_TVOUT
:
4257 case INTEL_OUTPUT_DISPLAYPORT
:
4265 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4268 * Returns a set of divisors for the desired target clock with the given
4269 * refclk, or FALSE. The returned values represent the clock equation:
4270 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4272 limit
= intel_limit(crtc
, refclk
);
4273 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4276 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4280 /* Ensure that the cursor is valid for the new mode before changing... */
4281 intel_crtc_update_cursor(crtc
, true);
4283 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4285 * Ensure we match the reduced clock's P to the target clock.
4286 * If the clocks don't match, we can't switch the display clock
4287 * by using the FP0/FP1. In such case we will disable the LVDS
4288 * downclock feature.
4290 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4291 dev_priv
->lvds_downclock
,
4297 if (is_sdvo
&& is_tv
)
4298 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4300 i9xx_update_pll_dividers(crtc
, &clock
, has_reduced_clock
?
4301 &reduced_clock
: NULL
);
4304 i8xx_update_pll(crtc
, adjusted_mode
, &clock
, num_connectors
);
4305 else if (IS_VALLEYVIEW(dev
))
4306 vlv_update_pll(crtc
, mode
,adjusted_mode
, &clock
, NULL
,
4307 refclk
, num_connectors
);
4309 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4310 has_reduced_clock
? &reduced_clock
: NULL
,
4313 /* setup pipeconf */
4314 pipeconf
= I915_READ(PIPECONF(pipe
));
4316 /* Set up the display plane register */
4317 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4320 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4322 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4324 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4325 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4328 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4332 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4333 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4335 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4338 /* default to 8bpc */
4339 pipeconf
&= ~(PIPECONF_BPP_MASK
| PIPECONF_DITHER_EN
);
4341 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4342 pipeconf
|= PIPECONF_BPP_6
|
4343 PIPECONF_DITHER_EN
|
4344 PIPECONF_DITHER_TYPE_SP
;
4348 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4349 drm_mode_debug_printmodeline(mode
);
4351 if (HAS_PIPE_CXSR(dev
)) {
4352 if (intel_crtc
->lowfreq_avail
) {
4353 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4354 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4356 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4357 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4361 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4362 if (!IS_GEN2(dev
) &&
4363 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4364 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4365 /* the chip adds 2 halflines automatically */
4366 adjusted_mode
->crtc_vtotal
-= 1;
4367 adjusted_mode
->crtc_vblank_end
-= 1;
4368 vsyncshift
= adjusted_mode
->crtc_hsync_start
4369 - adjusted_mode
->crtc_htotal
/2;
4371 pipeconf
|= PIPECONF_PROGRESSIVE
;
4376 I915_WRITE(VSYNCSHIFT(pipe
), vsyncshift
);
4378 I915_WRITE(HTOTAL(pipe
),
4379 (adjusted_mode
->crtc_hdisplay
- 1) |
4380 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4381 I915_WRITE(HBLANK(pipe
),
4382 (adjusted_mode
->crtc_hblank_start
- 1) |
4383 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4384 I915_WRITE(HSYNC(pipe
),
4385 (adjusted_mode
->crtc_hsync_start
- 1) |
4386 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4388 I915_WRITE(VTOTAL(pipe
),
4389 (adjusted_mode
->crtc_vdisplay
- 1) |
4390 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4391 I915_WRITE(VBLANK(pipe
),
4392 (adjusted_mode
->crtc_vblank_start
- 1) |
4393 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4394 I915_WRITE(VSYNC(pipe
),
4395 (adjusted_mode
->crtc_vsync_start
- 1) |
4396 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4398 /* pipesrc and dspsize control the size that is scaled from,
4399 * which should always be the user's requested size.
4401 I915_WRITE(DSPSIZE(plane
),
4402 ((mode
->vdisplay
- 1) << 16) |
4403 (mode
->hdisplay
- 1));
4404 I915_WRITE(DSPPOS(plane
), 0);
4405 I915_WRITE(PIPESRC(pipe
),
4406 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4408 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4409 POSTING_READ(PIPECONF(pipe
));
4410 intel_enable_pipe(dev_priv
, pipe
, false);
4412 intel_wait_for_vblank(dev
, pipe
);
4414 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4415 POSTING_READ(DSPCNTR(plane
));
4417 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4419 intel_update_watermarks(dev
);
4425 * Initialize reference clocks when the driver loads
4427 void ironlake_init_pch_refclk(struct drm_device
*dev
)
4429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4430 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4431 struct intel_encoder
*encoder
;
4433 bool has_lvds
= false;
4434 bool has_cpu_edp
= false;
4435 bool has_pch_edp
= false;
4436 bool has_panel
= false;
4437 bool has_ck505
= false;
4438 bool can_ssc
= false;
4440 /* We need to take the global config into account */
4441 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4443 switch (encoder
->type
) {
4444 case INTEL_OUTPUT_LVDS
:
4448 case INTEL_OUTPUT_EDP
:
4450 if (intel_encoder_is_pch_edp(&encoder
->base
))
4458 if (HAS_PCH_IBX(dev
)) {
4459 has_ck505
= dev_priv
->display_clock_mode
;
4460 can_ssc
= has_ck505
;
4466 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4467 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4470 /* Ironlake: try to setup display ref clock before DPLL
4471 * enabling. This is only under driver's control after
4472 * PCH B stepping, previous chipset stepping should be
4473 * ignoring this setting.
4475 temp
= I915_READ(PCH_DREF_CONTROL
);
4476 /* Always enable nonspread source */
4477 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4480 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4482 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4485 temp
&= ~DREF_SSC_SOURCE_MASK
;
4486 temp
|= DREF_SSC_SOURCE_ENABLE
;
4488 /* SSC must be turned on before enabling the CPU output */
4489 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4490 DRM_DEBUG_KMS("Using SSC on panel\n");
4491 temp
|= DREF_SSC1_ENABLE
;
4493 temp
&= ~DREF_SSC1_ENABLE
;
4495 /* Get SSC going before enabling the outputs */
4496 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4497 POSTING_READ(PCH_DREF_CONTROL
);
4500 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4502 /* Enable CPU source on CPU attached eDP */
4504 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4505 DRM_DEBUG_KMS("Using SSC on eDP\n");
4506 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4509 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4511 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4513 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4514 POSTING_READ(PCH_DREF_CONTROL
);
4517 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4519 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4521 /* Turn off CPU output */
4522 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4524 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4525 POSTING_READ(PCH_DREF_CONTROL
);
4528 /* Turn off the SSC source */
4529 temp
&= ~DREF_SSC_SOURCE_MASK
;
4530 temp
|= DREF_SSC_SOURCE_DISABLE
;
4533 temp
&= ~ DREF_SSC1_ENABLE
;
4535 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4536 POSTING_READ(PCH_DREF_CONTROL
);
4541 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
4543 struct drm_device
*dev
= crtc
->dev
;
4544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4545 struct intel_encoder
*encoder
;
4546 struct intel_encoder
*edp_encoder
= NULL
;
4547 int num_connectors
= 0;
4548 bool is_lvds
= false;
4550 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4551 switch (encoder
->type
) {
4552 case INTEL_OUTPUT_LVDS
:
4555 case INTEL_OUTPUT_EDP
:
4556 edp_encoder
= encoder
;
4562 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4563 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4564 dev_priv
->lvds_ssc_freq
);
4565 return dev_priv
->lvds_ssc_freq
* 1000;
4571 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
4572 struct drm_display_mode
*mode
,
4573 struct drm_display_mode
*adjusted_mode
,
4575 struct drm_framebuffer
*old_fb
)
4577 struct drm_device
*dev
= crtc
->dev
;
4578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4579 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4580 int pipe
= intel_crtc
->pipe
;
4581 int plane
= intel_crtc
->plane
;
4582 int refclk
, num_connectors
= 0;
4583 intel_clock_t clock
, reduced_clock
;
4584 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
4585 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4586 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
4587 struct intel_encoder
*encoder
, *edp_encoder
= NULL
;
4588 const intel_limit_t
*limit
;
4590 struct fdi_m_n m_n
= {0};
4592 int target_clock
, pixel_multiplier
, lane
, link_bw
, factor
;
4593 unsigned int pipe_bpp
;
4595 bool is_cpu_edp
= false, is_pch_edp
= false;
4597 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4598 switch (encoder
->type
) {
4599 case INTEL_OUTPUT_LVDS
:
4602 case INTEL_OUTPUT_SDVO
:
4603 case INTEL_OUTPUT_HDMI
:
4605 if (encoder
->needs_tv_clock
)
4608 case INTEL_OUTPUT_TVOUT
:
4611 case INTEL_OUTPUT_ANALOG
:
4614 case INTEL_OUTPUT_DISPLAYPORT
:
4617 case INTEL_OUTPUT_EDP
:
4619 if (intel_encoder_is_pch_edp(&encoder
->base
))
4623 edp_encoder
= encoder
;
4630 refclk
= ironlake_get_refclk(crtc
);
4633 * Returns a set of divisors for the desired target clock with the given
4634 * refclk, or FALSE. The returned values represent the clock equation:
4635 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4637 limit
= intel_limit(crtc
, refclk
);
4638 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4641 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4645 /* Ensure that the cursor is valid for the new mode before changing... */
4646 intel_crtc_update_cursor(crtc
, true);
4648 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4650 * Ensure we match the reduced clock's P to the target clock.
4651 * If the clocks don't match, we can't switch the display clock
4652 * by using the FP0/FP1. In such case we will disable the LVDS
4653 * downclock feature.
4655 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4656 dev_priv
->lvds_downclock
,
4662 if (is_sdvo
&& is_tv
)
4663 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4667 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4669 /* CPU eDP doesn't require FDI link, so just set DP M/N
4670 according to current link config */
4672 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
4674 /* FDI is a binary signal running at ~2.7GHz, encoding
4675 * each output octet as 10 bits. The actual frequency
4676 * is stored as a divider into a 100MHz clock, and the
4677 * mode pixel clock is stored in units of 1KHz.
4678 * Hence the bw of each lane in terms of the mode signal
4681 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4684 /* [e]DP over FDI requires target mode clock instead of link clock. */
4686 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
4688 target_clock
= mode
->clock
;
4690 target_clock
= adjusted_mode
->clock
;
4692 /* determine panel color depth */
4693 temp
= I915_READ(PIPECONF(pipe
));
4694 temp
&= ~PIPE_BPC_MASK
;
4695 dither
= intel_choose_pipe_bpp_dither(crtc
, &pipe_bpp
, mode
);
4710 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4717 intel_crtc
->bpp
= pipe_bpp
;
4718 I915_WRITE(PIPECONF(pipe
), temp
);
4722 * Account for spread spectrum to avoid
4723 * oversubscribing the link. Max center spread
4724 * is 2.5%; use 5% for safety's sake.
4726 u32 bps
= target_clock
* intel_crtc
->bpp
* 21 / 20;
4727 lane
= bps
/ (link_bw
* 8) + 1;
4730 intel_crtc
->fdi_lanes
= lane
;
4732 if (pixel_multiplier
> 1)
4733 link_bw
*= pixel_multiplier
;
4734 ironlake_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
,
4737 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
4738 if (has_reduced_clock
)
4739 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
4742 /* Enable autotuning of the PLL clock (if permissible) */
4745 if ((intel_panel_use_ssc(dev_priv
) &&
4746 dev_priv
->lvds_ssc_freq
== 100) ||
4747 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
4749 } else if (is_sdvo
&& is_tv
)
4752 if (clock
.m
< factor
* clock
.n
)
4758 dpll
|= DPLLB_MODE_LVDS
;
4760 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4762 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4763 if (pixel_multiplier
> 1) {
4764 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
4766 dpll
|= DPLL_DVO_HIGH_SPEED
;
4768 if (is_dp
&& !is_cpu_edp
)
4769 dpll
|= DPLL_DVO_HIGH_SPEED
;
4771 /* compute bitmask from p1 value */
4772 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4774 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4778 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4781 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4784 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4787 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4791 if (is_sdvo
&& is_tv
)
4792 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4794 /* XXX: just matching BIOS for now */
4795 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4797 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4798 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4800 dpll
|= PLL_REF_INPUT_DREFCLK
;
4802 /* setup pipeconf */
4803 pipeconf
= I915_READ(PIPECONF(pipe
));
4805 /* Set up the display plane register */
4806 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4808 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
4809 drm_mode_debug_printmodeline(mode
);
4811 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4812 * pre-Haswell/LPT generation */
4813 if (HAS_PCH_LPT(dev
)) {
4814 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4816 } else if (!is_cpu_edp
) {
4817 struct intel_pch_pll
*pll
;
4819 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
4821 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4826 intel_put_pch_pll(intel_crtc
);
4828 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4829 * This is an exception to the general rule that mode_set doesn't turn
4833 temp
= I915_READ(PCH_LVDS
);
4834 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4835 if (HAS_PCH_CPT(dev
)) {
4836 temp
&= ~PORT_TRANS_SEL_MASK
;
4837 temp
|= PORT_TRANS_SEL_CPT(pipe
);
4840 temp
|= LVDS_PIPEB_SELECT
;
4842 temp
&= ~LVDS_PIPEB_SELECT
;
4845 /* set the corresponsding LVDS_BORDER bit */
4846 temp
|= dev_priv
->lvds_border_bits
;
4847 /* Set the B0-B3 data pairs corresponding to whether we're going to
4848 * set the DPLLs for dual-channel mode or not.
4851 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4853 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4855 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4856 * appropriately here, but we need to look more thoroughly into how
4857 * panels behave in the two modes.
4859 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4860 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4861 temp
|= LVDS_HSYNC_POLARITY
;
4862 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4863 temp
|= LVDS_VSYNC_POLARITY
;
4864 I915_WRITE(PCH_LVDS
, temp
);
4867 pipeconf
&= ~PIPECONF_DITHER_EN
;
4868 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
4869 if ((is_lvds
&& dev_priv
->lvds_dither
) || dither
) {
4870 pipeconf
|= PIPECONF_DITHER_EN
;
4871 pipeconf
|= PIPECONF_DITHER_TYPE_SP
;
4873 if (is_dp
&& !is_cpu_edp
) {
4874 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4876 /* For non-DP output, clear any trans DP clock recovery setting.*/
4877 I915_WRITE(TRANSDATA_M1(pipe
), 0);
4878 I915_WRITE(TRANSDATA_N1(pipe
), 0);
4879 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
4880 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
4883 if (intel_crtc
->pch_pll
) {
4884 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
4886 /* Wait for the clocks to stabilize. */
4887 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
4890 /* The pixel multiplier can only be updated once the
4891 * DPLL is enabled and the clocks are stable.
4893 * So write it again.
4895 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
4898 intel_crtc
->lowfreq_avail
= false;
4899 if (intel_crtc
->pch_pll
) {
4900 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4901 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
4902 intel_crtc
->lowfreq_avail
= true;
4904 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
4908 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4909 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4910 pipeconf
|= PIPECONF_INTERLACED_ILK
;
4911 /* the chip adds 2 halflines automatically */
4912 adjusted_mode
->crtc_vtotal
-= 1;
4913 adjusted_mode
->crtc_vblank_end
-= 1;
4914 I915_WRITE(VSYNCSHIFT(pipe
),
4915 adjusted_mode
->crtc_hsync_start
4916 - adjusted_mode
->crtc_htotal
/2);
4918 pipeconf
|= PIPECONF_PROGRESSIVE
;
4919 I915_WRITE(VSYNCSHIFT(pipe
), 0);
4922 I915_WRITE(HTOTAL(pipe
),
4923 (adjusted_mode
->crtc_hdisplay
- 1) |
4924 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4925 I915_WRITE(HBLANK(pipe
),
4926 (adjusted_mode
->crtc_hblank_start
- 1) |
4927 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4928 I915_WRITE(HSYNC(pipe
),
4929 (adjusted_mode
->crtc_hsync_start
- 1) |
4930 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4932 I915_WRITE(VTOTAL(pipe
),
4933 (adjusted_mode
->crtc_vdisplay
- 1) |
4934 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4935 I915_WRITE(VBLANK(pipe
),
4936 (adjusted_mode
->crtc_vblank_start
- 1) |
4937 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4938 I915_WRITE(VSYNC(pipe
),
4939 (adjusted_mode
->crtc_vsync_start
- 1) |
4940 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4942 /* pipesrc controls the size that is scaled from, which should
4943 * always be the user's requested size.
4945 I915_WRITE(PIPESRC(pipe
),
4946 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4948 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
4949 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
4950 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
4951 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
4954 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
4956 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4957 POSTING_READ(PIPECONF(pipe
));
4959 intel_wait_for_vblank(dev
, pipe
);
4961 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4962 POSTING_READ(DSPCNTR(plane
));
4964 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4966 intel_update_watermarks(dev
);
4968 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
4973 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
4974 struct drm_display_mode
*mode
,
4975 struct drm_display_mode
*adjusted_mode
,
4977 struct drm_framebuffer
*old_fb
)
4979 struct drm_device
*dev
= crtc
->dev
;
4980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4981 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4982 int pipe
= intel_crtc
->pipe
;
4985 drm_vblank_pre_modeset(dev
, pipe
);
4987 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
4989 drm_vblank_post_modeset(dev
, pipe
);
4992 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
4994 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_ON
;
4999 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5000 int reg_eldv
, uint32_t bits_eldv
,
5001 int reg_elda
, uint32_t bits_elda
,
5004 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5005 uint8_t *eld
= connector
->eld
;
5008 i
= I915_READ(reg_eldv
);
5017 i
= I915_READ(reg_elda
);
5019 I915_WRITE(reg_elda
, i
);
5021 for (i
= 0; i
< eld
[2]; i
++)
5022 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5028 static void g4x_write_eld(struct drm_connector
*connector
,
5029 struct drm_crtc
*crtc
)
5031 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5032 uint8_t *eld
= connector
->eld
;
5037 i
= I915_READ(G4X_AUD_VID_DID
);
5039 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5040 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5042 eldv
= G4X_ELDV_DEVCTG
;
5044 if (intel_eld_uptodate(connector
,
5045 G4X_AUD_CNTL_ST
, eldv
,
5046 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5047 G4X_HDMIW_HDMIEDID
))
5050 i
= I915_READ(G4X_AUD_CNTL_ST
);
5051 i
&= ~(eldv
| G4X_ELD_ADDR
);
5052 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5053 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5058 len
= min_t(uint8_t, eld
[2], len
);
5059 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5060 for (i
= 0; i
< len
; i
++)
5061 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5063 i
= I915_READ(G4X_AUD_CNTL_ST
);
5065 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5068 static void ironlake_write_eld(struct drm_connector
*connector
,
5069 struct drm_crtc
*crtc
)
5071 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5072 uint8_t *eld
= connector
->eld
;
5081 if (HAS_PCH_IBX(connector
->dev
)) {
5082 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID_A
;
5083 aud_config
= IBX_AUD_CONFIG_A
;
5084 aud_cntl_st
= IBX_AUD_CNTL_ST_A
;
5085 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
5087 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID_A
;
5088 aud_config
= CPT_AUD_CONFIG_A
;
5089 aud_cntl_st
= CPT_AUD_CNTL_ST_A
;
5090 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
5093 i
= to_intel_crtc(crtc
)->pipe
;
5094 hdmiw_hdmiedid
+= i
* 0x100;
5095 aud_cntl_st
+= i
* 0x100;
5096 aud_config
+= i
* 0x100;
5098 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i
));
5100 i
= I915_READ(aud_cntl_st
);
5101 i
= (i
>> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5103 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5104 /* operate blindly on all ports */
5105 eldv
= IBX_ELD_VALIDB
;
5106 eldv
|= IBX_ELD_VALIDB
<< 4;
5107 eldv
|= IBX_ELD_VALIDB
<< 8;
5109 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
5110 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
5113 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5114 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5115 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5116 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5118 I915_WRITE(aud_config
, 0);
5120 if (intel_eld_uptodate(connector
,
5121 aud_cntrl_st2
, eldv
,
5122 aud_cntl_st
, IBX_ELD_ADDRESS
,
5126 i
= I915_READ(aud_cntrl_st2
);
5128 I915_WRITE(aud_cntrl_st2
, i
);
5133 i
= I915_READ(aud_cntl_st
);
5134 i
&= ~IBX_ELD_ADDRESS
;
5135 I915_WRITE(aud_cntl_st
, i
);
5137 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5138 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5139 for (i
= 0; i
< len
; i
++)
5140 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5142 i
= I915_READ(aud_cntrl_st2
);
5144 I915_WRITE(aud_cntrl_st2
, i
);
5147 void intel_write_eld(struct drm_encoder
*encoder
,
5148 struct drm_display_mode
*mode
)
5150 struct drm_crtc
*crtc
= encoder
->crtc
;
5151 struct drm_connector
*connector
;
5152 struct drm_device
*dev
= encoder
->dev
;
5153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5155 connector
= drm_select_eld(encoder
, mode
);
5159 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5161 drm_get_connector_name(connector
),
5162 connector
->encoder
->base
.id
,
5163 drm_get_encoder_name(connector
->encoder
));
5165 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
5167 if (dev_priv
->display
.write_eld
)
5168 dev_priv
->display
.write_eld(connector
, crtc
);
5171 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5172 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
5174 struct drm_device
*dev
= crtc
->dev
;
5175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5176 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5177 int palreg
= PALETTE(intel_crtc
->pipe
);
5180 /* The clocks have to be on to load the palette. */
5181 if (!crtc
->enabled
|| !intel_crtc
->active
)
5184 /* use legacy palette for Ironlake */
5185 if (HAS_PCH_SPLIT(dev
))
5186 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
5188 for (i
= 0; i
< 256; i
++) {
5189 I915_WRITE(palreg
+ 4 * i
,
5190 (intel_crtc
->lut_r
[i
] << 16) |
5191 (intel_crtc
->lut_g
[i
] << 8) |
5192 intel_crtc
->lut_b
[i
]);
5196 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5198 struct drm_device
*dev
= crtc
->dev
;
5199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5200 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5201 bool visible
= base
!= 0;
5204 if (intel_crtc
->cursor_visible
== visible
)
5207 cntl
= I915_READ(_CURACNTR
);
5209 /* On these chipsets we can only modify the base whilst
5210 * the cursor is disabled.
5212 I915_WRITE(_CURABASE
, base
);
5214 cntl
&= ~(CURSOR_FORMAT_MASK
);
5215 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5216 cntl
|= CURSOR_ENABLE
|
5217 CURSOR_GAMMA_ENABLE
|
5220 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
5221 I915_WRITE(_CURACNTR
, cntl
);
5223 intel_crtc
->cursor_visible
= visible
;
5226 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5228 struct drm_device
*dev
= crtc
->dev
;
5229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5230 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5231 int pipe
= intel_crtc
->pipe
;
5232 bool visible
= base
!= 0;
5234 if (intel_crtc
->cursor_visible
!= visible
) {
5235 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
5237 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
5238 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5239 cntl
|= pipe
<< 28; /* Connect to correct pipe */
5241 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5242 cntl
|= CURSOR_MODE_DISABLE
;
5244 I915_WRITE(CURCNTR(pipe
), cntl
);
5246 intel_crtc
->cursor_visible
= visible
;
5248 /* and commit changes on next vblank */
5249 I915_WRITE(CURBASE(pipe
), base
);
5252 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5254 struct drm_device
*dev
= crtc
->dev
;
5255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5256 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5257 int pipe
= intel_crtc
->pipe
;
5258 bool visible
= base
!= 0;
5260 if (intel_crtc
->cursor_visible
!= visible
) {
5261 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
5263 cntl
&= ~CURSOR_MODE
;
5264 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5266 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5267 cntl
|= CURSOR_MODE_DISABLE
;
5269 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
5271 intel_crtc
->cursor_visible
= visible
;
5273 /* and commit changes on next vblank */
5274 I915_WRITE(CURBASE_IVB(pipe
), base
);
5277 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5278 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
5281 struct drm_device
*dev
= crtc
->dev
;
5282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5283 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5284 int pipe
= intel_crtc
->pipe
;
5285 int x
= intel_crtc
->cursor_x
;
5286 int y
= intel_crtc
->cursor_y
;
5292 if (on
&& crtc
->enabled
&& crtc
->fb
) {
5293 base
= intel_crtc
->cursor_addr
;
5294 if (x
> (int) crtc
->fb
->width
)
5297 if (y
> (int) crtc
->fb
->height
)
5303 if (x
+ intel_crtc
->cursor_width
< 0)
5306 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
5309 pos
|= x
<< CURSOR_X_SHIFT
;
5312 if (y
+ intel_crtc
->cursor_height
< 0)
5315 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
5318 pos
|= y
<< CURSOR_Y_SHIFT
;
5320 visible
= base
!= 0;
5321 if (!visible
&& !intel_crtc
->cursor_visible
)
5324 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
5325 I915_WRITE(CURPOS_IVB(pipe
), pos
);
5326 ivb_update_cursor(crtc
, base
);
5328 I915_WRITE(CURPOS(pipe
), pos
);
5329 if (IS_845G(dev
) || IS_I865G(dev
))
5330 i845_update_cursor(crtc
, base
);
5332 i9xx_update_cursor(crtc
, base
);
5336 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
5337 struct drm_file
*file
,
5339 uint32_t width
, uint32_t height
)
5341 struct drm_device
*dev
= crtc
->dev
;
5342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5343 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5344 struct drm_i915_gem_object
*obj
;
5348 DRM_DEBUG_KMS("\n");
5350 /* if we want to turn off the cursor ignore width and height */
5352 DRM_DEBUG_KMS("cursor off\n");
5355 mutex_lock(&dev
->struct_mutex
);
5359 /* Currently we only support 64x64 cursors */
5360 if (width
!= 64 || height
!= 64) {
5361 DRM_ERROR("we currently only support 64x64 cursors\n");
5365 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
5366 if (&obj
->base
== NULL
)
5369 if (obj
->base
.size
< width
* height
* 4) {
5370 DRM_ERROR("buffer is to small\n");
5375 /* we only need to pin inside GTT if cursor is non-phy */
5376 mutex_lock(&dev
->struct_mutex
);
5377 if (!dev_priv
->info
->cursor_needs_physical
) {
5378 if (obj
->tiling_mode
) {
5379 DRM_ERROR("cursor cannot be tiled\n");
5384 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
5386 DRM_ERROR("failed to move cursor bo into the GTT\n");
5390 ret
= i915_gem_object_put_fence(obj
);
5392 DRM_ERROR("failed to release fence for cursor");
5396 addr
= obj
->gtt_offset
;
5398 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
5399 ret
= i915_gem_attach_phys_object(dev
, obj
,
5400 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
5403 DRM_ERROR("failed to attach phys object\n");
5406 addr
= obj
->phys_obj
->handle
->busaddr
;
5410 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
5413 if (intel_crtc
->cursor_bo
) {
5414 if (dev_priv
->info
->cursor_needs_physical
) {
5415 if (intel_crtc
->cursor_bo
!= obj
)
5416 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
5418 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
5419 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
5422 mutex_unlock(&dev
->struct_mutex
);
5424 intel_crtc
->cursor_addr
= addr
;
5425 intel_crtc
->cursor_bo
= obj
;
5426 intel_crtc
->cursor_width
= width
;
5427 intel_crtc
->cursor_height
= height
;
5429 intel_crtc_update_cursor(crtc
, true);
5433 i915_gem_object_unpin(obj
);
5435 mutex_unlock(&dev
->struct_mutex
);
5437 drm_gem_object_unreference_unlocked(&obj
->base
);
5441 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
5443 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5445 intel_crtc
->cursor_x
= x
;
5446 intel_crtc
->cursor_y
= y
;
5448 intel_crtc_update_cursor(crtc
, true);
5453 /** Sets the color ramps on behalf of RandR */
5454 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
5455 u16 blue
, int regno
)
5457 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5459 intel_crtc
->lut_r
[regno
] = red
>> 8;
5460 intel_crtc
->lut_g
[regno
] = green
>> 8;
5461 intel_crtc
->lut_b
[regno
] = blue
>> 8;
5464 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5465 u16
*blue
, int regno
)
5467 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5469 *red
= intel_crtc
->lut_r
[regno
] << 8;
5470 *green
= intel_crtc
->lut_g
[regno
] << 8;
5471 *blue
= intel_crtc
->lut_b
[regno
] << 8;
5474 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5475 u16
*blue
, uint32_t start
, uint32_t size
)
5477 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
5478 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5480 for (i
= start
; i
< end
; i
++) {
5481 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
5482 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
5483 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
5486 intel_crtc_load_lut(crtc
);
5490 * Get a pipe with a simple mode set on it for doing load-based monitor
5493 * It will be up to the load-detect code to adjust the pipe as appropriate for
5494 * its requirements. The pipe will be connected to no other encoders.
5496 * Currently this code will only succeed if there is a pipe with no encoders
5497 * configured for it. In the future, it could choose to temporarily disable
5498 * some outputs to free up a pipe for its use.
5500 * \return crtc, or NULL if no pipes are available.
5503 /* VESA 640x480x72Hz mode to set on the pipe */
5504 static struct drm_display_mode load_detect_mode
= {
5505 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
5506 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
5509 static struct drm_framebuffer
*
5510 intel_framebuffer_create(struct drm_device
*dev
,
5511 struct drm_mode_fb_cmd2
*mode_cmd
,
5512 struct drm_i915_gem_object
*obj
)
5514 struct intel_framebuffer
*intel_fb
;
5517 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5519 drm_gem_object_unreference_unlocked(&obj
->base
);
5520 return ERR_PTR(-ENOMEM
);
5523 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
5525 drm_gem_object_unreference_unlocked(&obj
->base
);
5527 return ERR_PTR(ret
);
5530 return &intel_fb
->base
;
5534 intel_framebuffer_pitch_for_width(int width
, int bpp
)
5536 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
5537 return ALIGN(pitch
, 64);
5541 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
5543 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
5544 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
5547 static struct drm_framebuffer
*
5548 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
5549 struct drm_display_mode
*mode
,
5552 struct drm_i915_gem_object
*obj
;
5553 struct drm_mode_fb_cmd2 mode_cmd
;
5555 obj
= i915_gem_alloc_object(dev
,
5556 intel_framebuffer_size_for_mode(mode
, bpp
));
5558 return ERR_PTR(-ENOMEM
);
5560 mode_cmd
.width
= mode
->hdisplay
;
5561 mode_cmd
.height
= mode
->vdisplay
;
5562 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
5564 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
5566 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
5569 static struct drm_framebuffer
*
5570 mode_fits_in_fbdev(struct drm_device
*dev
,
5571 struct drm_display_mode
*mode
)
5573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5574 struct drm_i915_gem_object
*obj
;
5575 struct drm_framebuffer
*fb
;
5577 if (dev_priv
->fbdev
== NULL
)
5580 obj
= dev_priv
->fbdev
->ifb
.obj
;
5584 fb
= &dev_priv
->fbdev
->ifb
.base
;
5585 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
5586 fb
->bits_per_pixel
))
5589 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
5595 bool intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5596 struct drm_connector
*connector
,
5597 struct drm_display_mode
*mode
,
5598 struct intel_load_detect_pipe
*old
)
5600 struct intel_crtc
*intel_crtc
;
5601 struct drm_crtc
*possible_crtc
;
5602 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5603 struct drm_crtc
*crtc
= NULL
;
5604 struct drm_device
*dev
= encoder
->dev
;
5605 struct drm_framebuffer
*old_fb
;
5608 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5609 connector
->base
.id
, drm_get_connector_name(connector
),
5610 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5613 * Algorithm gets a little messy:
5615 * - if the connector already has an assigned crtc, use it (but make
5616 * sure it's on first)
5618 * - try to find the first unused crtc that can drive this connector,
5619 * and use that if we find one
5622 /* See if we already have a CRTC for this connector */
5623 if (encoder
->crtc
) {
5624 crtc
= encoder
->crtc
;
5626 intel_crtc
= to_intel_crtc(crtc
);
5627 old
->dpms_mode
= intel_crtc
->dpms_mode
;
5628 old
->load_detect_temp
= false;
5630 /* Make sure the crtc and connector are running */
5631 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5632 struct drm_encoder_helper_funcs
*encoder_funcs
;
5633 struct drm_crtc_helper_funcs
*crtc_funcs
;
5635 crtc_funcs
= crtc
->helper_private
;
5636 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
5638 encoder_funcs
= encoder
->helper_private
;
5639 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
5645 /* Find an unused one (if possible) */
5646 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
5648 if (!(encoder
->possible_crtcs
& (1 << i
)))
5650 if (!possible_crtc
->enabled
) {
5651 crtc
= possible_crtc
;
5657 * If we didn't find an unused CRTC, don't use any.
5660 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5664 encoder
->crtc
= crtc
;
5665 connector
->encoder
= encoder
;
5667 intel_crtc
= to_intel_crtc(crtc
);
5668 old
->dpms_mode
= intel_crtc
->dpms_mode
;
5669 old
->load_detect_temp
= true;
5670 old
->release_fb
= NULL
;
5673 mode
= &load_detect_mode
;
5677 /* We need a framebuffer large enough to accommodate all accesses
5678 * that the plane may generate whilst we perform load detection.
5679 * We can not rely on the fbcon either being present (we get called
5680 * during its initialisation to detect all boot displays, or it may
5681 * not even exist) or that it is large enough to satisfy the
5684 crtc
->fb
= mode_fits_in_fbdev(dev
, mode
);
5685 if (crtc
->fb
== NULL
) {
5686 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5687 crtc
->fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
5688 old
->release_fb
= crtc
->fb
;
5690 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5691 if (IS_ERR(crtc
->fb
)) {
5692 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5697 if (!drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, old_fb
)) {
5698 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5699 if (old
->release_fb
)
5700 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5705 /* let the connector get through one full cycle before testing */
5706 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
5711 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5712 struct drm_connector
*connector
,
5713 struct intel_load_detect_pipe
*old
)
5715 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5716 struct drm_device
*dev
= encoder
->dev
;
5717 struct drm_crtc
*crtc
= encoder
->crtc
;
5718 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
5719 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
5721 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5722 connector
->base
.id
, drm_get_connector_name(connector
),
5723 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5725 if (old
->load_detect_temp
) {
5726 connector
->encoder
= NULL
;
5727 drm_helper_disable_unused_functions(dev
);
5729 if (old
->release_fb
)
5730 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5735 /* Switch crtc and encoder back off if necessary */
5736 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5737 encoder_funcs
->dpms(encoder
, old
->dpms_mode
);
5738 crtc_funcs
->dpms(crtc
, old
->dpms_mode
);
5742 /* Returns the clock of the currently programmed mode of the given pipe. */
5743 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
5745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5746 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5747 int pipe
= intel_crtc
->pipe
;
5748 u32 dpll
= I915_READ(DPLL(pipe
));
5750 intel_clock_t clock
;
5752 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
5753 fp
= I915_READ(FP0(pipe
));
5755 fp
= I915_READ(FP1(pipe
));
5757 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
5758 if (IS_PINEVIEW(dev
)) {
5759 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
5760 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5762 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
5763 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5766 if (!IS_GEN2(dev
)) {
5767 if (IS_PINEVIEW(dev
))
5768 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
5769 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
5771 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
5772 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5774 switch (dpll
& DPLL_MODE_MASK
) {
5775 case DPLLB_MODE_DAC_SERIAL
:
5776 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
5779 case DPLLB_MODE_LVDS
:
5780 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
5784 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5785 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
5789 /* XXX: Handle the 100Mhz refclk */
5790 intel_clock(dev
, 96000, &clock
);
5792 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
5795 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
5796 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5799 if ((dpll
& PLL_REF_INPUT_MASK
) ==
5800 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
5801 /* XXX: might not be 66MHz */
5802 intel_clock(dev
, 66000, &clock
);
5804 intel_clock(dev
, 48000, &clock
);
5806 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
5809 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
5810 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
5812 if (dpll
& PLL_P2_DIVIDE_BY_4
)
5817 intel_clock(dev
, 48000, &clock
);
5821 /* XXX: It would be nice to validate the clocks, but we can't reuse
5822 * i830PllIsValid() because it relies on the xf86_config connector
5823 * configuration being accurate, which it isn't necessarily.
5829 /** Returns the currently programmed mode of the given pipe. */
5830 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
5831 struct drm_crtc
*crtc
)
5833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5834 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5835 int pipe
= intel_crtc
->pipe
;
5836 struct drm_display_mode
*mode
;
5837 int htot
= I915_READ(HTOTAL(pipe
));
5838 int hsync
= I915_READ(HSYNC(pipe
));
5839 int vtot
= I915_READ(VTOTAL(pipe
));
5840 int vsync
= I915_READ(VSYNC(pipe
));
5842 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
5846 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
5847 mode
->hdisplay
= (htot
& 0xffff) + 1;
5848 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
5849 mode
->hsync_start
= (hsync
& 0xffff) + 1;
5850 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
5851 mode
->vdisplay
= (vtot
& 0xffff) + 1;
5852 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
5853 mode
->vsync_start
= (vsync
& 0xffff) + 1;
5854 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
5856 drm_mode_set_name(mode
);
5861 #define GPU_IDLE_TIMEOUT 500 /* ms */
5863 /* When this timer fires, we've been idle for awhile */
5864 static void intel_gpu_idle_timer(unsigned long arg
)
5866 struct drm_device
*dev
= (struct drm_device
*)arg
;
5867 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5869 if (!list_empty(&dev_priv
->mm
.active_list
)) {
5870 /* Still processing requests, so just re-arm the timer. */
5871 mod_timer(&dev_priv
->idle_timer
, jiffies
+
5872 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
5876 dev_priv
->busy
= false;
5877 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5880 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5882 static void intel_crtc_idle_timer(unsigned long arg
)
5884 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
5885 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5886 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
5887 struct intel_framebuffer
*intel_fb
;
5889 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5890 if (intel_fb
&& intel_fb
->obj
->active
) {
5891 /* The framebuffer is still being accessed by the GPU. */
5892 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5893 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5897 intel_crtc
->busy
= false;
5898 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5901 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
5903 struct drm_device
*dev
= crtc
->dev
;
5904 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5905 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5906 int pipe
= intel_crtc
->pipe
;
5907 int dpll_reg
= DPLL(pipe
);
5910 if (HAS_PCH_SPLIT(dev
))
5913 if (!dev_priv
->lvds_downclock_avail
)
5916 dpll
= I915_READ(dpll_reg
);
5917 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
5918 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5920 assert_panel_unlocked(dev_priv
, pipe
);
5922 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
5923 I915_WRITE(dpll_reg
, dpll
);
5924 intel_wait_for_vblank(dev
, pipe
);
5926 dpll
= I915_READ(dpll_reg
);
5927 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
5928 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5931 /* Schedule downclock */
5932 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5933 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5936 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
5938 struct drm_device
*dev
= crtc
->dev
;
5939 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5940 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5942 if (HAS_PCH_SPLIT(dev
))
5945 if (!dev_priv
->lvds_downclock_avail
)
5949 * Since this is called by a timer, we should never get here in
5952 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
5953 int pipe
= intel_crtc
->pipe
;
5954 int dpll_reg
= DPLL(pipe
);
5957 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5959 assert_panel_unlocked(dev_priv
, pipe
);
5961 dpll
= I915_READ(dpll_reg
);
5962 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
5963 I915_WRITE(dpll_reg
, dpll
);
5964 intel_wait_for_vblank(dev
, pipe
);
5965 dpll
= I915_READ(dpll_reg
);
5966 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
5967 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5973 * intel_idle_update - adjust clocks for idleness
5974 * @work: work struct
5976 * Either the GPU or display (or both) went idle. Check the busy status
5977 * here and adjust the CRTC and GPU clocks as necessary.
5979 static void intel_idle_update(struct work_struct
*work
)
5981 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
5983 struct drm_device
*dev
= dev_priv
->dev
;
5984 struct drm_crtc
*crtc
;
5985 struct intel_crtc
*intel_crtc
;
5987 if (!i915_powersave
)
5990 mutex_lock(&dev
->struct_mutex
);
5992 i915_update_gfx_val(dev_priv
);
5994 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5995 /* Skip inactive CRTCs */
5999 intel_crtc
= to_intel_crtc(crtc
);
6000 if (!intel_crtc
->busy
)
6001 intel_decrease_pllclock(crtc
);
6005 mutex_unlock(&dev
->struct_mutex
);
6009 * intel_mark_busy - mark the GPU and possibly the display busy
6011 * @obj: object we're operating on
6013 * Callers can use this function to indicate that the GPU is busy processing
6014 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6015 * buffer), we'll also mark the display as busy, so we know to increase its
6018 void intel_mark_busy(struct drm_device
*dev
, struct drm_i915_gem_object
*obj
)
6020 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6021 struct drm_crtc
*crtc
= NULL
;
6022 struct intel_framebuffer
*intel_fb
;
6023 struct intel_crtc
*intel_crtc
;
6025 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
6028 if (!dev_priv
->busy
) {
6029 intel_sanitize_pm(dev
);
6030 dev_priv
->busy
= true;
6032 mod_timer(&dev_priv
->idle_timer
, jiffies
+
6033 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
6038 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6042 intel_crtc
= to_intel_crtc(crtc
);
6043 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6044 if (intel_fb
->obj
== obj
) {
6045 if (!intel_crtc
->busy
) {
6046 /* Non-busy -> busy, upclock */
6047 intel_increase_pllclock(crtc
);
6048 intel_crtc
->busy
= true;
6050 /* Busy -> busy, put off timer */
6051 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
6052 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
6058 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6060 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6061 struct drm_device
*dev
= crtc
->dev
;
6062 struct intel_unpin_work
*work
;
6063 unsigned long flags
;
6065 spin_lock_irqsave(&dev
->event_lock
, flags
);
6066 work
= intel_crtc
->unpin_work
;
6067 intel_crtc
->unpin_work
= NULL
;
6068 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6071 cancel_work_sync(&work
->work
);
6075 drm_crtc_cleanup(crtc
);
6080 static void intel_unpin_work_fn(struct work_struct
*__work
)
6082 struct intel_unpin_work
*work
=
6083 container_of(__work
, struct intel_unpin_work
, work
);
6085 mutex_lock(&work
->dev
->struct_mutex
);
6086 intel_unpin_fb_obj(work
->old_fb_obj
);
6087 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6088 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6090 intel_update_fbc(work
->dev
);
6091 mutex_unlock(&work
->dev
->struct_mutex
);
6095 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6096 struct drm_crtc
*crtc
)
6098 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6099 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6100 struct intel_unpin_work
*work
;
6101 struct drm_i915_gem_object
*obj
;
6102 struct drm_pending_vblank_event
*e
;
6103 struct timeval tnow
, tvbl
;
6104 unsigned long flags
;
6106 /* Ignore early vblank irqs */
6107 if (intel_crtc
== NULL
)
6110 do_gettimeofday(&tnow
);
6112 spin_lock_irqsave(&dev
->event_lock
, flags
);
6113 work
= intel_crtc
->unpin_work
;
6114 if (work
== NULL
|| !work
->pending
) {
6115 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6119 intel_crtc
->unpin_work
= NULL
;
6123 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
6125 /* Called before vblank count and timestamps have
6126 * been updated for the vblank interval of flip
6127 * completion? Need to increment vblank count and
6128 * add one videorefresh duration to returned timestamp
6129 * to account for this. We assume this happened if we
6130 * get called over 0.9 frame durations after the last
6131 * timestamped vblank.
6133 * This calculation can not be used with vrefresh rates
6134 * below 5Hz (10Hz to be on the safe side) without
6135 * promoting to 64 integers.
6137 if (10 * (timeval_to_ns(&tnow
) - timeval_to_ns(&tvbl
)) >
6138 9 * crtc
->framedur_ns
) {
6139 e
->event
.sequence
++;
6140 tvbl
= ns_to_timeval(timeval_to_ns(&tvbl
) +
6144 e
->event
.tv_sec
= tvbl
.tv_sec
;
6145 e
->event
.tv_usec
= tvbl
.tv_usec
;
6147 list_add_tail(&e
->base
.link
,
6148 &e
->base
.file_priv
->event_list
);
6149 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
6152 drm_vblank_put(dev
, intel_crtc
->pipe
);
6154 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6156 obj
= work
->old_fb_obj
;
6158 atomic_clear_mask(1 << intel_crtc
->plane
,
6159 &obj
->pending_flip
.counter
);
6160 if (atomic_read(&obj
->pending_flip
) == 0)
6161 wake_up(&dev_priv
->pending_flip_queue
);
6163 schedule_work(&work
->work
);
6165 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6168 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6170 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6171 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6173 do_intel_finish_page_flip(dev
, crtc
);
6176 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6178 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6179 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6181 do_intel_finish_page_flip(dev
, crtc
);
6184 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6186 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6187 struct intel_crtc
*intel_crtc
=
6188 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6189 unsigned long flags
;
6191 spin_lock_irqsave(&dev
->event_lock
, flags
);
6192 if (intel_crtc
->unpin_work
) {
6193 if ((++intel_crtc
->unpin_work
->pending
) > 1)
6194 DRM_ERROR("Prepared flip multiple times\n");
6196 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6198 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6201 static int intel_gen2_queue_flip(struct drm_device
*dev
,
6202 struct drm_crtc
*crtc
,
6203 struct drm_framebuffer
*fb
,
6204 struct drm_i915_gem_object
*obj
)
6206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6207 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6209 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6212 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6216 ret
= intel_ring_begin(ring
, 6);
6220 /* Can't queue multiple flips, so wait for the previous
6221 * one to finish before executing the next.
6223 if (intel_crtc
->plane
)
6224 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6226 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6227 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6228 intel_ring_emit(ring
, MI_NOOP
);
6229 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6230 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6231 intel_ring_emit(ring
, fb
->pitches
[0]);
6232 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6233 intel_ring_emit(ring
, 0); /* aux display base address, unused */
6234 intel_ring_advance(ring
);
6238 intel_unpin_fb_obj(obj
);
6243 static int intel_gen3_queue_flip(struct drm_device
*dev
,
6244 struct drm_crtc
*crtc
,
6245 struct drm_framebuffer
*fb
,
6246 struct drm_i915_gem_object
*obj
)
6248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6249 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6251 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6254 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6258 ret
= intel_ring_begin(ring
, 6);
6262 if (intel_crtc
->plane
)
6263 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6265 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6266 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6267 intel_ring_emit(ring
, MI_NOOP
);
6268 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
6269 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6270 intel_ring_emit(ring
, fb
->pitches
[0]);
6271 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6272 intel_ring_emit(ring
, MI_NOOP
);
6274 intel_ring_advance(ring
);
6278 intel_unpin_fb_obj(obj
);
6283 static int intel_gen4_queue_flip(struct drm_device
*dev
,
6284 struct drm_crtc
*crtc
,
6285 struct drm_framebuffer
*fb
,
6286 struct drm_i915_gem_object
*obj
)
6288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6289 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6290 uint32_t pf
, pipesrc
;
6291 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6294 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6298 ret
= intel_ring_begin(ring
, 4);
6302 /* i965+ uses the linear or tiled offsets from the
6303 * Display Registers (which do not change across a page-flip)
6304 * so we need only reprogram the base address.
6306 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6307 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6308 intel_ring_emit(ring
, fb
->pitches
[0]);
6309 intel_ring_emit(ring
,
6310 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
6313 /* XXX Enabling the panel-fitter across page-flip is so far
6314 * untested on non-native modes, so ignore it for now.
6315 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6318 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6319 intel_ring_emit(ring
, pf
| pipesrc
);
6320 intel_ring_advance(ring
);
6324 intel_unpin_fb_obj(obj
);
6329 static int intel_gen6_queue_flip(struct drm_device
*dev
,
6330 struct drm_crtc
*crtc
,
6331 struct drm_framebuffer
*fb
,
6332 struct drm_i915_gem_object
*obj
)
6334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6335 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6336 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6337 uint32_t pf
, pipesrc
;
6340 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6344 ret
= intel_ring_begin(ring
, 4);
6348 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6349 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6350 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
6351 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6353 /* Contrary to the suggestions in the documentation,
6354 * "Enable Panel Fitter" does not seem to be required when page
6355 * flipping with a non-native mode, and worse causes a normal
6357 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6360 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6361 intel_ring_emit(ring
, pf
| pipesrc
);
6362 intel_ring_advance(ring
);
6366 intel_unpin_fb_obj(obj
);
6372 * On gen7 we currently use the blit ring because (in early silicon at least)
6373 * the render ring doesn't give us interrpts for page flip completion, which
6374 * means clients will hang after the first flip is queued. Fortunately the
6375 * blit ring generates interrupts properly, so use it instead.
6377 static int intel_gen7_queue_flip(struct drm_device
*dev
,
6378 struct drm_crtc
*crtc
,
6379 struct drm_framebuffer
*fb
,
6380 struct drm_i915_gem_object
*obj
)
6382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6383 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6384 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
6385 uint32_t plane_bit
= 0;
6388 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6392 switch(intel_crtc
->plane
) {
6394 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
6397 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
6400 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
6403 WARN_ONCE(1, "unknown plane in flip command\n");
6408 ret
= intel_ring_begin(ring
, 4);
6412 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
6413 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
6414 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6415 intel_ring_emit(ring
, (MI_NOOP
));
6416 intel_ring_advance(ring
);
6420 intel_unpin_fb_obj(obj
);
6425 static int intel_default_queue_flip(struct drm_device
*dev
,
6426 struct drm_crtc
*crtc
,
6427 struct drm_framebuffer
*fb
,
6428 struct drm_i915_gem_object
*obj
)
6433 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
6434 struct drm_framebuffer
*fb
,
6435 struct drm_pending_vblank_event
*event
)
6437 struct drm_device
*dev
= crtc
->dev
;
6438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6439 struct intel_framebuffer
*intel_fb
;
6440 struct drm_i915_gem_object
*obj
;
6441 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6442 struct intel_unpin_work
*work
;
6443 unsigned long flags
;
6446 /* Can't change pixel format via MI display flips. */
6447 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
6451 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6452 * Note that pitch changes could also affect these register.
6454 if (INTEL_INFO(dev
)->gen
> 3 &&
6455 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
6456 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
6459 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
6463 work
->event
= event
;
6464 work
->dev
= crtc
->dev
;
6465 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6466 work
->old_fb_obj
= intel_fb
->obj
;
6467 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
6469 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
6473 /* We borrow the event spin lock for protecting unpin_work */
6474 spin_lock_irqsave(&dev
->event_lock
, flags
);
6475 if (intel_crtc
->unpin_work
) {
6476 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6478 drm_vblank_put(dev
, intel_crtc
->pipe
);
6480 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6483 intel_crtc
->unpin_work
= work
;
6484 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6486 intel_fb
= to_intel_framebuffer(fb
);
6487 obj
= intel_fb
->obj
;
6489 ret
= i915_mutex_lock_interruptible(dev
);
6493 /* Reference the objects for the scheduled work. */
6494 drm_gem_object_reference(&work
->old_fb_obj
->base
);
6495 drm_gem_object_reference(&obj
->base
);
6499 work
->pending_flip_obj
= obj
;
6501 work
->enable_stall_check
= true;
6503 /* Block clients from rendering to the new back buffer until
6504 * the flip occurs and the object is no longer visible.
6506 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6508 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
6510 goto cleanup_pending
;
6512 intel_disable_fbc(dev
);
6513 intel_mark_busy(dev
, obj
);
6514 mutex_unlock(&dev
->struct_mutex
);
6516 trace_i915_flip_request(intel_crtc
->plane
, obj
);
6521 atomic_sub(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6522 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6523 drm_gem_object_unreference(&obj
->base
);
6524 mutex_unlock(&dev
->struct_mutex
);
6527 spin_lock_irqsave(&dev
->event_lock
, flags
);
6528 intel_crtc
->unpin_work
= NULL
;
6529 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6531 drm_vblank_put(dev
, intel_crtc
->pipe
);
6538 static void intel_sanitize_modesetting(struct drm_device
*dev
,
6539 int pipe
, int plane
)
6541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6545 /* Clear any frame start delays used for debugging left by the BIOS */
6548 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
6551 if (HAS_PCH_SPLIT(dev
))
6554 /* Who knows what state these registers were left in by the BIOS or
6557 * If we leave the registers in a conflicting state (e.g. with the
6558 * display plane reading from the other pipe than the one we intend
6559 * to use) then when we attempt to teardown the active mode, we will
6560 * not disable the pipes and planes in the correct order -- leaving
6561 * a plane reading from a disabled pipe and possibly leading to
6562 * undefined behaviour.
6565 reg
= DSPCNTR(plane
);
6566 val
= I915_READ(reg
);
6568 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
6570 if (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == pipe
)
6573 /* This display plane is active and attached to the other CPU pipe. */
6576 /* Disable the plane and wait for it to stop reading from the pipe. */
6577 intel_disable_plane(dev_priv
, plane
, pipe
);
6578 intel_disable_pipe(dev_priv
, pipe
);
6581 static void intel_crtc_reset(struct drm_crtc
*crtc
)
6583 struct drm_device
*dev
= crtc
->dev
;
6584 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6586 /* Reset flags back to the 'unknown' status so that they
6587 * will be correctly set on the initial modeset.
6589 intel_crtc
->dpms_mode
= -1;
6591 /* We need to fix up any BIOS configuration that conflicts with
6594 intel_sanitize_modesetting(dev
, intel_crtc
->pipe
, intel_crtc
->plane
);
6597 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
6598 .dpms
= intel_crtc_dpms
,
6599 .mode_fixup
= intel_crtc_mode_fixup
,
6600 .mode_set
= intel_crtc_mode_set
,
6601 .mode_set_base
= intel_pipe_set_base
,
6602 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
6603 .load_lut
= intel_crtc_load_lut
,
6604 .disable
= intel_crtc_disable
,
6607 static const struct drm_crtc_funcs intel_crtc_funcs
= {
6608 .reset
= intel_crtc_reset
,
6609 .cursor_set
= intel_crtc_cursor_set
,
6610 .cursor_move
= intel_crtc_cursor_move
,
6611 .gamma_set
= intel_crtc_gamma_set
,
6612 .set_config
= drm_crtc_helper_set_config
,
6613 .destroy
= intel_crtc_destroy
,
6614 .page_flip
= intel_crtc_page_flip
,
6617 static void intel_pch_pll_init(struct drm_device
*dev
)
6619 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6622 if (dev_priv
->num_pch_pll
== 0) {
6623 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6627 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
6628 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
6629 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
6630 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
6634 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
6636 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6637 struct intel_crtc
*intel_crtc
;
6640 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
6641 if (intel_crtc
== NULL
)
6644 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
6646 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
6647 for (i
= 0; i
< 256; i
++) {
6648 intel_crtc
->lut_r
[i
] = i
;
6649 intel_crtc
->lut_g
[i
] = i
;
6650 intel_crtc
->lut_b
[i
] = i
;
6653 /* Swap pipes & planes for FBC on pre-965 */
6654 intel_crtc
->pipe
= pipe
;
6655 intel_crtc
->plane
= pipe
;
6656 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
6657 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6658 intel_crtc
->plane
= !pipe
;
6661 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
6662 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
6663 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
6664 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
6666 intel_crtc_reset(&intel_crtc
->base
);
6667 intel_crtc
->active
= true; /* force the pipe off on setup_init_config */
6668 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
6670 if (HAS_PCH_SPLIT(dev
)) {
6671 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
6672 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
6674 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
6675 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
6678 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
6680 intel_crtc
->busy
= false;
6682 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
6683 (unsigned long)intel_crtc
);
6686 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
6687 struct drm_file
*file
)
6689 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
6690 struct drm_mode_object
*drmmode_obj
;
6691 struct intel_crtc
*crtc
;
6693 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
6696 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
6697 DRM_MODE_OBJECT_CRTC
);
6700 DRM_ERROR("no such CRTC id\n");
6704 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
6705 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
6710 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
6712 struct intel_encoder
*encoder
;
6716 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6717 if (type_mask
& encoder
->clone_mask
)
6718 index_mask
|= (1 << entry
);
6725 static bool has_edp_a(struct drm_device
*dev
)
6727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6729 if (!IS_MOBILE(dev
))
6732 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
6736 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
6742 static void intel_setup_outputs(struct drm_device
*dev
)
6744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6745 struct intel_encoder
*encoder
;
6746 bool dpd_is_edp
= false;
6749 has_lvds
= intel_lvds_init(dev
);
6750 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
6751 /* disable the panel fitter on everything but LVDS */
6752 I915_WRITE(PFIT_CONTROL
, 0);
6755 if (HAS_PCH_SPLIT(dev
)) {
6756 dpd_is_edp
= intel_dpd_is_edp(dev
);
6759 intel_dp_init(dev
, DP_A
);
6761 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6762 intel_dp_init(dev
, PCH_DP_D
);
6765 intel_crt_init(dev
);
6767 if (IS_HASWELL(dev
)) {
6770 /* Haswell uses DDI functions to detect digital outputs */
6771 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
6772 /* DDI A only supports eDP */
6774 intel_ddi_init(dev
, PORT_A
);
6776 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6778 found
= I915_READ(SFUSE_STRAP
);
6780 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
6781 intel_ddi_init(dev
, PORT_B
);
6782 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
6783 intel_ddi_init(dev
, PORT_C
);
6784 if (found
& SFUSE_STRAP_DDID_DETECTED
)
6785 intel_ddi_init(dev
, PORT_D
);
6786 } else if (HAS_PCH_SPLIT(dev
)) {
6789 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
6790 /* PCH SDVOB multiplex with HDMIB */
6791 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
6793 intel_hdmi_init(dev
, HDMIB
);
6794 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
6795 intel_dp_init(dev
, PCH_DP_B
);
6798 if (I915_READ(HDMIC
) & PORT_DETECTED
)
6799 intel_hdmi_init(dev
, HDMIC
);
6801 if (!dpd_is_edp
&& I915_READ(HDMID
) & PORT_DETECTED
)
6802 intel_hdmi_init(dev
, HDMID
);
6804 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
6805 intel_dp_init(dev
, PCH_DP_C
);
6807 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6808 intel_dp_init(dev
, PCH_DP_D
);
6809 } else if (IS_VALLEYVIEW(dev
)) {
6812 if (I915_READ(SDVOB
) & PORT_DETECTED
) {
6813 /* SDVOB multiplex with HDMIB */
6814 found
= intel_sdvo_init(dev
, SDVOB
, true);
6816 intel_hdmi_init(dev
, SDVOB
);
6817 if (!found
&& (I915_READ(DP_B
) & DP_DETECTED
))
6818 intel_dp_init(dev
, DP_B
);
6821 if (I915_READ(SDVOC
) & PORT_DETECTED
)
6822 intel_hdmi_init(dev
, SDVOC
);
6824 /* Shares lanes with HDMI on SDVOC */
6825 if (I915_READ(DP_C
) & DP_DETECTED
)
6826 intel_dp_init(dev
, DP_C
);
6827 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
6830 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6831 DRM_DEBUG_KMS("probing SDVOB\n");
6832 found
= intel_sdvo_init(dev
, SDVOB
, true);
6833 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
6834 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6835 intel_hdmi_init(dev
, SDVOB
);
6838 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
6839 DRM_DEBUG_KMS("probing DP_B\n");
6840 intel_dp_init(dev
, DP_B
);
6844 /* Before G4X SDVOC doesn't have its own detect register */
6846 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6847 DRM_DEBUG_KMS("probing SDVOC\n");
6848 found
= intel_sdvo_init(dev
, SDVOC
, false);
6851 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
6853 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
6854 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6855 intel_hdmi_init(dev
, SDVOC
);
6857 if (SUPPORTS_INTEGRATED_DP(dev
)) {
6858 DRM_DEBUG_KMS("probing DP_C\n");
6859 intel_dp_init(dev
, DP_C
);
6863 if (SUPPORTS_INTEGRATED_DP(dev
) &&
6864 (I915_READ(DP_D
) & DP_DETECTED
)) {
6865 DRM_DEBUG_KMS("probing DP_D\n");
6866 intel_dp_init(dev
, DP_D
);
6868 } else if (IS_GEN2(dev
))
6869 intel_dvo_init(dev
);
6871 if (SUPPORTS_TV(dev
))
6874 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6875 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
6876 encoder
->base
.possible_clones
=
6877 intel_encoder_clones(dev
, encoder
->clone_mask
);
6880 /* disable all the possible outputs/crtcs before entering KMS mode */
6881 drm_helper_disable_unused_functions(dev
);
6883 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6884 ironlake_init_pch_refclk(dev
);
6887 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
6889 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6891 drm_framebuffer_cleanup(fb
);
6892 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
6897 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
6898 struct drm_file
*file
,
6899 unsigned int *handle
)
6901 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6902 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
6904 return drm_gem_handle_create(file
, &obj
->base
, handle
);
6907 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
6908 .destroy
= intel_user_framebuffer_destroy
,
6909 .create_handle
= intel_user_framebuffer_create_handle
,
6912 int intel_framebuffer_init(struct drm_device
*dev
,
6913 struct intel_framebuffer
*intel_fb
,
6914 struct drm_mode_fb_cmd2
*mode_cmd
,
6915 struct drm_i915_gem_object
*obj
)
6919 if (obj
->tiling_mode
== I915_TILING_Y
)
6922 if (mode_cmd
->pitches
[0] & 63)
6925 switch (mode_cmd
->pixel_format
) {
6926 case DRM_FORMAT_RGB332
:
6927 case DRM_FORMAT_RGB565
:
6928 case DRM_FORMAT_XRGB8888
:
6929 case DRM_FORMAT_XBGR8888
:
6930 case DRM_FORMAT_ARGB8888
:
6931 case DRM_FORMAT_XRGB2101010
:
6932 case DRM_FORMAT_ARGB2101010
:
6933 /* RGB formats are common across chipsets */
6935 case DRM_FORMAT_YUYV
:
6936 case DRM_FORMAT_UYVY
:
6937 case DRM_FORMAT_YVYU
:
6938 case DRM_FORMAT_VYUY
:
6941 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6942 mode_cmd
->pixel_format
);
6946 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
6948 DRM_ERROR("framebuffer init failed %d\n", ret
);
6952 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
6953 intel_fb
->obj
= obj
;
6957 static struct drm_framebuffer
*
6958 intel_user_framebuffer_create(struct drm_device
*dev
,
6959 struct drm_file
*filp
,
6960 struct drm_mode_fb_cmd2
*mode_cmd
)
6962 struct drm_i915_gem_object
*obj
;
6964 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
6965 mode_cmd
->handles
[0]));
6966 if (&obj
->base
== NULL
)
6967 return ERR_PTR(-ENOENT
);
6969 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
6972 static const struct drm_mode_config_funcs intel_mode_funcs
= {
6973 .fb_create
= intel_user_framebuffer_create
,
6974 .output_poll_changed
= intel_fb_output_poll_changed
,
6977 /* Set up chip specific display functions */
6978 static void intel_init_display(struct drm_device
*dev
)
6980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6982 /* We always want a DPMS function */
6983 if (HAS_PCH_SPLIT(dev
)) {
6984 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
6985 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
6986 dev_priv
->display
.off
= ironlake_crtc_off
;
6987 dev_priv
->display
.update_plane
= ironlake_update_plane
;
6989 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
6990 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
6991 dev_priv
->display
.off
= i9xx_crtc_off
;
6992 dev_priv
->display
.update_plane
= i9xx_update_plane
;
6995 /* Returns the core display clock speed */
6996 if (IS_VALLEYVIEW(dev
))
6997 dev_priv
->display
.get_display_clock_speed
=
6998 valleyview_get_display_clock_speed
;
6999 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
7000 dev_priv
->display
.get_display_clock_speed
=
7001 i945_get_display_clock_speed
;
7002 else if (IS_I915G(dev
))
7003 dev_priv
->display
.get_display_clock_speed
=
7004 i915_get_display_clock_speed
;
7005 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
7006 dev_priv
->display
.get_display_clock_speed
=
7007 i9xx_misc_get_display_clock_speed
;
7008 else if (IS_I915GM(dev
))
7009 dev_priv
->display
.get_display_clock_speed
=
7010 i915gm_get_display_clock_speed
;
7011 else if (IS_I865G(dev
))
7012 dev_priv
->display
.get_display_clock_speed
=
7013 i865_get_display_clock_speed
;
7014 else if (IS_I85X(dev
))
7015 dev_priv
->display
.get_display_clock_speed
=
7016 i855_get_display_clock_speed
;
7018 dev_priv
->display
.get_display_clock_speed
=
7019 i830_get_display_clock_speed
;
7021 if (HAS_PCH_SPLIT(dev
)) {
7023 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
7024 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7025 } else if (IS_GEN6(dev
)) {
7026 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
7027 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7028 } else if (IS_IVYBRIDGE(dev
)) {
7029 /* FIXME: detect B0+ stepping and use auto training */
7030 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
7031 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7032 } else if (IS_HASWELL(dev
)) {
7033 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
7034 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7036 dev_priv
->display
.update_wm
= NULL
;
7037 } else if (IS_G4X(dev
)) {
7038 dev_priv
->display
.write_eld
= g4x_write_eld
;
7041 /* Default just returns -ENODEV to indicate unsupported */
7042 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
7044 switch (INTEL_INFO(dev
)->gen
) {
7046 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
7050 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
7055 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
7059 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
7062 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
7068 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7069 * resume, or other times. This quirk makes sure that's the case for
7072 static void quirk_pipea_force(struct drm_device
*dev
)
7074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7076 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
7077 DRM_INFO("applying pipe a force quirk\n");
7081 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7083 static void quirk_ssc_force_disable(struct drm_device
*dev
)
7085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7086 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
7087 DRM_INFO("applying lvds SSC disable quirk\n");
7091 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7094 static void quirk_invert_brightness(struct drm_device
*dev
)
7096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7097 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
7098 DRM_INFO("applying inverted panel brightness quirk\n");
7101 struct intel_quirk
{
7103 int subsystem_vendor
;
7104 int subsystem_device
;
7105 void (*hook
)(struct drm_device
*dev
);
7108 static struct intel_quirk intel_quirks
[] = {
7109 /* HP Mini needs pipe A force quirk (LP: #322104) */
7110 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
7112 /* Thinkpad R31 needs pipe A force quirk */
7113 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
7114 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7115 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
7117 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7118 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
7119 /* ThinkPad X40 needs pipe A force quirk */
7121 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7122 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
7124 /* 855 & before need to leave pipe A & dpll A up */
7125 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7126 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7128 /* Lenovo U160 cannot use SSC on LVDS */
7129 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
7131 /* Sony Vaio Y cannot use SSC on LVDS */
7132 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
7134 /* Acer Aspire 5734Z must invert backlight brightness */
7135 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
7138 static void intel_init_quirks(struct drm_device
*dev
)
7140 struct pci_dev
*d
= dev
->pdev
;
7143 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
7144 struct intel_quirk
*q
= &intel_quirks
[i
];
7146 if (d
->device
== q
->device
&&
7147 (d
->subsystem_vendor
== q
->subsystem_vendor
||
7148 q
->subsystem_vendor
== PCI_ANY_ID
) &&
7149 (d
->subsystem_device
== q
->subsystem_device
||
7150 q
->subsystem_device
== PCI_ANY_ID
))
7155 /* Disable the VGA plane that we never use */
7156 static void i915_disable_vga(struct drm_device
*dev
)
7158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7162 if (HAS_PCH_SPLIT(dev
))
7163 vga_reg
= CPU_VGACNTRL
;
7167 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7168 outb(SR01
, VGA_SR_INDEX
);
7169 sr1
= inb(VGA_SR_DATA
);
7170 outb(sr1
| 1<<5, VGA_SR_DATA
);
7171 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7174 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
7175 POSTING_READ(vga_reg
);
7178 void intel_modeset_init_hw(struct drm_device
*dev
)
7180 /* We attempt to init the necessary power wells early in the initialization
7181 * time, so the subsystems that expect power to be enabled can work.
7183 intel_init_power_wells(dev
);
7185 intel_prepare_ddi(dev
);
7187 intel_init_clock_gating(dev
);
7189 mutex_lock(&dev
->struct_mutex
);
7190 intel_enable_gt_powersave(dev
);
7191 mutex_unlock(&dev
->struct_mutex
);
7194 void intel_modeset_init(struct drm_device
*dev
)
7196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7199 drm_mode_config_init(dev
);
7201 dev
->mode_config
.min_width
= 0;
7202 dev
->mode_config
.min_height
= 0;
7204 dev
->mode_config
.preferred_depth
= 24;
7205 dev
->mode_config
.prefer_shadow
= 1;
7207 dev
->mode_config
.funcs
= &intel_mode_funcs
;
7209 intel_init_quirks(dev
);
7213 intel_init_display(dev
);
7216 dev
->mode_config
.max_width
= 2048;
7217 dev
->mode_config
.max_height
= 2048;
7218 } else if (IS_GEN3(dev
)) {
7219 dev
->mode_config
.max_width
= 4096;
7220 dev
->mode_config
.max_height
= 4096;
7222 dev
->mode_config
.max_width
= 8192;
7223 dev
->mode_config
.max_height
= 8192;
7225 dev
->mode_config
.fb_base
= dev_priv
->mm
.gtt_base_addr
;
7227 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7228 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
7230 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
7231 intel_crtc_init(dev
, i
);
7232 ret
= intel_plane_init(dev
, i
);
7234 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
7237 intel_pch_pll_init(dev
);
7239 /* Just disable it once at startup */
7240 i915_disable_vga(dev
);
7241 intel_setup_outputs(dev
);
7243 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
7244 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
7245 (unsigned long)dev
);
7248 void intel_modeset_gem_init(struct drm_device
*dev
)
7250 intel_modeset_init_hw(dev
);
7252 intel_setup_overlay(dev
);
7255 void intel_modeset_cleanup(struct drm_device
*dev
)
7257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7258 struct drm_crtc
*crtc
;
7259 struct intel_crtc
*intel_crtc
;
7261 drm_kms_helper_poll_fini(dev
);
7262 mutex_lock(&dev
->struct_mutex
);
7264 intel_unregister_dsm_handler();
7267 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7268 /* Skip inactive CRTCs */
7272 intel_crtc
= to_intel_crtc(crtc
);
7273 intel_increase_pllclock(crtc
);
7276 intel_disable_fbc(dev
);
7278 intel_disable_gt_powersave(dev
);
7280 ironlake_teardown_rc6(dev
);
7282 if (IS_VALLEYVIEW(dev
))
7285 mutex_unlock(&dev
->struct_mutex
);
7287 /* Disable the irq before mode object teardown, for the irq might
7288 * enqueue unpin/hotplug work. */
7289 drm_irq_uninstall(dev
);
7290 cancel_work_sync(&dev_priv
->hotplug_work
);
7291 cancel_work_sync(&dev_priv
->rps_work
);
7293 /* flush any delayed tasks or pending work */
7294 flush_scheduled_work();
7296 /* Shut off idle work before the crtcs get freed. */
7297 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7298 intel_crtc
= to_intel_crtc(crtc
);
7299 del_timer_sync(&intel_crtc
->idle_timer
);
7301 del_timer_sync(&dev_priv
->idle_timer
);
7302 cancel_work_sync(&dev_priv
->idle_work
);
7304 drm_mode_config_cleanup(dev
);
7308 * Return which encoder is currently attached for connector.
7310 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
7312 return &intel_attached_encoder(connector
)->base
;
7315 void intel_connector_attach_encoder(struct intel_connector
*connector
,
7316 struct intel_encoder
*encoder
)
7318 connector
->encoder
= encoder
;
7319 drm_mode_connector_attach_encoder(&connector
->base
,
7324 * set vga decode state - true == enable VGA decode
7326 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
7328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7331 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
7333 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
7335 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
7336 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
7340 #ifdef CONFIG_DEBUG_FS
7341 #include <linux/seq_file.h>
7343 struct intel_display_error_state
{
7344 struct intel_cursor_error_state
{
7351 struct intel_pipe_error_state
{
7363 struct intel_plane_error_state
{
7374 struct intel_display_error_state
*
7375 intel_display_capture_error_state(struct drm_device
*dev
)
7377 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7378 struct intel_display_error_state
*error
;
7381 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
7385 for (i
= 0; i
< 2; i
++) {
7386 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
7387 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
7388 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
7390 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
7391 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
7392 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
7393 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
7394 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
7395 if (INTEL_INFO(dev
)->gen
>= 4) {
7396 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
7397 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
7400 error
->pipe
[i
].conf
= I915_READ(PIPECONF(i
));
7401 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
7402 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(i
));
7403 error
->pipe
[i
].hblank
= I915_READ(HBLANK(i
));
7404 error
->pipe
[i
].hsync
= I915_READ(HSYNC(i
));
7405 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(i
));
7406 error
->pipe
[i
].vblank
= I915_READ(VBLANK(i
));
7407 error
->pipe
[i
].vsync
= I915_READ(VSYNC(i
));
7414 intel_display_print_error_state(struct seq_file
*m
,
7415 struct drm_device
*dev
,
7416 struct intel_display_error_state
*error
)
7420 for (i
= 0; i
< 2; i
++) {
7421 seq_printf(m
, "Pipe [%d]:\n", i
);
7422 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
7423 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
7424 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
7425 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
7426 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
7427 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
7428 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
7429 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
7431 seq_printf(m
, "Plane [%d]:\n", i
);
7432 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
7433 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
7434 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
7435 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
7436 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
7437 if (INTEL_INFO(dev
)->gen
>= 4) {
7438 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
7439 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
7442 seq_printf(m
, "Cursor [%d]:\n", i
);
7443 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
7444 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
7445 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);