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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58 } intel_clock_t;
59
60 typedef struct {
61 int min, max;
62 } intel_range_t;
63
64 typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
92 };
93
94 /* FDI */
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
97 int
98 intel_pch_rawclk(struct drm_device *dev)
99 {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105 }
106
107 static bool
108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
111 static bool
112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
116 static bool
117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
120 static bool
121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
124
125 static bool
126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
130 static inline u32 /* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device *dev)
132 {
133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
138 }
139
140 static const intel_limit_t intel_limits_i8xx_dvo = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
151 .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i8xx_lvds = {
155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
166 };
167
168 static const intel_limit_t intel_limits_i9xx_sdvo = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
179 .find_pll = intel_find_best_PLL,
180 };
181
182 static const intel_limit_t intel_limits_i9xx_lvds = {
183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
193 .find_pll = intel_find_best_PLL,
194 };
195
196
197 static const intel_limit_t intel_limits_g4x_sdvo = {
198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
209 },
210 .find_pll = intel_g4x_find_best_PLL,
211 };
212
213 static const intel_limit_t intel_limits_g4x_hdmi = {
214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
224 .find_pll = intel_g4x_find_best_PLL,
225 };
226
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
238 },
239 .find_pll = intel_g4x_find_best_PLL,
240 };
241
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
253 },
254 .find_pll = intel_g4x_find_best_PLL,
255 };
256
257 static const intel_limit_t intel_limits_g4x_display_port = {
258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 10, .p2_fast = 10 },
268 .find_pll = intel_find_pll_g4x_dp,
269 };
270
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_find_best_PLL,
285 };
286
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_find_best_PLL,
299 };
300
301 /* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
306 static const intel_limit_t intel_limits_ironlake_dac = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
317 .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
332 };
333
334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
346 };
347
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
357 .p1 = { .min = 2, .max = 8 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
360 .find_pll = intel_g4x_find_best_PLL,
361 };
362
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 .find_pll = intel_g4x_find_best_PLL,
375 };
376
377 static const intel_limit_t intel_limits_ironlake_display_port = {
378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
387 .p2_slow = 10, .p2_fast = 10 },
388 .find_pll = intel_find_pll_ironlake_dp,
389 };
390
391 static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403 };
404
405 static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
407 .vco = { .min = 4000000, .max = 5994000},
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417 };
418
419 static const intel_limit_t intel_limits_vlv_dp = {
420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
422 .n = { .min = 1, .max = 7 },
423 .m = { .min = 22, .max = 450 },
424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431 };
432
433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434 {
435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
436
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
439 return 0;
440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
447 return 0;
448 }
449
450 return I915_READ(DPIO_DATA);
451 }
452
453 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455 {
456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
457
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
460 return;
461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
469 }
470
471 static void vlv_init_dpio(struct drm_device *dev)
472 {
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480 }
481
482 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
484 {
485 struct drm_device *dev = crtc->dev;
486 const intel_limit_t *limit;
487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
489 if (intel_is_dual_link_lvds(dev)) {
490 if (refclk == 100000)
491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
495 if (refclk == 100000)
496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
502 limit = &intel_limits_ironlake_display_port;
503 else
504 limit = &intel_limits_ironlake_dac;
505
506 return limit;
507 }
508
509 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510 {
511 struct drm_device *dev = crtc->dev;
512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
515 if (intel_is_dual_link_lvds(dev))
516 limit = &intel_limits_g4x_dual_channel_lvds;
517 else
518 limit = &intel_limits_g4x_single_channel_lvds;
519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
521 limit = &intel_limits_g4x_hdmi;
522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
523 limit = &intel_limits_g4x_sdvo;
524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
525 limit = &intel_limits_g4x_display_port;
526 } else /* The option is for other outputs */
527 limit = &intel_limits_i9xx_sdvo;
528
529 return limit;
530 }
531
532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
533 {
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
537 if (HAS_PCH_SPLIT(dev))
538 limit = intel_ironlake_limit(crtc, refclk);
539 else if (IS_G4X(dev)) {
540 limit = intel_g4x_limit(crtc);
541 } else if (IS_PINEVIEW(dev)) {
542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_pineview_lvds;
544 else
545 limit = &intel_limits_pineview_sdvo;
546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
560 limit = &intel_limits_i8xx_lvds;
561 else
562 limit = &intel_limits_i8xx_dvo;
563 }
564 return limit;
565 }
566
567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
568 static void pineview_clock(int refclk, intel_clock_t *clock)
569 {
570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574 }
575
576 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577 {
578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
580 return;
581 }
582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586 }
587
588 /**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
591 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
592 {
593 struct drm_device *dev = crtc->dev;
594 struct intel_encoder *encoder;
595
596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
598 return true;
599
600 return false;
601 }
602
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
604 /**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
609 static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
612 {
613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock->p < limit->p.min || limit->p.max < clock->p)
616 INTELPllInvalid("p out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
622 INTELPllInvalid("m1 <= m2\n");
623 if (clock->m < limit->m.min || limit->m.max < clock->m)
624 INTELPllInvalid("m out of range\n");
625 if (clock->n < limit->n.min || limit->n.max < clock->n)
626 INTELPllInvalid("n out of range\n");
627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
633 INTELPllInvalid("dot out of range\n");
634
635 return true;
636 }
637
638 static bool
639 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
642
643 {
644 struct drm_device *dev = crtc->dev;
645 intel_clock_t clock;
646 int err = target;
647
648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
649 /*
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
653 */
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
678 int this_err;
679
680 intel_clock(dev, refclk, &clock);
681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
683 continue;
684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699 }
700
701 static bool
702 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
705 {
706 struct drm_device *dev = crtc->dev;
707 intel_clock_t clock;
708 int max_n;
709 bool found;
710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
715 int lvds_reg;
716
717 if (HAS_PCH_SPLIT(dev))
718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
721 if (intel_is_dual_link_lvds(dev))
722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
736 /* based on hardware requirement, prefere larger m1,m2 */
737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
745 intel_clock(dev, refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
748 continue;
749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
752
753 this_err = abs(clock.dot - target);
754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
764 return found;
765 }
766
767 static bool
768 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
771 {
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
774
775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791 }
792
793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
794 static bool
795 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
798 {
799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
819 }
820 static bool
821 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824 {
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
831 flag = 0;
832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887 }
888
889 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891 {
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->config.cpu_transcoder;
896 }
897
898 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899 {
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907 }
908
909 /**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
918 {
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 int pipestat_reg = PIPESTAT(pipe);
921
922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
943 /* Wait for vblank interrupt bit to set */
944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
947 DRM_DEBUG_KMS("vblank wait timed out\n");
948 }
949
950 /*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
965 *
966 */
967 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
968 {
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
972
973 if (INTEL_INFO(dev)->gen >= 4) {
974 int reg = PIPECONF(cpu_transcoder);
975
976 /* Wait for the Pipe State to go off */
977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
979 WARN(1, "pipe_off wait timed out\n");
980 } else {
981 u32 last_line, line_mask;
982 int reg = PIPEDSL(pipe);
983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
990 /* Wait for the display line to settle */
991 do {
992 last_line = I915_READ(reg) & line_mask;
993 mdelay(5);
994 } while (((I915_READ(reg) & line_mask) != last_line) &&
995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
997 WARN(1, "pipe_off wait timed out\n");
998 }
999 }
1000
1001 /*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010 {
1011 u32 bit;
1012
1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044 }
1045
1046 static const char *state_string(bool enabled)
1047 {
1048 return enabled ? "on" : "off";
1049 }
1050
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054 {
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065 }
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
1069 /* For ILK+ */
1070 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
1074 {
1075 u32 val;
1076 bool cur_state;
1077
1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1085 return;
1086
1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
1110 }
1111 }
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1114
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117 {
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
1123
1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137 }
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160 {
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv->dev))
1170 return;
1171
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175 }
1176
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179 {
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190 {
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
1194 bool locked = true;
1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
1214 pipe_name(pipe));
1215 }
1216
1217 void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 int reg;
1221 u32 val;
1222 bool cur_state;
1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
1225
1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
1230 if (!intel_using_power_well(dev_priv->dev) &&
1231 cpu_transcoder != TRANSCODER_EDP) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1246 {
1247 int reg;
1248 u32 val;
1249 bool cur_state;
1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
1269 /* Planes are fixed to pipes on ILK+ */
1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
1276 return;
1277 }
1278
1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
1288 }
1289 }
1290
1291 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int reg, i;
1295 u32 val;
1296
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1298 return;
1299
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe));
1307 }
1308 }
1309
1310 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311 {
1312 u32 val;
1313 bool enabled;
1314
1315 if (HAS_PCH_LPT(dev_priv->dev)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317 return;
1318 }
1319
1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324 }
1325
1326 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328 {
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
1336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
1339 }
1340
1341 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
1343 {
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else {
1353 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354 return false;
1355 }
1356 return true;
1357 }
1358
1359 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361 {
1362 if ((val & SDVO_ENABLE) == 0)
1363 return false;
1364
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
1366 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1367 return false;
1368 } else {
1369 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1370 return false;
1371 }
1372 return true;
1373 }
1374
1375 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1377 {
1378 if ((val & LVDS_PORT_EN) == 0)
1379 return false;
1380
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383 return false;
1384 } else {
1385 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386 return false;
1387 }
1388 return true;
1389 }
1390
1391 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393 {
1394 if ((val & ADPA_DAC_ENABLE) == 0)
1395 return false;
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398 return false;
1399 } else {
1400 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, int reg, u32 port_sel)
1408 {
1409 u32 val = I915_READ(reg);
1410 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1412 reg, pipe_name(pipe));
1413
1414 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415 && (val & DP_PIPEB_SELECT),
1416 "IBX PCH dp port still using transcoder B\n");
1417 }
1418
1419 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, int reg)
1421 {
1422 u32 val = I915_READ(reg);
1423 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1425 reg, pipe_name(pipe));
1426
1427 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1428 && (val & SDVO_PIPE_B_SELECT),
1429 "IBX PCH hdmi port still using transcoder B\n");
1430 }
1431
1432 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434 {
1435 int reg;
1436 u32 val;
1437
1438 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1441
1442 reg = PCH_ADPA;
1443 val = I915_READ(reg);
1444 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
1446 pipe_name(pipe));
1447
1448 reg = PCH_LVDS;
1449 val = I915_READ(reg);
1450 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1452 pipe_name(pipe));
1453
1454 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1457 }
1458
1459 /**
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1463 *
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1467 *
1468 * Note! This is for pre-ILK only.
1469 *
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1471 */
1472 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474 int reg;
1475 u32 val;
1476
1477 /* No really, not for ILK+ */
1478 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1479
1480 /* PLL is protected by panel, make sure we can write it */
1481 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1482 assert_panel_unlocked(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val |= DPLL_VCO_ENABLE;
1487
1488 /* We do this three times for luck */
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491 udelay(150); /* wait for warmup */
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494 udelay(150); /* wait for warmup */
1495 I915_WRITE(reg, val);
1496 POSTING_READ(reg);
1497 udelay(150); /* wait for warmup */
1498 }
1499
1500 /**
1501 * intel_disable_pll - disable a PLL
1502 * @dev_priv: i915 private structure
1503 * @pipe: pipe PLL to disable
1504 *
1505 * Disable the PLL for @pipe, making sure the pipe is off first.
1506 *
1507 * Note! This is for pre-ILK only.
1508 */
1509 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1510 {
1511 int reg;
1512 u32 val;
1513
1514 /* Don't disable pipe A or pipe A PLLs if needed */
1515 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1516 return;
1517
1518 /* Make sure the pipe isn't still relying on us */
1519 assert_pipe_disabled(dev_priv, pipe);
1520
1521 reg = DPLL(pipe);
1522 val = I915_READ(reg);
1523 val &= ~DPLL_VCO_ENABLE;
1524 I915_WRITE(reg, val);
1525 POSTING_READ(reg);
1526 }
1527
1528 /* SBI access */
1529 static void
1530 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531 enum intel_sbi_destination destination)
1532 {
1533 u32 tmp;
1534
1535 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1536
1537 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
1540 return;
1541 }
1542
1543 I915_WRITE(SBI_ADDR, (reg << 16));
1544 I915_WRITE(SBI_DATA, value);
1545
1546 if (destination == SBI_ICLK)
1547 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548 else
1549 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1550 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1551
1552 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1553 100)) {
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1555 return;
1556 }
1557 }
1558
1559 static u32
1560 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561 enum intel_sbi_destination destination)
1562 {
1563 u32 value = 0;
1564 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1565
1566 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
1569 return 0;
1570 }
1571
1572 I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574 if (destination == SBI_ICLK)
1575 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576 else
1577 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1579
1580 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1581 100)) {
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1583 return 0;
1584 }
1585
1586 return I915_READ(SBI_DATA);
1587 }
1588
1589 /**
1590 * ironlake_enable_pch_pll - enable PCH PLL
1591 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable
1593 *
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock.
1596 */
1597 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1598 {
1599 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1600 struct intel_pch_pll *pll;
1601 int reg;
1602 u32 val;
1603
1604 /* PCH PLLs only available on ILK, SNB and IVB */
1605 BUG_ON(dev_priv->info->gen < 5);
1606 pll = intel_crtc->pch_pll;
1607 if (pll == NULL)
1608 return;
1609
1610 if (WARN_ON(pll->refcount == 0))
1611 return;
1612
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614 pll->pll_reg, pll->active, pll->on,
1615 intel_crtc->base.base.id);
1616
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv);
1619
1620 if (pll->active++ && pll->on) {
1621 assert_pch_pll_enabled(dev_priv, pll, NULL);
1622 return;
1623 }
1624
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1626
1627 reg = pll->pll_reg;
1628 val = I915_READ(reg);
1629 val |= DPLL_VCO_ENABLE;
1630 I915_WRITE(reg, val);
1631 POSTING_READ(reg);
1632 udelay(200);
1633
1634 pll->on = true;
1635 }
1636
1637 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1638 {
1639 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1640 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1641 int reg;
1642 u32 val;
1643
1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5);
1646 if (pll == NULL)
1647 return;
1648
1649 if (WARN_ON(pll->refcount == 0))
1650 return;
1651
1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653 pll->pll_reg, pll->active, pll->on,
1654 intel_crtc->base.base.id);
1655
1656 if (WARN_ON(pll->active == 0)) {
1657 assert_pch_pll_disabled(dev_priv, pll, NULL);
1658 return;
1659 }
1660
1661 if (--pll->active) {
1662 assert_pch_pll_enabled(dev_priv, pll, NULL);
1663 return;
1664 }
1665
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1667
1668 /* Make sure transcoder isn't still depending on us */
1669 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1670
1671 reg = pll->pll_reg;
1672 val = I915_READ(reg);
1673 val &= ~DPLL_VCO_ENABLE;
1674 I915_WRITE(reg, val);
1675 POSTING_READ(reg);
1676 udelay(200);
1677
1678 pll->on = false;
1679 }
1680
1681 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
1683 {
1684 struct drm_device *dev = dev_priv->dev;
1685 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1686 uint32_t reg, val, pipeconf_val;
1687
1688 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv->info->gen < 5);
1690
1691 /* Make sure PCH DPLL is enabled */
1692 assert_pch_pll_enabled(dev_priv,
1693 to_intel_crtc(crtc)->pch_pll,
1694 to_intel_crtc(crtc));
1695
1696 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv, pipe);
1698 assert_fdi_rx_enabled(dev_priv, pipe);
1699
1700 if (HAS_PCH_CPT(dev)) {
1701 /* Workaround: Set the timing override bit before enabling the
1702 * pch transcoder. */
1703 reg = TRANS_CHICKEN2(pipe);
1704 val = I915_READ(reg);
1705 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1706 I915_WRITE(reg, val);
1707 }
1708
1709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
1711 pipeconf_val = I915_READ(PIPECONF(pipe));
1712
1713 if (HAS_PCH_IBX(dev_priv->dev)) {
1714 /*
1715 * make the BPC in transcoder be consistent with
1716 * that in pipeconf reg.
1717 */
1718 val &= ~PIPECONF_BPC_MASK;
1719 val |= pipeconf_val & PIPECONF_BPC_MASK;
1720 }
1721
1722 val &= ~TRANS_INTERLACE_MASK;
1723 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1724 if (HAS_PCH_IBX(dev_priv->dev) &&
1725 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1726 val |= TRANS_LEGACY_INTERLACED_ILK;
1727 else
1728 val |= TRANS_INTERLACED;
1729 else
1730 val |= TRANS_PROGRESSIVE;
1731
1732 I915_WRITE(reg, val | TRANS_ENABLE);
1733 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1735 }
1736
1737 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1738 enum transcoder cpu_transcoder)
1739 {
1740 u32 val, pipeconf_val;
1741
1742 /* PCH only available on ILK+ */
1743 BUG_ON(dev_priv->info->gen < 5);
1744
1745 /* FDI must be feeding us bits for PCH ports */
1746 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1747 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1748
1749 /* Workaround: set timing override bit. */
1750 val = I915_READ(_TRANSA_CHICKEN2);
1751 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1752 I915_WRITE(_TRANSA_CHICKEN2, val);
1753
1754 val = TRANS_ENABLE;
1755 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1756
1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1758 PIPECONF_INTERLACED_ILK)
1759 val |= TRANS_INTERLACED;
1760 else
1761 val |= TRANS_PROGRESSIVE;
1762
1763 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1764 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n");
1766 }
1767
1768 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum pipe pipe)
1770 {
1771 struct drm_device *dev = dev_priv->dev;
1772 uint32_t reg, val;
1773
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv, pipe);
1776 assert_fdi_rx_disabled(dev_priv, pipe);
1777
1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe);
1780
1781 reg = TRANSCONF(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1787 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1788
1789 if (!HAS_PCH_IBX(dev)) {
1790 /* Workaround: Clear the timing override chicken bit again. */
1791 reg = TRANS_CHICKEN2(pipe);
1792 val = I915_READ(reg);
1793 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1794 I915_WRITE(reg, val);
1795 }
1796 }
1797
1798 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1799 {
1800 u32 val;
1801
1802 val = I915_READ(_TRANSACONF);
1803 val &= ~TRANS_ENABLE;
1804 I915_WRITE(_TRANSACONF, val);
1805 /* wait for PCH transcoder off, transcoder state */
1806 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n");
1808
1809 /* Workaround: clear timing override bit. */
1810 val = I915_READ(_TRANSA_CHICKEN2);
1811 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1812 I915_WRITE(_TRANSA_CHICKEN2, val);
1813 }
1814
1815 /**
1816 * intel_enable_pipe - enable a pipe, asserting requirements
1817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
1819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1820 *
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823 *
1824 * @pipe should be %PIPE_A or %PIPE_B.
1825 *
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1827 * returning.
1828 */
1829 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830 bool pch_port)
1831 {
1832 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833 pipe);
1834 enum pipe pch_transcoder;
1835 int reg;
1836 u32 val;
1837
1838 if (HAS_PCH_LPT(dev_priv->dev))
1839 pch_transcoder = TRANSCODER_A;
1840 else
1841 pch_transcoder = pipe;
1842
1843 /*
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1846 * need the check.
1847 */
1848 if (!HAS_PCH_SPLIT(dev_priv->dev))
1849 assert_pll_enabled(dev_priv, pipe);
1850 else {
1851 if (pch_port) {
1852 /* if driving the PCH, we need FDI enabled */
1853 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1854 assert_fdi_tx_pll_enabled(dev_priv,
1855 (enum pipe) cpu_transcoder);
1856 }
1857 /* FIXME: assert CPU port conditions for SNB+ */
1858 }
1859
1860 reg = PIPECONF(cpu_transcoder);
1861 val = I915_READ(reg);
1862 if (val & PIPECONF_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | PIPECONF_ENABLE);
1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867 }
1868
1869 /**
1870 * intel_disable_pipe - disable a pipe, asserting requirements
1871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1873 *
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876 *
1877 * @pipe should be %PIPE_A or %PIPE_B.
1878 *
1879 * Will wait until the pipe has shut down before returning.
1880 */
1881 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882 enum pipe pipe)
1883 {
1884 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885 pipe);
1886 int reg;
1887 u32 val;
1888
1889 /*
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1892 */
1893 assert_planes_disabled(dev_priv, pipe);
1894 assert_sprites_disabled(dev_priv, pipe);
1895
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898 return;
1899
1900 reg = PIPECONF(cpu_transcoder);
1901 val = I915_READ(reg);
1902 if ((val & PIPECONF_ENABLE) == 0)
1903 return;
1904
1905 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1906 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907 }
1908
1909 /*
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1912 */
1913 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1914 enum plane plane)
1915 {
1916 if (dev_priv->info->gen >= 4)
1917 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918 else
1919 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1920 }
1921
1922 /**
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1927 *
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1929 */
1930 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932 {
1933 int reg;
1934 u32 val;
1935
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv, pipe);
1938
1939 reg = DSPCNTR(plane);
1940 val = I915_READ(reg);
1941 if (val & DISPLAY_PLANE_ENABLE)
1942 return;
1943
1944 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1945 intel_flush_display_plane(dev_priv, plane);
1946 intel_wait_for_vblank(dev_priv->dev, pipe);
1947 }
1948
1949 /**
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1954 *
1955 * Disable @plane; should be an independent operation.
1956 */
1957 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958 enum plane plane, enum pipe pipe)
1959 {
1960 int reg;
1961 u32 val;
1962
1963 reg = DSPCNTR(plane);
1964 val = I915_READ(reg);
1965 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966 return;
1967
1968 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1969 intel_flush_display_plane(dev_priv, plane);
1970 intel_wait_for_vblank(dev_priv->dev, pipe);
1971 }
1972
1973 static bool need_vtd_wa(struct drm_device *dev)
1974 {
1975 #ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977 return true;
1978 #endif
1979 return false;
1980 }
1981
1982 int
1983 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1984 struct drm_i915_gem_object *obj,
1985 struct intel_ring_buffer *pipelined)
1986 {
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 u32 alignment;
1989 int ret;
1990
1991 switch (obj->tiling_mode) {
1992 case I915_TILING_NONE:
1993 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994 alignment = 128 * 1024;
1995 else if (INTEL_INFO(dev)->gen >= 4)
1996 alignment = 4 * 1024;
1997 else
1998 alignment = 64 * 1024;
1999 break;
2000 case I915_TILING_X:
2001 /* pin() will align the object as required by fence */
2002 alignment = 0;
2003 break;
2004 case I915_TILING_Y:
2005 /* Despite that we check this in framebuffer_init userspace can
2006 * screw us over and change the tiling after the fact. Only
2007 * pinned buffers can't change their tiling. */
2008 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2009 return -EINVAL;
2010 default:
2011 BUG();
2012 }
2013
2014 /* Note that the w/a also requires 64 PTE of padding following the
2015 * bo. We currently fill all unused PTE with the shadow page and so
2016 * we should always have valid PTE following the scanout preventing
2017 * the VT-d warning.
2018 */
2019 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2020 alignment = 256 * 1024;
2021
2022 dev_priv->mm.interruptible = false;
2023 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2024 if (ret)
2025 goto err_interruptible;
2026
2027 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2028 * fence, whereas 965+ only requires a fence if using
2029 * framebuffer compression. For simplicity, we always install
2030 * a fence as the cost is not that onerous.
2031 */
2032 ret = i915_gem_object_get_fence(obj);
2033 if (ret)
2034 goto err_unpin;
2035
2036 i915_gem_object_pin_fence(obj);
2037
2038 dev_priv->mm.interruptible = true;
2039 return 0;
2040
2041 err_unpin:
2042 i915_gem_object_unpin(obj);
2043 err_interruptible:
2044 dev_priv->mm.interruptible = true;
2045 return ret;
2046 }
2047
2048 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2049 {
2050 i915_gem_object_unpin_fence(obj);
2051 i915_gem_object_unpin(obj);
2052 }
2053
2054 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2055 * is assumed to be a power-of-two. */
2056 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2057 unsigned int tiling_mode,
2058 unsigned int cpp,
2059 unsigned int pitch)
2060 {
2061 if (tiling_mode != I915_TILING_NONE) {
2062 unsigned int tile_rows, tiles;
2063
2064 tile_rows = *y / 8;
2065 *y %= 8;
2066
2067 tiles = *x / (512/cpp);
2068 *x %= 512/cpp;
2069
2070 return tile_rows * pitch * 8 + tiles * 4096;
2071 } else {
2072 unsigned int offset;
2073
2074 offset = *y * pitch + *x * cpp;
2075 *y = 0;
2076 *x = (offset & 4095) / cpp;
2077 return offset & -4096;
2078 }
2079 }
2080
2081 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2082 int x, int y)
2083 {
2084 struct drm_device *dev = crtc->dev;
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2087 struct intel_framebuffer *intel_fb;
2088 struct drm_i915_gem_object *obj;
2089 int plane = intel_crtc->plane;
2090 unsigned long linear_offset;
2091 u32 dspcntr;
2092 u32 reg;
2093
2094 switch (plane) {
2095 case 0:
2096 case 1:
2097 break;
2098 default:
2099 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2100 return -EINVAL;
2101 }
2102
2103 intel_fb = to_intel_framebuffer(fb);
2104 obj = intel_fb->obj;
2105
2106 reg = DSPCNTR(plane);
2107 dspcntr = I915_READ(reg);
2108 /* Mask out pixel format bits in case we change it */
2109 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2110 switch (fb->pixel_format) {
2111 case DRM_FORMAT_C8:
2112 dspcntr |= DISPPLANE_8BPP;
2113 break;
2114 case DRM_FORMAT_XRGB1555:
2115 case DRM_FORMAT_ARGB1555:
2116 dspcntr |= DISPPLANE_BGRX555;
2117 break;
2118 case DRM_FORMAT_RGB565:
2119 dspcntr |= DISPPLANE_BGRX565;
2120 break;
2121 case DRM_FORMAT_XRGB8888:
2122 case DRM_FORMAT_ARGB8888:
2123 dspcntr |= DISPPLANE_BGRX888;
2124 break;
2125 case DRM_FORMAT_XBGR8888:
2126 case DRM_FORMAT_ABGR8888:
2127 dspcntr |= DISPPLANE_RGBX888;
2128 break;
2129 case DRM_FORMAT_XRGB2101010:
2130 case DRM_FORMAT_ARGB2101010:
2131 dspcntr |= DISPPLANE_BGRX101010;
2132 break;
2133 case DRM_FORMAT_XBGR2101010:
2134 case DRM_FORMAT_ABGR2101010:
2135 dspcntr |= DISPPLANE_RGBX101010;
2136 break;
2137 default:
2138 BUG();
2139 }
2140
2141 if (INTEL_INFO(dev)->gen >= 4) {
2142 if (obj->tiling_mode != I915_TILING_NONE)
2143 dspcntr |= DISPPLANE_TILED;
2144 else
2145 dspcntr &= ~DISPPLANE_TILED;
2146 }
2147
2148 I915_WRITE(reg, dspcntr);
2149
2150 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2151
2152 if (INTEL_INFO(dev)->gen >= 4) {
2153 intel_crtc->dspaddr_offset =
2154 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2155 fb->bits_per_pixel / 8,
2156 fb->pitches[0]);
2157 linear_offset -= intel_crtc->dspaddr_offset;
2158 } else {
2159 intel_crtc->dspaddr_offset = linear_offset;
2160 }
2161
2162 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2163 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2164 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2165 if (INTEL_INFO(dev)->gen >= 4) {
2166 I915_MODIFY_DISPBASE(DSPSURF(plane),
2167 obj->gtt_offset + intel_crtc->dspaddr_offset);
2168 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2169 I915_WRITE(DSPLINOFF(plane), linear_offset);
2170 } else
2171 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2172 POSTING_READ(reg);
2173
2174 return 0;
2175 }
2176
2177 static int ironlake_update_plane(struct drm_crtc *crtc,
2178 struct drm_framebuffer *fb, int x, int y)
2179 {
2180 struct drm_device *dev = crtc->dev;
2181 struct drm_i915_private *dev_priv = dev->dev_private;
2182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2183 struct intel_framebuffer *intel_fb;
2184 struct drm_i915_gem_object *obj;
2185 int plane = intel_crtc->plane;
2186 unsigned long linear_offset;
2187 u32 dspcntr;
2188 u32 reg;
2189
2190 switch (plane) {
2191 case 0:
2192 case 1:
2193 case 2:
2194 break;
2195 default:
2196 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2197 return -EINVAL;
2198 }
2199
2200 intel_fb = to_intel_framebuffer(fb);
2201 obj = intel_fb->obj;
2202
2203 reg = DSPCNTR(plane);
2204 dspcntr = I915_READ(reg);
2205 /* Mask out pixel format bits in case we change it */
2206 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2207 switch (fb->pixel_format) {
2208 case DRM_FORMAT_C8:
2209 dspcntr |= DISPPLANE_8BPP;
2210 break;
2211 case DRM_FORMAT_RGB565:
2212 dspcntr |= DISPPLANE_BGRX565;
2213 break;
2214 case DRM_FORMAT_XRGB8888:
2215 case DRM_FORMAT_ARGB8888:
2216 dspcntr |= DISPPLANE_BGRX888;
2217 break;
2218 case DRM_FORMAT_XBGR8888:
2219 case DRM_FORMAT_ABGR8888:
2220 dspcntr |= DISPPLANE_RGBX888;
2221 break;
2222 case DRM_FORMAT_XRGB2101010:
2223 case DRM_FORMAT_ARGB2101010:
2224 dspcntr |= DISPPLANE_BGRX101010;
2225 break;
2226 case DRM_FORMAT_XBGR2101010:
2227 case DRM_FORMAT_ABGR2101010:
2228 dspcntr |= DISPPLANE_RGBX101010;
2229 break;
2230 default:
2231 BUG();
2232 }
2233
2234 if (obj->tiling_mode != I915_TILING_NONE)
2235 dspcntr |= DISPPLANE_TILED;
2236 else
2237 dspcntr &= ~DISPPLANE_TILED;
2238
2239 /* must disable */
2240 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2241
2242 I915_WRITE(reg, dspcntr);
2243
2244 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2245 intel_crtc->dspaddr_offset =
2246 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2247 fb->bits_per_pixel / 8,
2248 fb->pitches[0]);
2249 linear_offset -= intel_crtc->dspaddr_offset;
2250
2251 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2252 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2253 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2254 I915_MODIFY_DISPBASE(DSPSURF(plane),
2255 obj->gtt_offset + intel_crtc->dspaddr_offset);
2256 if (IS_HASWELL(dev)) {
2257 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2258 } else {
2259 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2260 I915_WRITE(DSPLINOFF(plane), linear_offset);
2261 }
2262 POSTING_READ(reg);
2263
2264 return 0;
2265 }
2266
2267 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2268 static int
2269 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2270 int x, int y, enum mode_set_atomic state)
2271 {
2272 struct drm_device *dev = crtc->dev;
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274
2275 if (dev_priv->display.disable_fbc)
2276 dev_priv->display.disable_fbc(dev);
2277 intel_increase_pllclock(crtc);
2278
2279 return dev_priv->display.update_plane(crtc, fb, x, y);
2280 }
2281
2282 void intel_display_handle_reset(struct drm_device *dev)
2283 {
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 struct drm_crtc *crtc;
2286
2287 /*
2288 * Flips in the rings have been nuked by the reset,
2289 * so complete all pending flips so that user space
2290 * will get its events and not get stuck.
2291 *
2292 * Also update the base address of all primary
2293 * planes to the the last fb to make sure we're
2294 * showing the correct fb after a reset.
2295 *
2296 * Need to make two loops over the crtcs so that we
2297 * don't try to grab a crtc mutex before the
2298 * pending_flip_queue really got woken up.
2299 */
2300
2301 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303 enum plane plane = intel_crtc->plane;
2304
2305 intel_prepare_page_flip(dev, plane);
2306 intel_finish_page_flip_plane(dev, plane);
2307 }
2308
2309 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2311
2312 mutex_lock(&crtc->mutex);
2313 if (intel_crtc->active)
2314 dev_priv->display.update_plane(crtc, crtc->fb,
2315 crtc->x, crtc->y);
2316 mutex_unlock(&crtc->mutex);
2317 }
2318 }
2319
2320 static int
2321 intel_finish_fb(struct drm_framebuffer *old_fb)
2322 {
2323 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2324 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2325 bool was_interruptible = dev_priv->mm.interruptible;
2326 int ret;
2327
2328 /* Big Hammer, we also need to ensure that any pending
2329 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2330 * current scanout is retired before unpinning the old
2331 * framebuffer.
2332 *
2333 * This should only fail upon a hung GPU, in which case we
2334 * can safely continue.
2335 */
2336 dev_priv->mm.interruptible = false;
2337 ret = i915_gem_object_finish_gpu(obj);
2338 dev_priv->mm.interruptible = was_interruptible;
2339
2340 return ret;
2341 }
2342
2343 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2344 {
2345 struct drm_device *dev = crtc->dev;
2346 struct drm_i915_master_private *master_priv;
2347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2348
2349 if (!dev->primary->master)
2350 return;
2351
2352 master_priv = dev->primary->master->driver_priv;
2353 if (!master_priv->sarea_priv)
2354 return;
2355
2356 switch (intel_crtc->pipe) {
2357 case 0:
2358 master_priv->sarea_priv->pipeA_x = x;
2359 master_priv->sarea_priv->pipeA_y = y;
2360 break;
2361 case 1:
2362 master_priv->sarea_priv->pipeB_x = x;
2363 master_priv->sarea_priv->pipeB_y = y;
2364 break;
2365 default:
2366 break;
2367 }
2368 }
2369
2370 static int
2371 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2372 struct drm_framebuffer *fb)
2373 {
2374 struct drm_device *dev = crtc->dev;
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2377 struct drm_framebuffer *old_fb;
2378 int ret;
2379
2380 /* no fb bound */
2381 if (!fb) {
2382 DRM_ERROR("No FB bound\n");
2383 return 0;
2384 }
2385
2386 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2387 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2388 intel_crtc->plane,
2389 INTEL_INFO(dev)->num_pipes);
2390 return -EINVAL;
2391 }
2392
2393 mutex_lock(&dev->struct_mutex);
2394 ret = intel_pin_and_fence_fb_obj(dev,
2395 to_intel_framebuffer(fb)->obj,
2396 NULL);
2397 if (ret != 0) {
2398 mutex_unlock(&dev->struct_mutex);
2399 DRM_ERROR("pin & fence failed\n");
2400 return ret;
2401 }
2402
2403 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2404 if (ret) {
2405 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2406 mutex_unlock(&dev->struct_mutex);
2407 DRM_ERROR("failed to update base address\n");
2408 return ret;
2409 }
2410
2411 old_fb = crtc->fb;
2412 crtc->fb = fb;
2413 crtc->x = x;
2414 crtc->y = y;
2415
2416 if (old_fb) {
2417 intel_wait_for_vblank(dev, intel_crtc->pipe);
2418 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2419 }
2420
2421 intel_update_fbc(dev);
2422 mutex_unlock(&dev->struct_mutex);
2423
2424 intel_crtc_update_sarea_pos(crtc, x, y);
2425
2426 return 0;
2427 }
2428
2429 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2430 {
2431 struct drm_device *dev = crtc->dev;
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2434 int pipe = intel_crtc->pipe;
2435 u32 reg, temp;
2436
2437 /* enable normal train */
2438 reg = FDI_TX_CTL(pipe);
2439 temp = I915_READ(reg);
2440 if (IS_IVYBRIDGE(dev)) {
2441 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2442 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2443 } else {
2444 temp &= ~FDI_LINK_TRAIN_NONE;
2445 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2446 }
2447 I915_WRITE(reg, temp);
2448
2449 reg = FDI_RX_CTL(pipe);
2450 temp = I915_READ(reg);
2451 if (HAS_PCH_CPT(dev)) {
2452 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2453 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2454 } else {
2455 temp &= ~FDI_LINK_TRAIN_NONE;
2456 temp |= FDI_LINK_TRAIN_NONE;
2457 }
2458 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2459
2460 /* wait one idle pattern time */
2461 POSTING_READ(reg);
2462 udelay(1000);
2463
2464 /* IVB wants error correction enabled */
2465 if (IS_IVYBRIDGE(dev))
2466 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2467 FDI_FE_ERRC_ENABLE);
2468 }
2469
2470 static void ivb_modeset_global_resources(struct drm_device *dev)
2471 {
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473 struct intel_crtc *pipe_B_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2475 struct intel_crtc *pipe_C_crtc =
2476 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2477 uint32_t temp;
2478
2479 /* When everything is off disable fdi C so that we could enable fdi B
2480 * with all lanes. XXX: This misses the case where a pipe is not using
2481 * any pch resources and so doesn't need any fdi lanes. */
2482 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2483 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2485
2486 temp = I915_READ(SOUTH_CHICKEN1);
2487 temp &= ~FDI_BC_BIFURCATION_SELECT;
2488 DRM_DEBUG_KMS("disabling fdi C rx\n");
2489 I915_WRITE(SOUTH_CHICKEN1, temp);
2490 }
2491 }
2492
2493 /* The FDI link training functions for ILK/Ibexpeak. */
2494 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2495 {
2496 struct drm_device *dev = crtc->dev;
2497 struct drm_i915_private *dev_priv = dev->dev_private;
2498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2499 int pipe = intel_crtc->pipe;
2500 int plane = intel_crtc->plane;
2501 u32 reg, temp, tries;
2502
2503 /* FDI needs bits from pipe & plane first */
2504 assert_pipe_enabled(dev_priv, pipe);
2505 assert_plane_enabled(dev_priv, plane);
2506
2507 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2508 for train result */
2509 reg = FDI_RX_IMR(pipe);
2510 temp = I915_READ(reg);
2511 temp &= ~FDI_RX_SYMBOL_LOCK;
2512 temp &= ~FDI_RX_BIT_LOCK;
2513 I915_WRITE(reg, temp);
2514 I915_READ(reg);
2515 udelay(150);
2516
2517 /* enable CPU FDI TX and PCH FDI RX */
2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
2520 temp &= ~(7 << 19);
2521 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
2524 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2525
2526 reg = FDI_RX_CTL(pipe);
2527 temp = I915_READ(reg);
2528 temp &= ~FDI_LINK_TRAIN_NONE;
2529 temp |= FDI_LINK_TRAIN_PATTERN_1;
2530 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2531
2532 POSTING_READ(reg);
2533 udelay(150);
2534
2535 /* Ironlake workaround, enable clock pointer after FDI enable*/
2536 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2537 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2538 FDI_RX_PHASE_SYNC_POINTER_EN);
2539
2540 reg = FDI_RX_IIR(pipe);
2541 for (tries = 0; tries < 5; tries++) {
2542 temp = I915_READ(reg);
2543 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2544
2545 if ((temp & FDI_RX_BIT_LOCK)) {
2546 DRM_DEBUG_KMS("FDI train 1 done.\n");
2547 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2548 break;
2549 }
2550 }
2551 if (tries == 5)
2552 DRM_ERROR("FDI train 1 fail!\n");
2553
2554 /* Train 2 */
2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
2557 temp &= ~FDI_LINK_TRAIN_NONE;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2;
2559 I915_WRITE(reg, temp);
2560
2561 reg = FDI_RX_CTL(pipe);
2562 temp = I915_READ(reg);
2563 temp &= ~FDI_LINK_TRAIN_NONE;
2564 temp |= FDI_LINK_TRAIN_PATTERN_2;
2565 I915_WRITE(reg, temp);
2566
2567 POSTING_READ(reg);
2568 udelay(150);
2569
2570 reg = FDI_RX_IIR(pipe);
2571 for (tries = 0; tries < 5; tries++) {
2572 temp = I915_READ(reg);
2573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574
2575 if (temp & FDI_RX_SYMBOL_LOCK) {
2576 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2577 DRM_DEBUG_KMS("FDI train 2 done.\n");
2578 break;
2579 }
2580 }
2581 if (tries == 5)
2582 DRM_ERROR("FDI train 2 fail!\n");
2583
2584 DRM_DEBUG_KMS("FDI train done\n");
2585
2586 }
2587
2588 static const int snb_b_fdi_train_param[] = {
2589 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2590 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2591 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2592 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2593 };
2594
2595 /* The FDI link training functions for SNB/Cougarpoint. */
2596 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2597 {
2598 struct drm_device *dev = crtc->dev;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 int pipe = intel_crtc->pipe;
2602 u32 reg, temp, i, retry;
2603
2604 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2605 for train result */
2606 reg = FDI_RX_IMR(pipe);
2607 temp = I915_READ(reg);
2608 temp &= ~FDI_RX_SYMBOL_LOCK;
2609 temp &= ~FDI_RX_BIT_LOCK;
2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
2613 udelay(150);
2614
2615 /* enable CPU FDI TX and PCH FDI RX */
2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
2618 temp &= ~(7 << 19);
2619 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2620 temp &= ~FDI_LINK_TRAIN_NONE;
2621 temp |= FDI_LINK_TRAIN_PATTERN_1;
2622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2623 /* SNB-B */
2624 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2625 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2626
2627 I915_WRITE(FDI_RX_MISC(pipe),
2628 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 if (HAS_PCH_CPT(dev)) {
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635 } else {
2636 temp &= ~FDI_LINK_TRAIN_NONE;
2637 temp |= FDI_LINK_TRAIN_PATTERN_1;
2638 }
2639 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2640
2641 POSTING_READ(reg);
2642 udelay(150);
2643
2644 for (i = 0; i < 4; i++) {
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
2652 udelay(500);
2653
2654 for (retry = 0; retry < 5; retry++) {
2655 reg = FDI_RX_IIR(pipe);
2656 temp = I915_READ(reg);
2657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658 if (temp & FDI_RX_BIT_LOCK) {
2659 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2660 DRM_DEBUG_KMS("FDI train 1 done.\n");
2661 break;
2662 }
2663 udelay(50);
2664 }
2665 if (retry < 5)
2666 break;
2667 }
2668 if (i == 4)
2669 DRM_ERROR("FDI train 1 fail!\n");
2670
2671 /* Train 2 */
2672 reg = FDI_TX_CTL(pipe);
2673 temp = I915_READ(reg);
2674 temp &= ~FDI_LINK_TRAIN_NONE;
2675 temp |= FDI_LINK_TRAIN_PATTERN_2;
2676 if (IS_GEN6(dev)) {
2677 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678 /* SNB-B */
2679 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2680 }
2681 I915_WRITE(reg, temp);
2682
2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 if (HAS_PCH_CPT(dev)) {
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2688 } else {
2689 temp &= ~FDI_LINK_TRAIN_NONE;
2690 temp |= FDI_LINK_TRAIN_PATTERN_2;
2691 }
2692 I915_WRITE(reg, temp);
2693
2694 POSTING_READ(reg);
2695 udelay(150);
2696
2697 for (i = 0; i < 4; i++) {
2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
2700 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701 temp |= snb_b_fdi_train_param[i];
2702 I915_WRITE(reg, temp);
2703
2704 POSTING_READ(reg);
2705 udelay(500);
2706
2707 for (retry = 0; retry < 5; retry++) {
2708 reg = FDI_RX_IIR(pipe);
2709 temp = I915_READ(reg);
2710 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2711 if (temp & FDI_RX_SYMBOL_LOCK) {
2712 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2713 DRM_DEBUG_KMS("FDI train 2 done.\n");
2714 break;
2715 }
2716 udelay(50);
2717 }
2718 if (retry < 5)
2719 break;
2720 }
2721 if (i == 4)
2722 DRM_ERROR("FDI train 2 fail!\n");
2723
2724 DRM_DEBUG_KMS("FDI train done.\n");
2725 }
2726
2727 /* Manual link training for Ivy Bridge A0 parts */
2728 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2729 {
2730 struct drm_device *dev = crtc->dev;
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2733 int pipe = intel_crtc->pipe;
2734 u32 reg, temp, i;
2735
2736 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2737 for train result */
2738 reg = FDI_RX_IMR(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~FDI_RX_SYMBOL_LOCK;
2741 temp &= ~FDI_RX_BIT_LOCK;
2742 I915_WRITE(reg, temp);
2743
2744 POSTING_READ(reg);
2745 udelay(150);
2746
2747 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2748 I915_READ(FDI_RX_IIR(pipe)));
2749
2750 /* enable CPU FDI TX and PCH FDI RX */
2751 reg = FDI_TX_CTL(pipe);
2752 temp = I915_READ(reg);
2753 temp &= ~(7 << 19);
2754 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2755 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2756 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2757 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2759 temp |= FDI_COMPOSITE_SYNC;
2760 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2761
2762 I915_WRITE(FDI_RX_MISC(pipe),
2763 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2764
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 temp &= ~FDI_LINK_TRAIN_AUTO;
2768 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2769 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2770 temp |= FDI_COMPOSITE_SYNC;
2771 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2772
2773 POSTING_READ(reg);
2774 udelay(150);
2775
2776 for (i = 0; i < 4; i++) {
2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2780 temp |= snb_b_fdi_train_param[i];
2781 I915_WRITE(reg, temp);
2782
2783 POSTING_READ(reg);
2784 udelay(500);
2785
2786 reg = FDI_RX_IIR(pipe);
2787 temp = I915_READ(reg);
2788 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2789
2790 if (temp & FDI_RX_BIT_LOCK ||
2791 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2792 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2793 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2794 break;
2795 }
2796 }
2797 if (i == 4)
2798 DRM_ERROR("FDI train 1 fail!\n");
2799
2800 /* Train 2 */
2801 reg = FDI_TX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2804 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2805 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2806 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2807 I915_WRITE(reg, temp);
2808
2809 reg = FDI_RX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2813 I915_WRITE(reg, temp);
2814
2815 POSTING_READ(reg);
2816 udelay(150);
2817
2818 for (i = 0; i < 4; i++) {
2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2822 temp |= snb_b_fdi_train_param[i];
2823 I915_WRITE(reg, temp);
2824
2825 POSTING_READ(reg);
2826 udelay(500);
2827
2828 reg = FDI_RX_IIR(pipe);
2829 temp = I915_READ(reg);
2830 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2831
2832 if (temp & FDI_RX_SYMBOL_LOCK) {
2833 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2834 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2835 break;
2836 }
2837 }
2838 if (i == 4)
2839 DRM_ERROR("FDI train 2 fail!\n");
2840
2841 DRM_DEBUG_KMS("FDI train done.\n");
2842 }
2843
2844 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2845 {
2846 struct drm_device *dev = intel_crtc->base.dev;
2847 struct drm_i915_private *dev_priv = dev->dev_private;
2848 int pipe = intel_crtc->pipe;
2849 u32 reg, temp;
2850
2851
2852 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2853 reg = FDI_RX_CTL(pipe);
2854 temp = I915_READ(reg);
2855 temp &= ~((0x7 << 19) | (0x7 << 16));
2856 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2858 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2859
2860 POSTING_READ(reg);
2861 udelay(200);
2862
2863 /* Switch from Rawclk to PCDclk */
2864 temp = I915_READ(reg);
2865 I915_WRITE(reg, temp | FDI_PCDCLK);
2866
2867 POSTING_READ(reg);
2868 udelay(200);
2869
2870 /* Enable CPU FDI TX PLL, always on for Ironlake */
2871 reg = FDI_TX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2874 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2875
2876 POSTING_READ(reg);
2877 udelay(100);
2878 }
2879 }
2880
2881 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2882 {
2883 struct drm_device *dev = intel_crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 int pipe = intel_crtc->pipe;
2886 u32 reg, temp;
2887
2888 /* Switch from PCDclk to Rawclk */
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2892
2893 /* Disable CPU FDI TX PLL */
2894 reg = FDI_TX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2897
2898 POSTING_READ(reg);
2899 udelay(100);
2900
2901 reg = FDI_RX_CTL(pipe);
2902 temp = I915_READ(reg);
2903 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2904
2905 /* Wait for the clocks to turn off. */
2906 POSTING_READ(reg);
2907 udelay(100);
2908 }
2909
2910 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2911 {
2912 struct drm_device *dev = crtc->dev;
2913 struct drm_i915_private *dev_priv = dev->dev_private;
2914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2915 int pipe = intel_crtc->pipe;
2916 u32 reg, temp;
2917
2918 /* disable CPU FDI tx and PCH FDI rx */
2919 reg = FDI_TX_CTL(pipe);
2920 temp = I915_READ(reg);
2921 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2922 POSTING_READ(reg);
2923
2924 reg = FDI_RX_CTL(pipe);
2925 temp = I915_READ(reg);
2926 temp &= ~(0x7 << 16);
2927 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2928 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2929
2930 POSTING_READ(reg);
2931 udelay(100);
2932
2933 /* Ironlake workaround, disable clock pointer after downing FDI */
2934 if (HAS_PCH_IBX(dev)) {
2935 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2936 }
2937
2938 /* still set train pattern 1 */
2939 reg = FDI_TX_CTL(pipe);
2940 temp = I915_READ(reg);
2941 temp &= ~FDI_LINK_TRAIN_NONE;
2942 temp |= FDI_LINK_TRAIN_PATTERN_1;
2943 I915_WRITE(reg, temp);
2944
2945 reg = FDI_RX_CTL(pipe);
2946 temp = I915_READ(reg);
2947 if (HAS_PCH_CPT(dev)) {
2948 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2949 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2950 } else {
2951 temp &= ~FDI_LINK_TRAIN_NONE;
2952 temp |= FDI_LINK_TRAIN_PATTERN_1;
2953 }
2954 /* BPC in FDI rx is consistent with that in PIPECONF */
2955 temp &= ~(0x07 << 16);
2956 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2957 I915_WRITE(reg, temp);
2958
2959 POSTING_READ(reg);
2960 udelay(100);
2961 }
2962
2963 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2964 {
2965 struct drm_device *dev = crtc->dev;
2966 struct drm_i915_private *dev_priv = dev->dev_private;
2967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2968 unsigned long flags;
2969 bool pending;
2970
2971 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2972 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2973 return false;
2974
2975 spin_lock_irqsave(&dev->event_lock, flags);
2976 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2977 spin_unlock_irqrestore(&dev->event_lock, flags);
2978
2979 return pending;
2980 }
2981
2982 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2983 {
2984 struct drm_device *dev = crtc->dev;
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986
2987 if (crtc->fb == NULL)
2988 return;
2989
2990 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2991
2992 wait_event(dev_priv->pending_flip_queue,
2993 !intel_crtc_has_pending_flip(crtc));
2994
2995 mutex_lock(&dev->struct_mutex);
2996 intel_finish_fb(crtc->fb);
2997 mutex_unlock(&dev->struct_mutex);
2998 }
2999
3000 /* Program iCLKIP clock to the desired frequency */
3001 static void lpt_program_iclkip(struct drm_crtc *crtc)
3002 {
3003 struct drm_device *dev = crtc->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3006 u32 temp;
3007
3008 mutex_lock(&dev_priv->dpio_lock);
3009
3010 /* It is necessary to ungate the pixclk gate prior to programming
3011 * the divisors, and gate it back when it is done.
3012 */
3013 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3014
3015 /* Disable SSCCTL */
3016 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3017 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3018 SBI_SSCCTL_DISABLE,
3019 SBI_ICLK);
3020
3021 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3022 if (crtc->mode.clock == 20000) {
3023 auxdiv = 1;
3024 divsel = 0x41;
3025 phaseinc = 0x20;
3026 } else {
3027 /* The iCLK virtual clock root frequency is in MHz,
3028 * but the crtc->mode.clock in in KHz. To get the divisors,
3029 * it is necessary to divide one by another, so we
3030 * convert the virtual clock precision to KHz here for higher
3031 * precision.
3032 */
3033 u32 iclk_virtual_root_freq = 172800 * 1000;
3034 u32 iclk_pi_range = 64;
3035 u32 desired_divisor, msb_divisor_value, pi_value;
3036
3037 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3038 msb_divisor_value = desired_divisor / iclk_pi_range;
3039 pi_value = desired_divisor % iclk_pi_range;
3040
3041 auxdiv = 0;
3042 divsel = msb_divisor_value - 2;
3043 phaseinc = pi_value;
3044 }
3045
3046 /* This should not happen with any sane values */
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3048 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3049 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3050 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3051
3052 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3053 crtc->mode.clock,
3054 auxdiv,
3055 divsel,
3056 phasedir,
3057 phaseinc);
3058
3059 /* Program SSCDIVINTPHASE6 */
3060 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3061 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3062 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3063 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3064 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3065 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3066 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3067 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3068
3069 /* Program SSCAUXDIV */
3070 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3071 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3072 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3073 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3074
3075 /* Enable modulator and associated divider */
3076 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3077 temp &= ~SBI_SSCCTL_DISABLE;
3078 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3079
3080 /* Wait for initialization time */
3081 udelay(24);
3082
3083 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3084
3085 mutex_unlock(&dev_priv->dpio_lock);
3086 }
3087
3088 /*
3089 * Enable PCH resources required for PCH ports:
3090 * - PCH PLLs
3091 * - FDI training & RX/TX
3092 * - update transcoder timings
3093 * - DP transcoding bits
3094 * - transcoder
3095 */
3096 static void ironlake_pch_enable(struct drm_crtc *crtc)
3097 {
3098 struct drm_device *dev = crtc->dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101 int pipe = intel_crtc->pipe;
3102 u32 reg, temp;
3103
3104 assert_transcoder_disabled(dev_priv, pipe);
3105
3106 /* Write the TU size bits before fdi link training, so that error
3107 * detection works. */
3108 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3109 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3110
3111 /* For PCH output, training FDI link */
3112 dev_priv->display.fdi_link_train(crtc);
3113
3114 /* XXX: pch pll's can be enabled any time before we enable the PCH
3115 * transcoder, and we actually should do this to not upset any PCH
3116 * transcoder that already use the clock when we share it.
3117 *
3118 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3119 * unconditionally resets the pll - we need that to have the right LVDS
3120 * enable sequence. */
3121 ironlake_enable_pch_pll(intel_crtc);
3122
3123 if (HAS_PCH_CPT(dev)) {
3124 u32 sel;
3125
3126 temp = I915_READ(PCH_DPLL_SEL);
3127 switch (pipe) {
3128 default:
3129 case 0:
3130 temp |= TRANSA_DPLL_ENABLE;
3131 sel = TRANSA_DPLLB_SEL;
3132 break;
3133 case 1:
3134 temp |= TRANSB_DPLL_ENABLE;
3135 sel = TRANSB_DPLLB_SEL;
3136 break;
3137 case 2:
3138 temp |= TRANSC_DPLL_ENABLE;
3139 sel = TRANSC_DPLLB_SEL;
3140 break;
3141 }
3142 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3143 temp |= sel;
3144 else
3145 temp &= ~sel;
3146 I915_WRITE(PCH_DPLL_SEL, temp);
3147 }
3148
3149 /* set transcoder timing, panel must allow it */
3150 assert_panel_unlocked(dev_priv, pipe);
3151 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3152 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3153 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3154
3155 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3156 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3157 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3158 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3159
3160 intel_fdi_normal_train(crtc);
3161
3162 /* For PCH DP, enable TRANS_DP_CTL */
3163 if (HAS_PCH_CPT(dev) &&
3164 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3165 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3166 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3167 reg = TRANS_DP_CTL(pipe);
3168 temp = I915_READ(reg);
3169 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3170 TRANS_DP_SYNC_MASK |
3171 TRANS_DP_BPC_MASK);
3172 temp |= (TRANS_DP_OUTPUT_ENABLE |
3173 TRANS_DP_ENH_FRAMING);
3174 temp |= bpc << 9; /* same format but at 11:9 */
3175
3176 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3177 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3178 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3179 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3180
3181 switch (intel_trans_dp_port_sel(crtc)) {
3182 case PCH_DP_B:
3183 temp |= TRANS_DP_PORT_SEL_B;
3184 break;
3185 case PCH_DP_C:
3186 temp |= TRANS_DP_PORT_SEL_C;
3187 break;
3188 case PCH_DP_D:
3189 temp |= TRANS_DP_PORT_SEL_D;
3190 break;
3191 default:
3192 BUG();
3193 }
3194
3195 I915_WRITE(reg, temp);
3196 }
3197
3198 ironlake_enable_pch_transcoder(dev_priv, pipe);
3199 }
3200
3201 static void lpt_pch_enable(struct drm_crtc *crtc)
3202 {
3203 struct drm_device *dev = crtc->dev;
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3206 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3207
3208 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3209
3210 lpt_program_iclkip(crtc);
3211
3212 /* Set transcoder timing. */
3213 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3214 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3215 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3216
3217 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3218 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3219 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3220 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3221
3222 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3223 }
3224
3225 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3226 {
3227 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3228
3229 if (pll == NULL)
3230 return;
3231
3232 if (pll->refcount == 0) {
3233 WARN(1, "bad PCH PLL refcount\n");
3234 return;
3235 }
3236
3237 --pll->refcount;
3238 intel_crtc->pch_pll = NULL;
3239 }
3240
3241 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3242 {
3243 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3244 struct intel_pch_pll *pll;
3245 int i;
3246
3247 pll = intel_crtc->pch_pll;
3248 if (pll) {
3249 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3250 intel_crtc->base.base.id, pll->pll_reg);
3251 goto prepare;
3252 }
3253
3254 if (HAS_PCH_IBX(dev_priv->dev)) {
3255 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3256 i = intel_crtc->pipe;
3257 pll = &dev_priv->pch_plls[i];
3258
3259 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3260 intel_crtc->base.base.id, pll->pll_reg);
3261
3262 goto found;
3263 }
3264
3265 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3266 pll = &dev_priv->pch_plls[i];
3267
3268 /* Only want to check enabled timings first */
3269 if (pll->refcount == 0)
3270 continue;
3271
3272 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3273 fp == I915_READ(pll->fp0_reg)) {
3274 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3275 intel_crtc->base.base.id,
3276 pll->pll_reg, pll->refcount, pll->active);
3277
3278 goto found;
3279 }
3280 }
3281
3282 /* Ok no matching timings, maybe there's a free one? */
3283 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3284 pll = &dev_priv->pch_plls[i];
3285 if (pll->refcount == 0) {
3286 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3287 intel_crtc->base.base.id, pll->pll_reg);
3288 goto found;
3289 }
3290 }
3291
3292 return NULL;
3293
3294 found:
3295 intel_crtc->pch_pll = pll;
3296 pll->refcount++;
3297 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3298 prepare: /* separate function? */
3299 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3300
3301 /* Wait for the clocks to stabilize before rewriting the regs */
3302 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3303 POSTING_READ(pll->pll_reg);
3304 udelay(150);
3305
3306 I915_WRITE(pll->fp0_reg, fp);
3307 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3308 pll->on = false;
3309 return pll;
3310 }
3311
3312 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3313 {
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 int dslreg = PIPEDSL(pipe);
3316 u32 temp;
3317
3318 temp = I915_READ(dslreg);
3319 udelay(500);
3320 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3321 if (wait_for(I915_READ(dslreg) != temp, 5))
3322 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3323 }
3324 }
3325
3326 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3327 {
3328 struct drm_device *dev = crtc->dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3331 struct intel_encoder *encoder;
3332 int pipe = intel_crtc->pipe;
3333 int plane = intel_crtc->plane;
3334 u32 temp;
3335
3336 WARN_ON(!crtc->enabled);
3337
3338 if (intel_crtc->active)
3339 return;
3340
3341 intel_crtc->active = true;
3342 intel_update_watermarks(dev);
3343
3344 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3345 temp = I915_READ(PCH_LVDS);
3346 if ((temp & LVDS_PORT_EN) == 0)
3347 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3348 }
3349
3350
3351 if (intel_crtc->config.has_pch_encoder) {
3352 /* Note: FDI PLL enabling _must_ be done before we enable the
3353 * cpu pipes, hence this is separate from all the other fdi/pch
3354 * enabling. */
3355 ironlake_fdi_pll_enable(intel_crtc);
3356 } else {
3357 assert_fdi_tx_disabled(dev_priv, pipe);
3358 assert_fdi_rx_disabled(dev_priv, pipe);
3359 }
3360
3361 for_each_encoder_on_crtc(dev, crtc, encoder)
3362 if (encoder->pre_enable)
3363 encoder->pre_enable(encoder);
3364
3365 /* Enable panel fitting for LVDS */
3366 if (dev_priv->pch_pf_size &&
3367 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3368 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3369 /* Force use of hard-coded filter coefficients
3370 * as some pre-programmed values are broken,
3371 * e.g. x201.
3372 */
3373 if (IS_IVYBRIDGE(dev))
3374 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3375 PF_PIPE_SEL_IVB(pipe));
3376 else
3377 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3378 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3379 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3380 }
3381
3382 /*
3383 * On ILK+ LUT must be loaded before the pipe is running but with
3384 * clocks enabled
3385 */
3386 intel_crtc_load_lut(crtc);
3387
3388 intel_enable_pipe(dev_priv, pipe,
3389 intel_crtc->config.has_pch_encoder);
3390 intel_enable_plane(dev_priv, plane, pipe);
3391
3392 if (intel_crtc->config.has_pch_encoder)
3393 ironlake_pch_enable(crtc);
3394
3395 mutex_lock(&dev->struct_mutex);
3396 intel_update_fbc(dev);
3397 mutex_unlock(&dev->struct_mutex);
3398
3399 intel_crtc_update_cursor(crtc, true);
3400
3401 for_each_encoder_on_crtc(dev, crtc, encoder)
3402 encoder->enable(encoder);
3403
3404 if (HAS_PCH_CPT(dev))
3405 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3406
3407 /*
3408 * There seems to be a race in PCH platform hw (at least on some
3409 * outputs) where an enabled pipe still completes any pageflip right
3410 * away (as if the pipe is off) instead of waiting for vblank. As soon
3411 * as the first vblank happend, everything works as expected. Hence just
3412 * wait for one vblank before returning to avoid strange things
3413 * happening.
3414 */
3415 intel_wait_for_vblank(dev, intel_crtc->pipe);
3416 }
3417
3418 static void haswell_crtc_enable(struct drm_crtc *crtc)
3419 {
3420 struct drm_device *dev = crtc->dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423 struct intel_encoder *encoder;
3424 int pipe = intel_crtc->pipe;
3425 int plane = intel_crtc->plane;
3426
3427 WARN_ON(!crtc->enabled);
3428
3429 if (intel_crtc->active)
3430 return;
3431
3432 intel_crtc->active = true;
3433 intel_update_watermarks(dev);
3434
3435 if (intel_crtc->config.has_pch_encoder)
3436 dev_priv->display.fdi_link_train(crtc);
3437
3438 for_each_encoder_on_crtc(dev, crtc, encoder)
3439 if (encoder->pre_enable)
3440 encoder->pre_enable(encoder);
3441
3442 intel_ddi_enable_pipe_clock(intel_crtc);
3443
3444 /* Enable panel fitting for eDP */
3445 if (dev_priv->pch_pf_size &&
3446 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3447 /* Force use of hard-coded filter coefficients
3448 * as some pre-programmed values are broken,
3449 * e.g. x201.
3450 */
3451 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3452 PF_PIPE_SEL_IVB(pipe));
3453 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3454 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3455 }
3456
3457 /*
3458 * On ILK+ LUT must be loaded before the pipe is running but with
3459 * clocks enabled
3460 */
3461 intel_crtc_load_lut(crtc);
3462
3463 intel_ddi_set_pipe_settings(crtc);
3464 intel_ddi_enable_transcoder_func(crtc);
3465
3466 intel_enable_pipe(dev_priv, pipe,
3467 intel_crtc->config.has_pch_encoder);
3468 intel_enable_plane(dev_priv, plane, pipe);
3469
3470 if (intel_crtc->config.has_pch_encoder)
3471 lpt_pch_enable(crtc);
3472
3473 mutex_lock(&dev->struct_mutex);
3474 intel_update_fbc(dev);
3475 mutex_unlock(&dev->struct_mutex);
3476
3477 intel_crtc_update_cursor(crtc, true);
3478
3479 for_each_encoder_on_crtc(dev, crtc, encoder)
3480 encoder->enable(encoder);
3481
3482 /*
3483 * There seems to be a race in PCH platform hw (at least on some
3484 * outputs) where an enabled pipe still completes any pageflip right
3485 * away (as if the pipe is off) instead of waiting for vblank. As soon
3486 * as the first vblank happend, everything works as expected. Hence just
3487 * wait for one vblank before returning to avoid strange things
3488 * happening.
3489 */
3490 intel_wait_for_vblank(dev, intel_crtc->pipe);
3491 }
3492
3493 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3494 {
3495 struct drm_device *dev = crtc->dev;
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498 struct intel_encoder *encoder;
3499 int pipe = intel_crtc->pipe;
3500 int plane = intel_crtc->plane;
3501 u32 reg, temp;
3502
3503
3504 if (!intel_crtc->active)
3505 return;
3506
3507 for_each_encoder_on_crtc(dev, crtc, encoder)
3508 encoder->disable(encoder);
3509
3510 intel_crtc_wait_for_pending_flips(crtc);
3511 drm_vblank_off(dev, pipe);
3512 intel_crtc_update_cursor(crtc, false);
3513
3514 intel_disable_plane(dev_priv, plane, pipe);
3515
3516 if (dev_priv->cfb_plane == plane)
3517 intel_disable_fbc(dev);
3518
3519 intel_disable_pipe(dev_priv, pipe);
3520
3521 /* Disable PF */
3522 I915_WRITE(PF_CTL(pipe), 0);
3523 I915_WRITE(PF_WIN_SZ(pipe), 0);
3524
3525 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 if (encoder->post_disable)
3527 encoder->post_disable(encoder);
3528
3529 ironlake_fdi_disable(crtc);
3530
3531 ironlake_disable_pch_transcoder(dev_priv, pipe);
3532
3533 if (HAS_PCH_CPT(dev)) {
3534 /* disable TRANS_DP_CTL */
3535 reg = TRANS_DP_CTL(pipe);
3536 temp = I915_READ(reg);
3537 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3538 temp |= TRANS_DP_PORT_SEL_NONE;
3539 I915_WRITE(reg, temp);
3540
3541 /* disable DPLL_SEL */
3542 temp = I915_READ(PCH_DPLL_SEL);
3543 switch (pipe) {
3544 case 0:
3545 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3546 break;
3547 case 1:
3548 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3549 break;
3550 case 2:
3551 /* C shares PLL A or B */
3552 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3553 break;
3554 default:
3555 BUG(); /* wtf */
3556 }
3557 I915_WRITE(PCH_DPLL_SEL, temp);
3558 }
3559
3560 /* disable PCH DPLL */
3561 intel_disable_pch_pll(intel_crtc);
3562
3563 ironlake_fdi_pll_disable(intel_crtc);
3564
3565 intel_crtc->active = false;
3566 intel_update_watermarks(dev);
3567
3568 mutex_lock(&dev->struct_mutex);
3569 intel_update_fbc(dev);
3570 mutex_unlock(&dev->struct_mutex);
3571 }
3572
3573 static void haswell_crtc_disable(struct drm_crtc *crtc)
3574 {
3575 struct drm_device *dev = crtc->dev;
3576 struct drm_i915_private *dev_priv = dev->dev_private;
3577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3578 struct intel_encoder *encoder;
3579 int pipe = intel_crtc->pipe;
3580 int plane = intel_crtc->plane;
3581 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3582
3583 if (!intel_crtc->active)
3584 return;
3585
3586 for_each_encoder_on_crtc(dev, crtc, encoder)
3587 encoder->disable(encoder);
3588
3589 intel_crtc_wait_for_pending_flips(crtc);
3590 drm_vblank_off(dev, pipe);
3591 intel_crtc_update_cursor(crtc, false);
3592
3593 intel_disable_plane(dev_priv, plane, pipe);
3594
3595 if (dev_priv->cfb_plane == plane)
3596 intel_disable_fbc(dev);
3597
3598 intel_disable_pipe(dev_priv, pipe);
3599
3600 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3601
3602 /* XXX: Once we have proper panel fitter state tracking implemented with
3603 * hardware state read/check support we should switch to only disable
3604 * the panel fitter when we know it's used. */
3605 if (intel_using_power_well(dev)) {
3606 I915_WRITE(PF_CTL(pipe), 0);
3607 I915_WRITE(PF_WIN_SZ(pipe), 0);
3608 }
3609
3610 intel_ddi_disable_pipe_clock(intel_crtc);
3611
3612 for_each_encoder_on_crtc(dev, crtc, encoder)
3613 if (encoder->post_disable)
3614 encoder->post_disable(encoder);
3615
3616 if (intel_crtc->config.has_pch_encoder) {
3617 lpt_disable_pch_transcoder(dev_priv);
3618 intel_ddi_fdi_disable(crtc);
3619 }
3620
3621 intel_crtc->active = false;
3622 intel_update_watermarks(dev);
3623
3624 mutex_lock(&dev->struct_mutex);
3625 intel_update_fbc(dev);
3626 mutex_unlock(&dev->struct_mutex);
3627 }
3628
3629 static void ironlake_crtc_off(struct drm_crtc *crtc)
3630 {
3631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3632 intel_put_pch_pll(intel_crtc);
3633 }
3634
3635 static void haswell_crtc_off(struct drm_crtc *crtc)
3636 {
3637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638
3639 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3640 * start using it. */
3641 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3642
3643 intel_ddi_put_crtc_pll(crtc);
3644 }
3645
3646 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3647 {
3648 if (!enable && intel_crtc->overlay) {
3649 struct drm_device *dev = intel_crtc->base.dev;
3650 struct drm_i915_private *dev_priv = dev->dev_private;
3651
3652 mutex_lock(&dev->struct_mutex);
3653 dev_priv->mm.interruptible = false;
3654 (void) intel_overlay_switch_off(intel_crtc->overlay);
3655 dev_priv->mm.interruptible = true;
3656 mutex_unlock(&dev->struct_mutex);
3657 }
3658
3659 /* Let userspace switch the overlay on again. In most cases userspace
3660 * has to recompute where to put it anyway.
3661 */
3662 }
3663
3664 /**
3665 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3666 * cursor plane briefly if not already running after enabling the display
3667 * plane.
3668 * This workaround avoids occasional blank screens when self refresh is
3669 * enabled.
3670 */
3671 static void
3672 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3673 {
3674 u32 cntl = I915_READ(CURCNTR(pipe));
3675
3676 if ((cntl & CURSOR_MODE) == 0) {
3677 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3678
3679 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3680 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3681 intel_wait_for_vblank(dev_priv->dev, pipe);
3682 I915_WRITE(CURCNTR(pipe), cntl);
3683 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3684 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3685 }
3686 }
3687
3688 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3689 {
3690 struct drm_device *dev = crtc->dev;
3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3693 struct intel_encoder *encoder;
3694 int pipe = intel_crtc->pipe;
3695 int plane = intel_crtc->plane;
3696
3697 WARN_ON(!crtc->enabled);
3698
3699 if (intel_crtc->active)
3700 return;
3701
3702 intel_crtc->active = true;
3703 intel_update_watermarks(dev);
3704
3705 intel_enable_pll(dev_priv, pipe);
3706
3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 if (encoder->pre_enable)
3709 encoder->pre_enable(encoder);
3710
3711 intel_enable_pipe(dev_priv, pipe, false);
3712 intel_enable_plane(dev_priv, plane, pipe);
3713 if (IS_G4X(dev))
3714 g4x_fixup_plane(dev_priv, pipe);
3715
3716 intel_crtc_load_lut(crtc);
3717 intel_update_fbc(dev);
3718
3719 /* Give the overlay scaler a chance to enable if it's on this pipe */
3720 intel_crtc_dpms_overlay(intel_crtc, true);
3721 intel_crtc_update_cursor(crtc, true);
3722
3723 for_each_encoder_on_crtc(dev, crtc, encoder)
3724 encoder->enable(encoder);
3725 }
3726
3727 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3728 {
3729 struct drm_device *dev = crtc->base.dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 enum pipe pipe;
3732 uint32_t pctl = I915_READ(PFIT_CONTROL);
3733
3734 assert_pipe_disabled(dev_priv, crtc->pipe);
3735
3736 if (INTEL_INFO(dev)->gen >= 4)
3737 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3738 else
3739 pipe = PIPE_B;
3740
3741 if (pipe == crtc->pipe) {
3742 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3743 I915_WRITE(PFIT_CONTROL, 0);
3744 }
3745 }
3746
3747 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3748 {
3749 struct drm_device *dev = crtc->dev;
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3752 struct intel_encoder *encoder;
3753 int pipe = intel_crtc->pipe;
3754 int plane = intel_crtc->plane;
3755
3756 if (!intel_crtc->active)
3757 return;
3758
3759 for_each_encoder_on_crtc(dev, crtc, encoder)
3760 encoder->disable(encoder);
3761
3762 /* Give the overlay scaler a chance to disable if it's on this pipe */
3763 intel_crtc_wait_for_pending_flips(crtc);
3764 drm_vblank_off(dev, pipe);
3765 intel_crtc_dpms_overlay(intel_crtc, false);
3766 intel_crtc_update_cursor(crtc, false);
3767
3768 if (dev_priv->cfb_plane == plane)
3769 intel_disable_fbc(dev);
3770
3771 intel_disable_plane(dev_priv, plane, pipe);
3772 intel_disable_pipe(dev_priv, pipe);
3773
3774 i9xx_pfit_disable(intel_crtc);
3775
3776 intel_disable_pll(dev_priv, pipe);
3777
3778 intel_crtc->active = false;
3779 intel_update_fbc(dev);
3780 intel_update_watermarks(dev);
3781 }
3782
3783 static void i9xx_crtc_off(struct drm_crtc *crtc)
3784 {
3785 }
3786
3787 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3788 bool enabled)
3789 {
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_master_private *master_priv;
3792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3793 int pipe = intel_crtc->pipe;
3794
3795 if (!dev->primary->master)
3796 return;
3797
3798 master_priv = dev->primary->master->driver_priv;
3799 if (!master_priv->sarea_priv)
3800 return;
3801
3802 switch (pipe) {
3803 case 0:
3804 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3805 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3806 break;
3807 case 1:
3808 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3809 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3810 break;
3811 default:
3812 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3813 break;
3814 }
3815 }
3816
3817 /**
3818 * Sets the power management mode of the pipe and plane.
3819 */
3820 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3821 {
3822 struct drm_device *dev = crtc->dev;
3823 struct drm_i915_private *dev_priv = dev->dev_private;
3824 struct intel_encoder *intel_encoder;
3825 bool enable = false;
3826
3827 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3828 enable |= intel_encoder->connectors_active;
3829
3830 if (enable)
3831 dev_priv->display.crtc_enable(crtc);
3832 else
3833 dev_priv->display.crtc_disable(crtc);
3834
3835 intel_crtc_update_sarea(crtc, enable);
3836 }
3837
3838 static void intel_crtc_disable(struct drm_crtc *crtc)
3839 {
3840 struct drm_device *dev = crtc->dev;
3841 struct drm_connector *connector;
3842 struct drm_i915_private *dev_priv = dev->dev_private;
3843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3844
3845 /* crtc should still be enabled when we disable it. */
3846 WARN_ON(!crtc->enabled);
3847
3848 intel_crtc->eld_vld = false;
3849 dev_priv->display.crtc_disable(crtc);
3850 intel_crtc_update_sarea(crtc, false);
3851 dev_priv->display.off(crtc);
3852
3853 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3854 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3855
3856 if (crtc->fb) {
3857 mutex_lock(&dev->struct_mutex);
3858 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3859 mutex_unlock(&dev->struct_mutex);
3860 crtc->fb = NULL;
3861 }
3862
3863 /* Update computed state. */
3864 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3865 if (!connector->encoder || !connector->encoder->crtc)
3866 continue;
3867
3868 if (connector->encoder->crtc != crtc)
3869 continue;
3870
3871 connector->dpms = DRM_MODE_DPMS_OFF;
3872 to_intel_encoder(connector->encoder)->connectors_active = false;
3873 }
3874 }
3875
3876 void intel_modeset_disable(struct drm_device *dev)
3877 {
3878 struct drm_crtc *crtc;
3879
3880 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3881 if (crtc->enabled)
3882 intel_crtc_disable(crtc);
3883 }
3884 }
3885
3886 void intel_encoder_destroy(struct drm_encoder *encoder)
3887 {
3888 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3889
3890 drm_encoder_cleanup(encoder);
3891 kfree(intel_encoder);
3892 }
3893
3894 /* Simple dpms helper for encodres with just one connector, no cloning and only
3895 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3896 * state of the entire output pipe. */
3897 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3898 {
3899 if (mode == DRM_MODE_DPMS_ON) {
3900 encoder->connectors_active = true;
3901
3902 intel_crtc_update_dpms(encoder->base.crtc);
3903 } else {
3904 encoder->connectors_active = false;
3905
3906 intel_crtc_update_dpms(encoder->base.crtc);
3907 }
3908 }
3909
3910 /* Cross check the actual hw state with our own modeset state tracking (and it's
3911 * internal consistency). */
3912 static void intel_connector_check_state(struct intel_connector *connector)
3913 {
3914 if (connector->get_hw_state(connector)) {
3915 struct intel_encoder *encoder = connector->encoder;
3916 struct drm_crtc *crtc;
3917 bool encoder_enabled;
3918 enum pipe pipe;
3919
3920 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3921 connector->base.base.id,
3922 drm_get_connector_name(&connector->base));
3923
3924 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3925 "wrong connector dpms state\n");
3926 WARN(connector->base.encoder != &encoder->base,
3927 "active connector not linked to encoder\n");
3928 WARN(!encoder->connectors_active,
3929 "encoder->connectors_active not set\n");
3930
3931 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3932 WARN(!encoder_enabled, "encoder not enabled\n");
3933 if (WARN_ON(!encoder->base.crtc))
3934 return;
3935
3936 crtc = encoder->base.crtc;
3937
3938 WARN(!crtc->enabled, "crtc not enabled\n");
3939 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3940 WARN(pipe != to_intel_crtc(crtc)->pipe,
3941 "encoder active on the wrong pipe\n");
3942 }
3943 }
3944
3945 /* Even simpler default implementation, if there's really no special case to
3946 * consider. */
3947 void intel_connector_dpms(struct drm_connector *connector, int mode)
3948 {
3949 /* All the simple cases only support two dpms states. */
3950 if (mode != DRM_MODE_DPMS_ON)
3951 mode = DRM_MODE_DPMS_OFF;
3952
3953 if (mode == connector->dpms)
3954 return;
3955
3956 connector->dpms = mode;
3957
3958 /* Only need to change hw state when actually enabled */
3959 if (connector->encoder)
3960 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
3961
3962 intel_modeset_check_state(connector->dev);
3963 }
3964
3965 /* Simple connector->get_hw_state implementation for encoders that support only
3966 * one connector and no cloning and hence the encoder state determines the state
3967 * of the connector. */
3968 bool intel_connector_get_hw_state(struct intel_connector *connector)
3969 {
3970 enum pipe pipe = 0;
3971 struct intel_encoder *encoder = connector->encoder;
3972
3973 return encoder->get_hw_state(encoder, &pipe);
3974 }
3975
3976 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3977 struct intel_crtc_config *pipe_config)
3978 {
3979 struct drm_device *dev = crtc->dev;
3980 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3981
3982 if (HAS_PCH_SPLIT(dev)) {
3983 /* FDI link clock is fixed at 2.7G */
3984 if (pipe_config->requested_mode.clock * 3
3985 > IRONLAKE_FDI_FREQ * 4)
3986 return false;
3987 }
3988
3989 /* All interlaced capable intel hw wants timings in frames. Note though
3990 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3991 * timings, so we need to be careful not to clobber these.*/
3992 if (!pipe_config->timings_set)
3993 drm_mode_set_crtcinfo(adjusted_mode, 0);
3994
3995 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3996 * with a hsync front porch of 0.
3997 */
3998 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3999 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4000 return false;
4001
4002 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4003 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4004 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4005 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4006 * for lvds. */
4007 pipe_config->pipe_bpp = 8*3;
4008 }
4009
4010 return true;
4011 }
4012
4013 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4014 {
4015 return 400000; /* FIXME */
4016 }
4017
4018 static int i945_get_display_clock_speed(struct drm_device *dev)
4019 {
4020 return 400000;
4021 }
4022
4023 static int i915_get_display_clock_speed(struct drm_device *dev)
4024 {
4025 return 333000;
4026 }
4027
4028 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4029 {
4030 return 200000;
4031 }
4032
4033 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4034 {
4035 u16 gcfgc = 0;
4036
4037 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4038
4039 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4040 return 133000;
4041 else {
4042 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4043 case GC_DISPLAY_CLOCK_333_MHZ:
4044 return 333000;
4045 default:
4046 case GC_DISPLAY_CLOCK_190_200_MHZ:
4047 return 190000;
4048 }
4049 }
4050 }
4051
4052 static int i865_get_display_clock_speed(struct drm_device *dev)
4053 {
4054 return 266000;
4055 }
4056
4057 static int i855_get_display_clock_speed(struct drm_device *dev)
4058 {
4059 u16 hpllcc = 0;
4060 /* Assume that the hardware is in the high speed state. This
4061 * should be the default.
4062 */
4063 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4064 case GC_CLOCK_133_200:
4065 case GC_CLOCK_100_200:
4066 return 200000;
4067 case GC_CLOCK_166_250:
4068 return 250000;
4069 case GC_CLOCK_100_133:
4070 return 133000;
4071 }
4072
4073 /* Shouldn't happen */
4074 return 0;
4075 }
4076
4077 static int i830_get_display_clock_speed(struct drm_device *dev)
4078 {
4079 return 133000;
4080 }
4081
4082 static void
4083 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4084 {
4085 while (*num > DATA_LINK_M_N_MASK ||
4086 *den > DATA_LINK_M_N_MASK) {
4087 *num >>= 1;
4088 *den >>= 1;
4089 }
4090 }
4091
4092 static void compute_m_n(unsigned int m, unsigned int n,
4093 uint32_t *ret_m, uint32_t *ret_n)
4094 {
4095 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4096 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4097 intel_reduce_m_n_ratio(ret_m, ret_n);
4098 }
4099
4100 void
4101 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4102 int pixel_clock, int link_clock,
4103 struct intel_link_m_n *m_n)
4104 {
4105 m_n->tu = 64;
4106
4107 compute_m_n(bits_per_pixel * pixel_clock,
4108 link_clock * nlanes * 8,
4109 &m_n->gmch_m, &m_n->gmch_n);
4110
4111 compute_m_n(pixel_clock, link_clock,
4112 &m_n->link_m, &m_n->link_n);
4113 }
4114
4115 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4116 {
4117 if (i915_panel_use_ssc >= 0)
4118 return i915_panel_use_ssc != 0;
4119 return dev_priv->lvds_use_ssc
4120 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4121 }
4122
4123 static int vlv_get_refclk(struct drm_crtc *crtc)
4124 {
4125 struct drm_device *dev = crtc->dev;
4126 struct drm_i915_private *dev_priv = dev->dev_private;
4127 int refclk = 27000; /* for DP & HDMI */
4128
4129 return 100000; /* only one validated so far */
4130
4131 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4132 refclk = 96000;
4133 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4134 if (intel_panel_use_ssc(dev_priv))
4135 refclk = 100000;
4136 else
4137 refclk = 96000;
4138 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4139 refclk = 100000;
4140 }
4141
4142 return refclk;
4143 }
4144
4145 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4146 {
4147 struct drm_device *dev = crtc->dev;
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 int refclk;
4150
4151 if (IS_VALLEYVIEW(dev)) {
4152 refclk = vlv_get_refclk(crtc);
4153 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4154 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4155 refclk = dev_priv->lvds_ssc_freq * 1000;
4156 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4157 refclk / 1000);
4158 } else if (!IS_GEN2(dev)) {
4159 refclk = 96000;
4160 } else {
4161 refclk = 48000;
4162 }
4163
4164 return refclk;
4165 }
4166
4167 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4168 {
4169 unsigned dotclock = crtc->config.adjusted_mode.clock;
4170 struct dpll *clock = &crtc->config.dpll;
4171
4172 /* SDVO TV has fixed PLL values depend on its clock range,
4173 this mirrors vbios setting. */
4174 if (dotclock >= 100000 && dotclock < 140500) {
4175 clock->p1 = 2;
4176 clock->p2 = 10;
4177 clock->n = 3;
4178 clock->m1 = 16;
4179 clock->m2 = 8;
4180 } else if (dotclock >= 140500 && dotclock <= 200000) {
4181 clock->p1 = 1;
4182 clock->p2 = 10;
4183 clock->n = 6;
4184 clock->m1 = 12;
4185 clock->m2 = 8;
4186 }
4187
4188 crtc->config.clock_set = true;
4189 }
4190
4191 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4192 intel_clock_t *reduced_clock)
4193 {
4194 struct drm_device *dev = crtc->base.dev;
4195 struct drm_i915_private *dev_priv = dev->dev_private;
4196 int pipe = crtc->pipe;
4197 u32 fp, fp2 = 0;
4198 struct dpll *clock = &crtc->config.dpll;
4199
4200 if (IS_PINEVIEW(dev)) {
4201 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4202 if (reduced_clock)
4203 fp2 = (1 << reduced_clock->n) << 16 |
4204 reduced_clock->m1 << 8 | reduced_clock->m2;
4205 } else {
4206 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4207 if (reduced_clock)
4208 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4209 reduced_clock->m2;
4210 }
4211
4212 I915_WRITE(FP0(pipe), fp);
4213
4214 crtc->lowfreq_avail = false;
4215 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4216 reduced_clock && i915_powersave) {
4217 I915_WRITE(FP1(pipe), fp2);
4218 crtc->lowfreq_avail = true;
4219 } else {
4220 I915_WRITE(FP1(pipe), fp);
4221 }
4222 }
4223
4224 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4225 {
4226 if (crtc->config.has_pch_encoder)
4227 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4228 else
4229 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4230 }
4231
4232 static void vlv_update_pll(struct intel_crtc *crtc)
4233 {
4234 struct drm_device *dev = crtc->base.dev;
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236 int pipe = crtc->pipe;
4237 u32 dpll, mdiv, pdiv;
4238 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4239 bool is_sdvo;
4240 u32 temp;
4241
4242 mutex_lock(&dev_priv->dpio_lock);
4243
4244 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4245 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4246
4247 dpll = DPLL_VGA_MODE_DIS;
4248 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4249 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4250 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4251
4252 I915_WRITE(DPLL(pipe), dpll);
4253 POSTING_READ(DPLL(pipe));
4254
4255 bestn = crtc->config.dpll.n;
4256 bestm1 = crtc->config.dpll.m1;
4257 bestm2 = crtc->config.dpll.m2;
4258 bestp1 = crtc->config.dpll.p1;
4259 bestp2 = crtc->config.dpll.p2;
4260
4261 /*
4262 * In Valleyview PLL and program lane counter registers are exposed
4263 * through DPIO interface
4264 */
4265 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4266 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4267 mdiv |= ((bestn << DPIO_N_SHIFT));
4268 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4269 mdiv |= (1 << DPIO_K_SHIFT);
4270 mdiv |= DPIO_ENABLE_CALIBRATION;
4271 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4272
4273 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4274
4275 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4276 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4277 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4278 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4279 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4280
4281 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4282
4283 dpll |= DPLL_VCO_ENABLE;
4284 I915_WRITE(DPLL(pipe), dpll);
4285 POSTING_READ(DPLL(pipe));
4286 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4287 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4288
4289 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4290
4291 if (crtc->config.has_dp_encoder)
4292 intel_dp_set_m_n(crtc);
4293
4294 I915_WRITE(DPLL(pipe), dpll);
4295
4296 /* Wait for the clocks to stabilize. */
4297 POSTING_READ(DPLL(pipe));
4298 udelay(150);
4299
4300 temp = 0;
4301 if (is_sdvo) {
4302 temp = 0;
4303 if (crtc->config.pixel_multiplier > 1) {
4304 temp = (crtc->config.pixel_multiplier - 1)
4305 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4306 }
4307 }
4308 I915_WRITE(DPLL_MD(pipe), temp);
4309 POSTING_READ(DPLL_MD(pipe));
4310
4311 /* Now program lane control registers */
4312 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
4313 || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
4314 temp = 0x1000C4;
4315 if(pipe == 1)
4316 temp |= (1 << 21);
4317 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4318 }
4319
4320 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
4321 temp = 0x1000C4;
4322 if(pipe == 1)
4323 temp |= (1 << 21);
4324 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4325 }
4326
4327 mutex_unlock(&dev_priv->dpio_lock);
4328 }
4329
4330 static void i9xx_update_pll(struct intel_crtc *crtc,
4331 intel_clock_t *reduced_clock,
4332 int num_connectors,
4333 bool needs_tv_clock)
4334 {
4335 struct drm_device *dev = crtc->base.dev;
4336 struct drm_i915_private *dev_priv = dev->dev_private;
4337 struct intel_encoder *encoder;
4338 int pipe = crtc->pipe;
4339 u32 dpll;
4340 bool is_sdvo;
4341 struct dpll *clock = &crtc->config.dpll;
4342
4343 i9xx_update_pll_dividers(crtc, reduced_clock);
4344
4345 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4346 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4347
4348 dpll = DPLL_VGA_MODE_DIS;
4349
4350 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4351 dpll |= DPLLB_MODE_LVDS;
4352 else
4353 dpll |= DPLLB_MODE_DAC_SERIAL;
4354
4355 if (is_sdvo) {
4356 if ((crtc->config.pixel_multiplier > 1) &&
4357 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4358 dpll |= (crtc->config.pixel_multiplier - 1)
4359 << SDVO_MULTIPLIER_SHIFT_HIRES;
4360 }
4361 dpll |= DPLL_DVO_HIGH_SPEED;
4362 }
4363 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4364 dpll |= DPLL_DVO_HIGH_SPEED;
4365
4366 /* compute bitmask from p1 value */
4367 if (IS_PINEVIEW(dev))
4368 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4369 else {
4370 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4371 if (IS_G4X(dev) && reduced_clock)
4372 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4373 }
4374 switch (clock->p2) {
4375 case 5:
4376 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4377 break;
4378 case 7:
4379 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4380 break;
4381 case 10:
4382 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4383 break;
4384 case 14:
4385 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4386 break;
4387 }
4388 if (INTEL_INFO(dev)->gen >= 4)
4389 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4390
4391 if (is_sdvo && needs_tv_clock)
4392 dpll |= PLL_REF_INPUT_TVCLKINBC;
4393 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4394 /* XXX: just matching BIOS for now */
4395 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4396 dpll |= 3;
4397 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4398 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4399 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4400 else
4401 dpll |= PLL_REF_INPUT_DREFCLK;
4402
4403 dpll |= DPLL_VCO_ENABLE;
4404 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4405 POSTING_READ(DPLL(pipe));
4406 udelay(150);
4407
4408 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4409 if (encoder->pre_pll_enable)
4410 encoder->pre_pll_enable(encoder);
4411
4412 if (crtc->config.has_dp_encoder)
4413 intel_dp_set_m_n(crtc);
4414
4415 I915_WRITE(DPLL(pipe), dpll);
4416
4417 /* Wait for the clocks to stabilize. */
4418 POSTING_READ(DPLL(pipe));
4419 udelay(150);
4420
4421 if (INTEL_INFO(dev)->gen >= 4) {
4422 u32 temp = 0;
4423 if (is_sdvo) {
4424 temp = 0;
4425 if (crtc->config.pixel_multiplier > 1) {
4426 temp = (crtc->config.pixel_multiplier - 1)
4427 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4428 }
4429 }
4430 I915_WRITE(DPLL_MD(pipe), temp);
4431 } else {
4432 /* The pixel multiplier can only be updated once the
4433 * DPLL is enabled and the clocks are stable.
4434 *
4435 * So write it again.
4436 */
4437 I915_WRITE(DPLL(pipe), dpll);
4438 }
4439 }
4440
4441 static void i8xx_update_pll(struct intel_crtc *crtc,
4442 struct drm_display_mode *adjusted_mode,
4443 intel_clock_t *reduced_clock,
4444 int num_connectors)
4445 {
4446 struct drm_device *dev = crtc->base.dev;
4447 struct drm_i915_private *dev_priv = dev->dev_private;
4448 struct intel_encoder *encoder;
4449 int pipe = crtc->pipe;
4450 u32 dpll;
4451 struct dpll *clock = &crtc->config.dpll;
4452
4453 i9xx_update_pll_dividers(crtc, reduced_clock);
4454
4455 dpll = DPLL_VGA_MODE_DIS;
4456
4457 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4458 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4459 } else {
4460 if (clock->p1 == 2)
4461 dpll |= PLL_P1_DIVIDE_BY_TWO;
4462 else
4463 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4464 if (clock->p2 == 4)
4465 dpll |= PLL_P2_DIVIDE_BY_4;
4466 }
4467
4468 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4469 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4470 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4471 else
4472 dpll |= PLL_REF_INPUT_DREFCLK;
4473
4474 dpll |= DPLL_VCO_ENABLE;
4475 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4476 POSTING_READ(DPLL(pipe));
4477 udelay(150);
4478
4479 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4480 if (encoder->pre_pll_enable)
4481 encoder->pre_pll_enable(encoder);
4482
4483 I915_WRITE(DPLL(pipe), dpll);
4484
4485 /* Wait for the clocks to stabilize. */
4486 POSTING_READ(DPLL(pipe));
4487 udelay(150);
4488
4489 /* The pixel multiplier can only be updated once the
4490 * DPLL is enabled and the clocks are stable.
4491 *
4492 * So write it again.
4493 */
4494 I915_WRITE(DPLL(pipe), dpll);
4495 }
4496
4497 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4498 struct drm_display_mode *mode,
4499 struct drm_display_mode *adjusted_mode)
4500 {
4501 struct drm_device *dev = intel_crtc->base.dev;
4502 struct drm_i915_private *dev_priv = dev->dev_private;
4503 enum pipe pipe = intel_crtc->pipe;
4504 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4505 uint32_t vsyncshift;
4506
4507 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4508 /* the chip adds 2 halflines automatically */
4509 adjusted_mode->crtc_vtotal -= 1;
4510 adjusted_mode->crtc_vblank_end -= 1;
4511 vsyncshift = adjusted_mode->crtc_hsync_start
4512 - adjusted_mode->crtc_htotal / 2;
4513 } else {
4514 vsyncshift = 0;
4515 }
4516
4517 if (INTEL_INFO(dev)->gen > 3)
4518 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4519
4520 I915_WRITE(HTOTAL(cpu_transcoder),
4521 (adjusted_mode->crtc_hdisplay - 1) |
4522 ((adjusted_mode->crtc_htotal - 1) << 16));
4523 I915_WRITE(HBLANK(cpu_transcoder),
4524 (adjusted_mode->crtc_hblank_start - 1) |
4525 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4526 I915_WRITE(HSYNC(cpu_transcoder),
4527 (adjusted_mode->crtc_hsync_start - 1) |
4528 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4529
4530 I915_WRITE(VTOTAL(cpu_transcoder),
4531 (adjusted_mode->crtc_vdisplay - 1) |
4532 ((adjusted_mode->crtc_vtotal - 1) << 16));
4533 I915_WRITE(VBLANK(cpu_transcoder),
4534 (adjusted_mode->crtc_vblank_start - 1) |
4535 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4536 I915_WRITE(VSYNC(cpu_transcoder),
4537 (adjusted_mode->crtc_vsync_start - 1) |
4538 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4539
4540 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4541 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4542 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4543 * bits. */
4544 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4545 (pipe == PIPE_B || pipe == PIPE_C))
4546 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4547
4548 /* pipesrc controls the size that is scaled from, which should
4549 * always be the user's requested size.
4550 */
4551 I915_WRITE(PIPESRC(pipe),
4552 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4553 }
4554
4555 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4556 {
4557 struct drm_device *dev = intel_crtc->base.dev;
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 uint32_t pipeconf;
4560
4561 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4562
4563 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4564 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4565 pipeconf |= PIPECONF_ENABLE;
4566
4567 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4568 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4569 * core speed.
4570 *
4571 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4572 * pipe == 0 check?
4573 */
4574 if (intel_crtc->config.requested_mode.clock >
4575 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4576 pipeconf |= PIPECONF_DOUBLE_WIDE;
4577 else
4578 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4579 }
4580
4581 /* default to 8bpc */
4582 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4583 if (intel_crtc->config.has_dp_encoder) {
4584 if (intel_crtc->config.dither) {
4585 pipeconf |= PIPECONF_6BPC |
4586 PIPECONF_DITHER_EN |
4587 PIPECONF_DITHER_TYPE_SP;
4588 }
4589 }
4590
4591 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4592 INTEL_OUTPUT_EDP)) {
4593 if (intel_crtc->config.dither) {
4594 pipeconf |= PIPECONF_6BPC |
4595 PIPECONF_ENABLE |
4596 I965_PIPECONF_ACTIVE;
4597 }
4598 }
4599
4600 if (HAS_PIPE_CXSR(dev)) {
4601 if (intel_crtc->lowfreq_avail) {
4602 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4603 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4604 } else {
4605 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4606 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4607 }
4608 }
4609
4610 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4611 if (!IS_GEN2(dev) &&
4612 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4613 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4614 else
4615 pipeconf |= PIPECONF_PROGRESSIVE;
4616
4617 if (IS_VALLEYVIEW(dev)) {
4618 if (intel_crtc->config.limited_color_range)
4619 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4620 else
4621 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4622 }
4623
4624 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4625 POSTING_READ(PIPECONF(intel_crtc->pipe));
4626 }
4627
4628 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4629 int x, int y,
4630 struct drm_framebuffer *fb)
4631 {
4632 struct drm_device *dev = crtc->dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4635 struct drm_display_mode *adjusted_mode =
4636 &intel_crtc->config.adjusted_mode;
4637 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4638 int pipe = intel_crtc->pipe;
4639 int plane = intel_crtc->plane;
4640 int refclk, num_connectors = 0;
4641 intel_clock_t clock, reduced_clock;
4642 u32 dspcntr;
4643 bool ok, has_reduced_clock = false, is_sdvo = false;
4644 bool is_lvds = false, is_tv = false;
4645 struct intel_encoder *encoder;
4646 const intel_limit_t *limit;
4647 int ret;
4648
4649 for_each_encoder_on_crtc(dev, crtc, encoder) {
4650 switch (encoder->type) {
4651 case INTEL_OUTPUT_LVDS:
4652 is_lvds = true;
4653 break;
4654 case INTEL_OUTPUT_SDVO:
4655 case INTEL_OUTPUT_HDMI:
4656 is_sdvo = true;
4657 if (encoder->needs_tv_clock)
4658 is_tv = true;
4659 break;
4660 case INTEL_OUTPUT_TVOUT:
4661 is_tv = true;
4662 break;
4663 }
4664
4665 num_connectors++;
4666 }
4667
4668 refclk = i9xx_get_refclk(crtc, num_connectors);
4669
4670 /*
4671 * Returns a set of divisors for the desired target clock with the given
4672 * refclk, or FALSE. The returned values represent the clock equation:
4673 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4674 */
4675 limit = intel_limit(crtc, refclk);
4676 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4677 &clock);
4678 if (!ok) {
4679 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4680 return -EINVAL;
4681 }
4682
4683 /* Ensure that the cursor is valid for the new mode before changing... */
4684 intel_crtc_update_cursor(crtc, true);
4685
4686 if (is_lvds && dev_priv->lvds_downclock_avail) {
4687 /*
4688 * Ensure we match the reduced clock's P to the target clock.
4689 * If the clocks don't match, we can't switch the display clock
4690 * by using the FP0/FP1. In such case we will disable the LVDS
4691 * downclock feature.
4692 */
4693 has_reduced_clock = limit->find_pll(limit, crtc,
4694 dev_priv->lvds_downclock,
4695 refclk,
4696 &clock,
4697 &reduced_clock);
4698 }
4699 /* Compat-code for transition, will disappear. */
4700 if (!intel_crtc->config.clock_set) {
4701 intel_crtc->config.dpll.n = clock.n;
4702 intel_crtc->config.dpll.m1 = clock.m1;
4703 intel_crtc->config.dpll.m2 = clock.m2;
4704 intel_crtc->config.dpll.p1 = clock.p1;
4705 intel_crtc->config.dpll.p2 = clock.p2;
4706 }
4707
4708 if (is_sdvo && is_tv)
4709 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4710
4711 if (IS_GEN2(dev))
4712 i8xx_update_pll(intel_crtc, adjusted_mode,
4713 has_reduced_clock ? &reduced_clock : NULL,
4714 num_connectors);
4715 else if (IS_VALLEYVIEW(dev))
4716 vlv_update_pll(intel_crtc);
4717 else
4718 i9xx_update_pll(intel_crtc,
4719 has_reduced_clock ? &reduced_clock : NULL,
4720 num_connectors,
4721 is_sdvo && is_tv);
4722
4723 /* Set up the display plane register */
4724 dspcntr = DISPPLANE_GAMMA_ENABLE;
4725
4726 if (!IS_VALLEYVIEW(dev)) {
4727 if (pipe == 0)
4728 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4729 else
4730 dspcntr |= DISPPLANE_SEL_PIPE_B;
4731 }
4732
4733 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4734 drm_mode_debug_printmodeline(mode);
4735
4736 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4737
4738 /* pipesrc and dspsize control the size that is scaled from,
4739 * which should always be the user's requested size.
4740 */
4741 I915_WRITE(DSPSIZE(plane),
4742 ((mode->vdisplay - 1) << 16) |
4743 (mode->hdisplay - 1));
4744 I915_WRITE(DSPPOS(plane), 0);
4745
4746 i9xx_set_pipeconf(intel_crtc);
4747
4748 intel_enable_pipe(dev_priv, pipe, false);
4749
4750 intel_wait_for_vblank(dev, pipe);
4751
4752 I915_WRITE(DSPCNTR(plane), dspcntr);
4753 POSTING_READ(DSPCNTR(plane));
4754
4755 ret = intel_pipe_set_base(crtc, x, y, fb);
4756
4757 intel_update_watermarks(dev);
4758
4759 return ret;
4760 }
4761
4762 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4763 struct intel_crtc_config *pipe_config)
4764 {
4765 struct drm_device *dev = crtc->base.dev;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 uint32_t tmp;
4768
4769 tmp = I915_READ(PIPECONF(crtc->pipe));
4770 if (!(tmp & PIPECONF_ENABLE))
4771 return false;
4772
4773 return true;
4774 }
4775
4776 static void ironlake_init_pch_refclk(struct drm_device *dev)
4777 {
4778 struct drm_i915_private *dev_priv = dev->dev_private;
4779 struct drm_mode_config *mode_config = &dev->mode_config;
4780 struct intel_encoder *encoder;
4781 u32 val, final;
4782 bool has_lvds = false;
4783 bool has_cpu_edp = false;
4784 bool has_pch_edp = false;
4785 bool has_panel = false;
4786 bool has_ck505 = false;
4787 bool can_ssc = false;
4788
4789 /* We need to take the global config into account */
4790 list_for_each_entry(encoder, &mode_config->encoder_list,
4791 base.head) {
4792 switch (encoder->type) {
4793 case INTEL_OUTPUT_LVDS:
4794 has_panel = true;
4795 has_lvds = true;
4796 break;
4797 case INTEL_OUTPUT_EDP:
4798 has_panel = true;
4799 if (intel_encoder_is_pch_edp(&encoder->base))
4800 has_pch_edp = true;
4801 else
4802 has_cpu_edp = true;
4803 break;
4804 }
4805 }
4806
4807 if (HAS_PCH_IBX(dev)) {
4808 has_ck505 = dev_priv->display_clock_mode;
4809 can_ssc = has_ck505;
4810 } else {
4811 has_ck505 = false;
4812 can_ssc = true;
4813 }
4814
4815 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4816 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4817 has_ck505);
4818
4819 /* Ironlake: try to setup display ref clock before DPLL
4820 * enabling. This is only under driver's control after
4821 * PCH B stepping, previous chipset stepping should be
4822 * ignoring this setting.
4823 */
4824 val = I915_READ(PCH_DREF_CONTROL);
4825
4826 /* As we must carefully and slowly disable/enable each source in turn,
4827 * compute the final state we want first and check if we need to
4828 * make any changes at all.
4829 */
4830 final = val;
4831 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4832 if (has_ck505)
4833 final |= DREF_NONSPREAD_CK505_ENABLE;
4834 else
4835 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4836
4837 final &= ~DREF_SSC_SOURCE_MASK;
4838 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4839 final &= ~DREF_SSC1_ENABLE;
4840
4841 if (has_panel) {
4842 final |= DREF_SSC_SOURCE_ENABLE;
4843
4844 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4845 final |= DREF_SSC1_ENABLE;
4846
4847 if (has_cpu_edp) {
4848 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4849 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4850 else
4851 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4852 } else
4853 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4854 } else {
4855 final |= DREF_SSC_SOURCE_DISABLE;
4856 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4857 }
4858
4859 if (final == val)
4860 return;
4861
4862 /* Always enable nonspread source */
4863 val &= ~DREF_NONSPREAD_SOURCE_MASK;
4864
4865 if (has_ck505)
4866 val |= DREF_NONSPREAD_CK505_ENABLE;
4867 else
4868 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4869
4870 if (has_panel) {
4871 val &= ~DREF_SSC_SOURCE_MASK;
4872 val |= DREF_SSC_SOURCE_ENABLE;
4873
4874 /* SSC must be turned on before enabling the CPU output */
4875 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4876 DRM_DEBUG_KMS("Using SSC on panel\n");
4877 val |= DREF_SSC1_ENABLE;
4878 } else
4879 val &= ~DREF_SSC1_ENABLE;
4880
4881 /* Get SSC going before enabling the outputs */
4882 I915_WRITE(PCH_DREF_CONTROL, val);
4883 POSTING_READ(PCH_DREF_CONTROL);
4884 udelay(200);
4885
4886 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4887
4888 /* Enable CPU source on CPU attached eDP */
4889 if (has_cpu_edp) {
4890 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4891 DRM_DEBUG_KMS("Using SSC on eDP\n");
4892 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4893 }
4894 else
4895 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4896 } else
4897 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4898
4899 I915_WRITE(PCH_DREF_CONTROL, val);
4900 POSTING_READ(PCH_DREF_CONTROL);
4901 udelay(200);
4902 } else {
4903 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4904
4905 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4906
4907 /* Turn off CPU output */
4908 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4909
4910 I915_WRITE(PCH_DREF_CONTROL, val);
4911 POSTING_READ(PCH_DREF_CONTROL);
4912 udelay(200);
4913
4914 /* Turn off the SSC source */
4915 val &= ~DREF_SSC_SOURCE_MASK;
4916 val |= DREF_SSC_SOURCE_DISABLE;
4917
4918 /* Turn off SSC1 */
4919 val &= ~DREF_SSC1_ENABLE;
4920
4921 I915_WRITE(PCH_DREF_CONTROL, val);
4922 POSTING_READ(PCH_DREF_CONTROL);
4923 udelay(200);
4924 }
4925
4926 BUG_ON(val != final);
4927 }
4928
4929 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4930 static void lpt_init_pch_refclk(struct drm_device *dev)
4931 {
4932 struct drm_i915_private *dev_priv = dev->dev_private;
4933 struct drm_mode_config *mode_config = &dev->mode_config;
4934 struct intel_encoder *encoder;
4935 bool has_vga = false;
4936 bool is_sdv = false;
4937 u32 tmp;
4938
4939 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4940 switch (encoder->type) {
4941 case INTEL_OUTPUT_ANALOG:
4942 has_vga = true;
4943 break;
4944 }
4945 }
4946
4947 if (!has_vga)
4948 return;
4949
4950 mutex_lock(&dev_priv->dpio_lock);
4951
4952 /* XXX: Rip out SDV support once Haswell ships for real. */
4953 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4954 is_sdv = true;
4955
4956 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4957 tmp &= ~SBI_SSCCTL_DISABLE;
4958 tmp |= SBI_SSCCTL_PATHALT;
4959 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4960
4961 udelay(24);
4962
4963 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4964 tmp &= ~SBI_SSCCTL_PATHALT;
4965 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4966
4967 if (!is_sdv) {
4968 tmp = I915_READ(SOUTH_CHICKEN2);
4969 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4970 I915_WRITE(SOUTH_CHICKEN2, tmp);
4971
4972 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4973 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4974 DRM_ERROR("FDI mPHY reset assert timeout\n");
4975
4976 tmp = I915_READ(SOUTH_CHICKEN2);
4977 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4978 I915_WRITE(SOUTH_CHICKEN2, tmp);
4979
4980 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4981 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4982 100))
4983 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4984 }
4985
4986 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4987 tmp &= ~(0xFF << 24);
4988 tmp |= (0x12 << 24);
4989 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4990
4991 if (is_sdv) {
4992 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4993 tmp |= 0x7FFF;
4994 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4995 }
4996
4997 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4998 tmp |= (1 << 11);
4999 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5000
5001 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5002 tmp |= (1 << 11);
5003 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5004
5005 if (is_sdv) {
5006 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5007 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5008 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5009
5010 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5011 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5012 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5013
5014 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5015 tmp |= (0x3F << 8);
5016 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5017
5018 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5019 tmp |= (0x3F << 8);
5020 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5021 }
5022
5023 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5024 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5025 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5026
5027 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5028 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5029 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5030
5031 if (!is_sdv) {
5032 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5033 tmp &= ~(7 << 13);
5034 tmp |= (5 << 13);
5035 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5036
5037 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5038 tmp &= ~(7 << 13);
5039 tmp |= (5 << 13);
5040 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5041 }
5042
5043 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5044 tmp &= ~0xFF;
5045 tmp |= 0x1C;
5046 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5047
5048 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5049 tmp &= ~0xFF;
5050 tmp |= 0x1C;
5051 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5052
5053 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5054 tmp &= ~(0xFF << 16);
5055 tmp |= (0x1C << 16);
5056 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5057
5058 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5059 tmp &= ~(0xFF << 16);
5060 tmp |= (0x1C << 16);
5061 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5062
5063 if (!is_sdv) {
5064 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5065 tmp |= (1 << 27);
5066 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5067
5068 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5069 tmp |= (1 << 27);
5070 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5071
5072 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5073 tmp &= ~(0xF << 28);
5074 tmp |= (4 << 28);
5075 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5076
5077 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5078 tmp &= ~(0xF << 28);
5079 tmp |= (4 << 28);
5080 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5081 }
5082
5083 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5084 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5085 tmp |= SBI_DBUFF0_ENABLE;
5086 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5087
5088 mutex_unlock(&dev_priv->dpio_lock);
5089 }
5090
5091 /*
5092 * Initialize reference clocks when the driver loads
5093 */
5094 void intel_init_pch_refclk(struct drm_device *dev)
5095 {
5096 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5097 ironlake_init_pch_refclk(dev);
5098 else if (HAS_PCH_LPT(dev))
5099 lpt_init_pch_refclk(dev);
5100 }
5101
5102 static int ironlake_get_refclk(struct drm_crtc *crtc)
5103 {
5104 struct drm_device *dev = crtc->dev;
5105 struct drm_i915_private *dev_priv = dev->dev_private;
5106 struct intel_encoder *encoder;
5107 struct intel_encoder *edp_encoder = NULL;
5108 int num_connectors = 0;
5109 bool is_lvds = false;
5110
5111 for_each_encoder_on_crtc(dev, crtc, encoder) {
5112 switch (encoder->type) {
5113 case INTEL_OUTPUT_LVDS:
5114 is_lvds = true;
5115 break;
5116 case INTEL_OUTPUT_EDP:
5117 edp_encoder = encoder;
5118 break;
5119 }
5120 num_connectors++;
5121 }
5122
5123 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5124 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5125 dev_priv->lvds_ssc_freq);
5126 return dev_priv->lvds_ssc_freq * 1000;
5127 }
5128
5129 return 120000;
5130 }
5131
5132 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5133 struct drm_display_mode *adjusted_mode,
5134 bool dither)
5135 {
5136 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5138 int pipe = intel_crtc->pipe;
5139 uint32_t val;
5140
5141 val = I915_READ(PIPECONF(pipe));
5142
5143 val &= ~PIPECONF_BPC_MASK;
5144 switch (intel_crtc->config.pipe_bpp) {
5145 case 18:
5146 val |= PIPECONF_6BPC;
5147 break;
5148 case 24:
5149 val |= PIPECONF_8BPC;
5150 break;
5151 case 30:
5152 val |= PIPECONF_10BPC;
5153 break;
5154 case 36:
5155 val |= PIPECONF_12BPC;
5156 break;
5157 default:
5158 /* Case prevented by intel_choose_pipe_bpp_dither. */
5159 BUG();
5160 }
5161
5162 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5163 if (dither)
5164 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5165
5166 val &= ~PIPECONF_INTERLACE_MASK;
5167 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5168 val |= PIPECONF_INTERLACED_ILK;
5169 else
5170 val |= PIPECONF_PROGRESSIVE;
5171
5172 if (intel_crtc->config.limited_color_range)
5173 val |= PIPECONF_COLOR_RANGE_SELECT;
5174 else
5175 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5176
5177 I915_WRITE(PIPECONF(pipe), val);
5178 POSTING_READ(PIPECONF(pipe));
5179 }
5180
5181 /*
5182 * Set up the pipe CSC unit.
5183 *
5184 * Currently only full range RGB to limited range RGB conversion
5185 * is supported, but eventually this should handle various
5186 * RGB<->YCbCr scenarios as well.
5187 */
5188 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5189 {
5190 struct drm_device *dev = crtc->dev;
5191 struct drm_i915_private *dev_priv = dev->dev_private;
5192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5193 int pipe = intel_crtc->pipe;
5194 uint16_t coeff = 0x7800; /* 1.0 */
5195
5196 /*
5197 * TODO: Check what kind of values actually come out of the pipe
5198 * with these coeff/postoff values and adjust to get the best
5199 * accuracy. Perhaps we even need to take the bpc value into
5200 * consideration.
5201 */
5202
5203 if (intel_crtc->config.limited_color_range)
5204 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5205
5206 /*
5207 * GY/GU and RY/RU should be the other way around according
5208 * to BSpec, but reality doesn't agree. Just set them up in
5209 * a way that results in the correct picture.
5210 */
5211 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5212 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5213
5214 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5215 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5216
5217 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5218 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5219
5220 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5221 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5222 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5223
5224 if (INTEL_INFO(dev)->gen > 6) {
5225 uint16_t postoff = 0;
5226
5227 if (intel_crtc->config.limited_color_range)
5228 postoff = (16 * (1 << 12) / 255) & 0x1fff;
5229
5230 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5231 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5232 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5233
5234 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5235 } else {
5236 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5237
5238 if (intel_crtc->config.limited_color_range)
5239 mode |= CSC_BLACK_SCREEN_OFFSET;
5240
5241 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5242 }
5243 }
5244
5245 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5246 struct drm_display_mode *adjusted_mode,
5247 bool dither)
5248 {
5249 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5251 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5252 uint32_t val;
5253
5254 val = I915_READ(PIPECONF(cpu_transcoder));
5255
5256 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5257 if (dither)
5258 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5259
5260 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5261 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5262 val |= PIPECONF_INTERLACED_ILK;
5263 else
5264 val |= PIPECONF_PROGRESSIVE;
5265
5266 I915_WRITE(PIPECONF(cpu_transcoder), val);
5267 POSTING_READ(PIPECONF(cpu_transcoder));
5268 }
5269
5270 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5271 struct drm_display_mode *adjusted_mode,
5272 intel_clock_t *clock,
5273 bool *has_reduced_clock,
5274 intel_clock_t *reduced_clock)
5275 {
5276 struct drm_device *dev = crtc->dev;
5277 struct drm_i915_private *dev_priv = dev->dev_private;
5278 struct intel_encoder *intel_encoder;
5279 int refclk;
5280 const intel_limit_t *limit;
5281 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5282
5283 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5284 switch (intel_encoder->type) {
5285 case INTEL_OUTPUT_LVDS:
5286 is_lvds = true;
5287 break;
5288 case INTEL_OUTPUT_SDVO:
5289 case INTEL_OUTPUT_HDMI:
5290 is_sdvo = true;
5291 if (intel_encoder->needs_tv_clock)
5292 is_tv = true;
5293 break;
5294 case INTEL_OUTPUT_TVOUT:
5295 is_tv = true;
5296 break;
5297 }
5298 }
5299
5300 refclk = ironlake_get_refclk(crtc);
5301
5302 /*
5303 * Returns a set of divisors for the desired target clock with the given
5304 * refclk, or FALSE. The returned values represent the clock equation:
5305 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5306 */
5307 limit = intel_limit(crtc, refclk);
5308 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5309 clock);
5310 if (!ret)
5311 return false;
5312
5313 if (is_lvds && dev_priv->lvds_downclock_avail) {
5314 /*
5315 * Ensure we match the reduced clock's P to the target clock.
5316 * If the clocks don't match, we can't switch the display clock
5317 * by using the FP0/FP1. In such case we will disable the LVDS
5318 * downclock feature.
5319 */
5320 *has_reduced_clock = limit->find_pll(limit, crtc,
5321 dev_priv->lvds_downclock,
5322 refclk,
5323 clock,
5324 reduced_clock);
5325 }
5326
5327 if (is_sdvo && is_tv)
5328 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5329
5330 return true;
5331 }
5332
5333 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5334 {
5335 struct drm_i915_private *dev_priv = dev->dev_private;
5336 uint32_t temp;
5337
5338 temp = I915_READ(SOUTH_CHICKEN1);
5339 if (temp & FDI_BC_BIFURCATION_SELECT)
5340 return;
5341
5342 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5343 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5344
5345 temp |= FDI_BC_BIFURCATION_SELECT;
5346 DRM_DEBUG_KMS("enabling fdi C rx\n");
5347 I915_WRITE(SOUTH_CHICKEN1, temp);
5348 POSTING_READ(SOUTH_CHICKEN1);
5349 }
5350
5351 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5352 {
5353 struct drm_device *dev = intel_crtc->base.dev;
5354 struct drm_i915_private *dev_priv = dev->dev_private;
5355 struct intel_crtc *pipe_B_crtc =
5356 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5357
5358 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5359 intel_crtc->pipe, intel_crtc->fdi_lanes);
5360 if (intel_crtc->fdi_lanes > 4) {
5361 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5362 intel_crtc->pipe, intel_crtc->fdi_lanes);
5363 /* Clamp lanes to avoid programming the hw with bogus values. */
5364 intel_crtc->fdi_lanes = 4;
5365
5366 return false;
5367 }
5368
5369 if (INTEL_INFO(dev)->num_pipes == 2)
5370 return true;
5371
5372 switch (intel_crtc->pipe) {
5373 case PIPE_A:
5374 return true;
5375 case PIPE_B:
5376 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5377 intel_crtc->fdi_lanes > 2) {
5378 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5379 intel_crtc->pipe, intel_crtc->fdi_lanes);
5380 /* Clamp lanes to avoid programming the hw with bogus values. */
5381 intel_crtc->fdi_lanes = 2;
5382
5383 return false;
5384 }
5385
5386 if (intel_crtc->fdi_lanes > 2)
5387 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5388 else
5389 cpt_enable_fdi_bc_bifurcation(dev);
5390
5391 return true;
5392 case PIPE_C:
5393 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5394 if (intel_crtc->fdi_lanes > 2) {
5395 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5396 intel_crtc->pipe, intel_crtc->fdi_lanes);
5397 /* Clamp lanes to avoid programming the hw with bogus values. */
5398 intel_crtc->fdi_lanes = 2;
5399
5400 return false;
5401 }
5402 } else {
5403 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5404 return false;
5405 }
5406
5407 cpt_enable_fdi_bc_bifurcation(dev);
5408
5409 return true;
5410 default:
5411 BUG();
5412 }
5413 }
5414
5415 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5416 {
5417 /*
5418 * Account for spread spectrum to avoid
5419 * oversubscribing the link. Max center spread
5420 * is 2.5%; use 5% for safety's sake.
5421 */
5422 u32 bps = target_clock * bpp * 21 / 20;
5423 return bps / (link_bw * 8) + 1;
5424 }
5425
5426 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5427 struct intel_link_m_n *m_n)
5428 {
5429 struct drm_device *dev = crtc->base.dev;
5430 struct drm_i915_private *dev_priv = dev->dev_private;
5431 int pipe = crtc->pipe;
5432
5433 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5434 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5435 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5436 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5437 }
5438
5439 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5440 struct intel_link_m_n *m_n)
5441 {
5442 struct drm_device *dev = crtc->base.dev;
5443 struct drm_i915_private *dev_priv = dev->dev_private;
5444 int pipe = crtc->pipe;
5445 enum transcoder transcoder = crtc->config.cpu_transcoder;
5446
5447 if (INTEL_INFO(dev)->gen >= 5) {
5448 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5449 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5450 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5451 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5452 } else {
5453 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5454 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5455 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5456 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5457 }
5458 }
5459
5460 static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5461 {
5462 struct drm_device *dev = crtc->dev;
5463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5464 struct drm_display_mode *adjusted_mode =
5465 &intel_crtc->config.adjusted_mode;
5466 struct intel_link_m_n m_n = {0};
5467 int target_clock, lane, link_bw;
5468
5469 /* FDI is a binary signal running at ~2.7GHz, encoding
5470 * each output octet as 10 bits. The actual frequency
5471 * is stored as a divider into a 100MHz clock, and the
5472 * mode pixel clock is stored in units of 1KHz.
5473 * Hence the bw of each lane in terms of the mode signal
5474 * is:
5475 */
5476 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5477
5478 if (intel_crtc->config.pixel_target_clock)
5479 target_clock = intel_crtc->config.pixel_target_clock;
5480 else
5481 target_clock = adjusted_mode->clock;
5482
5483 lane = ironlake_get_lanes_required(target_clock, link_bw,
5484 intel_crtc->config.pipe_bpp);
5485
5486 intel_crtc->fdi_lanes = lane;
5487
5488 if (intel_crtc->config.pixel_multiplier > 1)
5489 link_bw *= intel_crtc->config.pixel_multiplier;
5490 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5491 link_bw, &m_n);
5492
5493 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
5494 }
5495
5496 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5497 intel_clock_t *clock, u32 *fp,
5498 intel_clock_t *reduced_clock, u32 *fp2)
5499 {
5500 struct drm_crtc *crtc = &intel_crtc->base;
5501 struct drm_device *dev = crtc->dev;
5502 struct drm_i915_private *dev_priv = dev->dev_private;
5503 struct intel_encoder *intel_encoder;
5504 uint32_t dpll;
5505 int factor, num_connectors = 0;
5506 bool is_lvds = false, is_sdvo = false, is_tv = false;
5507
5508 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5509 switch (intel_encoder->type) {
5510 case INTEL_OUTPUT_LVDS:
5511 is_lvds = true;
5512 break;
5513 case INTEL_OUTPUT_SDVO:
5514 case INTEL_OUTPUT_HDMI:
5515 is_sdvo = true;
5516 if (intel_encoder->needs_tv_clock)
5517 is_tv = true;
5518 break;
5519 case INTEL_OUTPUT_TVOUT:
5520 is_tv = true;
5521 break;
5522 }
5523
5524 num_connectors++;
5525 }
5526
5527 /* Enable autotuning of the PLL clock (if permissible) */
5528 factor = 21;
5529 if (is_lvds) {
5530 if ((intel_panel_use_ssc(dev_priv) &&
5531 dev_priv->lvds_ssc_freq == 100) ||
5532 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5533 factor = 25;
5534 } else if (is_sdvo && is_tv)
5535 factor = 20;
5536
5537 if (clock->m < factor * clock->n)
5538 *fp |= FP_CB_TUNE;
5539
5540 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5541 *fp2 |= FP_CB_TUNE;
5542
5543 dpll = 0;
5544
5545 if (is_lvds)
5546 dpll |= DPLLB_MODE_LVDS;
5547 else
5548 dpll |= DPLLB_MODE_DAC_SERIAL;
5549 if (is_sdvo) {
5550 if (intel_crtc->config.pixel_multiplier > 1) {
5551 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5552 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5553 }
5554 dpll |= DPLL_DVO_HIGH_SPEED;
5555 }
5556 if (intel_crtc->config.has_dp_encoder &&
5557 intel_crtc->config.has_pch_encoder)
5558 dpll |= DPLL_DVO_HIGH_SPEED;
5559
5560 /* compute bitmask from p1 value */
5561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5562 /* also FPA1 */
5563 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5564
5565 switch (clock->p2) {
5566 case 5:
5567 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5568 break;
5569 case 7:
5570 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5571 break;
5572 case 10:
5573 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5574 break;
5575 case 14:
5576 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5577 break;
5578 }
5579
5580 if (is_sdvo && is_tv)
5581 dpll |= PLL_REF_INPUT_TVCLKINBC;
5582 else if (is_tv)
5583 /* XXX: just matching BIOS for now */
5584 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5585 dpll |= 3;
5586 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5587 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5588 else
5589 dpll |= PLL_REF_INPUT_DREFCLK;
5590
5591 return dpll;
5592 }
5593
5594 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5595 int x, int y,
5596 struct drm_framebuffer *fb)
5597 {
5598 struct drm_device *dev = crtc->dev;
5599 struct drm_i915_private *dev_priv = dev->dev_private;
5600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5601 struct drm_display_mode *adjusted_mode =
5602 &intel_crtc->config.adjusted_mode;
5603 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5604 int pipe = intel_crtc->pipe;
5605 int plane = intel_crtc->plane;
5606 int num_connectors = 0;
5607 intel_clock_t clock, reduced_clock;
5608 u32 dpll, fp = 0, fp2 = 0;
5609 bool ok, has_reduced_clock = false;
5610 bool is_lvds = false;
5611 struct intel_encoder *encoder;
5612 int ret;
5613 bool dither, fdi_config_ok;
5614
5615 for_each_encoder_on_crtc(dev, crtc, encoder) {
5616 switch (encoder->type) {
5617 case INTEL_OUTPUT_LVDS:
5618 is_lvds = true;
5619 break;
5620 }
5621
5622 num_connectors++;
5623 }
5624
5625 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5626 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5627
5628 intel_crtc->config.cpu_transcoder = pipe;
5629
5630 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5631 &has_reduced_clock, &reduced_clock);
5632 if (!ok) {
5633 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5634 return -EINVAL;
5635 }
5636 /* Compat-code for transition, will disappear. */
5637 if (!intel_crtc->config.clock_set) {
5638 intel_crtc->config.dpll.n = clock.n;
5639 intel_crtc->config.dpll.m1 = clock.m1;
5640 intel_crtc->config.dpll.m2 = clock.m2;
5641 intel_crtc->config.dpll.p1 = clock.p1;
5642 intel_crtc->config.dpll.p2 = clock.p2;
5643 }
5644
5645 /* Ensure that the cursor is valid for the new mode before changing... */
5646 intel_crtc_update_cursor(crtc, true);
5647
5648 /* determine panel color depth */
5649 dither = intel_crtc->config.dither;
5650 if (is_lvds && dev_priv->lvds_dither)
5651 dither = true;
5652
5653 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5654 if (has_reduced_clock)
5655 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5656 reduced_clock.m2;
5657
5658 dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
5659 has_reduced_clock ? &fp2 : NULL);
5660
5661 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5662 drm_mode_debug_printmodeline(mode);
5663
5664 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5665 if (intel_crtc->config.has_pch_encoder) {
5666 struct intel_pch_pll *pll;
5667
5668 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5669 if (pll == NULL) {
5670 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5671 pipe);
5672 return -EINVAL;
5673 }
5674 } else
5675 intel_put_pch_pll(intel_crtc);
5676
5677 if (intel_crtc->config.has_dp_encoder)
5678 intel_dp_set_m_n(intel_crtc);
5679
5680 for_each_encoder_on_crtc(dev, crtc, encoder)
5681 if (encoder->pre_pll_enable)
5682 encoder->pre_pll_enable(encoder);
5683
5684 if (intel_crtc->pch_pll) {
5685 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5686
5687 /* Wait for the clocks to stabilize. */
5688 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5689 udelay(150);
5690
5691 /* The pixel multiplier can only be updated once the
5692 * DPLL is enabled and the clocks are stable.
5693 *
5694 * So write it again.
5695 */
5696 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5697 }
5698
5699 intel_crtc->lowfreq_avail = false;
5700 if (intel_crtc->pch_pll) {
5701 if (is_lvds && has_reduced_clock && i915_powersave) {
5702 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5703 intel_crtc->lowfreq_avail = true;
5704 } else {
5705 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5706 }
5707 }
5708
5709 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5710
5711 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5712 * ironlake_check_fdi_lanes. */
5713 intel_crtc->fdi_lanes = 0;
5714 if (intel_crtc->config.has_pch_encoder)
5715 ironlake_fdi_set_m_n(crtc);
5716
5717 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5718
5719 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5720
5721 intel_wait_for_vblank(dev, pipe);
5722
5723 /* Set up the display plane register */
5724 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5725 POSTING_READ(DSPCNTR(plane));
5726
5727 ret = intel_pipe_set_base(crtc, x, y, fb);
5728
5729 intel_update_watermarks(dev);
5730
5731 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5732
5733 return fdi_config_ok ? ret : -EINVAL;
5734 }
5735
5736 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5737 struct intel_crtc_config *pipe_config)
5738 {
5739 struct drm_device *dev = crtc->base.dev;
5740 struct drm_i915_private *dev_priv = dev->dev_private;
5741 uint32_t tmp;
5742
5743 tmp = I915_READ(PIPECONF(crtc->pipe));
5744 if (!(tmp & PIPECONF_ENABLE))
5745 return false;
5746
5747 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5748 pipe_config->has_pch_encoder = true;
5749
5750 return true;
5751 }
5752
5753 static void haswell_modeset_global_resources(struct drm_device *dev)
5754 {
5755 struct drm_i915_private *dev_priv = dev->dev_private;
5756 bool enable = false;
5757 struct intel_crtc *crtc;
5758 struct intel_encoder *encoder;
5759
5760 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5761 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5762 enable = true;
5763 /* XXX: Should check for edp transcoder here, but thanks to init
5764 * sequence that's not yet available. Just in case desktop eDP
5765 * on PORT D is possible on haswell, too. */
5766 }
5767
5768 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5769 base.head) {
5770 if (encoder->type != INTEL_OUTPUT_EDP &&
5771 encoder->connectors_active)
5772 enable = true;
5773 }
5774
5775 /* Even the eDP panel fitter is outside the always-on well. */
5776 if (dev_priv->pch_pf_size)
5777 enable = true;
5778
5779 intel_set_power_well(dev, enable);
5780 }
5781
5782 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5783 int x, int y,
5784 struct drm_framebuffer *fb)
5785 {
5786 struct drm_device *dev = crtc->dev;
5787 struct drm_i915_private *dev_priv = dev->dev_private;
5788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5789 struct drm_display_mode *adjusted_mode =
5790 &intel_crtc->config.adjusted_mode;
5791 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5792 int pipe = intel_crtc->pipe;
5793 int plane = intel_crtc->plane;
5794 int num_connectors = 0;
5795 bool is_cpu_edp = false;
5796 struct intel_encoder *encoder;
5797 int ret;
5798 bool dither;
5799
5800 for_each_encoder_on_crtc(dev, crtc, encoder) {
5801 switch (encoder->type) {
5802 case INTEL_OUTPUT_EDP:
5803 if (!intel_encoder_is_pch_edp(&encoder->base))
5804 is_cpu_edp = true;
5805 break;
5806 }
5807
5808 num_connectors++;
5809 }
5810
5811 if (is_cpu_edp)
5812 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5813 else
5814 intel_crtc->config.cpu_transcoder = pipe;
5815
5816 /* We are not sure yet this won't happen. */
5817 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5818 INTEL_PCH_TYPE(dev));
5819
5820 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5821 num_connectors, pipe_name(pipe));
5822
5823 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5824 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5825
5826 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5827
5828 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5829 return -EINVAL;
5830
5831 /* Ensure that the cursor is valid for the new mode before changing... */
5832 intel_crtc_update_cursor(crtc, true);
5833
5834 /* determine panel color depth */
5835 dither = intel_crtc->config.dither;
5836
5837 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5838 drm_mode_debug_printmodeline(mode);
5839
5840 if (intel_crtc->config.has_dp_encoder)
5841 intel_dp_set_m_n(intel_crtc);
5842
5843 intel_crtc->lowfreq_avail = false;
5844
5845 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5846
5847 if (intel_crtc->config.has_pch_encoder)
5848 ironlake_fdi_set_m_n(crtc);
5849
5850 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5851
5852 intel_set_pipe_csc(crtc);
5853
5854 /* Set up the display plane register */
5855 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5856 POSTING_READ(DSPCNTR(plane));
5857
5858 ret = intel_pipe_set_base(crtc, x, y, fb);
5859
5860 intel_update_watermarks(dev);
5861
5862 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5863
5864 return ret;
5865 }
5866
5867 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5868 struct intel_crtc_config *pipe_config)
5869 {
5870 struct drm_device *dev = crtc->base.dev;
5871 struct drm_i915_private *dev_priv = dev->dev_private;
5872 uint32_t tmp;
5873
5874 tmp = I915_READ(PIPECONF(crtc->config.cpu_transcoder));
5875 if (!(tmp & PIPECONF_ENABLE))
5876 return false;
5877
5878 /*
5879 * aswell has only FDI/PCH transcoder A. It is which is connected to
5880 * DDI E. So just check whether this pipe is wired to DDI E and whether
5881 * the PCH transcoder is on.
5882 */
5883 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
5884 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5885 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5886 pipe_config->has_pch_encoder = true;
5887
5888
5889 return true;
5890 }
5891
5892 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5893 int x, int y,
5894 struct drm_framebuffer *fb)
5895 {
5896 struct drm_device *dev = crtc->dev;
5897 struct drm_i915_private *dev_priv = dev->dev_private;
5898 struct drm_encoder_helper_funcs *encoder_funcs;
5899 struct intel_encoder *encoder;
5900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5901 struct drm_display_mode *adjusted_mode =
5902 &intel_crtc->config.adjusted_mode;
5903 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5904 int pipe = intel_crtc->pipe;
5905 int ret;
5906
5907 drm_vblank_pre_modeset(dev, pipe);
5908
5909 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5910
5911 drm_vblank_post_modeset(dev, pipe);
5912
5913 if (ret != 0)
5914 return ret;
5915
5916 for_each_encoder_on_crtc(dev, crtc, encoder) {
5917 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5918 encoder->base.base.id,
5919 drm_get_encoder_name(&encoder->base),
5920 mode->base.id, mode->name);
5921 if (encoder->mode_set) {
5922 encoder->mode_set(encoder);
5923 } else {
5924 encoder_funcs = encoder->base.helper_private;
5925 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5926 }
5927 }
5928
5929 return 0;
5930 }
5931
5932 static bool intel_eld_uptodate(struct drm_connector *connector,
5933 int reg_eldv, uint32_t bits_eldv,
5934 int reg_elda, uint32_t bits_elda,
5935 int reg_edid)
5936 {
5937 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5938 uint8_t *eld = connector->eld;
5939 uint32_t i;
5940
5941 i = I915_READ(reg_eldv);
5942 i &= bits_eldv;
5943
5944 if (!eld[0])
5945 return !i;
5946
5947 if (!i)
5948 return false;
5949
5950 i = I915_READ(reg_elda);
5951 i &= ~bits_elda;
5952 I915_WRITE(reg_elda, i);
5953
5954 for (i = 0; i < eld[2]; i++)
5955 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5956 return false;
5957
5958 return true;
5959 }
5960
5961 static void g4x_write_eld(struct drm_connector *connector,
5962 struct drm_crtc *crtc)
5963 {
5964 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5965 uint8_t *eld = connector->eld;
5966 uint32_t eldv;
5967 uint32_t len;
5968 uint32_t i;
5969
5970 i = I915_READ(G4X_AUD_VID_DID);
5971
5972 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5973 eldv = G4X_ELDV_DEVCL_DEVBLC;
5974 else
5975 eldv = G4X_ELDV_DEVCTG;
5976
5977 if (intel_eld_uptodate(connector,
5978 G4X_AUD_CNTL_ST, eldv,
5979 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5980 G4X_HDMIW_HDMIEDID))
5981 return;
5982
5983 i = I915_READ(G4X_AUD_CNTL_ST);
5984 i &= ~(eldv | G4X_ELD_ADDR);
5985 len = (i >> 9) & 0x1f; /* ELD buffer size */
5986 I915_WRITE(G4X_AUD_CNTL_ST, i);
5987
5988 if (!eld[0])
5989 return;
5990
5991 len = min_t(uint8_t, eld[2], len);
5992 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5993 for (i = 0; i < len; i++)
5994 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5995
5996 i = I915_READ(G4X_AUD_CNTL_ST);
5997 i |= eldv;
5998 I915_WRITE(G4X_AUD_CNTL_ST, i);
5999 }
6000
6001 static void haswell_write_eld(struct drm_connector *connector,
6002 struct drm_crtc *crtc)
6003 {
6004 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6005 uint8_t *eld = connector->eld;
6006 struct drm_device *dev = crtc->dev;
6007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6008 uint32_t eldv;
6009 uint32_t i;
6010 int len;
6011 int pipe = to_intel_crtc(crtc)->pipe;
6012 int tmp;
6013
6014 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6015 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6016 int aud_config = HSW_AUD_CFG(pipe);
6017 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6018
6019
6020 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6021
6022 /* Audio output enable */
6023 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6024 tmp = I915_READ(aud_cntrl_st2);
6025 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6026 I915_WRITE(aud_cntrl_st2, tmp);
6027
6028 /* Wait for 1 vertical blank */
6029 intel_wait_for_vblank(dev, pipe);
6030
6031 /* Set ELD valid state */
6032 tmp = I915_READ(aud_cntrl_st2);
6033 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6034 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6035 I915_WRITE(aud_cntrl_st2, tmp);
6036 tmp = I915_READ(aud_cntrl_st2);
6037 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6038
6039 /* Enable HDMI mode */
6040 tmp = I915_READ(aud_config);
6041 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6042 /* clear N_programing_enable and N_value_index */
6043 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6044 I915_WRITE(aud_config, tmp);
6045
6046 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6047
6048 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6049 intel_crtc->eld_vld = true;
6050
6051 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6052 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6053 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6054 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6055 } else
6056 I915_WRITE(aud_config, 0);
6057
6058 if (intel_eld_uptodate(connector,
6059 aud_cntrl_st2, eldv,
6060 aud_cntl_st, IBX_ELD_ADDRESS,
6061 hdmiw_hdmiedid))
6062 return;
6063
6064 i = I915_READ(aud_cntrl_st2);
6065 i &= ~eldv;
6066 I915_WRITE(aud_cntrl_st2, i);
6067
6068 if (!eld[0])
6069 return;
6070
6071 i = I915_READ(aud_cntl_st);
6072 i &= ~IBX_ELD_ADDRESS;
6073 I915_WRITE(aud_cntl_st, i);
6074 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6075 DRM_DEBUG_DRIVER("port num:%d\n", i);
6076
6077 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6078 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6079 for (i = 0; i < len; i++)
6080 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6081
6082 i = I915_READ(aud_cntrl_st2);
6083 i |= eldv;
6084 I915_WRITE(aud_cntrl_st2, i);
6085
6086 }
6087
6088 static void ironlake_write_eld(struct drm_connector *connector,
6089 struct drm_crtc *crtc)
6090 {
6091 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6092 uint8_t *eld = connector->eld;
6093 uint32_t eldv;
6094 uint32_t i;
6095 int len;
6096 int hdmiw_hdmiedid;
6097 int aud_config;
6098 int aud_cntl_st;
6099 int aud_cntrl_st2;
6100 int pipe = to_intel_crtc(crtc)->pipe;
6101
6102 if (HAS_PCH_IBX(connector->dev)) {
6103 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6104 aud_config = IBX_AUD_CFG(pipe);
6105 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6106 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6107 } else {
6108 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6109 aud_config = CPT_AUD_CFG(pipe);
6110 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6111 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6112 }
6113
6114 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6115
6116 i = I915_READ(aud_cntl_st);
6117 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6118 if (!i) {
6119 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6120 /* operate blindly on all ports */
6121 eldv = IBX_ELD_VALIDB;
6122 eldv |= IBX_ELD_VALIDB << 4;
6123 eldv |= IBX_ELD_VALIDB << 8;
6124 } else {
6125 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6126 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6127 }
6128
6129 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6130 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6131 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6132 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6133 } else
6134 I915_WRITE(aud_config, 0);
6135
6136 if (intel_eld_uptodate(connector,
6137 aud_cntrl_st2, eldv,
6138 aud_cntl_st, IBX_ELD_ADDRESS,
6139 hdmiw_hdmiedid))
6140 return;
6141
6142 i = I915_READ(aud_cntrl_st2);
6143 i &= ~eldv;
6144 I915_WRITE(aud_cntrl_st2, i);
6145
6146 if (!eld[0])
6147 return;
6148
6149 i = I915_READ(aud_cntl_st);
6150 i &= ~IBX_ELD_ADDRESS;
6151 I915_WRITE(aud_cntl_st, i);
6152
6153 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6154 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6155 for (i = 0; i < len; i++)
6156 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6157
6158 i = I915_READ(aud_cntrl_st2);
6159 i |= eldv;
6160 I915_WRITE(aud_cntrl_st2, i);
6161 }
6162
6163 void intel_write_eld(struct drm_encoder *encoder,
6164 struct drm_display_mode *mode)
6165 {
6166 struct drm_crtc *crtc = encoder->crtc;
6167 struct drm_connector *connector;
6168 struct drm_device *dev = encoder->dev;
6169 struct drm_i915_private *dev_priv = dev->dev_private;
6170
6171 connector = drm_select_eld(encoder, mode);
6172 if (!connector)
6173 return;
6174
6175 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6176 connector->base.id,
6177 drm_get_connector_name(connector),
6178 connector->encoder->base.id,
6179 drm_get_encoder_name(connector->encoder));
6180
6181 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6182
6183 if (dev_priv->display.write_eld)
6184 dev_priv->display.write_eld(connector, crtc);
6185 }
6186
6187 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6188 void intel_crtc_load_lut(struct drm_crtc *crtc)
6189 {
6190 struct drm_device *dev = crtc->dev;
6191 struct drm_i915_private *dev_priv = dev->dev_private;
6192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6193 int palreg = PALETTE(intel_crtc->pipe);
6194 int i;
6195
6196 /* The clocks have to be on to load the palette. */
6197 if (!crtc->enabled || !intel_crtc->active)
6198 return;
6199
6200 /* use legacy palette for Ironlake */
6201 if (HAS_PCH_SPLIT(dev))
6202 palreg = LGC_PALETTE(intel_crtc->pipe);
6203
6204 for (i = 0; i < 256; i++) {
6205 I915_WRITE(palreg + 4 * i,
6206 (intel_crtc->lut_r[i] << 16) |
6207 (intel_crtc->lut_g[i] << 8) |
6208 intel_crtc->lut_b[i]);
6209 }
6210 }
6211
6212 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6213 {
6214 struct drm_device *dev = crtc->dev;
6215 struct drm_i915_private *dev_priv = dev->dev_private;
6216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6217 bool visible = base != 0;
6218 u32 cntl;
6219
6220 if (intel_crtc->cursor_visible == visible)
6221 return;
6222
6223 cntl = I915_READ(_CURACNTR);
6224 if (visible) {
6225 /* On these chipsets we can only modify the base whilst
6226 * the cursor is disabled.
6227 */
6228 I915_WRITE(_CURABASE, base);
6229
6230 cntl &= ~(CURSOR_FORMAT_MASK);
6231 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6232 cntl |= CURSOR_ENABLE |
6233 CURSOR_GAMMA_ENABLE |
6234 CURSOR_FORMAT_ARGB;
6235 } else
6236 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6237 I915_WRITE(_CURACNTR, cntl);
6238
6239 intel_crtc->cursor_visible = visible;
6240 }
6241
6242 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6243 {
6244 struct drm_device *dev = crtc->dev;
6245 struct drm_i915_private *dev_priv = dev->dev_private;
6246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6247 int pipe = intel_crtc->pipe;
6248 bool visible = base != 0;
6249
6250 if (intel_crtc->cursor_visible != visible) {
6251 uint32_t cntl = I915_READ(CURCNTR(pipe));
6252 if (base) {
6253 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6254 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6255 cntl |= pipe << 28; /* Connect to correct pipe */
6256 } else {
6257 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6258 cntl |= CURSOR_MODE_DISABLE;
6259 }
6260 I915_WRITE(CURCNTR(pipe), cntl);
6261
6262 intel_crtc->cursor_visible = visible;
6263 }
6264 /* and commit changes on next vblank */
6265 POSTING_READ(CURCNTR(pipe));
6266 I915_WRITE(CURBASE(pipe), base);
6267 POSTING_READ(CURBASE(pipe));
6268 }
6269
6270 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6271 {
6272 struct drm_device *dev = crtc->dev;
6273 struct drm_i915_private *dev_priv = dev->dev_private;
6274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6275 int pipe = intel_crtc->pipe;
6276 bool visible = base != 0;
6277
6278 if (intel_crtc->cursor_visible != visible) {
6279 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6280 if (base) {
6281 cntl &= ~CURSOR_MODE;
6282 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6283 } else {
6284 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6285 cntl |= CURSOR_MODE_DISABLE;
6286 }
6287 if (IS_HASWELL(dev))
6288 cntl |= CURSOR_PIPE_CSC_ENABLE;
6289 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6290
6291 intel_crtc->cursor_visible = visible;
6292 }
6293 /* and commit changes on next vblank */
6294 POSTING_READ(CURCNTR_IVB(pipe));
6295 I915_WRITE(CURBASE_IVB(pipe), base);
6296 POSTING_READ(CURBASE_IVB(pipe));
6297 }
6298
6299 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6300 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6301 bool on)
6302 {
6303 struct drm_device *dev = crtc->dev;
6304 struct drm_i915_private *dev_priv = dev->dev_private;
6305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6306 int pipe = intel_crtc->pipe;
6307 int x = intel_crtc->cursor_x;
6308 int y = intel_crtc->cursor_y;
6309 u32 base, pos;
6310 bool visible;
6311
6312 pos = 0;
6313
6314 if (on && crtc->enabled && crtc->fb) {
6315 base = intel_crtc->cursor_addr;
6316 if (x > (int) crtc->fb->width)
6317 base = 0;
6318
6319 if (y > (int) crtc->fb->height)
6320 base = 0;
6321 } else
6322 base = 0;
6323
6324 if (x < 0) {
6325 if (x + intel_crtc->cursor_width < 0)
6326 base = 0;
6327
6328 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6329 x = -x;
6330 }
6331 pos |= x << CURSOR_X_SHIFT;
6332
6333 if (y < 0) {
6334 if (y + intel_crtc->cursor_height < 0)
6335 base = 0;
6336
6337 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6338 y = -y;
6339 }
6340 pos |= y << CURSOR_Y_SHIFT;
6341
6342 visible = base != 0;
6343 if (!visible && !intel_crtc->cursor_visible)
6344 return;
6345
6346 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6347 I915_WRITE(CURPOS_IVB(pipe), pos);
6348 ivb_update_cursor(crtc, base);
6349 } else {
6350 I915_WRITE(CURPOS(pipe), pos);
6351 if (IS_845G(dev) || IS_I865G(dev))
6352 i845_update_cursor(crtc, base);
6353 else
6354 i9xx_update_cursor(crtc, base);
6355 }
6356 }
6357
6358 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6359 struct drm_file *file,
6360 uint32_t handle,
6361 uint32_t width, uint32_t height)
6362 {
6363 struct drm_device *dev = crtc->dev;
6364 struct drm_i915_private *dev_priv = dev->dev_private;
6365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6366 struct drm_i915_gem_object *obj;
6367 uint32_t addr;
6368 int ret;
6369
6370 /* if we want to turn off the cursor ignore width and height */
6371 if (!handle) {
6372 DRM_DEBUG_KMS("cursor off\n");
6373 addr = 0;
6374 obj = NULL;
6375 mutex_lock(&dev->struct_mutex);
6376 goto finish;
6377 }
6378
6379 /* Currently we only support 64x64 cursors */
6380 if (width != 64 || height != 64) {
6381 DRM_ERROR("we currently only support 64x64 cursors\n");
6382 return -EINVAL;
6383 }
6384
6385 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6386 if (&obj->base == NULL)
6387 return -ENOENT;
6388
6389 if (obj->base.size < width * height * 4) {
6390 DRM_ERROR("buffer is to small\n");
6391 ret = -ENOMEM;
6392 goto fail;
6393 }
6394
6395 /* we only need to pin inside GTT if cursor is non-phy */
6396 mutex_lock(&dev->struct_mutex);
6397 if (!dev_priv->info->cursor_needs_physical) {
6398 unsigned alignment;
6399
6400 if (obj->tiling_mode) {
6401 DRM_ERROR("cursor cannot be tiled\n");
6402 ret = -EINVAL;
6403 goto fail_locked;
6404 }
6405
6406 /* Note that the w/a also requires 2 PTE of padding following
6407 * the bo. We currently fill all unused PTE with the shadow
6408 * page and so we should always have valid PTE following the
6409 * cursor preventing the VT-d warning.
6410 */
6411 alignment = 0;
6412 if (need_vtd_wa(dev))
6413 alignment = 64*1024;
6414
6415 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6416 if (ret) {
6417 DRM_ERROR("failed to move cursor bo into the GTT\n");
6418 goto fail_locked;
6419 }
6420
6421 ret = i915_gem_object_put_fence(obj);
6422 if (ret) {
6423 DRM_ERROR("failed to release fence for cursor");
6424 goto fail_unpin;
6425 }
6426
6427 addr = obj->gtt_offset;
6428 } else {
6429 int align = IS_I830(dev) ? 16 * 1024 : 256;
6430 ret = i915_gem_attach_phys_object(dev, obj,
6431 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6432 align);
6433 if (ret) {
6434 DRM_ERROR("failed to attach phys object\n");
6435 goto fail_locked;
6436 }
6437 addr = obj->phys_obj->handle->busaddr;
6438 }
6439
6440 if (IS_GEN2(dev))
6441 I915_WRITE(CURSIZE, (height << 12) | width);
6442
6443 finish:
6444 if (intel_crtc->cursor_bo) {
6445 if (dev_priv->info->cursor_needs_physical) {
6446 if (intel_crtc->cursor_bo != obj)
6447 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6448 } else
6449 i915_gem_object_unpin(intel_crtc->cursor_bo);
6450 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6451 }
6452
6453 mutex_unlock(&dev->struct_mutex);
6454
6455 intel_crtc->cursor_addr = addr;
6456 intel_crtc->cursor_bo = obj;
6457 intel_crtc->cursor_width = width;
6458 intel_crtc->cursor_height = height;
6459
6460 intel_crtc_update_cursor(crtc, true);
6461
6462 return 0;
6463 fail_unpin:
6464 i915_gem_object_unpin(obj);
6465 fail_locked:
6466 mutex_unlock(&dev->struct_mutex);
6467 fail:
6468 drm_gem_object_unreference_unlocked(&obj->base);
6469 return ret;
6470 }
6471
6472 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6473 {
6474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6475
6476 intel_crtc->cursor_x = x;
6477 intel_crtc->cursor_y = y;
6478
6479 intel_crtc_update_cursor(crtc, true);
6480
6481 return 0;
6482 }
6483
6484 /** Sets the color ramps on behalf of RandR */
6485 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6486 u16 blue, int regno)
6487 {
6488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6489
6490 intel_crtc->lut_r[regno] = red >> 8;
6491 intel_crtc->lut_g[regno] = green >> 8;
6492 intel_crtc->lut_b[regno] = blue >> 8;
6493 }
6494
6495 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6496 u16 *blue, int regno)
6497 {
6498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6499
6500 *red = intel_crtc->lut_r[regno] << 8;
6501 *green = intel_crtc->lut_g[regno] << 8;
6502 *blue = intel_crtc->lut_b[regno] << 8;
6503 }
6504
6505 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6506 u16 *blue, uint32_t start, uint32_t size)
6507 {
6508 int end = (start + size > 256) ? 256 : start + size, i;
6509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6510
6511 for (i = start; i < end; i++) {
6512 intel_crtc->lut_r[i] = red[i] >> 8;
6513 intel_crtc->lut_g[i] = green[i] >> 8;
6514 intel_crtc->lut_b[i] = blue[i] >> 8;
6515 }
6516
6517 intel_crtc_load_lut(crtc);
6518 }
6519
6520 /* VESA 640x480x72Hz mode to set on the pipe */
6521 static struct drm_display_mode load_detect_mode = {
6522 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6523 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6524 };
6525
6526 static struct drm_framebuffer *
6527 intel_framebuffer_create(struct drm_device *dev,
6528 struct drm_mode_fb_cmd2 *mode_cmd,
6529 struct drm_i915_gem_object *obj)
6530 {
6531 struct intel_framebuffer *intel_fb;
6532 int ret;
6533
6534 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6535 if (!intel_fb) {
6536 drm_gem_object_unreference_unlocked(&obj->base);
6537 return ERR_PTR(-ENOMEM);
6538 }
6539
6540 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6541 if (ret) {
6542 drm_gem_object_unreference_unlocked(&obj->base);
6543 kfree(intel_fb);
6544 return ERR_PTR(ret);
6545 }
6546
6547 return &intel_fb->base;
6548 }
6549
6550 static u32
6551 intel_framebuffer_pitch_for_width(int width, int bpp)
6552 {
6553 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6554 return ALIGN(pitch, 64);
6555 }
6556
6557 static u32
6558 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6559 {
6560 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6561 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6562 }
6563
6564 static struct drm_framebuffer *
6565 intel_framebuffer_create_for_mode(struct drm_device *dev,
6566 struct drm_display_mode *mode,
6567 int depth, int bpp)
6568 {
6569 struct drm_i915_gem_object *obj;
6570 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6571
6572 obj = i915_gem_alloc_object(dev,
6573 intel_framebuffer_size_for_mode(mode, bpp));
6574 if (obj == NULL)
6575 return ERR_PTR(-ENOMEM);
6576
6577 mode_cmd.width = mode->hdisplay;
6578 mode_cmd.height = mode->vdisplay;
6579 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6580 bpp);
6581 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6582
6583 return intel_framebuffer_create(dev, &mode_cmd, obj);
6584 }
6585
6586 static struct drm_framebuffer *
6587 mode_fits_in_fbdev(struct drm_device *dev,
6588 struct drm_display_mode *mode)
6589 {
6590 struct drm_i915_private *dev_priv = dev->dev_private;
6591 struct drm_i915_gem_object *obj;
6592 struct drm_framebuffer *fb;
6593
6594 if (dev_priv->fbdev == NULL)
6595 return NULL;
6596
6597 obj = dev_priv->fbdev->ifb.obj;
6598 if (obj == NULL)
6599 return NULL;
6600
6601 fb = &dev_priv->fbdev->ifb.base;
6602 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6603 fb->bits_per_pixel))
6604 return NULL;
6605
6606 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6607 return NULL;
6608
6609 return fb;
6610 }
6611
6612 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6613 struct drm_display_mode *mode,
6614 struct intel_load_detect_pipe *old)
6615 {
6616 struct intel_crtc *intel_crtc;
6617 struct intel_encoder *intel_encoder =
6618 intel_attached_encoder(connector);
6619 struct drm_crtc *possible_crtc;
6620 struct drm_encoder *encoder = &intel_encoder->base;
6621 struct drm_crtc *crtc = NULL;
6622 struct drm_device *dev = encoder->dev;
6623 struct drm_framebuffer *fb;
6624 int i = -1;
6625
6626 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6627 connector->base.id, drm_get_connector_name(connector),
6628 encoder->base.id, drm_get_encoder_name(encoder));
6629
6630 /*
6631 * Algorithm gets a little messy:
6632 *
6633 * - if the connector already has an assigned crtc, use it (but make
6634 * sure it's on first)
6635 *
6636 * - try to find the first unused crtc that can drive this connector,
6637 * and use that if we find one
6638 */
6639
6640 /* See if we already have a CRTC for this connector */
6641 if (encoder->crtc) {
6642 crtc = encoder->crtc;
6643
6644 mutex_lock(&crtc->mutex);
6645
6646 old->dpms_mode = connector->dpms;
6647 old->load_detect_temp = false;
6648
6649 /* Make sure the crtc and connector are running */
6650 if (connector->dpms != DRM_MODE_DPMS_ON)
6651 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6652
6653 return true;
6654 }
6655
6656 /* Find an unused one (if possible) */
6657 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6658 i++;
6659 if (!(encoder->possible_crtcs & (1 << i)))
6660 continue;
6661 if (!possible_crtc->enabled) {
6662 crtc = possible_crtc;
6663 break;
6664 }
6665 }
6666
6667 /*
6668 * If we didn't find an unused CRTC, don't use any.
6669 */
6670 if (!crtc) {
6671 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6672 return false;
6673 }
6674
6675 mutex_lock(&crtc->mutex);
6676 intel_encoder->new_crtc = to_intel_crtc(crtc);
6677 to_intel_connector(connector)->new_encoder = intel_encoder;
6678
6679 intel_crtc = to_intel_crtc(crtc);
6680 old->dpms_mode = connector->dpms;
6681 old->load_detect_temp = true;
6682 old->release_fb = NULL;
6683
6684 if (!mode)
6685 mode = &load_detect_mode;
6686
6687 /* We need a framebuffer large enough to accommodate all accesses
6688 * that the plane may generate whilst we perform load detection.
6689 * We can not rely on the fbcon either being present (we get called
6690 * during its initialisation to detect all boot displays, or it may
6691 * not even exist) or that it is large enough to satisfy the
6692 * requested mode.
6693 */
6694 fb = mode_fits_in_fbdev(dev, mode);
6695 if (fb == NULL) {
6696 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6697 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6698 old->release_fb = fb;
6699 } else
6700 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6701 if (IS_ERR(fb)) {
6702 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6703 mutex_unlock(&crtc->mutex);
6704 return false;
6705 }
6706
6707 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6708 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6709 if (old->release_fb)
6710 old->release_fb->funcs->destroy(old->release_fb);
6711 mutex_unlock(&crtc->mutex);
6712 return false;
6713 }
6714
6715 /* let the connector get through one full cycle before testing */
6716 intel_wait_for_vblank(dev, intel_crtc->pipe);
6717 return true;
6718 }
6719
6720 void intel_release_load_detect_pipe(struct drm_connector *connector,
6721 struct intel_load_detect_pipe *old)
6722 {
6723 struct intel_encoder *intel_encoder =
6724 intel_attached_encoder(connector);
6725 struct drm_encoder *encoder = &intel_encoder->base;
6726 struct drm_crtc *crtc = encoder->crtc;
6727
6728 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6729 connector->base.id, drm_get_connector_name(connector),
6730 encoder->base.id, drm_get_encoder_name(encoder));
6731
6732 if (old->load_detect_temp) {
6733 to_intel_connector(connector)->new_encoder = NULL;
6734 intel_encoder->new_crtc = NULL;
6735 intel_set_mode(crtc, NULL, 0, 0, NULL);
6736
6737 if (old->release_fb) {
6738 drm_framebuffer_unregister_private(old->release_fb);
6739 drm_framebuffer_unreference(old->release_fb);
6740 }
6741
6742 mutex_unlock(&crtc->mutex);
6743 return;
6744 }
6745
6746 /* Switch crtc and encoder back off if necessary */
6747 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6748 connector->funcs->dpms(connector, old->dpms_mode);
6749
6750 mutex_unlock(&crtc->mutex);
6751 }
6752
6753 /* Returns the clock of the currently programmed mode of the given pipe. */
6754 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6755 {
6756 struct drm_i915_private *dev_priv = dev->dev_private;
6757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6758 int pipe = intel_crtc->pipe;
6759 u32 dpll = I915_READ(DPLL(pipe));
6760 u32 fp;
6761 intel_clock_t clock;
6762
6763 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6764 fp = I915_READ(FP0(pipe));
6765 else
6766 fp = I915_READ(FP1(pipe));
6767
6768 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6769 if (IS_PINEVIEW(dev)) {
6770 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6771 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6772 } else {
6773 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6774 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6775 }
6776
6777 if (!IS_GEN2(dev)) {
6778 if (IS_PINEVIEW(dev))
6779 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6780 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6781 else
6782 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6783 DPLL_FPA01_P1_POST_DIV_SHIFT);
6784
6785 switch (dpll & DPLL_MODE_MASK) {
6786 case DPLLB_MODE_DAC_SERIAL:
6787 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6788 5 : 10;
6789 break;
6790 case DPLLB_MODE_LVDS:
6791 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6792 7 : 14;
6793 break;
6794 default:
6795 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6796 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6797 return 0;
6798 }
6799
6800 /* XXX: Handle the 100Mhz refclk */
6801 intel_clock(dev, 96000, &clock);
6802 } else {
6803 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6804
6805 if (is_lvds) {
6806 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6807 DPLL_FPA01_P1_POST_DIV_SHIFT);
6808 clock.p2 = 14;
6809
6810 if ((dpll & PLL_REF_INPUT_MASK) ==
6811 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6812 /* XXX: might not be 66MHz */
6813 intel_clock(dev, 66000, &clock);
6814 } else
6815 intel_clock(dev, 48000, &clock);
6816 } else {
6817 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6818 clock.p1 = 2;
6819 else {
6820 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6821 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6822 }
6823 if (dpll & PLL_P2_DIVIDE_BY_4)
6824 clock.p2 = 4;
6825 else
6826 clock.p2 = 2;
6827
6828 intel_clock(dev, 48000, &clock);
6829 }
6830 }
6831
6832 /* XXX: It would be nice to validate the clocks, but we can't reuse
6833 * i830PllIsValid() because it relies on the xf86_config connector
6834 * configuration being accurate, which it isn't necessarily.
6835 */
6836
6837 return clock.dot;
6838 }
6839
6840 /** Returns the currently programmed mode of the given pipe. */
6841 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6842 struct drm_crtc *crtc)
6843 {
6844 struct drm_i915_private *dev_priv = dev->dev_private;
6845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6846 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6847 struct drm_display_mode *mode;
6848 int htot = I915_READ(HTOTAL(cpu_transcoder));
6849 int hsync = I915_READ(HSYNC(cpu_transcoder));
6850 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6851 int vsync = I915_READ(VSYNC(cpu_transcoder));
6852
6853 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6854 if (!mode)
6855 return NULL;
6856
6857 mode->clock = intel_crtc_clock_get(dev, crtc);
6858 mode->hdisplay = (htot & 0xffff) + 1;
6859 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6860 mode->hsync_start = (hsync & 0xffff) + 1;
6861 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6862 mode->vdisplay = (vtot & 0xffff) + 1;
6863 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6864 mode->vsync_start = (vsync & 0xffff) + 1;
6865 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6866
6867 drm_mode_set_name(mode);
6868
6869 return mode;
6870 }
6871
6872 static void intel_increase_pllclock(struct drm_crtc *crtc)
6873 {
6874 struct drm_device *dev = crtc->dev;
6875 drm_i915_private_t *dev_priv = dev->dev_private;
6876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6877 int pipe = intel_crtc->pipe;
6878 int dpll_reg = DPLL(pipe);
6879 int dpll;
6880
6881 if (HAS_PCH_SPLIT(dev))
6882 return;
6883
6884 if (!dev_priv->lvds_downclock_avail)
6885 return;
6886
6887 dpll = I915_READ(dpll_reg);
6888 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6889 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6890
6891 assert_panel_unlocked(dev_priv, pipe);
6892
6893 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6894 I915_WRITE(dpll_reg, dpll);
6895 intel_wait_for_vblank(dev, pipe);
6896
6897 dpll = I915_READ(dpll_reg);
6898 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6899 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6900 }
6901 }
6902
6903 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6904 {
6905 struct drm_device *dev = crtc->dev;
6906 drm_i915_private_t *dev_priv = dev->dev_private;
6907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6908
6909 if (HAS_PCH_SPLIT(dev))
6910 return;
6911
6912 if (!dev_priv->lvds_downclock_avail)
6913 return;
6914
6915 /*
6916 * Since this is called by a timer, we should never get here in
6917 * the manual case.
6918 */
6919 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6920 int pipe = intel_crtc->pipe;
6921 int dpll_reg = DPLL(pipe);
6922 int dpll;
6923
6924 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6925
6926 assert_panel_unlocked(dev_priv, pipe);
6927
6928 dpll = I915_READ(dpll_reg);
6929 dpll |= DISPLAY_RATE_SELECT_FPA1;
6930 I915_WRITE(dpll_reg, dpll);
6931 intel_wait_for_vblank(dev, pipe);
6932 dpll = I915_READ(dpll_reg);
6933 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6934 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6935 }
6936
6937 }
6938
6939 void intel_mark_busy(struct drm_device *dev)
6940 {
6941 i915_update_gfx_val(dev->dev_private);
6942 }
6943
6944 void intel_mark_idle(struct drm_device *dev)
6945 {
6946 struct drm_crtc *crtc;
6947
6948 if (!i915_powersave)
6949 return;
6950
6951 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6952 if (!crtc->fb)
6953 continue;
6954
6955 intel_decrease_pllclock(crtc);
6956 }
6957 }
6958
6959 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6960 {
6961 struct drm_device *dev = obj->base.dev;
6962 struct drm_crtc *crtc;
6963
6964 if (!i915_powersave)
6965 return;
6966
6967 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6968 if (!crtc->fb)
6969 continue;
6970
6971 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6972 intel_increase_pllclock(crtc);
6973 }
6974 }
6975
6976 static void intel_crtc_destroy(struct drm_crtc *crtc)
6977 {
6978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6979 struct drm_device *dev = crtc->dev;
6980 struct intel_unpin_work *work;
6981 unsigned long flags;
6982
6983 spin_lock_irqsave(&dev->event_lock, flags);
6984 work = intel_crtc->unpin_work;
6985 intel_crtc->unpin_work = NULL;
6986 spin_unlock_irqrestore(&dev->event_lock, flags);
6987
6988 if (work) {
6989 cancel_work_sync(&work->work);
6990 kfree(work);
6991 }
6992
6993 drm_crtc_cleanup(crtc);
6994
6995 kfree(intel_crtc);
6996 }
6997
6998 static void intel_unpin_work_fn(struct work_struct *__work)
6999 {
7000 struct intel_unpin_work *work =
7001 container_of(__work, struct intel_unpin_work, work);
7002 struct drm_device *dev = work->crtc->dev;
7003
7004 mutex_lock(&dev->struct_mutex);
7005 intel_unpin_fb_obj(work->old_fb_obj);
7006 drm_gem_object_unreference(&work->pending_flip_obj->base);
7007 drm_gem_object_unreference(&work->old_fb_obj->base);
7008
7009 intel_update_fbc(dev);
7010 mutex_unlock(&dev->struct_mutex);
7011
7012 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7013 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7014
7015 kfree(work);
7016 }
7017
7018 static void do_intel_finish_page_flip(struct drm_device *dev,
7019 struct drm_crtc *crtc)
7020 {
7021 drm_i915_private_t *dev_priv = dev->dev_private;
7022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7023 struct intel_unpin_work *work;
7024 unsigned long flags;
7025
7026 /* Ignore early vblank irqs */
7027 if (intel_crtc == NULL)
7028 return;
7029
7030 spin_lock_irqsave(&dev->event_lock, flags);
7031 work = intel_crtc->unpin_work;
7032
7033 /* Ensure we don't miss a work->pending update ... */
7034 smp_rmb();
7035
7036 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7037 spin_unlock_irqrestore(&dev->event_lock, flags);
7038 return;
7039 }
7040
7041 /* and that the unpin work is consistent wrt ->pending. */
7042 smp_rmb();
7043
7044 intel_crtc->unpin_work = NULL;
7045
7046 if (work->event)
7047 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7048
7049 drm_vblank_put(dev, intel_crtc->pipe);
7050
7051 spin_unlock_irqrestore(&dev->event_lock, flags);
7052
7053 wake_up_all(&dev_priv->pending_flip_queue);
7054
7055 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7056
7057 queue_work(dev_priv->wq, &work->work);
7058 }
7059
7060 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7061 {
7062 drm_i915_private_t *dev_priv = dev->dev_private;
7063 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7064
7065 do_intel_finish_page_flip(dev, crtc);
7066 }
7067
7068 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7069 {
7070 drm_i915_private_t *dev_priv = dev->dev_private;
7071 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7072
7073 do_intel_finish_page_flip(dev, crtc);
7074 }
7075
7076 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7077 {
7078 drm_i915_private_t *dev_priv = dev->dev_private;
7079 struct intel_crtc *intel_crtc =
7080 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7081 unsigned long flags;
7082
7083 /* NB: An MMIO update of the plane base pointer will also
7084 * generate a page-flip completion irq, i.e. every modeset
7085 * is also accompanied by a spurious intel_prepare_page_flip().
7086 */
7087 spin_lock_irqsave(&dev->event_lock, flags);
7088 if (intel_crtc->unpin_work)
7089 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7090 spin_unlock_irqrestore(&dev->event_lock, flags);
7091 }
7092
7093 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7094 {
7095 /* Ensure that the work item is consistent when activating it ... */
7096 smp_wmb();
7097 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7098 /* and that it is marked active as soon as the irq could fire. */
7099 smp_wmb();
7100 }
7101
7102 static int intel_gen2_queue_flip(struct drm_device *dev,
7103 struct drm_crtc *crtc,
7104 struct drm_framebuffer *fb,
7105 struct drm_i915_gem_object *obj)
7106 {
7107 struct drm_i915_private *dev_priv = dev->dev_private;
7108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7109 u32 flip_mask;
7110 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7111 int ret;
7112
7113 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7114 if (ret)
7115 goto err;
7116
7117 ret = intel_ring_begin(ring, 6);
7118 if (ret)
7119 goto err_unpin;
7120
7121 /* Can't queue multiple flips, so wait for the previous
7122 * one to finish before executing the next.
7123 */
7124 if (intel_crtc->plane)
7125 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7126 else
7127 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7128 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7129 intel_ring_emit(ring, MI_NOOP);
7130 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7131 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7132 intel_ring_emit(ring, fb->pitches[0]);
7133 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7134 intel_ring_emit(ring, 0); /* aux display base address, unused */
7135
7136 intel_mark_page_flip_active(intel_crtc);
7137 intel_ring_advance(ring);
7138 return 0;
7139
7140 err_unpin:
7141 intel_unpin_fb_obj(obj);
7142 err:
7143 return ret;
7144 }
7145
7146 static int intel_gen3_queue_flip(struct drm_device *dev,
7147 struct drm_crtc *crtc,
7148 struct drm_framebuffer *fb,
7149 struct drm_i915_gem_object *obj)
7150 {
7151 struct drm_i915_private *dev_priv = dev->dev_private;
7152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7153 u32 flip_mask;
7154 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7155 int ret;
7156
7157 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7158 if (ret)
7159 goto err;
7160
7161 ret = intel_ring_begin(ring, 6);
7162 if (ret)
7163 goto err_unpin;
7164
7165 if (intel_crtc->plane)
7166 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7167 else
7168 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7169 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7170 intel_ring_emit(ring, MI_NOOP);
7171 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7172 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7173 intel_ring_emit(ring, fb->pitches[0]);
7174 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7175 intel_ring_emit(ring, MI_NOOP);
7176
7177 intel_mark_page_flip_active(intel_crtc);
7178 intel_ring_advance(ring);
7179 return 0;
7180
7181 err_unpin:
7182 intel_unpin_fb_obj(obj);
7183 err:
7184 return ret;
7185 }
7186
7187 static int intel_gen4_queue_flip(struct drm_device *dev,
7188 struct drm_crtc *crtc,
7189 struct drm_framebuffer *fb,
7190 struct drm_i915_gem_object *obj)
7191 {
7192 struct drm_i915_private *dev_priv = dev->dev_private;
7193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7194 uint32_t pf, pipesrc;
7195 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7196 int ret;
7197
7198 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7199 if (ret)
7200 goto err;
7201
7202 ret = intel_ring_begin(ring, 4);
7203 if (ret)
7204 goto err_unpin;
7205
7206 /* i965+ uses the linear or tiled offsets from the
7207 * Display Registers (which do not change across a page-flip)
7208 * so we need only reprogram the base address.
7209 */
7210 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7211 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7212 intel_ring_emit(ring, fb->pitches[0]);
7213 intel_ring_emit(ring,
7214 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7215 obj->tiling_mode);
7216
7217 /* XXX Enabling the panel-fitter across page-flip is so far
7218 * untested on non-native modes, so ignore it for now.
7219 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7220 */
7221 pf = 0;
7222 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7223 intel_ring_emit(ring, pf | pipesrc);
7224
7225 intel_mark_page_flip_active(intel_crtc);
7226 intel_ring_advance(ring);
7227 return 0;
7228
7229 err_unpin:
7230 intel_unpin_fb_obj(obj);
7231 err:
7232 return ret;
7233 }
7234
7235 static int intel_gen6_queue_flip(struct drm_device *dev,
7236 struct drm_crtc *crtc,
7237 struct drm_framebuffer *fb,
7238 struct drm_i915_gem_object *obj)
7239 {
7240 struct drm_i915_private *dev_priv = dev->dev_private;
7241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7242 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7243 uint32_t pf, pipesrc;
7244 int ret;
7245
7246 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7247 if (ret)
7248 goto err;
7249
7250 ret = intel_ring_begin(ring, 4);
7251 if (ret)
7252 goto err_unpin;
7253
7254 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7255 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7256 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7257 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7258
7259 /* Contrary to the suggestions in the documentation,
7260 * "Enable Panel Fitter" does not seem to be required when page
7261 * flipping with a non-native mode, and worse causes a normal
7262 * modeset to fail.
7263 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7264 */
7265 pf = 0;
7266 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7267 intel_ring_emit(ring, pf | pipesrc);
7268
7269 intel_mark_page_flip_active(intel_crtc);
7270 intel_ring_advance(ring);
7271 return 0;
7272
7273 err_unpin:
7274 intel_unpin_fb_obj(obj);
7275 err:
7276 return ret;
7277 }
7278
7279 /*
7280 * On gen7 we currently use the blit ring because (in early silicon at least)
7281 * the render ring doesn't give us interrpts for page flip completion, which
7282 * means clients will hang after the first flip is queued. Fortunately the
7283 * blit ring generates interrupts properly, so use it instead.
7284 */
7285 static int intel_gen7_queue_flip(struct drm_device *dev,
7286 struct drm_crtc *crtc,
7287 struct drm_framebuffer *fb,
7288 struct drm_i915_gem_object *obj)
7289 {
7290 struct drm_i915_private *dev_priv = dev->dev_private;
7291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7292 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7293 uint32_t plane_bit = 0;
7294 int ret;
7295
7296 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7297 if (ret)
7298 goto err;
7299
7300 switch(intel_crtc->plane) {
7301 case PLANE_A:
7302 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7303 break;
7304 case PLANE_B:
7305 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7306 break;
7307 case PLANE_C:
7308 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7309 break;
7310 default:
7311 WARN_ONCE(1, "unknown plane in flip command\n");
7312 ret = -ENODEV;
7313 goto err_unpin;
7314 }
7315
7316 ret = intel_ring_begin(ring, 4);
7317 if (ret)
7318 goto err_unpin;
7319
7320 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7321 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7322 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7323 intel_ring_emit(ring, (MI_NOOP));
7324
7325 intel_mark_page_flip_active(intel_crtc);
7326 intel_ring_advance(ring);
7327 return 0;
7328
7329 err_unpin:
7330 intel_unpin_fb_obj(obj);
7331 err:
7332 return ret;
7333 }
7334
7335 static int intel_default_queue_flip(struct drm_device *dev,
7336 struct drm_crtc *crtc,
7337 struct drm_framebuffer *fb,
7338 struct drm_i915_gem_object *obj)
7339 {
7340 return -ENODEV;
7341 }
7342
7343 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7344 struct drm_framebuffer *fb,
7345 struct drm_pending_vblank_event *event)
7346 {
7347 struct drm_device *dev = crtc->dev;
7348 struct drm_i915_private *dev_priv = dev->dev_private;
7349 struct drm_framebuffer *old_fb = crtc->fb;
7350 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7352 struct intel_unpin_work *work;
7353 unsigned long flags;
7354 int ret;
7355
7356 /* Can't change pixel format via MI display flips. */
7357 if (fb->pixel_format != crtc->fb->pixel_format)
7358 return -EINVAL;
7359
7360 /*
7361 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7362 * Note that pitch changes could also affect these register.
7363 */
7364 if (INTEL_INFO(dev)->gen > 3 &&
7365 (fb->offsets[0] != crtc->fb->offsets[0] ||
7366 fb->pitches[0] != crtc->fb->pitches[0]))
7367 return -EINVAL;
7368
7369 work = kzalloc(sizeof *work, GFP_KERNEL);
7370 if (work == NULL)
7371 return -ENOMEM;
7372
7373 work->event = event;
7374 work->crtc = crtc;
7375 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7376 INIT_WORK(&work->work, intel_unpin_work_fn);
7377
7378 ret = drm_vblank_get(dev, intel_crtc->pipe);
7379 if (ret)
7380 goto free_work;
7381
7382 /* We borrow the event spin lock for protecting unpin_work */
7383 spin_lock_irqsave(&dev->event_lock, flags);
7384 if (intel_crtc->unpin_work) {
7385 spin_unlock_irqrestore(&dev->event_lock, flags);
7386 kfree(work);
7387 drm_vblank_put(dev, intel_crtc->pipe);
7388
7389 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7390 return -EBUSY;
7391 }
7392 intel_crtc->unpin_work = work;
7393 spin_unlock_irqrestore(&dev->event_lock, flags);
7394
7395 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7396 flush_workqueue(dev_priv->wq);
7397
7398 ret = i915_mutex_lock_interruptible(dev);
7399 if (ret)
7400 goto cleanup;
7401
7402 /* Reference the objects for the scheduled work. */
7403 drm_gem_object_reference(&work->old_fb_obj->base);
7404 drm_gem_object_reference(&obj->base);
7405
7406 crtc->fb = fb;
7407
7408 work->pending_flip_obj = obj;
7409
7410 work->enable_stall_check = true;
7411
7412 atomic_inc(&intel_crtc->unpin_work_count);
7413 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7414
7415 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7416 if (ret)
7417 goto cleanup_pending;
7418
7419 intel_disable_fbc(dev);
7420 intel_mark_fb_busy(obj);
7421 mutex_unlock(&dev->struct_mutex);
7422
7423 trace_i915_flip_request(intel_crtc->plane, obj);
7424
7425 return 0;
7426
7427 cleanup_pending:
7428 atomic_dec(&intel_crtc->unpin_work_count);
7429 crtc->fb = old_fb;
7430 drm_gem_object_unreference(&work->old_fb_obj->base);
7431 drm_gem_object_unreference(&obj->base);
7432 mutex_unlock(&dev->struct_mutex);
7433
7434 cleanup:
7435 spin_lock_irqsave(&dev->event_lock, flags);
7436 intel_crtc->unpin_work = NULL;
7437 spin_unlock_irqrestore(&dev->event_lock, flags);
7438
7439 drm_vblank_put(dev, intel_crtc->pipe);
7440 free_work:
7441 kfree(work);
7442
7443 return ret;
7444 }
7445
7446 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7447 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7448 .load_lut = intel_crtc_load_lut,
7449 };
7450
7451 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7452 {
7453 struct intel_encoder *other_encoder;
7454 struct drm_crtc *crtc = &encoder->new_crtc->base;
7455
7456 if (WARN_ON(!crtc))
7457 return false;
7458
7459 list_for_each_entry(other_encoder,
7460 &crtc->dev->mode_config.encoder_list,
7461 base.head) {
7462
7463 if (&other_encoder->new_crtc->base != crtc ||
7464 encoder == other_encoder)
7465 continue;
7466 else
7467 return true;
7468 }
7469
7470 return false;
7471 }
7472
7473 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7474 struct drm_crtc *crtc)
7475 {
7476 struct drm_device *dev;
7477 struct drm_crtc *tmp;
7478 int crtc_mask = 1;
7479
7480 WARN(!crtc, "checking null crtc?\n");
7481
7482 dev = crtc->dev;
7483
7484 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7485 if (tmp == crtc)
7486 break;
7487 crtc_mask <<= 1;
7488 }
7489
7490 if (encoder->possible_crtcs & crtc_mask)
7491 return true;
7492 return false;
7493 }
7494
7495 /**
7496 * intel_modeset_update_staged_output_state
7497 *
7498 * Updates the staged output configuration state, e.g. after we've read out the
7499 * current hw state.
7500 */
7501 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7502 {
7503 struct intel_encoder *encoder;
7504 struct intel_connector *connector;
7505
7506 list_for_each_entry(connector, &dev->mode_config.connector_list,
7507 base.head) {
7508 connector->new_encoder =
7509 to_intel_encoder(connector->base.encoder);
7510 }
7511
7512 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7513 base.head) {
7514 encoder->new_crtc =
7515 to_intel_crtc(encoder->base.crtc);
7516 }
7517 }
7518
7519 /**
7520 * intel_modeset_commit_output_state
7521 *
7522 * This function copies the stage display pipe configuration to the real one.
7523 */
7524 static void intel_modeset_commit_output_state(struct drm_device *dev)
7525 {
7526 struct intel_encoder *encoder;
7527 struct intel_connector *connector;
7528
7529 list_for_each_entry(connector, &dev->mode_config.connector_list,
7530 base.head) {
7531 connector->base.encoder = &connector->new_encoder->base;
7532 }
7533
7534 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7535 base.head) {
7536 encoder->base.crtc = &encoder->new_crtc->base;
7537 }
7538 }
7539
7540 static int
7541 pipe_config_set_bpp(struct drm_crtc *crtc,
7542 struct drm_framebuffer *fb,
7543 struct intel_crtc_config *pipe_config)
7544 {
7545 struct drm_device *dev = crtc->dev;
7546 struct drm_connector *connector;
7547 int bpp;
7548
7549 switch (fb->pixel_format) {
7550 case DRM_FORMAT_C8:
7551 bpp = 8*3; /* since we go through a colormap */
7552 break;
7553 case DRM_FORMAT_XRGB1555:
7554 case DRM_FORMAT_ARGB1555:
7555 /* checked in intel_framebuffer_init already */
7556 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7557 return -EINVAL;
7558 case DRM_FORMAT_RGB565:
7559 bpp = 6*3; /* min is 18bpp */
7560 break;
7561 case DRM_FORMAT_XBGR8888:
7562 case DRM_FORMAT_ABGR8888:
7563 /* checked in intel_framebuffer_init already */
7564 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7565 return -EINVAL;
7566 case DRM_FORMAT_XRGB8888:
7567 case DRM_FORMAT_ARGB8888:
7568 bpp = 8*3;
7569 break;
7570 case DRM_FORMAT_XRGB2101010:
7571 case DRM_FORMAT_ARGB2101010:
7572 case DRM_FORMAT_XBGR2101010:
7573 case DRM_FORMAT_ABGR2101010:
7574 /* checked in intel_framebuffer_init already */
7575 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7576 return -EINVAL;
7577 bpp = 10*3;
7578 break;
7579 /* TODO: gen4+ supports 16 bpc floating point, too. */
7580 default:
7581 DRM_DEBUG_KMS("unsupported depth\n");
7582 return -EINVAL;
7583 }
7584
7585 pipe_config->pipe_bpp = bpp;
7586
7587 /* Clamp display bpp to EDID value */
7588 list_for_each_entry(connector, &dev->mode_config.connector_list,
7589 head) {
7590 if (connector->encoder && connector->encoder->crtc != crtc)
7591 continue;
7592
7593 /* Don't use an invalid EDID bpc value */
7594 if (connector->display_info.bpc &&
7595 connector->display_info.bpc * 3 < bpp) {
7596 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7597 bpp, connector->display_info.bpc*3);
7598 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7599 }
7600 }
7601
7602 return bpp;
7603 }
7604
7605 static struct intel_crtc_config *
7606 intel_modeset_pipe_config(struct drm_crtc *crtc,
7607 struct drm_framebuffer *fb,
7608 struct drm_display_mode *mode)
7609 {
7610 struct drm_device *dev = crtc->dev;
7611 struct drm_encoder_helper_funcs *encoder_funcs;
7612 struct intel_encoder *encoder;
7613 struct intel_crtc_config *pipe_config;
7614 int plane_bpp;
7615
7616 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7617 if (!pipe_config)
7618 return ERR_PTR(-ENOMEM);
7619
7620 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7621 drm_mode_copy(&pipe_config->requested_mode, mode);
7622
7623 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7624 if (plane_bpp < 0)
7625 goto fail;
7626
7627 /* Pass our mode to the connectors and the CRTC to give them a chance to
7628 * adjust it according to limitations or connector properties, and also
7629 * a chance to reject the mode entirely.
7630 */
7631 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7632 base.head) {
7633
7634 if (&encoder->new_crtc->base != crtc)
7635 continue;
7636
7637 if (encoder->compute_config) {
7638 if (!(encoder->compute_config(encoder, pipe_config))) {
7639 DRM_DEBUG_KMS("Encoder config failure\n");
7640 goto fail;
7641 }
7642
7643 continue;
7644 }
7645
7646 encoder_funcs = encoder->base.helper_private;
7647 if (!(encoder_funcs->mode_fixup(&encoder->base,
7648 &pipe_config->requested_mode,
7649 &pipe_config->adjusted_mode))) {
7650 DRM_DEBUG_KMS("Encoder fixup failed\n");
7651 goto fail;
7652 }
7653 }
7654
7655 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7656 DRM_DEBUG_KMS("CRTC fixup failed\n");
7657 goto fail;
7658 }
7659 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7660
7661 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7662 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7663 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7664
7665 return pipe_config;
7666 fail:
7667 kfree(pipe_config);
7668 return ERR_PTR(-EINVAL);
7669 }
7670
7671 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7672 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7673 static void
7674 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7675 unsigned *prepare_pipes, unsigned *disable_pipes)
7676 {
7677 struct intel_crtc *intel_crtc;
7678 struct drm_device *dev = crtc->dev;
7679 struct intel_encoder *encoder;
7680 struct intel_connector *connector;
7681 struct drm_crtc *tmp_crtc;
7682
7683 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7684
7685 /* Check which crtcs have changed outputs connected to them, these need
7686 * to be part of the prepare_pipes mask. We don't (yet) support global
7687 * modeset across multiple crtcs, so modeset_pipes will only have one
7688 * bit set at most. */
7689 list_for_each_entry(connector, &dev->mode_config.connector_list,
7690 base.head) {
7691 if (connector->base.encoder == &connector->new_encoder->base)
7692 continue;
7693
7694 if (connector->base.encoder) {
7695 tmp_crtc = connector->base.encoder->crtc;
7696
7697 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7698 }
7699
7700 if (connector->new_encoder)
7701 *prepare_pipes |=
7702 1 << connector->new_encoder->new_crtc->pipe;
7703 }
7704
7705 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7706 base.head) {
7707 if (encoder->base.crtc == &encoder->new_crtc->base)
7708 continue;
7709
7710 if (encoder->base.crtc) {
7711 tmp_crtc = encoder->base.crtc;
7712
7713 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7714 }
7715
7716 if (encoder->new_crtc)
7717 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7718 }
7719
7720 /* Check for any pipes that will be fully disabled ... */
7721 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7722 base.head) {
7723 bool used = false;
7724
7725 /* Don't try to disable disabled crtcs. */
7726 if (!intel_crtc->base.enabled)
7727 continue;
7728
7729 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7730 base.head) {
7731 if (encoder->new_crtc == intel_crtc)
7732 used = true;
7733 }
7734
7735 if (!used)
7736 *disable_pipes |= 1 << intel_crtc->pipe;
7737 }
7738
7739
7740 /* set_mode is also used to update properties on life display pipes. */
7741 intel_crtc = to_intel_crtc(crtc);
7742 if (crtc->enabled)
7743 *prepare_pipes |= 1 << intel_crtc->pipe;
7744
7745 /*
7746 * For simplicity do a full modeset on any pipe where the output routing
7747 * changed. We could be more clever, but that would require us to be
7748 * more careful with calling the relevant encoder->mode_set functions.
7749 */
7750 if (*prepare_pipes)
7751 *modeset_pipes = *prepare_pipes;
7752
7753 /* ... and mask these out. */
7754 *modeset_pipes &= ~(*disable_pipes);
7755 *prepare_pipes &= ~(*disable_pipes);
7756
7757 /*
7758 * HACK: We don't (yet) fully support global modesets. intel_set_config
7759 * obies this rule, but the modeset restore mode of
7760 * intel_modeset_setup_hw_state does not.
7761 */
7762 *modeset_pipes &= 1 << intel_crtc->pipe;
7763 *prepare_pipes &= 1 << intel_crtc->pipe;
7764 }
7765
7766 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7767 {
7768 struct drm_encoder *encoder;
7769 struct drm_device *dev = crtc->dev;
7770
7771 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7772 if (encoder->crtc == crtc)
7773 return true;
7774
7775 return false;
7776 }
7777
7778 static void
7779 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7780 {
7781 struct intel_encoder *intel_encoder;
7782 struct intel_crtc *intel_crtc;
7783 struct drm_connector *connector;
7784
7785 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7786 base.head) {
7787 if (!intel_encoder->base.crtc)
7788 continue;
7789
7790 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7791
7792 if (prepare_pipes & (1 << intel_crtc->pipe))
7793 intel_encoder->connectors_active = false;
7794 }
7795
7796 intel_modeset_commit_output_state(dev);
7797
7798 /* Update computed state. */
7799 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7800 base.head) {
7801 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7802 }
7803
7804 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7805 if (!connector->encoder || !connector->encoder->crtc)
7806 continue;
7807
7808 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7809
7810 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7811 struct drm_property *dpms_property =
7812 dev->mode_config.dpms_property;
7813
7814 connector->dpms = DRM_MODE_DPMS_ON;
7815 drm_object_property_set_value(&connector->base,
7816 dpms_property,
7817 DRM_MODE_DPMS_ON);
7818
7819 intel_encoder = to_intel_encoder(connector->encoder);
7820 intel_encoder->connectors_active = true;
7821 }
7822 }
7823
7824 }
7825
7826 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7827 list_for_each_entry((intel_crtc), \
7828 &(dev)->mode_config.crtc_list, \
7829 base.head) \
7830 if (mask & (1 <<(intel_crtc)->pipe)) \
7831
7832 static bool
7833 intel_pipe_config_compare(struct intel_crtc_config *current_config,
7834 struct intel_crtc_config *pipe_config)
7835 {
7836 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7837 DRM_ERROR("mismatch in has_pch_encoder "
7838 "(expected %i, found %i)\n",
7839 current_config->has_pch_encoder,
7840 pipe_config->has_pch_encoder);
7841 return false;
7842 }
7843
7844 return true;
7845 }
7846
7847 void
7848 intel_modeset_check_state(struct drm_device *dev)
7849 {
7850 drm_i915_private_t *dev_priv = dev->dev_private;
7851 struct intel_crtc *crtc;
7852 struct intel_encoder *encoder;
7853 struct intel_connector *connector;
7854 struct intel_crtc_config pipe_config;
7855
7856 list_for_each_entry(connector, &dev->mode_config.connector_list,
7857 base.head) {
7858 /* This also checks the encoder/connector hw state with the
7859 * ->get_hw_state callbacks. */
7860 intel_connector_check_state(connector);
7861
7862 WARN(&connector->new_encoder->base != connector->base.encoder,
7863 "connector's staged encoder doesn't match current encoder\n");
7864 }
7865
7866 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7867 base.head) {
7868 bool enabled = false;
7869 bool active = false;
7870 enum pipe pipe, tracked_pipe;
7871
7872 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7873 encoder->base.base.id,
7874 drm_get_encoder_name(&encoder->base));
7875
7876 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7877 "encoder's stage crtc doesn't match current crtc\n");
7878 WARN(encoder->connectors_active && !encoder->base.crtc,
7879 "encoder's active_connectors set, but no crtc\n");
7880
7881 list_for_each_entry(connector, &dev->mode_config.connector_list,
7882 base.head) {
7883 if (connector->base.encoder != &encoder->base)
7884 continue;
7885 enabled = true;
7886 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7887 active = true;
7888 }
7889 WARN(!!encoder->base.crtc != enabled,
7890 "encoder's enabled state mismatch "
7891 "(expected %i, found %i)\n",
7892 !!encoder->base.crtc, enabled);
7893 WARN(active && !encoder->base.crtc,
7894 "active encoder with no crtc\n");
7895
7896 WARN(encoder->connectors_active != active,
7897 "encoder's computed active state doesn't match tracked active state "
7898 "(expected %i, found %i)\n", active, encoder->connectors_active);
7899
7900 active = encoder->get_hw_state(encoder, &pipe);
7901 WARN(active != encoder->connectors_active,
7902 "encoder's hw state doesn't match sw tracking "
7903 "(expected %i, found %i)\n",
7904 encoder->connectors_active, active);
7905
7906 if (!encoder->base.crtc)
7907 continue;
7908
7909 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7910 WARN(active && pipe != tracked_pipe,
7911 "active encoder's pipe doesn't match"
7912 "(expected %i, found %i)\n",
7913 tracked_pipe, pipe);
7914
7915 }
7916
7917 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7918 base.head) {
7919 bool enabled = false;
7920 bool active = false;
7921
7922 DRM_DEBUG_KMS("[CRTC:%d]\n",
7923 crtc->base.base.id);
7924
7925 WARN(crtc->active && !crtc->base.enabled,
7926 "active crtc, but not enabled in sw tracking\n");
7927
7928 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7929 base.head) {
7930 if (encoder->base.crtc != &crtc->base)
7931 continue;
7932 enabled = true;
7933 if (encoder->connectors_active)
7934 active = true;
7935 }
7936 WARN(active != crtc->active,
7937 "crtc's computed active state doesn't match tracked active state "
7938 "(expected %i, found %i)\n", active, crtc->active);
7939 WARN(enabled != crtc->base.enabled,
7940 "crtc's computed enabled state doesn't match tracked enabled state "
7941 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7942
7943 memset(&pipe_config, 0, sizeof(pipe_config));
7944 active = dev_priv->display.get_pipe_config(crtc,
7945 &pipe_config);
7946
7947 /* hw state is inconsistent with the pipe A quirk */
7948 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
7949 active = crtc->active;
7950
7951 WARN(crtc->active != active,
7952 "crtc active state doesn't match with hw state "
7953 "(expected %i, found %i)\n", crtc->active, active);
7954
7955 WARN(active &&
7956 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7957 "pipe state doesn't match!\n");
7958 }
7959 }
7960
7961 static int __intel_set_mode(struct drm_crtc *crtc,
7962 struct drm_display_mode *mode,
7963 int x, int y, struct drm_framebuffer *fb)
7964 {
7965 struct drm_device *dev = crtc->dev;
7966 drm_i915_private_t *dev_priv = dev->dev_private;
7967 struct drm_display_mode *saved_mode, *saved_hwmode;
7968 struct intel_crtc_config *pipe_config = NULL;
7969 struct intel_crtc *intel_crtc;
7970 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7971 int ret = 0;
7972
7973 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7974 if (!saved_mode)
7975 return -ENOMEM;
7976 saved_hwmode = saved_mode + 1;
7977
7978 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7979 &prepare_pipes, &disable_pipes);
7980
7981 *saved_hwmode = crtc->hwmode;
7982 *saved_mode = crtc->mode;
7983
7984 /* Hack: Because we don't (yet) support global modeset on multiple
7985 * crtcs, we don't keep track of the new mode for more than one crtc.
7986 * Hence simply check whether any bit is set in modeset_pipes in all the
7987 * pieces of code that are not yet converted to deal with mutliple crtcs
7988 * changing their mode at the same time. */
7989 if (modeset_pipes) {
7990 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
7991 if (IS_ERR(pipe_config)) {
7992 ret = PTR_ERR(pipe_config);
7993 pipe_config = NULL;
7994
7995 goto out;
7996 }
7997 }
7998
7999 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8000 modeset_pipes, prepare_pipes, disable_pipes);
8001
8002 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8003 intel_crtc_disable(&intel_crtc->base);
8004
8005 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8006 if (intel_crtc->base.enabled)
8007 dev_priv->display.crtc_disable(&intel_crtc->base);
8008 }
8009
8010 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8011 * to set it here already despite that we pass it down the callchain.
8012 */
8013 if (modeset_pipes) {
8014 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8015 crtc->mode = *mode;
8016 /* mode_set/enable/disable functions rely on a correct pipe
8017 * config. */
8018 to_intel_crtc(crtc)->config = *pipe_config;
8019 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8020 }
8021
8022 /* Only after disabling all output pipelines that will be changed can we
8023 * update the the output configuration. */
8024 intel_modeset_update_state(dev, prepare_pipes);
8025
8026 if (dev_priv->display.modeset_global_resources)
8027 dev_priv->display.modeset_global_resources(dev);
8028
8029 /* Set up the DPLL and any encoders state that needs to adjust or depend
8030 * on the DPLL.
8031 */
8032 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8033 ret = intel_crtc_mode_set(&intel_crtc->base,
8034 x, y, fb);
8035 if (ret)
8036 goto done;
8037 }
8038
8039 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8040 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8041 dev_priv->display.crtc_enable(&intel_crtc->base);
8042
8043 if (modeset_pipes) {
8044 /* Store real post-adjustment hardware mode. */
8045 crtc->hwmode = pipe_config->adjusted_mode;
8046
8047 /* Calculate and store various constants which
8048 * are later needed by vblank and swap-completion
8049 * timestamping. They are derived from true hwmode.
8050 */
8051 drm_calc_timestamping_constants(crtc);
8052 }
8053
8054 /* FIXME: add subpixel order */
8055 done:
8056 if (ret && crtc->enabled) {
8057 crtc->hwmode = *saved_hwmode;
8058 crtc->mode = *saved_mode;
8059 }
8060
8061 out:
8062 kfree(pipe_config);
8063 kfree(saved_mode);
8064 return ret;
8065 }
8066
8067 int intel_set_mode(struct drm_crtc *crtc,
8068 struct drm_display_mode *mode,
8069 int x, int y, struct drm_framebuffer *fb)
8070 {
8071 int ret;
8072
8073 ret = __intel_set_mode(crtc, mode, x, y, fb);
8074
8075 if (ret == 0)
8076 intel_modeset_check_state(crtc->dev);
8077
8078 return ret;
8079 }
8080
8081 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8082 {
8083 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8084 }
8085
8086 #undef for_each_intel_crtc_masked
8087
8088 static void intel_set_config_free(struct intel_set_config *config)
8089 {
8090 if (!config)
8091 return;
8092
8093 kfree(config->save_connector_encoders);
8094 kfree(config->save_encoder_crtcs);
8095 kfree(config);
8096 }
8097
8098 static int intel_set_config_save_state(struct drm_device *dev,
8099 struct intel_set_config *config)
8100 {
8101 struct drm_encoder *encoder;
8102 struct drm_connector *connector;
8103 int count;
8104
8105 config->save_encoder_crtcs =
8106 kcalloc(dev->mode_config.num_encoder,
8107 sizeof(struct drm_crtc *), GFP_KERNEL);
8108 if (!config->save_encoder_crtcs)
8109 return -ENOMEM;
8110
8111 config->save_connector_encoders =
8112 kcalloc(dev->mode_config.num_connector,
8113 sizeof(struct drm_encoder *), GFP_KERNEL);
8114 if (!config->save_connector_encoders)
8115 return -ENOMEM;
8116
8117 /* Copy data. Note that driver private data is not affected.
8118 * Should anything bad happen only the expected state is
8119 * restored, not the drivers personal bookkeeping.
8120 */
8121 count = 0;
8122 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8123 config->save_encoder_crtcs[count++] = encoder->crtc;
8124 }
8125
8126 count = 0;
8127 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8128 config->save_connector_encoders[count++] = connector->encoder;
8129 }
8130
8131 return 0;
8132 }
8133
8134 static void intel_set_config_restore_state(struct drm_device *dev,
8135 struct intel_set_config *config)
8136 {
8137 struct intel_encoder *encoder;
8138 struct intel_connector *connector;
8139 int count;
8140
8141 count = 0;
8142 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8143 encoder->new_crtc =
8144 to_intel_crtc(config->save_encoder_crtcs[count++]);
8145 }
8146
8147 count = 0;
8148 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8149 connector->new_encoder =
8150 to_intel_encoder(config->save_connector_encoders[count++]);
8151 }
8152 }
8153
8154 static bool
8155 is_crtc_connector_off(struct drm_mode_set *set)
8156 {
8157 int i;
8158
8159 if (set->num_connectors == 0)
8160 return false;
8161
8162 if (WARN_ON(set->connectors == NULL))
8163 return false;
8164
8165 for (i = 0; i < set->num_connectors; i++)
8166 if (set->connectors[i]->encoder &&
8167 set->connectors[i]->encoder->crtc == set->crtc &&
8168 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
8169 return true;
8170
8171 return false;
8172 }
8173
8174 static void
8175 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8176 struct intel_set_config *config)
8177 {
8178
8179 /* We should be able to check here if the fb has the same properties
8180 * and then just flip_or_move it */
8181 if (is_crtc_connector_off(set)) {
8182 config->mode_changed = true;
8183 } else if (set->crtc->fb != set->fb) {
8184 /* If we have no fb then treat it as a full mode set */
8185 if (set->crtc->fb == NULL) {
8186 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8187 config->mode_changed = true;
8188 } else if (set->fb == NULL) {
8189 config->mode_changed = true;
8190 } else if (set->fb->pixel_format !=
8191 set->crtc->fb->pixel_format) {
8192 config->mode_changed = true;
8193 } else {
8194 config->fb_changed = true;
8195 }
8196 }
8197
8198 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8199 config->fb_changed = true;
8200
8201 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8202 DRM_DEBUG_KMS("modes are different, full mode set\n");
8203 drm_mode_debug_printmodeline(&set->crtc->mode);
8204 drm_mode_debug_printmodeline(set->mode);
8205 config->mode_changed = true;
8206 }
8207 }
8208
8209 static int
8210 intel_modeset_stage_output_state(struct drm_device *dev,
8211 struct drm_mode_set *set,
8212 struct intel_set_config *config)
8213 {
8214 struct drm_crtc *new_crtc;
8215 struct intel_connector *connector;
8216 struct intel_encoder *encoder;
8217 int count, ro;
8218
8219 /* The upper layers ensure that we either disable a crtc or have a list
8220 * of connectors. For paranoia, double-check this. */
8221 WARN_ON(!set->fb && (set->num_connectors != 0));
8222 WARN_ON(set->fb && (set->num_connectors == 0));
8223
8224 count = 0;
8225 list_for_each_entry(connector, &dev->mode_config.connector_list,
8226 base.head) {
8227 /* Otherwise traverse passed in connector list and get encoders
8228 * for them. */
8229 for (ro = 0; ro < set->num_connectors; ro++) {
8230 if (set->connectors[ro] == &connector->base) {
8231 connector->new_encoder = connector->encoder;
8232 break;
8233 }
8234 }
8235
8236 /* If we disable the crtc, disable all its connectors. Also, if
8237 * the connector is on the changing crtc but not on the new
8238 * connector list, disable it. */
8239 if ((!set->fb || ro == set->num_connectors) &&
8240 connector->base.encoder &&
8241 connector->base.encoder->crtc == set->crtc) {
8242 connector->new_encoder = NULL;
8243
8244 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8245 connector->base.base.id,
8246 drm_get_connector_name(&connector->base));
8247 }
8248
8249
8250 if (&connector->new_encoder->base != connector->base.encoder) {
8251 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8252 config->mode_changed = true;
8253 }
8254 }
8255 /* connector->new_encoder is now updated for all connectors. */
8256
8257 /* Update crtc of enabled connectors. */
8258 count = 0;
8259 list_for_each_entry(connector, &dev->mode_config.connector_list,
8260 base.head) {
8261 if (!connector->new_encoder)
8262 continue;
8263
8264 new_crtc = connector->new_encoder->base.crtc;
8265
8266 for (ro = 0; ro < set->num_connectors; ro++) {
8267 if (set->connectors[ro] == &connector->base)
8268 new_crtc = set->crtc;
8269 }
8270
8271 /* Make sure the new CRTC will work with the encoder */
8272 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8273 new_crtc)) {
8274 return -EINVAL;
8275 }
8276 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8277
8278 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8279 connector->base.base.id,
8280 drm_get_connector_name(&connector->base),
8281 new_crtc->base.id);
8282 }
8283
8284 /* Check for any encoders that needs to be disabled. */
8285 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8286 base.head) {
8287 list_for_each_entry(connector,
8288 &dev->mode_config.connector_list,
8289 base.head) {
8290 if (connector->new_encoder == encoder) {
8291 WARN_ON(!connector->new_encoder->new_crtc);
8292
8293 goto next_encoder;
8294 }
8295 }
8296 encoder->new_crtc = NULL;
8297 next_encoder:
8298 /* Only now check for crtc changes so we don't miss encoders
8299 * that will be disabled. */
8300 if (&encoder->new_crtc->base != encoder->base.crtc) {
8301 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8302 config->mode_changed = true;
8303 }
8304 }
8305 /* Now we've also updated encoder->new_crtc for all encoders. */
8306
8307 return 0;
8308 }
8309
8310 static int intel_crtc_set_config(struct drm_mode_set *set)
8311 {
8312 struct drm_device *dev;
8313 struct drm_mode_set save_set;
8314 struct intel_set_config *config;
8315 int ret;
8316
8317 BUG_ON(!set);
8318 BUG_ON(!set->crtc);
8319 BUG_ON(!set->crtc->helper_private);
8320
8321 /* Enforce sane interface api - has been abused by the fb helper. */
8322 BUG_ON(!set->mode && set->fb);
8323 BUG_ON(set->fb && set->num_connectors == 0);
8324
8325 if (set->fb) {
8326 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8327 set->crtc->base.id, set->fb->base.id,
8328 (int)set->num_connectors, set->x, set->y);
8329 } else {
8330 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8331 }
8332
8333 dev = set->crtc->dev;
8334
8335 ret = -ENOMEM;
8336 config = kzalloc(sizeof(*config), GFP_KERNEL);
8337 if (!config)
8338 goto out_config;
8339
8340 ret = intel_set_config_save_state(dev, config);
8341 if (ret)
8342 goto out_config;
8343
8344 save_set.crtc = set->crtc;
8345 save_set.mode = &set->crtc->mode;
8346 save_set.x = set->crtc->x;
8347 save_set.y = set->crtc->y;
8348 save_set.fb = set->crtc->fb;
8349
8350 /* Compute whether we need a full modeset, only an fb base update or no
8351 * change at all. In the future we might also check whether only the
8352 * mode changed, e.g. for LVDS where we only change the panel fitter in
8353 * such cases. */
8354 intel_set_config_compute_mode_changes(set, config);
8355
8356 ret = intel_modeset_stage_output_state(dev, set, config);
8357 if (ret)
8358 goto fail;
8359
8360 if (config->mode_changed) {
8361 if (set->mode) {
8362 DRM_DEBUG_KMS("attempting to set mode from"
8363 " userspace\n");
8364 drm_mode_debug_printmodeline(set->mode);
8365 }
8366
8367 ret = intel_set_mode(set->crtc, set->mode,
8368 set->x, set->y, set->fb);
8369 } else if (config->fb_changed) {
8370 intel_crtc_wait_for_pending_flips(set->crtc);
8371
8372 ret = intel_pipe_set_base(set->crtc,
8373 set->x, set->y, set->fb);
8374 }
8375
8376 if (ret) {
8377 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8378 set->crtc->base.id, ret);
8379 fail:
8380 intel_set_config_restore_state(dev, config);
8381
8382 /* Try to restore the config */
8383 if (config->mode_changed &&
8384 intel_set_mode(save_set.crtc, save_set.mode,
8385 save_set.x, save_set.y, save_set.fb))
8386 DRM_ERROR("failed to restore config after modeset failure\n");
8387 }
8388
8389 out_config:
8390 intel_set_config_free(config);
8391 return ret;
8392 }
8393
8394 static const struct drm_crtc_funcs intel_crtc_funcs = {
8395 .cursor_set = intel_crtc_cursor_set,
8396 .cursor_move = intel_crtc_cursor_move,
8397 .gamma_set = intel_crtc_gamma_set,
8398 .set_config = intel_crtc_set_config,
8399 .destroy = intel_crtc_destroy,
8400 .page_flip = intel_crtc_page_flip,
8401 };
8402
8403 static void intel_cpu_pll_init(struct drm_device *dev)
8404 {
8405 if (HAS_DDI(dev))
8406 intel_ddi_pll_init(dev);
8407 }
8408
8409 static void intel_pch_pll_init(struct drm_device *dev)
8410 {
8411 drm_i915_private_t *dev_priv = dev->dev_private;
8412 int i;
8413
8414 if (dev_priv->num_pch_pll == 0) {
8415 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8416 return;
8417 }
8418
8419 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8420 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8421 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8422 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8423 }
8424 }
8425
8426 static void intel_crtc_init(struct drm_device *dev, int pipe)
8427 {
8428 drm_i915_private_t *dev_priv = dev->dev_private;
8429 struct intel_crtc *intel_crtc;
8430 int i;
8431
8432 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8433 if (intel_crtc == NULL)
8434 return;
8435
8436 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8437
8438 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8439 for (i = 0; i < 256; i++) {
8440 intel_crtc->lut_r[i] = i;
8441 intel_crtc->lut_g[i] = i;
8442 intel_crtc->lut_b[i] = i;
8443 }
8444
8445 /* Swap pipes & planes for FBC on pre-965 */
8446 intel_crtc->pipe = pipe;
8447 intel_crtc->plane = pipe;
8448 intel_crtc->config.cpu_transcoder = pipe;
8449 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8450 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8451 intel_crtc->plane = !pipe;
8452 }
8453
8454 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8455 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8456 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8457 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8458
8459 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8460 }
8461
8462 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8463 struct drm_file *file)
8464 {
8465 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8466 struct drm_mode_object *drmmode_obj;
8467 struct intel_crtc *crtc;
8468
8469 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8470 return -ENODEV;
8471
8472 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8473 DRM_MODE_OBJECT_CRTC);
8474
8475 if (!drmmode_obj) {
8476 DRM_ERROR("no such CRTC id\n");
8477 return -EINVAL;
8478 }
8479
8480 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8481 pipe_from_crtc_id->pipe = crtc->pipe;
8482
8483 return 0;
8484 }
8485
8486 static int intel_encoder_clones(struct intel_encoder *encoder)
8487 {
8488 struct drm_device *dev = encoder->base.dev;
8489 struct intel_encoder *source_encoder;
8490 int index_mask = 0;
8491 int entry = 0;
8492
8493 list_for_each_entry(source_encoder,
8494 &dev->mode_config.encoder_list, base.head) {
8495
8496 if (encoder == source_encoder)
8497 index_mask |= (1 << entry);
8498
8499 /* Intel hw has only one MUX where enocoders could be cloned. */
8500 if (encoder->cloneable && source_encoder->cloneable)
8501 index_mask |= (1 << entry);
8502
8503 entry++;
8504 }
8505
8506 return index_mask;
8507 }
8508
8509 static bool has_edp_a(struct drm_device *dev)
8510 {
8511 struct drm_i915_private *dev_priv = dev->dev_private;
8512
8513 if (!IS_MOBILE(dev))
8514 return false;
8515
8516 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8517 return false;
8518
8519 if (IS_GEN5(dev) &&
8520 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8521 return false;
8522
8523 return true;
8524 }
8525
8526 static void intel_setup_outputs(struct drm_device *dev)
8527 {
8528 struct drm_i915_private *dev_priv = dev->dev_private;
8529 struct intel_encoder *encoder;
8530 bool dpd_is_edp = false;
8531 bool has_lvds;
8532
8533 has_lvds = intel_lvds_init(dev);
8534 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8535 /* disable the panel fitter on everything but LVDS */
8536 I915_WRITE(PFIT_CONTROL, 0);
8537 }
8538
8539 if (!IS_ULT(dev))
8540 intel_crt_init(dev);
8541
8542 if (HAS_DDI(dev)) {
8543 int found;
8544
8545 /* Haswell uses DDI functions to detect digital outputs */
8546 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8547 /* DDI A only supports eDP */
8548 if (found)
8549 intel_ddi_init(dev, PORT_A);
8550
8551 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8552 * register */
8553 found = I915_READ(SFUSE_STRAP);
8554
8555 if (found & SFUSE_STRAP_DDIB_DETECTED)
8556 intel_ddi_init(dev, PORT_B);
8557 if (found & SFUSE_STRAP_DDIC_DETECTED)
8558 intel_ddi_init(dev, PORT_C);
8559 if (found & SFUSE_STRAP_DDID_DETECTED)
8560 intel_ddi_init(dev, PORT_D);
8561 } else if (HAS_PCH_SPLIT(dev)) {
8562 int found;
8563 dpd_is_edp = intel_dpd_is_edp(dev);
8564
8565 if (has_edp_a(dev))
8566 intel_dp_init(dev, DP_A, PORT_A);
8567
8568 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8569 /* PCH SDVOB multiplex with HDMIB */
8570 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8571 if (!found)
8572 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8573 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8574 intel_dp_init(dev, PCH_DP_B, PORT_B);
8575 }
8576
8577 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8578 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8579
8580 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8581 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8582
8583 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8584 intel_dp_init(dev, PCH_DP_C, PORT_C);
8585
8586 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8587 intel_dp_init(dev, PCH_DP_D, PORT_D);
8588 } else if (IS_VALLEYVIEW(dev)) {
8589 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8590 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8591 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8592
8593 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8594 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8595 PORT_B);
8596 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8597 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8598 }
8599 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8600 bool found = false;
8601
8602 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8603 DRM_DEBUG_KMS("probing SDVOB\n");
8604 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8605 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8606 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8607 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8608 }
8609
8610 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8611 DRM_DEBUG_KMS("probing DP_B\n");
8612 intel_dp_init(dev, DP_B, PORT_B);
8613 }
8614 }
8615
8616 /* Before G4X SDVOC doesn't have its own detect register */
8617
8618 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8619 DRM_DEBUG_KMS("probing SDVOC\n");
8620 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8621 }
8622
8623 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8624
8625 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8626 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8627 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8628 }
8629 if (SUPPORTS_INTEGRATED_DP(dev)) {
8630 DRM_DEBUG_KMS("probing DP_C\n");
8631 intel_dp_init(dev, DP_C, PORT_C);
8632 }
8633 }
8634
8635 if (SUPPORTS_INTEGRATED_DP(dev) &&
8636 (I915_READ(DP_D) & DP_DETECTED)) {
8637 DRM_DEBUG_KMS("probing DP_D\n");
8638 intel_dp_init(dev, DP_D, PORT_D);
8639 }
8640 } else if (IS_GEN2(dev))
8641 intel_dvo_init(dev);
8642
8643 if (SUPPORTS_TV(dev))
8644 intel_tv_init(dev);
8645
8646 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8647 encoder->base.possible_crtcs = encoder->crtc_mask;
8648 encoder->base.possible_clones =
8649 intel_encoder_clones(encoder);
8650 }
8651
8652 intel_init_pch_refclk(dev);
8653
8654 drm_helper_move_panel_connectors_to_head(dev);
8655 }
8656
8657 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8658 {
8659 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8660
8661 drm_framebuffer_cleanup(fb);
8662 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8663
8664 kfree(intel_fb);
8665 }
8666
8667 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8668 struct drm_file *file,
8669 unsigned int *handle)
8670 {
8671 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8672 struct drm_i915_gem_object *obj = intel_fb->obj;
8673
8674 return drm_gem_handle_create(file, &obj->base, handle);
8675 }
8676
8677 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8678 .destroy = intel_user_framebuffer_destroy,
8679 .create_handle = intel_user_framebuffer_create_handle,
8680 };
8681
8682 int intel_framebuffer_init(struct drm_device *dev,
8683 struct intel_framebuffer *intel_fb,
8684 struct drm_mode_fb_cmd2 *mode_cmd,
8685 struct drm_i915_gem_object *obj)
8686 {
8687 int ret;
8688
8689 if (obj->tiling_mode == I915_TILING_Y) {
8690 DRM_DEBUG("hardware does not support tiling Y\n");
8691 return -EINVAL;
8692 }
8693
8694 if (mode_cmd->pitches[0] & 63) {
8695 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8696 mode_cmd->pitches[0]);
8697 return -EINVAL;
8698 }
8699
8700 /* FIXME <= Gen4 stride limits are bit unclear */
8701 if (mode_cmd->pitches[0] > 32768) {
8702 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8703 mode_cmd->pitches[0]);
8704 return -EINVAL;
8705 }
8706
8707 if (obj->tiling_mode != I915_TILING_NONE &&
8708 mode_cmd->pitches[0] != obj->stride) {
8709 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8710 mode_cmd->pitches[0], obj->stride);
8711 return -EINVAL;
8712 }
8713
8714 /* Reject formats not supported by any plane early. */
8715 switch (mode_cmd->pixel_format) {
8716 case DRM_FORMAT_C8:
8717 case DRM_FORMAT_RGB565:
8718 case DRM_FORMAT_XRGB8888:
8719 case DRM_FORMAT_ARGB8888:
8720 break;
8721 case DRM_FORMAT_XRGB1555:
8722 case DRM_FORMAT_ARGB1555:
8723 if (INTEL_INFO(dev)->gen > 3) {
8724 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8725 return -EINVAL;
8726 }
8727 break;
8728 case DRM_FORMAT_XBGR8888:
8729 case DRM_FORMAT_ABGR8888:
8730 case DRM_FORMAT_XRGB2101010:
8731 case DRM_FORMAT_ARGB2101010:
8732 case DRM_FORMAT_XBGR2101010:
8733 case DRM_FORMAT_ABGR2101010:
8734 if (INTEL_INFO(dev)->gen < 4) {
8735 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8736 return -EINVAL;
8737 }
8738 break;
8739 case DRM_FORMAT_YUYV:
8740 case DRM_FORMAT_UYVY:
8741 case DRM_FORMAT_YVYU:
8742 case DRM_FORMAT_VYUY:
8743 if (INTEL_INFO(dev)->gen < 5) {
8744 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8745 return -EINVAL;
8746 }
8747 break;
8748 default:
8749 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8750 return -EINVAL;
8751 }
8752
8753 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8754 if (mode_cmd->offsets[0] != 0)
8755 return -EINVAL;
8756
8757 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8758 intel_fb->obj = obj;
8759
8760 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8761 if (ret) {
8762 DRM_ERROR("framebuffer init failed %d\n", ret);
8763 return ret;
8764 }
8765
8766 return 0;
8767 }
8768
8769 static struct drm_framebuffer *
8770 intel_user_framebuffer_create(struct drm_device *dev,
8771 struct drm_file *filp,
8772 struct drm_mode_fb_cmd2 *mode_cmd)
8773 {
8774 struct drm_i915_gem_object *obj;
8775
8776 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8777 mode_cmd->handles[0]));
8778 if (&obj->base == NULL)
8779 return ERR_PTR(-ENOENT);
8780
8781 return intel_framebuffer_create(dev, mode_cmd, obj);
8782 }
8783
8784 static const struct drm_mode_config_funcs intel_mode_funcs = {
8785 .fb_create = intel_user_framebuffer_create,
8786 .output_poll_changed = intel_fb_output_poll_changed,
8787 };
8788
8789 /* Set up chip specific display functions */
8790 static void intel_init_display(struct drm_device *dev)
8791 {
8792 struct drm_i915_private *dev_priv = dev->dev_private;
8793
8794 if (HAS_DDI(dev)) {
8795 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8796 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8797 dev_priv->display.crtc_enable = haswell_crtc_enable;
8798 dev_priv->display.crtc_disable = haswell_crtc_disable;
8799 dev_priv->display.off = haswell_crtc_off;
8800 dev_priv->display.update_plane = ironlake_update_plane;
8801 } else if (HAS_PCH_SPLIT(dev)) {
8802 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8803 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8804 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8805 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8806 dev_priv->display.off = ironlake_crtc_off;
8807 dev_priv->display.update_plane = ironlake_update_plane;
8808 } else {
8809 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8810 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8811 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8812 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8813 dev_priv->display.off = i9xx_crtc_off;
8814 dev_priv->display.update_plane = i9xx_update_plane;
8815 }
8816
8817 /* Returns the core display clock speed */
8818 if (IS_VALLEYVIEW(dev))
8819 dev_priv->display.get_display_clock_speed =
8820 valleyview_get_display_clock_speed;
8821 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8822 dev_priv->display.get_display_clock_speed =
8823 i945_get_display_clock_speed;
8824 else if (IS_I915G(dev))
8825 dev_priv->display.get_display_clock_speed =
8826 i915_get_display_clock_speed;
8827 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8828 dev_priv->display.get_display_clock_speed =
8829 i9xx_misc_get_display_clock_speed;
8830 else if (IS_I915GM(dev))
8831 dev_priv->display.get_display_clock_speed =
8832 i915gm_get_display_clock_speed;
8833 else if (IS_I865G(dev))
8834 dev_priv->display.get_display_clock_speed =
8835 i865_get_display_clock_speed;
8836 else if (IS_I85X(dev))
8837 dev_priv->display.get_display_clock_speed =
8838 i855_get_display_clock_speed;
8839 else /* 852, 830 */
8840 dev_priv->display.get_display_clock_speed =
8841 i830_get_display_clock_speed;
8842
8843 if (HAS_PCH_SPLIT(dev)) {
8844 if (IS_GEN5(dev)) {
8845 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8846 dev_priv->display.write_eld = ironlake_write_eld;
8847 } else if (IS_GEN6(dev)) {
8848 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8849 dev_priv->display.write_eld = ironlake_write_eld;
8850 } else if (IS_IVYBRIDGE(dev)) {
8851 /* FIXME: detect B0+ stepping and use auto training */
8852 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8853 dev_priv->display.write_eld = ironlake_write_eld;
8854 dev_priv->display.modeset_global_resources =
8855 ivb_modeset_global_resources;
8856 } else if (IS_HASWELL(dev)) {
8857 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8858 dev_priv->display.write_eld = haswell_write_eld;
8859 dev_priv->display.modeset_global_resources =
8860 haswell_modeset_global_resources;
8861 }
8862 } else if (IS_G4X(dev)) {
8863 dev_priv->display.write_eld = g4x_write_eld;
8864 }
8865
8866 /* Default just returns -ENODEV to indicate unsupported */
8867 dev_priv->display.queue_flip = intel_default_queue_flip;
8868
8869 switch (INTEL_INFO(dev)->gen) {
8870 case 2:
8871 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8872 break;
8873
8874 case 3:
8875 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8876 break;
8877
8878 case 4:
8879 case 5:
8880 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8881 break;
8882
8883 case 6:
8884 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8885 break;
8886 case 7:
8887 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8888 break;
8889 }
8890 }
8891
8892 /*
8893 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8894 * resume, or other times. This quirk makes sure that's the case for
8895 * affected systems.
8896 */
8897 static void quirk_pipea_force(struct drm_device *dev)
8898 {
8899 struct drm_i915_private *dev_priv = dev->dev_private;
8900
8901 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8902 DRM_INFO("applying pipe a force quirk\n");
8903 }
8904
8905 /*
8906 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8907 */
8908 static void quirk_ssc_force_disable(struct drm_device *dev)
8909 {
8910 struct drm_i915_private *dev_priv = dev->dev_private;
8911 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8912 DRM_INFO("applying lvds SSC disable quirk\n");
8913 }
8914
8915 /*
8916 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8917 * brightness value
8918 */
8919 static void quirk_invert_brightness(struct drm_device *dev)
8920 {
8921 struct drm_i915_private *dev_priv = dev->dev_private;
8922 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8923 DRM_INFO("applying inverted panel brightness quirk\n");
8924 }
8925
8926 /*
8927 * Some machines (Dell XPS13) suffer broken backlight controls if
8928 * BLM_PCH_PWM_ENABLE is set.
8929 */
8930 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
8931 {
8932 struct drm_i915_private *dev_priv = dev->dev_private;
8933 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
8934 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
8935 }
8936
8937 struct intel_quirk {
8938 int device;
8939 int subsystem_vendor;
8940 int subsystem_device;
8941 void (*hook)(struct drm_device *dev);
8942 };
8943
8944 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8945 struct intel_dmi_quirk {
8946 void (*hook)(struct drm_device *dev);
8947 const struct dmi_system_id (*dmi_id_list)[];
8948 };
8949
8950 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8951 {
8952 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8953 return 1;
8954 }
8955
8956 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8957 {
8958 .dmi_id_list = &(const struct dmi_system_id[]) {
8959 {
8960 .callback = intel_dmi_reverse_brightness,
8961 .ident = "NCR Corporation",
8962 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8963 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8964 },
8965 },
8966 { } /* terminating entry */
8967 },
8968 .hook = quirk_invert_brightness,
8969 },
8970 };
8971
8972 static struct intel_quirk intel_quirks[] = {
8973 /* HP Mini needs pipe A force quirk (LP: #322104) */
8974 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8975
8976 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8977 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8978
8979 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8980 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8981
8982 /* 830/845 need to leave pipe A & dpll A up */
8983 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8984 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8985
8986 /* Lenovo U160 cannot use SSC on LVDS */
8987 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8988
8989 /* Sony Vaio Y cannot use SSC on LVDS */
8990 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8991
8992 /* Acer Aspire 5734Z must invert backlight brightness */
8993 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8994
8995 /* Acer/eMachines G725 */
8996 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8997
8998 /* Acer/eMachines e725 */
8999 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9000
9001 /* Acer/Packard Bell NCL20 */
9002 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9003
9004 /* Acer Aspire 4736Z */
9005 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9006
9007 /* Dell XPS13 HD Sandy Bridge */
9008 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9009 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9010 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
9011 };
9012
9013 static void intel_init_quirks(struct drm_device *dev)
9014 {
9015 struct pci_dev *d = dev->pdev;
9016 int i;
9017
9018 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9019 struct intel_quirk *q = &intel_quirks[i];
9020
9021 if (d->device == q->device &&
9022 (d->subsystem_vendor == q->subsystem_vendor ||
9023 q->subsystem_vendor == PCI_ANY_ID) &&
9024 (d->subsystem_device == q->subsystem_device ||
9025 q->subsystem_device == PCI_ANY_ID))
9026 q->hook(dev);
9027 }
9028 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9029 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9030 intel_dmi_quirks[i].hook(dev);
9031 }
9032 }
9033
9034 /* Disable the VGA plane that we never use */
9035 static void i915_disable_vga(struct drm_device *dev)
9036 {
9037 struct drm_i915_private *dev_priv = dev->dev_private;
9038 u8 sr1;
9039 u32 vga_reg = i915_vgacntrl_reg(dev);
9040
9041 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9042 outb(SR01, VGA_SR_INDEX);
9043 sr1 = inb(VGA_SR_DATA);
9044 outb(sr1 | 1<<5, VGA_SR_DATA);
9045 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9046 udelay(300);
9047
9048 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9049 POSTING_READ(vga_reg);
9050 }
9051
9052 void intel_modeset_init_hw(struct drm_device *dev)
9053 {
9054 intel_init_power_well(dev);
9055
9056 intel_prepare_ddi(dev);
9057
9058 intel_init_clock_gating(dev);
9059
9060 mutex_lock(&dev->struct_mutex);
9061 intel_enable_gt_powersave(dev);
9062 mutex_unlock(&dev->struct_mutex);
9063 }
9064
9065 void intel_modeset_init(struct drm_device *dev)
9066 {
9067 struct drm_i915_private *dev_priv = dev->dev_private;
9068 int i, j, ret;
9069
9070 drm_mode_config_init(dev);
9071
9072 dev->mode_config.min_width = 0;
9073 dev->mode_config.min_height = 0;
9074
9075 dev->mode_config.preferred_depth = 24;
9076 dev->mode_config.prefer_shadow = 1;
9077
9078 dev->mode_config.funcs = &intel_mode_funcs;
9079
9080 intel_init_quirks(dev);
9081
9082 intel_init_pm(dev);
9083
9084 if (INTEL_INFO(dev)->num_pipes == 0)
9085 return;
9086
9087 intel_init_display(dev);
9088
9089 if (IS_GEN2(dev)) {
9090 dev->mode_config.max_width = 2048;
9091 dev->mode_config.max_height = 2048;
9092 } else if (IS_GEN3(dev)) {
9093 dev->mode_config.max_width = 4096;
9094 dev->mode_config.max_height = 4096;
9095 } else {
9096 dev->mode_config.max_width = 8192;
9097 dev->mode_config.max_height = 8192;
9098 }
9099 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9100
9101 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9102 INTEL_INFO(dev)->num_pipes,
9103 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9104
9105 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9106 intel_crtc_init(dev, i);
9107 for (j = 0; j < dev_priv->num_plane; j++) {
9108 ret = intel_plane_init(dev, i, j);
9109 if (ret)
9110 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
9111 i, j, ret);
9112 }
9113 }
9114
9115 intel_cpu_pll_init(dev);
9116 intel_pch_pll_init(dev);
9117
9118 /* Just disable it once at startup */
9119 i915_disable_vga(dev);
9120 intel_setup_outputs(dev);
9121
9122 /* Just in case the BIOS is doing something questionable. */
9123 intel_disable_fbc(dev);
9124 }
9125
9126 static void intel_enable_pipe_a(struct drm_device *dev)
9127 {
9128 struct intel_connector *connector;
9129 struct drm_connector *crt = NULL;
9130 struct intel_load_detect_pipe load_detect_temp;
9131
9132 /* We can't just switch on the pipe A, we need to set things up with a
9133 * proper mode and output configuration. As a gross hack, enable pipe A
9134 * by enabling the load detect pipe once. */
9135 list_for_each_entry(connector,
9136 &dev->mode_config.connector_list,
9137 base.head) {
9138 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9139 crt = &connector->base;
9140 break;
9141 }
9142 }
9143
9144 if (!crt)
9145 return;
9146
9147 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9148 intel_release_load_detect_pipe(crt, &load_detect_temp);
9149
9150
9151 }
9152
9153 static bool
9154 intel_check_plane_mapping(struct intel_crtc *crtc)
9155 {
9156 struct drm_device *dev = crtc->base.dev;
9157 struct drm_i915_private *dev_priv = dev->dev_private;
9158 u32 reg, val;
9159
9160 if (INTEL_INFO(dev)->num_pipes == 1)
9161 return true;
9162
9163 reg = DSPCNTR(!crtc->plane);
9164 val = I915_READ(reg);
9165
9166 if ((val & DISPLAY_PLANE_ENABLE) &&
9167 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9168 return false;
9169
9170 return true;
9171 }
9172
9173 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9174 {
9175 struct drm_device *dev = crtc->base.dev;
9176 struct drm_i915_private *dev_priv = dev->dev_private;
9177 u32 reg;
9178
9179 /* Clear any frame start delays used for debugging left by the BIOS */
9180 reg = PIPECONF(crtc->config.cpu_transcoder);
9181 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9182
9183 /* We need to sanitize the plane -> pipe mapping first because this will
9184 * disable the crtc (and hence change the state) if it is wrong. Note
9185 * that gen4+ has a fixed plane -> pipe mapping. */
9186 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9187 struct intel_connector *connector;
9188 bool plane;
9189
9190 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9191 crtc->base.base.id);
9192
9193 /* Pipe has the wrong plane attached and the plane is active.
9194 * Temporarily change the plane mapping and disable everything
9195 * ... */
9196 plane = crtc->plane;
9197 crtc->plane = !plane;
9198 dev_priv->display.crtc_disable(&crtc->base);
9199 crtc->plane = plane;
9200
9201 /* ... and break all links. */
9202 list_for_each_entry(connector, &dev->mode_config.connector_list,
9203 base.head) {
9204 if (connector->encoder->base.crtc != &crtc->base)
9205 continue;
9206
9207 connector->base.dpms = DRM_MODE_DPMS_OFF;
9208 connector->base.encoder = NULL;
9209 }
9210 /* multiple connectors may have the same encoder:
9211 * handle them and break crtc link separately */
9212 list_for_each_entry(connector, &dev->mode_config.connector_list,
9213 base.head)
9214 if (connector->encoder->base.crtc == &crtc->base) {
9215 connector->encoder->base.crtc = NULL;
9216 connector->encoder->connectors_active = false;
9217 }
9218
9219 WARN_ON(crtc->active);
9220 crtc->base.enabled = false;
9221 }
9222
9223 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9224 crtc->pipe == PIPE_A && !crtc->active) {
9225 /* BIOS forgot to enable pipe A, this mostly happens after
9226 * resume. Force-enable the pipe to fix this, the update_dpms
9227 * call below we restore the pipe to the right state, but leave
9228 * the required bits on. */
9229 intel_enable_pipe_a(dev);
9230 }
9231
9232 /* Adjust the state of the output pipe according to whether we
9233 * have active connectors/encoders. */
9234 intel_crtc_update_dpms(&crtc->base);
9235
9236 if (crtc->active != crtc->base.enabled) {
9237 struct intel_encoder *encoder;
9238
9239 /* This can happen either due to bugs in the get_hw_state
9240 * functions or because the pipe is force-enabled due to the
9241 * pipe A quirk. */
9242 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9243 crtc->base.base.id,
9244 crtc->base.enabled ? "enabled" : "disabled",
9245 crtc->active ? "enabled" : "disabled");
9246
9247 crtc->base.enabled = crtc->active;
9248
9249 /* Because we only establish the connector -> encoder ->
9250 * crtc links if something is active, this means the
9251 * crtc is now deactivated. Break the links. connector
9252 * -> encoder links are only establish when things are
9253 * actually up, hence no need to break them. */
9254 WARN_ON(crtc->active);
9255
9256 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9257 WARN_ON(encoder->connectors_active);
9258 encoder->base.crtc = NULL;
9259 }
9260 }
9261 }
9262
9263 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9264 {
9265 struct intel_connector *connector;
9266 struct drm_device *dev = encoder->base.dev;
9267
9268 /* We need to check both for a crtc link (meaning that the
9269 * encoder is active and trying to read from a pipe) and the
9270 * pipe itself being active. */
9271 bool has_active_crtc = encoder->base.crtc &&
9272 to_intel_crtc(encoder->base.crtc)->active;
9273
9274 if (encoder->connectors_active && !has_active_crtc) {
9275 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9276 encoder->base.base.id,
9277 drm_get_encoder_name(&encoder->base));
9278
9279 /* Connector is active, but has no active pipe. This is
9280 * fallout from our resume register restoring. Disable
9281 * the encoder manually again. */
9282 if (encoder->base.crtc) {
9283 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9284 encoder->base.base.id,
9285 drm_get_encoder_name(&encoder->base));
9286 encoder->disable(encoder);
9287 }
9288 encoder->base.crtc = NULL;
9289 encoder->connectors_active = false;
9290
9291 /* Inconsistent output/port/pipe state happens presumably due to
9292 * a bug in one of the get_hw_state functions. Or someplace else
9293 * in our code, like the register restore mess on resume. Clamp
9294 * things to off as a safer default. */
9295 list_for_each_entry(connector,
9296 &dev->mode_config.connector_list,
9297 base.head) {
9298 if (connector->encoder != encoder)
9299 continue;
9300 connector->base.dpms = DRM_MODE_DPMS_OFF;
9301 connector->base.encoder = NULL;
9302 }
9303 }
9304 /* Enabled encoders without active connectors will be fixed in
9305 * the crtc fixup. */
9306 }
9307
9308 void i915_redisable_vga(struct drm_device *dev)
9309 {
9310 struct drm_i915_private *dev_priv = dev->dev_private;
9311 u32 vga_reg = i915_vgacntrl_reg(dev);
9312
9313 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9314 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9315 i915_disable_vga(dev);
9316 }
9317 }
9318
9319 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9320 * and i915 state tracking structures. */
9321 void intel_modeset_setup_hw_state(struct drm_device *dev,
9322 bool force_restore)
9323 {
9324 struct drm_i915_private *dev_priv = dev->dev_private;
9325 enum pipe pipe;
9326 u32 tmp;
9327 struct drm_plane *plane;
9328 struct intel_crtc *crtc;
9329 struct intel_encoder *encoder;
9330 struct intel_connector *connector;
9331
9332 if (HAS_DDI(dev)) {
9333 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9334
9335 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9336 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9337 case TRANS_DDI_EDP_INPUT_A_ON:
9338 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9339 pipe = PIPE_A;
9340 break;
9341 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9342 pipe = PIPE_B;
9343 break;
9344 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9345 pipe = PIPE_C;
9346 break;
9347 default:
9348 /* A bogus value has been programmed, disable
9349 * the transcoder */
9350 WARN(1, "Bogus eDP source %08x\n", tmp);
9351 intel_ddi_disable_transcoder_func(dev_priv,
9352 TRANSCODER_EDP);
9353 goto setup_pipes;
9354 }
9355
9356 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9357 crtc->config.cpu_transcoder = TRANSCODER_EDP;
9358
9359 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9360 pipe_name(pipe));
9361 }
9362 }
9363
9364 setup_pipes:
9365 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9366 base.head) {
9367 enum transcoder tmp = crtc->config.cpu_transcoder;
9368 memset(&crtc->config, 0, sizeof(crtc->config));
9369 crtc->config.cpu_transcoder = tmp;
9370
9371 crtc->active = dev_priv->display.get_pipe_config(crtc,
9372 &crtc->config);
9373
9374 crtc->base.enabled = crtc->active;
9375
9376 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9377 crtc->base.base.id,
9378 crtc->active ? "enabled" : "disabled");
9379 }
9380
9381 if (HAS_DDI(dev))
9382 intel_ddi_setup_hw_pll_state(dev);
9383
9384 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9385 base.head) {
9386 pipe = 0;
9387
9388 if (encoder->get_hw_state(encoder, &pipe)) {
9389 encoder->base.crtc =
9390 dev_priv->pipe_to_crtc_mapping[pipe];
9391 } else {
9392 encoder->base.crtc = NULL;
9393 }
9394
9395 encoder->connectors_active = false;
9396 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9397 encoder->base.base.id,
9398 drm_get_encoder_name(&encoder->base),
9399 encoder->base.crtc ? "enabled" : "disabled",
9400 pipe);
9401 }
9402
9403 list_for_each_entry(connector, &dev->mode_config.connector_list,
9404 base.head) {
9405 if (connector->get_hw_state(connector)) {
9406 connector->base.dpms = DRM_MODE_DPMS_ON;
9407 connector->encoder->connectors_active = true;
9408 connector->base.encoder = &connector->encoder->base;
9409 } else {
9410 connector->base.dpms = DRM_MODE_DPMS_OFF;
9411 connector->base.encoder = NULL;
9412 }
9413 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9414 connector->base.base.id,
9415 drm_get_connector_name(&connector->base),
9416 connector->base.encoder ? "enabled" : "disabled");
9417 }
9418
9419 /* HW state is read out, now we need to sanitize this mess. */
9420 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9421 base.head) {
9422 intel_sanitize_encoder(encoder);
9423 }
9424
9425 for_each_pipe(pipe) {
9426 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9427 intel_sanitize_crtc(crtc);
9428 }
9429
9430 if (force_restore) {
9431 /*
9432 * We need to use raw interfaces for restoring state to avoid
9433 * checking (bogus) intermediate states.
9434 */
9435 for_each_pipe(pipe) {
9436 struct drm_crtc *crtc =
9437 dev_priv->pipe_to_crtc_mapping[pipe];
9438
9439 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9440 crtc->fb);
9441 }
9442 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9443 intel_plane_restore(plane);
9444
9445 i915_redisable_vga(dev);
9446 } else {
9447 intel_modeset_update_staged_output_state(dev);
9448 }
9449
9450 intel_modeset_check_state(dev);
9451
9452 drm_mode_config_reset(dev);
9453 }
9454
9455 void intel_modeset_gem_init(struct drm_device *dev)
9456 {
9457 intel_modeset_init_hw(dev);
9458
9459 intel_setup_overlay(dev);
9460
9461 mutex_lock(&dev->mode_config.mutex);
9462 intel_modeset_setup_hw_state(dev, false);
9463 mutex_unlock(&dev->mode_config.mutex);
9464 }
9465
9466 void intel_modeset_cleanup(struct drm_device *dev)
9467 {
9468 struct drm_i915_private *dev_priv = dev->dev_private;
9469 struct drm_crtc *crtc;
9470 struct intel_crtc *intel_crtc;
9471
9472 drm_kms_helper_poll_fini(dev);
9473 mutex_lock(&dev->struct_mutex);
9474
9475 intel_unregister_dsm_handler();
9476
9477
9478 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9479 /* Skip inactive CRTCs */
9480 if (!crtc->fb)
9481 continue;
9482
9483 intel_crtc = to_intel_crtc(crtc);
9484 intel_increase_pllclock(crtc);
9485 }
9486
9487 intel_disable_fbc(dev);
9488
9489 intel_disable_gt_powersave(dev);
9490
9491 ironlake_teardown_rc6(dev);
9492
9493 if (IS_VALLEYVIEW(dev))
9494 vlv_init_dpio(dev);
9495
9496 mutex_unlock(&dev->struct_mutex);
9497
9498 /* Disable the irq before mode object teardown, for the irq might
9499 * enqueue unpin/hotplug work. */
9500 drm_irq_uninstall(dev);
9501 cancel_work_sync(&dev_priv->hotplug_work);
9502 cancel_work_sync(&dev_priv->rps.work);
9503
9504 /* flush any delayed tasks or pending work */
9505 flush_scheduled_work();
9506
9507 /* destroy backlight, if any, before the connectors */
9508 intel_panel_destroy_backlight(dev);
9509
9510 drm_mode_config_cleanup(dev);
9511
9512 intel_cleanup_overlay(dev);
9513 }
9514
9515 /*
9516 * Return which encoder is currently attached for connector.
9517 */
9518 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9519 {
9520 return &intel_attached_encoder(connector)->base;
9521 }
9522
9523 void intel_connector_attach_encoder(struct intel_connector *connector,
9524 struct intel_encoder *encoder)
9525 {
9526 connector->encoder = encoder;
9527 drm_mode_connector_attach_encoder(&connector->base,
9528 &encoder->base);
9529 }
9530
9531 /*
9532 * set vga decode state - true == enable VGA decode
9533 */
9534 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9535 {
9536 struct drm_i915_private *dev_priv = dev->dev_private;
9537 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
9538 u16 gmch_ctrl;
9539
9540 pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);
9541 if (state)
9542 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9543 else
9544 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9545 pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl);
9546 return 0;
9547 }
9548
9549 #ifdef CONFIG_DEBUG_FS
9550 #include <linux/seq_file.h>
9551
9552 struct intel_display_error_state {
9553 struct intel_cursor_error_state {
9554 u32 control;
9555 u32 position;
9556 u32 base;
9557 u32 size;
9558 } cursor[I915_MAX_PIPES];
9559
9560 struct intel_pipe_error_state {
9561 u32 conf;
9562 u32 source;
9563
9564 u32 htotal;
9565 u32 hblank;
9566 u32 hsync;
9567 u32 vtotal;
9568 u32 vblank;
9569 u32 vsync;
9570 } pipe[I915_MAX_PIPES];
9571
9572 struct intel_plane_error_state {
9573 u32 control;
9574 u32 stride;
9575 u32 size;
9576 u32 pos;
9577 u32 addr;
9578 u32 surface;
9579 u32 tile_offset;
9580 } plane[I915_MAX_PIPES];
9581 };
9582
9583 struct intel_display_error_state *
9584 intel_display_capture_error_state(struct drm_device *dev)
9585 {
9586 drm_i915_private_t *dev_priv = dev->dev_private;
9587 struct intel_display_error_state *error;
9588 enum transcoder cpu_transcoder;
9589 int i;
9590
9591 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9592 if (error == NULL)
9593 return NULL;
9594
9595 for_each_pipe(i) {
9596 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9597
9598 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9599 error->cursor[i].control = I915_READ(CURCNTR(i));
9600 error->cursor[i].position = I915_READ(CURPOS(i));
9601 error->cursor[i].base = I915_READ(CURBASE(i));
9602 } else {
9603 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9604 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9605 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9606 }
9607
9608 error->plane[i].control = I915_READ(DSPCNTR(i));
9609 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9610 if (INTEL_INFO(dev)->gen <= 3) {
9611 error->plane[i].size = I915_READ(DSPSIZE(i));
9612 error->plane[i].pos = I915_READ(DSPPOS(i));
9613 }
9614 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9615 error->plane[i].addr = I915_READ(DSPADDR(i));
9616 if (INTEL_INFO(dev)->gen >= 4) {
9617 error->plane[i].surface = I915_READ(DSPSURF(i));
9618 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9619 }
9620
9621 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9622 error->pipe[i].source = I915_READ(PIPESRC(i));
9623 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9624 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9625 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9626 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9627 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9628 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9629 }
9630
9631 return error;
9632 }
9633
9634 void
9635 intel_display_print_error_state(struct seq_file *m,
9636 struct drm_device *dev,
9637 struct intel_display_error_state *error)
9638 {
9639 int i;
9640
9641 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9642 for_each_pipe(i) {
9643 seq_printf(m, "Pipe [%d]:\n", i);
9644 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9645 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9646 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9647 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9648 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9649 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9650 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9651 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9652
9653 seq_printf(m, "Plane [%d]:\n", i);
9654 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9655 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9656 if (INTEL_INFO(dev)->gen <= 3) {
9657 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9658 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9659 }
9660 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9661 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9662 if (INTEL_INFO(dev)->gen >= 4) {
9663 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9664 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9665 }
9666
9667 seq_printf(m, "Cursor [%d]:\n", i);
9668 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9669 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9670 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9671 }
9672 }
9673 #endif
kernel source for telekom puls (alcatel/mediatek)