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drm/i915: split out Ironlake pipe bpp picking code
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include "drmP.h"
35 #include "intel_drv.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "i915_trace.h"
39 #include "drm_dp_helper.h"
40
41 #include "drm_crtc_helper.h"
42
43 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44
45 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
46 static void intel_update_watermarks(struct drm_device *dev);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
86 static bool
87 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
89
90 static bool
91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
93 static bool
94 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
96
97 static inline u32 /* units of 100MHz */
98 intel_fdi_link_freq(struct drm_device *dev)
99 {
100 if (IS_GEN5(dev)) {
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
103 } else
104 return 27;
105 }
106
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
118 .find_pll = intel_find_best_PLL,
119 };
120
121 static const intel_limit_t intel_limits_i8xx_lvds = {
122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
132 .find_pll = intel_find_best_PLL,
133 };
134
135 static const intel_limit_t intel_limits_i9xx_sdvo = {
136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
146 .find_pll = intel_find_best_PLL,
147 };
148
149 static const intel_limit_t intel_limits_i9xx_lvds = {
150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
160 .find_pll = intel_find_best_PLL,
161 };
162
163
164 static const intel_limit_t intel_limits_g4x_sdvo = {
165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
174 .p2_slow = 10,
175 .p2_fast = 10
176 },
177 .find_pll = intel_g4x_find_best_PLL,
178 };
179
180 static const intel_limit_t intel_limits_g4x_hdmi = {
181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
191 .find_pll = intel_g4x_find_best_PLL,
192 };
193
194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
205 },
206 .find_pll = intel_g4x_find_best_PLL,
207 };
208
209 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
220 },
221 .find_pll = intel_g4x_find_best_PLL,
222 };
223
224 static const intel_limit_t intel_limits_g4x_display_port = {
225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
235 .find_pll = intel_find_pll_g4x_dp,
236 };
237
238 static const intel_limit_t intel_limits_pineview_sdvo = {
239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
251 .find_pll = intel_find_best_PLL,
252 };
253
254 static const intel_limit_t intel_limits_pineview_lvds = {
255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
265 .find_pll = intel_find_best_PLL,
266 };
267
268 /* Ironlake / Sandybridge
269 *
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
272 */
273 static const intel_limit_t intel_limits_ironlake_dac = {
274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_g4x_find_best_PLL,
285 };
286
287 static const intel_limit_t intel_limits_ironlake_single_lvds = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_g4x_find_best_PLL,
299 };
300
301 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
312 .find_pll = intel_g4x_find_best_PLL,
313 };
314
315 /* LVDS 100mhz refclk limits. */
316 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 .find_pll = intel_g4x_find_best_PLL,
328 };
329
330 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341 .find_pll = intel_g4x_find_best_PLL,
342 };
343
344 static const intel_limit_t intel_limits_ironlake_display_port = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
355 .find_pll = intel_find_pll_ironlake_dp,
356 };
357
358 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359 int refclk)
360 {
361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
363 const intel_limit_t *limit;
364
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
369 if (refclk == 100000)
370 limit = &intel_limits_ironlake_dual_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_dual_lvds;
373 } else {
374 if (refclk == 100000)
375 limit = &intel_limits_ironlake_single_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_single_lvds;
378 }
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
380 HAS_eDP)
381 limit = &intel_limits_ironlake_display_port;
382 else
383 limit = &intel_limits_ironlake_dac;
384
385 return limit;
386 }
387
388 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
389 {
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
393
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
396 LVDS_CLKB_POWER_UP)
397 /* LVDS with dual channel */
398 limit = &intel_limits_g4x_dual_channel_lvds;
399 else
400 /* LVDS with dual channel */
401 limit = &intel_limits_g4x_single_channel_lvds;
402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
404 limit = &intel_limits_g4x_hdmi;
405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
406 limit = &intel_limits_g4x_sdvo;
407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
408 limit = &intel_limits_g4x_display_port;
409 } else /* The option is for other outputs */
410 limit = &intel_limits_i9xx_sdvo;
411
412 return limit;
413 }
414
415 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
416 {
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
419
420 if (HAS_PCH_SPLIT(dev))
421 limit = intel_ironlake_limit(crtc, refclk);
422 else if (IS_G4X(dev)) {
423 limit = intel_g4x_limit(crtc);
424 } else if (IS_PINEVIEW(dev)) {
425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
426 limit = &intel_limits_pineview_lvds;
427 else
428 limit = &intel_limits_pineview_sdvo;
429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
432 else
433 limit = &intel_limits_i9xx_sdvo;
434 } else {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i8xx_lvds;
437 else
438 limit = &intel_limits_i8xx_dvo;
439 }
440 return limit;
441 }
442
443 /* m1 is reserved as 0 in Pineview, n is a ring counter */
444 static void pineview_clock(int refclk, intel_clock_t *clock)
445 {
446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
450 }
451
452 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
453 {
454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
456 return;
457 }
458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
462 }
463
464 /**
465 * Returns whether any output on the specified pipe is of the specified type
466 */
467 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
468 {
469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
472
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
475 return true;
476
477 return false;
478 }
479
480 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
481 /**
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
484 */
485
486 static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
489 {
490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
508 */
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
511
512 return true;
513 }
514
515 static bool
516 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
518
519 {
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
522 intel_clock_t clock;
523 int err = target;
524
525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
526 (I915_READ(LVDS)) != 0) {
527 /*
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
531 * even can.
532 */
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534 LVDS_CLKB_POWER_UP)
535 clock.p2 = limit->p2.p2_fast;
536 else
537 clock.p2 = limit->p2.p2_slow;
538 } else {
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
541 else
542 clock.p2 = limit->p2.p2_fast;
543 }
544
545 memset (best_clock, 0, sizeof (*best_clock));
546
547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548 clock.m1++) {
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
553 break;
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
558 int this_err;
559
560 intel_clock(dev, refclk, &clock);
561 if (!intel_PLL_is_valid(dev, limit,
562 &clock))
563 continue;
564
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
567 *best_clock = clock;
568 err = this_err;
569 }
570 }
571 }
572 }
573 }
574
575 return (err != target);
576 }
577
578 static bool
579 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
581 {
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 intel_clock_t clock;
585 int max_n;
586 bool found;
587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
589 found = false;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
592 int lvds_reg;
593
594 if (HAS_PCH_SPLIT(dev))
595 lvds_reg = PCH_LVDS;
596 else
597 lvds_reg = LVDS;
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
599 LVDS_CLKB_POWER_UP)
600 clock.p2 = limit->p2.p2_fast;
601 else
602 clock.p2 = limit->p2.p2_slow;
603 } else {
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
606 else
607 clock.p2 = limit->p2.p2_fast;
608 }
609
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
612 /* based on hardware requirement, prefer smaller n to precision */
613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
614 /* based on hardware requirement, prefere larger m1,m2 */
615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
621 int this_err;
622
623 intel_clock(dev, refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627
628 this_err = abs(clock.dot - target);
629 if (this_err < err_most) {
630 *best_clock = clock;
631 err_most = this_err;
632 max_n = clock.n;
633 found = true;
634 }
635 }
636 }
637 }
638 }
639 return found;
640 }
641
642 static bool
643 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
645 {
646 struct drm_device *dev = crtc->dev;
647 intel_clock_t clock;
648
649 if (target < 200000) {
650 clock.n = 1;
651 clock.p1 = 2;
652 clock.p2 = 10;
653 clock.m1 = 12;
654 clock.m2 = 9;
655 } else {
656 clock.n = 2;
657 clock.p1 = 1;
658 clock.p2 = 10;
659 clock.m1 = 14;
660 clock.m2 = 8;
661 }
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
664 return true;
665 }
666
667 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
668 static bool
669 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
671 {
672 intel_clock_t clock;
673 if (target < 200000) {
674 clock.p1 = 2;
675 clock.p2 = 10;
676 clock.n = 2;
677 clock.m1 = 23;
678 clock.m2 = 8;
679 } else {
680 clock.p1 = 1;
681 clock.p2 = 10;
682 clock.n = 1;
683 clock.m1 = 14;
684 clock.m2 = 2;
685 }
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
689 clock.vco = 0;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
691 return true;
692 }
693
694 /**
695 * intel_wait_for_vblank - wait for vblank on a given pipe
696 * @dev: drm device
697 * @pipe: pipe to wait for
698 *
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
700 * mode setting code.
701 */
702 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
703 {
704 struct drm_i915_private *dev_priv = dev->dev_private;
705 int pipestat_reg = PIPESTAT(pipe);
706
707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
709 *
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
716 * vblanks...
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
719 */
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
722
723 /* Wait for vblank interrupt bit to set */
724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
726 50))
727 DRM_DEBUG_KMS("vblank wait timed out\n");
728 }
729
730 /*
731 * intel_wait_for_pipe_off - wait for pipe to turn off
732 * @dev: drm device
733 * @pipe: pipe to wait for
734 *
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
738 *
739 * On Gen4 and above:
740 * wait for the pipe register state bit to turn off
741 *
742 * Otherwise:
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
745 *
746 */
747 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
748 {
749 struct drm_i915_private *dev_priv = dev->dev_private;
750
751 if (INTEL_INFO(dev)->gen >= 4) {
752 int reg = PIPECONF(pipe);
753
754 /* Wait for the Pipe State to go off */
755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
756 100))
757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
758 } else {
759 u32 last_line;
760 int reg = PIPEDSL(pipe);
761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
762
763 /* Wait for the display line to settle */
764 do {
765 last_line = I915_READ(reg) & DSL_LINEMASK;
766 mdelay(5);
767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
771 }
772 }
773
774 static const char *state_string(bool enabled)
775 {
776 return enabled ? "on" : "off";
777 }
778
779 /* Only for pre-ILK configs */
780 static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
782 {
783 int reg;
784 u32 val;
785 bool cur_state;
786
787 reg = DPLL(pipe);
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
793 }
794 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
795 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
796
797 /* For ILK+ */
798 static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
800 {
801 int reg;
802 u32 val;
803 bool cur_state;
804
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
811 }
812 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814
815 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
817 {
818 int reg;
819 u32 val;
820 bool cur_state;
821
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
828 }
829 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831
832 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
834 {
835 int reg;
836 u32 val;
837 bool cur_state;
838
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
845 }
846 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848
849 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
850 enum pipe pipe)
851 {
852 int reg;
853 u32 val;
854
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
857 return;
858
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
862 }
863
864 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
865 enum pipe pipe)
866 {
867 int reg;
868 u32 val;
869
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
873 }
874
875 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
876 enum pipe pipe)
877 {
878 int pp_reg, lvds_reg;
879 u32 val;
880 enum pipe panel_pipe = PIPE_A;
881 bool locked = locked;
882
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
885 lvds_reg = PCH_LVDS;
886 } else {
887 pp_reg = PP_CONTROL;
888 lvds_reg = LVDS;
889 }
890
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
894 locked = false;
895
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
897 panel_pipe = PIPE_B;
898
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
901 pipe_name(pipe));
902 }
903
904 static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
906 {
907 int reg;
908 u32 val;
909 bool cur_state;
910
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
916 pipe_name(pipe), state_string(state), state_string(cur_state));
917 }
918 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
920
921 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
922 enum plane plane)
923 {
924 int reg;
925 u32 val;
926
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
931 plane_name(plane));
932 }
933
934 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
935 enum pipe pipe)
936 {
937 int reg, i;
938 u32 val;
939 int cur_pipe;
940
941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
943 return;
944
945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
947 reg = DSPCNTR(i);
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
954 }
955 }
956
957 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
958 {
959 u32 val;
960 bool enabled;
961
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
966 }
967
968 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
969 enum pipe pipe)
970 {
971 int reg;
972 u32 val;
973 bool enabled;
974
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
978 WARN(enabled,
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
980 pipe_name(pipe));
981 }
982
983 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
984 enum pipe pipe, int reg)
985 {
986 u32 val = I915_READ(reg);
987 WARN(DP_PIPE_ENABLED(val, pipe),
988 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
989 reg, pipe_name(pipe));
990 }
991
992 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe, int reg)
994 {
995 u32 val = I915_READ(reg);
996 WARN(HDMI_PIPE_ENABLED(val, pipe),
997 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
998 reg, pipe_name(pipe));
999 }
1000
1001 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003 {
1004 int reg;
1005 u32 val;
1006
1007 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1010
1011 reg = PCH_ADPA;
1012 val = I915_READ(reg);
1013 WARN(ADPA_PIPE_ENABLED(val, pipe),
1014 "PCH VGA enabled on transcoder %c, should be disabled\n",
1015 pipe_name(pipe));
1016
1017 reg = PCH_LVDS;
1018 val = I915_READ(reg);
1019 WARN(LVDS_PIPE_ENABLED(val, pipe),
1020 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1021 pipe_name(pipe));
1022
1023 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1026 }
1027
1028 /**
1029 * intel_enable_pll - enable a PLL
1030 * @dev_priv: i915 private structure
1031 * @pipe: pipe PLL to enable
1032 *
1033 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1034 * make sure the PLL reg is writable first though, since the panel write
1035 * protect mechanism may be enabled.
1036 *
1037 * Note! This is for pre-ILK only.
1038 */
1039 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1040 {
1041 int reg;
1042 u32 val;
1043
1044 /* No really, not for ILK+ */
1045 BUG_ON(dev_priv->info->gen >= 5);
1046
1047 /* PLL is protected by panel, make sure we can write it */
1048 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049 assert_panel_unlocked(dev_priv, pipe);
1050
1051 reg = DPLL(pipe);
1052 val = I915_READ(reg);
1053 val |= DPLL_VCO_ENABLE;
1054
1055 /* We do this three times for luck */
1056 I915_WRITE(reg, val);
1057 POSTING_READ(reg);
1058 udelay(150); /* wait for warmup */
1059 I915_WRITE(reg, val);
1060 POSTING_READ(reg);
1061 udelay(150); /* wait for warmup */
1062 I915_WRITE(reg, val);
1063 POSTING_READ(reg);
1064 udelay(150); /* wait for warmup */
1065 }
1066
1067 /**
1068 * intel_disable_pll - disable a PLL
1069 * @dev_priv: i915 private structure
1070 * @pipe: pipe PLL to disable
1071 *
1072 * Disable the PLL for @pipe, making sure the pipe is off first.
1073 *
1074 * Note! This is for pre-ILK only.
1075 */
1076 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1077 {
1078 int reg;
1079 u32 val;
1080
1081 /* Don't disable pipe A or pipe A PLLs if needed */
1082 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1083 return;
1084
1085 /* Make sure the pipe isn't still relying on us */
1086 assert_pipe_disabled(dev_priv, pipe);
1087
1088 reg = DPLL(pipe);
1089 val = I915_READ(reg);
1090 val &= ~DPLL_VCO_ENABLE;
1091 I915_WRITE(reg, val);
1092 POSTING_READ(reg);
1093 }
1094
1095 /**
1096 * intel_enable_pch_pll - enable PCH PLL
1097 * @dev_priv: i915 private structure
1098 * @pipe: pipe PLL to enable
1099 *
1100 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101 * drives the transcoder clock.
1102 */
1103 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1104 enum pipe pipe)
1105 {
1106 int reg;
1107 u32 val;
1108
1109 /* PCH only available on ILK+ */
1110 BUG_ON(dev_priv->info->gen < 5);
1111
1112 /* PCH refclock must be enabled first */
1113 assert_pch_refclk_enabled(dev_priv);
1114
1115 reg = PCH_DPLL(pipe);
1116 val = I915_READ(reg);
1117 val |= DPLL_VCO_ENABLE;
1118 I915_WRITE(reg, val);
1119 POSTING_READ(reg);
1120 udelay(200);
1121 }
1122
1123 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe)
1125 {
1126 int reg;
1127 u32 val;
1128
1129 /* PCH only available on ILK+ */
1130 BUG_ON(dev_priv->info->gen < 5);
1131
1132 /* Make sure transcoder isn't still depending on us */
1133 assert_transcoder_disabled(dev_priv, pipe);
1134
1135 reg = PCH_DPLL(pipe);
1136 val = I915_READ(reg);
1137 val &= ~DPLL_VCO_ENABLE;
1138 I915_WRITE(reg, val);
1139 POSTING_READ(reg);
1140 udelay(200);
1141 }
1142
1143 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1144 enum pipe pipe)
1145 {
1146 int reg;
1147 u32 val;
1148
1149 /* PCH only available on ILK+ */
1150 BUG_ON(dev_priv->info->gen < 5);
1151
1152 /* Make sure PCH DPLL is enabled */
1153 assert_pch_pll_enabled(dev_priv, pipe);
1154
1155 /* FDI must be feeding us bits for PCH ports */
1156 assert_fdi_tx_enabled(dev_priv, pipe);
1157 assert_fdi_rx_enabled(dev_priv, pipe);
1158
1159 reg = TRANSCONF(pipe);
1160 val = I915_READ(reg);
1161
1162 if (HAS_PCH_IBX(dev_priv->dev)) {
1163 /*
1164 * make the BPC in transcoder be consistent with
1165 * that in pipeconf reg.
1166 */
1167 val &= ~PIPE_BPC_MASK;
1168 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1169 }
1170 I915_WRITE(reg, val | TRANS_ENABLE);
1171 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1172 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1173 }
1174
1175 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177 {
1178 int reg;
1179 u32 val;
1180
1181 /* FDI relies on the transcoder */
1182 assert_fdi_tx_disabled(dev_priv, pipe);
1183 assert_fdi_rx_disabled(dev_priv, pipe);
1184
1185 /* Ports must be off as well */
1186 assert_pch_ports_disabled(dev_priv, pipe);
1187
1188 reg = TRANSCONF(pipe);
1189 val = I915_READ(reg);
1190 val &= ~TRANS_ENABLE;
1191 I915_WRITE(reg, val);
1192 /* wait for PCH transcoder off, transcoder state */
1193 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1194 DRM_ERROR("failed to disable transcoder\n");
1195 }
1196
1197 /**
1198 * intel_enable_pipe - enable a pipe, asserting requirements
1199 * @dev_priv: i915 private structure
1200 * @pipe: pipe to enable
1201 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1202 *
1203 * Enable @pipe, making sure that various hardware specific requirements
1204 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1205 *
1206 * @pipe should be %PIPE_A or %PIPE_B.
1207 *
1208 * Will wait until the pipe is actually running (i.e. first vblank) before
1209 * returning.
1210 */
1211 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1212 bool pch_port)
1213 {
1214 int reg;
1215 u32 val;
1216
1217 /*
1218 * A pipe without a PLL won't actually be able to drive bits from
1219 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1220 * need the check.
1221 */
1222 if (!HAS_PCH_SPLIT(dev_priv->dev))
1223 assert_pll_enabled(dev_priv, pipe);
1224 else {
1225 if (pch_port) {
1226 /* if driving the PCH, we need FDI enabled */
1227 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1228 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1229 }
1230 /* FIXME: assert CPU port conditions for SNB+ */
1231 }
1232
1233 reg = PIPECONF(pipe);
1234 val = I915_READ(reg);
1235 if (val & PIPECONF_ENABLE)
1236 return;
1237
1238 I915_WRITE(reg, val | PIPECONF_ENABLE);
1239 intel_wait_for_vblank(dev_priv->dev, pipe);
1240 }
1241
1242 /**
1243 * intel_disable_pipe - disable a pipe, asserting requirements
1244 * @dev_priv: i915 private structure
1245 * @pipe: pipe to disable
1246 *
1247 * Disable @pipe, making sure that various hardware specific requirements
1248 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1249 *
1250 * @pipe should be %PIPE_A or %PIPE_B.
1251 *
1252 * Will wait until the pipe has shut down before returning.
1253 */
1254 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256 {
1257 int reg;
1258 u32 val;
1259
1260 /*
1261 * Make sure planes won't keep trying to pump pixels to us,
1262 * or we might hang the display.
1263 */
1264 assert_planes_disabled(dev_priv, pipe);
1265
1266 /* Don't disable pipe A or pipe A PLLs if needed */
1267 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1268 return;
1269
1270 reg = PIPECONF(pipe);
1271 val = I915_READ(reg);
1272 if ((val & PIPECONF_ENABLE) == 0)
1273 return;
1274
1275 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1276 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1277 }
1278
1279 /**
1280 * intel_enable_plane - enable a display plane on a given pipe
1281 * @dev_priv: i915 private structure
1282 * @plane: plane to enable
1283 * @pipe: pipe being fed
1284 *
1285 * Enable @plane on @pipe, making sure that @pipe is running first.
1286 */
1287 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1288 enum plane plane, enum pipe pipe)
1289 {
1290 int reg;
1291 u32 val;
1292
1293 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1294 assert_pipe_enabled(dev_priv, pipe);
1295
1296 reg = DSPCNTR(plane);
1297 val = I915_READ(reg);
1298 if (val & DISPLAY_PLANE_ENABLE)
1299 return;
1300
1301 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1302 intel_wait_for_vblank(dev_priv->dev, pipe);
1303 }
1304
1305 /*
1306 * Plane regs are double buffered, going from enabled->disabled needs a
1307 * trigger in order to latch. The display address reg provides this.
1308 */
1309 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1310 enum plane plane)
1311 {
1312 u32 reg = DSPADDR(plane);
1313 I915_WRITE(reg, I915_READ(reg));
1314 }
1315
1316 /**
1317 * intel_disable_plane - disable a display plane
1318 * @dev_priv: i915 private structure
1319 * @plane: plane to disable
1320 * @pipe: pipe consuming the data
1321 *
1322 * Disable @plane; should be an independent operation.
1323 */
1324 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1325 enum plane plane, enum pipe pipe)
1326 {
1327 int reg;
1328 u32 val;
1329
1330 reg = DSPCNTR(plane);
1331 val = I915_READ(reg);
1332 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1333 return;
1334
1335 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1336 intel_flush_display_plane(dev_priv, plane);
1337 intel_wait_for_vblank(dev_priv->dev, pipe);
1338 }
1339
1340 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, int reg)
1342 {
1343 u32 val = I915_READ(reg);
1344 if (DP_PIPE_ENABLED(val, pipe))
1345 I915_WRITE(reg, val & ~DP_PORT_EN);
1346 }
1347
1348 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1349 enum pipe pipe, int reg)
1350 {
1351 u32 val = I915_READ(reg);
1352 if (HDMI_PIPE_ENABLED(val, pipe))
1353 I915_WRITE(reg, val & ~PORT_ENABLE);
1354 }
1355
1356 /* Disable any ports connected to this transcoder */
1357 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1358 enum pipe pipe)
1359 {
1360 u32 reg, val;
1361
1362 val = I915_READ(PCH_PP_CONTROL);
1363 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1364
1365 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1366 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1367 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1368
1369 reg = PCH_ADPA;
1370 val = I915_READ(reg);
1371 if (ADPA_PIPE_ENABLED(val, pipe))
1372 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1373
1374 reg = PCH_LVDS;
1375 val = I915_READ(reg);
1376 if (LVDS_PIPE_ENABLED(val, pipe)) {
1377 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1378 POSTING_READ(reg);
1379 udelay(100);
1380 }
1381
1382 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1383 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1384 disable_pch_hdmi(dev_priv, pipe, HDMID);
1385 }
1386
1387 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1388 {
1389 struct drm_device *dev = crtc->dev;
1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 struct drm_framebuffer *fb = crtc->fb;
1392 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1393 struct drm_i915_gem_object *obj = intel_fb->obj;
1394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1395 int plane, i;
1396 u32 fbc_ctl, fbc_ctl2;
1397
1398 if (fb->pitch == dev_priv->cfb_pitch &&
1399 obj->fence_reg == dev_priv->cfb_fence &&
1400 intel_crtc->plane == dev_priv->cfb_plane &&
1401 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1402 return;
1403
1404 i8xx_disable_fbc(dev);
1405
1406 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1407
1408 if (fb->pitch < dev_priv->cfb_pitch)
1409 dev_priv->cfb_pitch = fb->pitch;
1410
1411 /* FBC_CTL wants 64B units */
1412 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1413 dev_priv->cfb_fence = obj->fence_reg;
1414 dev_priv->cfb_plane = intel_crtc->plane;
1415 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1416
1417 /* Clear old tags */
1418 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1419 I915_WRITE(FBC_TAG + (i * 4), 0);
1420
1421 /* Set it up... */
1422 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1423 if (obj->tiling_mode != I915_TILING_NONE)
1424 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1425 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1426 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1427
1428 /* enable it... */
1429 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1430 if (IS_I945GM(dev))
1431 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1432 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1433 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1434 if (obj->tiling_mode != I915_TILING_NONE)
1435 fbc_ctl |= dev_priv->cfb_fence;
1436 I915_WRITE(FBC_CONTROL, fbc_ctl);
1437
1438 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1439 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1440 }
1441
1442 void i8xx_disable_fbc(struct drm_device *dev)
1443 {
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 u32 fbc_ctl;
1446
1447 /* Disable compression */
1448 fbc_ctl = I915_READ(FBC_CONTROL);
1449 if ((fbc_ctl & FBC_CTL_EN) == 0)
1450 return;
1451
1452 fbc_ctl &= ~FBC_CTL_EN;
1453 I915_WRITE(FBC_CONTROL, fbc_ctl);
1454
1455 /* Wait for compressing bit to clear */
1456 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1457 DRM_DEBUG_KMS("FBC idle timed out\n");
1458 return;
1459 }
1460
1461 DRM_DEBUG_KMS("disabled FBC\n");
1462 }
1463
1464 static bool i8xx_fbc_enabled(struct drm_device *dev)
1465 {
1466 struct drm_i915_private *dev_priv = dev->dev_private;
1467
1468 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1469 }
1470
1471 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1472 {
1473 struct drm_device *dev = crtc->dev;
1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 struct drm_framebuffer *fb = crtc->fb;
1476 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1477 struct drm_i915_gem_object *obj = intel_fb->obj;
1478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1479 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1480 unsigned long stall_watermark = 200;
1481 u32 dpfc_ctl;
1482
1483 dpfc_ctl = I915_READ(DPFC_CONTROL);
1484 if (dpfc_ctl & DPFC_CTL_EN) {
1485 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1486 dev_priv->cfb_fence == obj->fence_reg &&
1487 dev_priv->cfb_plane == intel_crtc->plane &&
1488 dev_priv->cfb_y == crtc->y)
1489 return;
1490
1491 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1492 intel_wait_for_vblank(dev, intel_crtc->pipe);
1493 }
1494
1495 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1496 dev_priv->cfb_fence = obj->fence_reg;
1497 dev_priv->cfb_plane = intel_crtc->plane;
1498 dev_priv->cfb_y = crtc->y;
1499
1500 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1501 if (obj->tiling_mode != I915_TILING_NONE) {
1502 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1503 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1504 } else {
1505 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1506 }
1507
1508 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1509 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1510 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1511 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1512
1513 /* enable it... */
1514 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1515
1516 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1517 }
1518
1519 void g4x_disable_fbc(struct drm_device *dev)
1520 {
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 u32 dpfc_ctl;
1523
1524 /* Disable compression */
1525 dpfc_ctl = I915_READ(DPFC_CONTROL);
1526 if (dpfc_ctl & DPFC_CTL_EN) {
1527 dpfc_ctl &= ~DPFC_CTL_EN;
1528 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1529
1530 DRM_DEBUG_KMS("disabled FBC\n");
1531 }
1532 }
1533
1534 static bool g4x_fbc_enabled(struct drm_device *dev)
1535 {
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537
1538 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1539 }
1540
1541 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1542 {
1543 struct drm_i915_private *dev_priv = dev->dev_private;
1544 u32 blt_ecoskpd;
1545
1546 /* Make sure blitter notifies FBC of writes */
1547 gen6_gt_force_wake_get(dev_priv);
1548 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1549 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1550 GEN6_BLITTER_LOCK_SHIFT;
1551 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1552 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1553 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1554 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1555 GEN6_BLITTER_LOCK_SHIFT);
1556 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1557 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1558 gen6_gt_force_wake_put(dev_priv);
1559 }
1560
1561 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1562 {
1563 struct drm_device *dev = crtc->dev;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565 struct drm_framebuffer *fb = crtc->fb;
1566 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1567 struct drm_i915_gem_object *obj = intel_fb->obj;
1568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1569 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1570 unsigned long stall_watermark = 200;
1571 u32 dpfc_ctl;
1572
1573 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1574 if (dpfc_ctl & DPFC_CTL_EN) {
1575 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1576 dev_priv->cfb_fence == obj->fence_reg &&
1577 dev_priv->cfb_plane == intel_crtc->plane &&
1578 dev_priv->cfb_offset == obj->gtt_offset &&
1579 dev_priv->cfb_y == crtc->y)
1580 return;
1581
1582 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1583 intel_wait_for_vblank(dev, intel_crtc->pipe);
1584 }
1585
1586 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1587 dev_priv->cfb_fence = obj->fence_reg;
1588 dev_priv->cfb_plane = intel_crtc->plane;
1589 dev_priv->cfb_offset = obj->gtt_offset;
1590 dev_priv->cfb_y = crtc->y;
1591
1592 dpfc_ctl &= DPFC_RESERVED;
1593 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1594 if (obj->tiling_mode != I915_TILING_NONE) {
1595 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1596 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1597 } else {
1598 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1599 }
1600
1601 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1602 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1603 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1604 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1605 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1606 /* enable it... */
1607 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1608
1609 if (IS_GEN6(dev)) {
1610 I915_WRITE(SNB_DPFC_CTL_SA,
1611 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1612 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1613 sandybridge_blit_fbc_update(dev);
1614 }
1615
1616 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1617 }
1618
1619 void ironlake_disable_fbc(struct drm_device *dev)
1620 {
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 u32 dpfc_ctl;
1623
1624 /* Disable compression */
1625 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1626 if (dpfc_ctl & DPFC_CTL_EN) {
1627 dpfc_ctl &= ~DPFC_CTL_EN;
1628 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1629
1630 DRM_DEBUG_KMS("disabled FBC\n");
1631 }
1632 }
1633
1634 static bool ironlake_fbc_enabled(struct drm_device *dev)
1635 {
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637
1638 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1639 }
1640
1641 bool intel_fbc_enabled(struct drm_device *dev)
1642 {
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644
1645 if (!dev_priv->display.fbc_enabled)
1646 return false;
1647
1648 return dev_priv->display.fbc_enabled(dev);
1649 }
1650
1651 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1652 {
1653 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1654
1655 if (!dev_priv->display.enable_fbc)
1656 return;
1657
1658 dev_priv->display.enable_fbc(crtc, interval);
1659 }
1660
1661 void intel_disable_fbc(struct drm_device *dev)
1662 {
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665 if (!dev_priv->display.disable_fbc)
1666 return;
1667
1668 dev_priv->display.disable_fbc(dev);
1669 }
1670
1671 /**
1672 * intel_update_fbc - enable/disable FBC as needed
1673 * @dev: the drm_device
1674 *
1675 * Set up the framebuffer compression hardware at mode set time. We
1676 * enable it if possible:
1677 * - plane A only (on pre-965)
1678 * - no pixel mulitply/line duplication
1679 * - no alpha buffer discard
1680 * - no dual wide
1681 * - framebuffer <= 2048 in width, 1536 in height
1682 *
1683 * We can't assume that any compression will take place (worst case),
1684 * so the compressed buffer has to be the same size as the uncompressed
1685 * one. It also must reside (along with the line length buffer) in
1686 * stolen memory.
1687 *
1688 * We need to enable/disable FBC on a global basis.
1689 */
1690 static void intel_update_fbc(struct drm_device *dev)
1691 {
1692 struct drm_i915_private *dev_priv = dev->dev_private;
1693 struct drm_crtc *crtc = NULL, *tmp_crtc;
1694 struct intel_crtc *intel_crtc;
1695 struct drm_framebuffer *fb;
1696 struct intel_framebuffer *intel_fb;
1697 struct drm_i915_gem_object *obj;
1698
1699 DRM_DEBUG_KMS("\n");
1700
1701 if (!i915_powersave)
1702 return;
1703
1704 if (!I915_HAS_FBC(dev))
1705 return;
1706
1707 /*
1708 * If FBC is already on, we just have to verify that we can
1709 * keep it that way...
1710 * Need to disable if:
1711 * - more than one pipe is active
1712 * - changing FBC params (stride, fence, mode)
1713 * - new fb is too large to fit in compressed buffer
1714 * - going to an unsupported config (interlace, pixel multiply, etc.)
1715 */
1716 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1717 if (tmp_crtc->enabled && tmp_crtc->fb) {
1718 if (crtc) {
1719 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1720 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1721 goto out_disable;
1722 }
1723 crtc = tmp_crtc;
1724 }
1725 }
1726
1727 if (!crtc || crtc->fb == NULL) {
1728 DRM_DEBUG_KMS("no output, disabling\n");
1729 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1730 goto out_disable;
1731 }
1732
1733 intel_crtc = to_intel_crtc(crtc);
1734 fb = crtc->fb;
1735 intel_fb = to_intel_framebuffer(fb);
1736 obj = intel_fb->obj;
1737
1738 if (!i915_enable_fbc) {
1739 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1740 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1741 goto out_disable;
1742 }
1743 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1744 DRM_DEBUG_KMS("framebuffer too large, disabling "
1745 "compression\n");
1746 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1747 goto out_disable;
1748 }
1749 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1750 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1751 DRM_DEBUG_KMS("mode incompatible with compression, "
1752 "disabling\n");
1753 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1754 goto out_disable;
1755 }
1756 if ((crtc->mode.hdisplay > 2048) ||
1757 (crtc->mode.vdisplay > 1536)) {
1758 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1759 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1760 goto out_disable;
1761 }
1762 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1763 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1764 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1765 goto out_disable;
1766 }
1767 if (obj->tiling_mode != I915_TILING_X) {
1768 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1769 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1770 goto out_disable;
1771 }
1772
1773 /* If the kernel debugger is active, always disable compression */
1774 if (in_dbg_master())
1775 goto out_disable;
1776
1777 intel_enable_fbc(crtc, 500);
1778 return;
1779
1780 out_disable:
1781 /* Multiple disables should be harmless */
1782 if (intel_fbc_enabled(dev)) {
1783 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1784 intel_disable_fbc(dev);
1785 }
1786 }
1787
1788 int
1789 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1790 struct drm_i915_gem_object *obj,
1791 struct intel_ring_buffer *pipelined)
1792 {
1793 struct drm_i915_private *dev_priv = dev->dev_private;
1794 u32 alignment;
1795 int ret;
1796
1797 switch (obj->tiling_mode) {
1798 case I915_TILING_NONE:
1799 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1800 alignment = 128 * 1024;
1801 else if (INTEL_INFO(dev)->gen >= 4)
1802 alignment = 4 * 1024;
1803 else
1804 alignment = 64 * 1024;
1805 break;
1806 case I915_TILING_X:
1807 /* pin() will align the object as required by fence */
1808 alignment = 0;
1809 break;
1810 case I915_TILING_Y:
1811 /* FIXME: Is this true? */
1812 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1813 return -EINVAL;
1814 default:
1815 BUG();
1816 }
1817
1818 dev_priv->mm.interruptible = false;
1819 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1820 if (ret)
1821 goto err_interruptible;
1822
1823 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1824 * fence, whereas 965+ only requires a fence if using
1825 * framebuffer compression. For simplicity, we always install
1826 * a fence as the cost is not that onerous.
1827 */
1828 if (obj->tiling_mode != I915_TILING_NONE) {
1829 ret = i915_gem_object_get_fence(obj, pipelined);
1830 if (ret)
1831 goto err_unpin;
1832 }
1833
1834 dev_priv->mm.interruptible = true;
1835 return 0;
1836
1837 err_unpin:
1838 i915_gem_object_unpin(obj);
1839 err_interruptible:
1840 dev_priv->mm.interruptible = true;
1841 return ret;
1842 }
1843
1844 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1845 static int
1846 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1847 int x, int y, enum mode_set_atomic state)
1848 {
1849 struct drm_device *dev = crtc->dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1852 struct intel_framebuffer *intel_fb;
1853 struct drm_i915_gem_object *obj;
1854 int plane = intel_crtc->plane;
1855 unsigned long Start, Offset;
1856 u32 dspcntr;
1857 u32 reg;
1858
1859 switch (plane) {
1860 case 0:
1861 case 1:
1862 break;
1863 default:
1864 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1865 return -EINVAL;
1866 }
1867
1868 intel_fb = to_intel_framebuffer(fb);
1869 obj = intel_fb->obj;
1870
1871 reg = DSPCNTR(plane);
1872 dspcntr = I915_READ(reg);
1873 /* Mask out pixel format bits in case we change it */
1874 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1875 switch (fb->bits_per_pixel) {
1876 case 8:
1877 dspcntr |= DISPPLANE_8BPP;
1878 break;
1879 case 16:
1880 if (fb->depth == 15)
1881 dspcntr |= DISPPLANE_15_16BPP;
1882 else
1883 dspcntr |= DISPPLANE_16BPP;
1884 break;
1885 case 24:
1886 case 32:
1887 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1888 break;
1889 default:
1890 DRM_ERROR("Unknown color depth\n");
1891 return -EINVAL;
1892 }
1893 if (INTEL_INFO(dev)->gen >= 4) {
1894 if (obj->tiling_mode != I915_TILING_NONE)
1895 dspcntr |= DISPPLANE_TILED;
1896 else
1897 dspcntr &= ~DISPPLANE_TILED;
1898 }
1899
1900 if (HAS_PCH_SPLIT(dev))
1901 /* must disable */
1902 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1903
1904 I915_WRITE(reg, dspcntr);
1905
1906 Start = obj->gtt_offset;
1907 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1908
1909 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1910 Start, Offset, x, y, fb->pitch);
1911 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1912 if (INTEL_INFO(dev)->gen >= 4) {
1913 I915_WRITE(DSPSURF(plane), Start);
1914 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1915 I915_WRITE(DSPADDR(plane), Offset);
1916 } else
1917 I915_WRITE(DSPADDR(plane), Start + Offset);
1918 POSTING_READ(reg);
1919
1920 intel_update_fbc(dev);
1921 intel_increase_pllclock(crtc);
1922
1923 return 0;
1924 }
1925
1926 static int
1927 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1928 struct drm_framebuffer *old_fb)
1929 {
1930 struct drm_device *dev = crtc->dev;
1931 struct drm_i915_master_private *master_priv;
1932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1933 int ret;
1934
1935 /* no fb bound */
1936 if (!crtc->fb) {
1937 DRM_DEBUG_KMS("No FB bound\n");
1938 return 0;
1939 }
1940
1941 switch (intel_crtc->plane) {
1942 case 0:
1943 case 1:
1944 break;
1945 default:
1946 return -EINVAL;
1947 }
1948
1949 mutex_lock(&dev->struct_mutex);
1950 ret = intel_pin_and_fence_fb_obj(dev,
1951 to_intel_framebuffer(crtc->fb)->obj,
1952 NULL);
1953 if (ret != 0) {
1954 mutex_unlock(&dev->struct_mutex);
1955 return ret;
1956 }
1957
1958 if (old_fb) {
1959 struct drm_i915_private *dev_priv = dev->dev_private;
1960 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1961
1962 wait_event(dev_priv->pending_flip_queue,
1963 atomic_read(&dev_priv->mm.wedged) ||
1964 atomic_read(&obj->pending_flip) == 0);
1965
1966 /* Big Hammer, we also need to ensure that any pending
1967 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1968 * current scanout is retired before unpinning the old
1969 * framebuffer.
1970 *
1971 * This should only fail upon a hung GPU, in which case we
1972 * can safely continue.
1973 */
1974 ret = i915_gem_object_finish_gpu(obj);
1975 (void) ret;
1976 }
1977
1978 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1979 LEAVE_ATOMIC_MODE_SET);
1980 if (ret) {
1981 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1982 mutex_unlock(&dev->struct_mutex);
1983 return ret;
1984 }
1985
1986 if (old_fb) {
1987 intel_wait_for_vblank(dev, intel_crtc->pipe);
1988 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1989 }
1990
1991 mutex_unlock(&dev->struct_mutex);
1992
1993 if (!dev->primary->master)
1994 return 0;
1995
1996 master_priv = dev->primary->master->driver_priv;
1997 if (!master_priv->sarea_priv)
1998 return 0;
1999
2000 if (intel_crtc->pipe) {
2001 master_priv->sarea_priv->pipeB_x = x;
2002 master_priv->sarea_priv->pipeB_y = y;
2003 } else {
2004 master_priv->sarea_priv->pipeA_x = x;
2005 master_priv->sarea_priv->pipeA_y = y;
2006 }
2007
2008 return 0;
2009 }
2010
2011 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2012 {
2013 struct drm_device *dev = crtc->dev;
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 u32 dpa_ctl;
2016
2017 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2018 dpa_ctl = I915_READ(DP_A);
2019 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2020
2021 if (clock < 200000) {
2022 u32 temp;
2023 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2024 /* workaround for 160Mhz:
2025 1) program 0x4600c bits 15:0 = 0x8124
2026 2) program 0x46010 bit 0 = 1
2027 3) program 0x46034 bit 24 = 1
2028 4) program 0x64000 bit 14 = 1
2029 */
2030 temp = I915_READ(0x4600c);
2031 temp &= 0xffff0000;
2032 I915_WRITE(0x4600c, temp | 0x8124);
2033
2034 temp = I915_READ(0x46010);
2035 I915_WRITE(0x46010, temp | 1);
2036
2037 temp = I915_READ(0x46034);
2038 I915_WRITE(0x46034, temp | (1 << 24));
2039 } else {
2040 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2041 }
2042 I915_WRITE(DP_A, dpa_ctl);
2043
2044 POSTING_READ(DP_A);
2045 udelay(500);
2046 }
2047
2048 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2049 {
2050 struct drm_device *dev = crtc->dev;
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2053 int pipe = intel_crtc->pipe;
2054 u32 reg, temp;
2055
2056 /* enable normal train */
2057 reg = FDI_TX_CTL(pipe);
2058 temp = I915_READ(reg);
2059 if (IS_IVYBRIDGE(dev)) {
2060 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2061 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2062 } else {
2063 temp &= ~FDI_LINK_TRAIN_NONE;
2064 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2065 }
2066 I915_WRITE(reg, temp);
2067
2068 reg = FDI_RX_CTL(pipe);
2069 temp = I915_READ(reg);
2070 if (HAS_PCH_CPT(dev)) {
2071 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2072 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2073 } else {
2074 temp &= ~FDI_LINK_TRAIN_NONE;
2075 temp |= FDI_LINK_TRAIN_NONE;
2076 }
2077 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2078
2079 /* wait one idle pattern time */
2080 POSTING_READ(reg);
2081 udelay(1000);
2082
2083 /* IVB wants error correction enabled */
2084 if (IS_IVYBRIDGE(dev))
2085 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2086 FDI_FE_ERRC_ENABLE);
2087 }
2088
2089 /* The FDI link training functions for ILK/Ibexpeak. */
2090 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2091 {
2092 struct drm_device *dev = crtc->dev;
2093 struct drm_i915_private *dev_priv = dev->dev_private;
2094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095 int pipe = intel_crtc->pipe;
2096 int plane = intel_crtc->plane;
2097 u32 reg, temp, tries;
2098
2099 /* FDI needs bits from pipe & plane first */
2100 assert_pipe_enabled(dev_priv, pipe);
2101 assert_plane_enabled(dev_priv, plane);
2102
2103 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2104 for train result */
2105 reg = FDI_RX_IMR(pipe);
2106 temp = I915_READ(reg);
2107 temp &= ~FDI_RX_SYMBOL_LOCK;
2108 temp &= ~FDI_RX_BIT_LOCK;
2109 I915_WRITE(reg, temp);
2110 I915_READ(reg);
2111 udelay(150);
2112
2113 /* enable CPU FDI TX and PCH FDI RX */
2114 reg = FDI_TX_CTL(pipe);
2115 temp = I915_READ(reg);
2116 temp &= ~(7 << 19);
2117 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2118 temp &= ~FDI_LINK_TRAIN_NONE;
2119 temp |= FDI_LINK_TRAIN_PATTERN_1;
2120 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2121
2122 reg = FDI_RX_CTL(pipe);
2123 temp = I915_READ(reg);
2124 temp &= ~FDI_LINK_TRAIN_NONE;
2125 temp |= FDI_LINK_TRAIN_PATTERN_1;
2126 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2127
2128 POSTING_READ(reg);
2129 udelay(150);
2130
2131 /* Ironlake workaround, enable clock pointer after FDI enable*/
2132 if (HAS_PCH_IBX(dev)) {
2133 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2134 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2135 FDI_RX_PHASE_SYNC_POINTER_EN);
2136 }
2137
2138 reg = FDI_RX_IIR(pipe);
2139 for (tries = 0; tries < 5; tries++) {
2140 temp = I915_READ(reg);
2141 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2142
2143 if ((temp & FDI_RX_BIT_LOCK)) {
2144 DRM_DEBUG_KMS("FDI train 1 done.\n");
2145 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2146 break;
2147 }
2148 }
2149 if (tries == 5)
2150 DRM_ERROR("FDI train 1 fail!\n");
2151
2152 /* Train 2 */
2153 reg = FDI_TX_CTL(pipe);
2154 temp = I915_READ(reg);
2155 temp &= ~FDI_LINK_TRAIN_NONE;
2156 temp |= FDI_LINK_TRAIN_PATTERN_2;
2157 I915_WRITE(reg, temp);
2158
2159 reg = FDI_RX_CTL(pipe);
2160 temp = I915_READ(reg);
2161 temp &= ~FDI_LINK_TRAIN_NONE;
2162 temp |= FDI_LINK_TRAIN_PATTERN_2;
2163 I915_WRITE(reg, temp);
2164
2165 POSTING_READ(reg);
2166 udelay(150);
2167
2168 reg = FDI_RX_IIR(pipe);
2169 for (tries = 0; tries < 5; tries++) {
2170 temp = I915_READ(reg);
2171 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2172
2173 if (temp & FDI_RX_SYMBOL_LOCK) {
2174 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2175 DRM_DEBUG_KMS("FDI train 2 done.\n");
2176 break;
2177 }
2178 }
2179 if (tries == 5)
2180 DRM_ERROR("FDI train 2 fail!\n");
2181
2182 DRM_DEBUG_KMS("FDI train done\n");
2183
2184 }
2185
2186 static const int snb_b_fdi_train_param [] = {
2187 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2188 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2189 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2190 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2191 };
2192
2193 /* The FDI link training functions for SNB/Cougarpoint. */
2194 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2195 {
2196 struct drm_device *dev = crtc->dev;
2197 struct drm_i915_private *dev_priv = dev->dev_private;
2198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2199 int pipe = intel_crtc->pipe;
2200 u32 reg, temp, i;
2201
2202 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2203 for train result */
2204 reg = FDI_RX_IMR(pipe);
2205 temp = I915_READ(reg);
2206 temp &= ~FDI_RX_SYMBOL_LOCK;
2207 temp &= ~FDI_RX_BIT_LOCK;
2208 I915_WRITE(reg, temp);
2209
2210 POSTING_READ(reg);
2211 udelay(150);
2212
2213 /* enable CPU FDI TX and PCH FDI RX */
2214 reg = FDI_TX_CTL(pipe);
2215 temp = I915_READ(reg);
2216 temp &= ~(7 << 19);
2217 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2218 temp &= ~FDI_LINK_TRAIN_NONE;
2219 temp |= FDI_LINK_TRAIN_PATTERN_1;
2220 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2221 /* SNB-B */
2222 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2223 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2224
2225 reg = FDI_RX_CTL(pipe);
2226 temp = I915_READ(reg);
2227 if (HAS_PCH_CPT(dev)) {
2228 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2229 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2230 } else {
2231 temp &= ~FDI_LINK_TRAIN_NONE;
2232 temp |= FDI_LINK_TRAIN_PATTERN_1;
2233 }
2234 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2235
2236 POSTING_READ(reg);
2237 udelay(150);
2238
2239 for (i = 0; i < 4; i++ ) {
2240 reg = FDI_TX_CTL(pipe);
2241 temp = I915_READ(reg);
2242 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2243 temp |= snb_b_fdi_train_param[i];
2244 I915_WRITE(reg, temp);
2245
2246 POSTING_READ(reg);
2247 udelay(500);
2248
2249 reg = FDI_RX_IIR(pipe);
2250 temp = I915_READ(reg);
2251 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2252
2253 if (temp & FDI_RX_BIT_LOCK) {
2254 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2255 DRM_DEBUG_KMS("FDI train 1 done.\n");
2256 break;
2257 }
2258 }
2259 if (i == 4)
2260 DRM_ERROR("FDI train 1 fail!\n");
2261
2262 /* Train 2 */
2263 reg = FDI_TX_CTL(pipe);
2264 temp = I915_READ(reg);
2265 temp &= ~FDI_LINK_TRAIN_NONE;
2266 temp |= FDI_LINK_TRAIN_PATTERN_2;
2267 if (IS_GEN6(dev)) {
2268 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2269 /* SNB-B */
2270 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2271 }
2272 I915_WRITE(reg, temp);
2273
2274 reg = FDI_RX_CTL(pipe);
2275 temp = I915_READ(reg);
2276 if (HAS_PCH_CPT(dev)) {
2277 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2278 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2279 } else {
2280 temp &= ~FDI_LINK_TRAIN_NONE;
2281 temp |= FDI_LINK_TRAIN_PATTERN_2;
2282 }
2283 I915_WRITE(reg, temp);
2284
2285 POSTING_READ(reg);
2286 udelay(150);
2287
2288 for (i = 0; i < 4; i++ ) {
2289 reg = FDI_TX_CTL(pipe);
2290 temp = I915_READ(reg);
2291 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2292 temp |= snb_b_fdi_train_param[i];
2293 I915_WRITE(reg, temp);
2294
2295 POSTING_READ(reg);
2296 udelay(500);
2297
2298 reg = FDI_RX_IIR(pipe);
2299 temp = I915_READ(reg);
2300 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2301
2302 if (temp & FDI_RX_SYMBOL_LOCK) {
2303 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2304 DRM_DEBUG_KMS("FDI train 2 done.\n");
2305 break;
2306 }
2307 }
2308 if (i == 4)
2309 DRM_ERROR("FDI train 2 fail!\n");
2310
2311 DRM_DEBUG_KMS("FDI train done.\n");
2312 }
2313
2314 /* Manual link training for Ivy Bridge A0 parts */
2315 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2316 {
2317 struct drm_device *dev = crtc->dev;
2318 struct drm_i915_private *dev_priv = dev->dev_private;
2319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2320 int pipe = intel_crtc->pipe;
2321 u32 reg, temp, i;
2322
2323 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2324 for train result */
2325 reg = FDI_RX_IMR(pipe);
2326 temp = I915_READ(reg);
2327 temp &= ~FDI_RX_SYMBOL_LOCK;
2328 temp &= ~FDI_RX_BIT_LOCK;
2329 I915_WRITE(reg, temp);
2330
2331 POSTING_READ(reg);
2332 udelay(150);
2333
2334 /* enable CPU FDI TX and PCH FDI RX */
2335 reg = FDI_TX_CTL(pipe);
2336 temp = I915_READ(reg);
2337 temp &= ~(7 << 19);
2338 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2339 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2340 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2341 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2342 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2343 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2344
2345 reg = FDI_RX_CTL(pipe);
2346 temp = I915_READ(reg);
2347 temp &= ~FDI_LINK_TRAIN_AUTO;
2348 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2349 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2350 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2351
2352 POSTING_READ(reg);
2353 udelay(150);
2354
2355 for (i = 0; i < 4; i++ ) {
2356 reg = FDI_TX_CTL(pipe);
2357 temp = I915_READ(reg);
2358 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2359 temp |= snb_b_fdi_train_param[i];
2360 I915_WRITE(reg, temp);
2361
2362 POSTING_READ(reg);
2363 udelay(500);
2364
2365 reg = FDI_RX_IIR(pipe);
2366 temp = I915_READ(reg);
2367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2368
2369 if (temp & FDI_RX_BIT_LOCK ||
2370 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2371 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
2373 break;
2374 }
2375 }
2376 if (i == 4)
2377 DRM_ERROR("FDI train 1 fail!\n");
2378
2379 /* Train 2 */
2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
2382 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2383 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2384 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2385 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2386 I915_WRITE(reg, temp);
2387
2388 reg = FDI_RX_CTL(pipe);
2389 temp = I915_READ(reg);
2390 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2391 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2392 I915_WRITE(reg, temp);
2393
2394 POSTING_READ(reg);
2395 udelay(150);
2396
2397 for (i = 0; i < 4; i++ ) {
2398 reg = FDI_TX_CTL(pipe);
2399 temp = I915_READ(reg);
2400 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2401 temp |= snb_b_fdi_train_param[i];
2402 I915_WRITE(reg, temp);
2403
2404 POSTING_READ(reg);
2405 udelay(500);
2406
2407 reg = FDI_RX_IIR(pipe);
2408 temp = I915_READ(reg);
2409 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2410
2411 if (temp & FDI_RX_SYMBOL_LOCK) {
2412 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2413 DRM_DEBUG_KMS("FDI train 2 done.\n");
2414 break;
2415 }
2416 }
2417 if (i == 4)
2418 DRM_ERROR("FDI train 2 fail!\n");
2419
2420 DRM_DEBUG_KMS("FDI train done.\n");
2421 }
2422
2423 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2424 {
2425 struct drm_device *dev = crtc->dev;
2426 struct drm_i915_private *dev_priv = dev->dev_private;
2427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2428 int pipe = intel_crtc->pipe;
2429 u32 reg, temp;
2430
2431 /* Write the TU size bits so error detection works */
2432 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2433 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2434
2435 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 temp &= ~((0x7 << 19) | (0x7 << 16));
2439 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2440 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2441 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2442
2443 POSTING_READ(reg);
2444 udelay(200);
2445
2446 /* Switch from Rawclk to PCDclk */
2447 temp = I915_READ(reg);
2448 I915_WRITE(reg, temp | FDI_PCDCLK);
2449
2450 POSTING_READ(reg);
2451 udelay(200);
2452
2453 /* Enable CPU FDI TX PLL, always on for Ironlake */
2454 reg = FDI_TX_CTL(pipe);
2455 temp = I915_READ(reg);
2456 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2457 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2458
2459 POSTING_READ(reg);
2460 udelay(100);
2461 }
2462 }
2463
2464 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2465 {
2466 struct drm_device *dev = crtc->dev;
2467 struct drm_i915_private *dev_priv = dev->dev_private;
2468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2469 int pipe = intel_crtc->pipe;
2470 u32 reg, temp;
2471
2472 /* disable CPU FDI tx and PCH FDI rx */
2473 reg = FDI_TX_CTL(pipe);
2474 temp = I915_READ(reg);
2475 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2476 POSTING_READ(reg);
2477
2478 reg = FDI_RX_CTL(pipe);
2479 temp = I915_READ(reg);
2480 temp &= ~(0x7 << 16);
2481 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2482 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2483
2484 POSTING_READ(reg);
2485 udelay(100);
2486
2487 /* Ironlake workaround, disable clock pointer after downing FDI */
2488 if (HAS_PCH_IBX(dev)) {
2489 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2490 I915_WRITE(FDI_RX_CHICKEN(pipe),
2491 I915_READ(FDI_RX_CHICKEN(pipe) &
2492 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2493 }
2494
2495 /* still set train pattern 1 */
2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 temp &= ~FDI_LINK_TRAIN_NONE;
2499 temp |= FDI_LINK_TRAIN_PATTERN_1;
2500 I915_WRITE(reg, temp);
2501
2502 reg = FDI_RX_CTL(pipe);
2503 temp = I915_READ(reg);
2504 if (HAS_PCH_CPT(dev)) {
2505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2506 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2507 } else {
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 }
2511 /* BPC in FDI rx is consistent with that in PIPECONF */
2512 temp &= ~(0x07 << 16);
2513 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
2517 udelay(100);
2518 }
2519
2520 /*
2521 * When we disable a pipe, we need to clear any pending scanline wait events
2522 * to avoid hanging the ring, which we assume we are waiting on.
2523 */
2524 static void intel_clear_scanline_wait(struct drm_device *dev)
2525 {
2526 struct drm_i915_private *dev_priv = dev->dev_private;
2527 struct intel_ring_buffer *ring;
2528 u32 tmp;
2529
2530 if (IS_GEN2(dev))
2531 /* Can't break the hang on i8xx */
2532 return;
2533
2534 ring = LP_RING(dev_priv);
2535 tmp = I915_READ_CTL(ring);
2536 if (tmp & RING_WAIT)
2537 I915_WRITE_CTL(ring, tmp);
2538 }
2539
2540 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2541 {
2542 struct drm_i915_gem_object *obj;
2543 struct drm_i915_private *dev_priv;
2544
2545 if (crtc->fb == NULL)
2546 return;
2547
2548 obj = to_intel_framebuffer(crtc->fb)->obj;
2549 dev_priv = crtc->dev->dev_private;
2550 wait_event(dev_priv->pending_flip_queue,
2551 atomic_read(&obj->pending_flip) == 0);
2552 }
2553
2554 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2555 {
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_mode_config *mode_config = &dev->mode_config;
2558 struct intel_encoder *encoder;
2559
2560 /*
2561 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2562 * must be driven by its own crtc; no sharing is possible.
2563 */
2564 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2565 if (encoder->base.crtc != crtc)
2566 continue;
2567
2568 switch (encoder->type) {
2569 case INTEL_OUTPUT_EDP:
2570 if (!intel_encoder_is_pch_edp(&encoder->base))
2571 return false;
2572 continue;
2573 }
2574 }
2575
2576 return true;
2577 }
2578
2579 /*
2580 * Enable PCH resources required for PCH ports:
2581 * - PCH PLLs
2582 * - FDI training & RX/TX
2583 * - update transcoder timings
2584 * - DP transcoding bits
2585 * - transcoder
2586 */
2587 static void ironlake_pch_enable(struct drm_crtc *crtc)
2588 {
2589 struct drm_device *dev = crtc->dev;
2590 struct drm_i915_private *dev_priv = dev->dev_private;
2591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2592 int pipe = intel_crtc->pipe;
2593 u32 reg, temp;
2594
2595 /* For PCH output, training FDI link */
2596 dev_priv->display.fdi_link_train(crtc);
2597
2598 intel_enable_pch_pll(dev_priv, pipe);
2599
2600 if (HAS_PCH_CPT(dev)) {
2601 /* Be sure PCH DPLL SEL is set */
2602 temp = I915_READ(PCH_DPLL_SEL);
2603 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2604 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2605 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2606 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2607 I915_WRITE(PCH_DPLL_SEL, temp);
2608 }
2609
2610 /* set transcoder timing, panel must allow it */
2611 assert_panel_unlocked(dev_priv, pipe);
2612 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2613 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2614 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2615
2616 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2617 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2618 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2619
2620 intel_fdi_normal_train(crtc);
2621
2622 /* For PCH DP, enable TRANS_DP_CTL */
2623 if (HAS_PCH_CPT(dev) &&
2624 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2625 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2626 reg = TRANS_DP_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2629 TRANS_DP_SYNC_MASK |
2630 TRANS_DP_BPC_MASK);
2631 temp |= (TRANS_DP_OUTPUT_ENABLE |
2632 TRANS_DP_ENH_FRAMING);
2633 temp |= bpc << 9; /* same format but at 11:9 */
2634
2635 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2636 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2637 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2638 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2639
2640 switch (intel_trans_dp_port_sel(crtc)) {
2641 case PCH_DP_B:
2642 temp |= TRANS_DP_PORT_SEL_B;
2643 break;
2644 case PCH_DP_C:
2645 temp |= TRANS_DP_PORT_SEL_C;
2646 break;
2647 case PCH_DP_D:
2648 temp |= TRANS_DP_PORT_SEL_D;
2649 break;
2650 default:
2651 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2652 temp |= TRANS_DP_PORT_SEL_B;
2653 break;
2654 }
2655
2656 I915_WRITE(reg, temp);
2657 }
2658
2659 intel_enable_transcoder(dev_priv, pipe);
2660 }
2661
2662 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2663 {
2664 struct drm_device *dev = crtc->dev;
2665 struct drm_i915_private *dev_priv = dev->dev_private;
2666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2667 int pipe = intel_crtc->pipe;
2668 int plane = intel_crtc->plane;
2669 u32 temp;
2670 bool is_pch_port;
2671
2672 if (intel_crtc->active)
2673 return;
2674
2675 intel_crtc->active = true;
2676 intel_update_watermarks(dev);
2677
2678 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2679 temp = I915_READ(PCH_LVDS);
2680 if ((temp & LVDS_PORT_EN) == 0)
2681 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2682 }
2683
2684 is_pch_port = intel_crtc_driving_pch(crtc);
2685
2686 if (is_pch_port)
2687 ironlake_fdi_pll_enable(crtc);
2688 else
2689 ironlake_fdi_disable(crtc);
2690
2691 /* Enable panel fitting for LVDS */
2692 if (dev_priv->pch_pf_size &&
2693 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2694 /* Force use of hard-coded filter coefficients
2695 * as some pre-programmed values are broken,
2696 * e.g. x201.
2697 */
2698 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2699 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2700 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2701 }
2702
2703 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2704 intel_enable_plane(dev_priv, plane, pipe);
2705
2706 if (is_pch_port)
2707 ironlake_pch_enable(crtc);
2708
2709 intel_crtc_load_lut(crtc);
2710
2711 mutex_lock(&dev->struct_mutex);
2712 intel_update_fbc(dev);
2713 mutex_unlock(&dev->struct_mutex);
2714
2715 intel_crtc_update_cursor(crtc, true);
2716 }
2717
2718 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2719 {
2720 struct drm_device *dev = crtc->dev;
2721 struct drm_i915_private *dev_priv = dev->dev_private;
2722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2723 int pipe = intel_crtc->pipe;
2724 int plane = intel_crtc->plane;
2725 u32 reg, temp;
2726
2727 if (!intel_crtc->active)
2728 return;
2729
2730 intel_crtc_wait_for_pending_flips(crtc);
2731 drm_vblank_off(dev, pipe);
2732 intel_crtc_update_cursor(crtc, false);
2733
2734 intel_disable_plane(dev_priv, plane, pipe);
2735
2736 if (dev_priv->cfb_plane == plane &&
2737 dev_priv->display.disable_fbc)
2738 dev_priv->display.disable_fbc(dev);
2739
2740 intel_disable_pipe(dev_priv, pipe);
2741
2742 /* Disable PF */
2743 I915_WRITE(PF_CTL(pipe), 0);
2744 I915_WRITE(PF_WIN_SZ(pipe), 0);
2745
2746 ironlake_fdi_disable(crtc);
2747
2748 /* This is a horrible layering violation; we should be doing this in
2749 * the connector/encoder ->prepare instead, but we don't always have
2750 * enough information there about the config to know whether it will
2751 * actually be necessary or just cause undesired flicker.
2752 */
2753 intel_disable_pch_ports(dev_priv, pipe);
2754
2755 intel_disable_transcoder(dev_priv, pipe);
2756
2757 if (HAS_PCH_CPT(dev)) {
2758 /* disable TRANS_DP_CTL */
2759 reg = TRANS_DP_CTL(pipe);
2760 temp = I915_READ(reg);
2761 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2762 temp |= TRANS_DP_PORT_SEL_NONE;
2763 I915_WRITE(reg, temp);
2764
2765 /* disable DPLL_SEL */
2766 temp = I915_READ(PCH_DPLL_SEL);
2767 switch (pipe) {
2768 case 0:
2769 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2770 break;
2771 case 1:
2772 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2773 break;
2774 case 2:
2775 /* FIXME: manage transcoder PLLs? */
2776 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2777 break;
2778 default:
2779 BUG(); /* wtf */
2780 }
2781 I915_WRITE(PCH_DPLL_SEL, temp);
2782 }
2783
2784 /* disable PCH DPLL */
2785 intel_disable_pch_pll(dev_priv, pipe);
2786
2787 /* Switch from PCDclk to Rawclk */
2788 reg = FDI_RX_CTL(pipe);
2789 temp = I915_READ(reg);
2790 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2791
2792 /* Disable CPU FDI TX PLL */
2793 reg = FDI_TX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2796
2797 POSTING_READ(reg);
2798 udelay(100);
2799
2800 reg = FDI_RX_CTL(pipe);
2801 temp = I915_READ(reg);
2802 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2803
2804 /* Wait for the clocks to turn off. */
2805 POSTING_READ(reg);
2806 udelay(100);
2807
2808 intel_crtc->active = false;
2809 intel_update_watermarks(dev);
2810
2811 mutex_lock(&dev->struct_mutex);
2812 intel_update_fbc(dev);
2813 intel_clear_scanline_wait(dev);
2814 mutex_unlock(&dev->struct_mutex);
2815 }
2816
2817 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2818 {
2819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2820 int pipe = intel_crtc->pipe;
2821 int plane = intel_crtc->plane;
2822
2823 /* XXX: When our outputs are all unaware of DPMS modes other than off
2824 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2825 */
2826 switch (mode) {
2827 case DRM_MODE_DPMS_ON:
2828 case DRM_MODE_DPMS_STANDBY:
2829 case DRM_MODE_DPMS_SUSPEND:
2830 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2831 ironlake_crtc_enable(crtc);
2832 break;
2833
2834 case DRM_MODE_DPMS_OFF:
2835 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2836 ironlake_crtc_disable(crtc);
2837 break;
2838 }
2839 }
2840
2841 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2842 {
2843 if (!enable && intel_crtc->overlay) {
2844 struct drm_device *dev = intel_crtc->base.dev;
2845 struct drm_i915_private *dev_priv = dev->dev_private;
2846
2847 mutex_lock(&dev->struct_mutex);
2848 dev_priv->mm.interruptible = false;
2849 (void) intel_overlay_switch_off(intel_crtc->overlay);
2850 dev_priv->mm.interruptible = true;
2851 mutex_unlock(&dev->struct_mutex);
2852 }
2853
2854 /* Let userspace switch the overlay on again. In most cases userspace
2855 * has to recompute where to put it anyway.
2856 */
2857 }
2858
2859 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2860 {
2861 struct drm_device *dev = crtc->dev;
2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2864 int pipe = intel_crtc->pipe;
2865 int plane = intel_crtc->plane;
2866
2867 if (intel_crtc->active)
2868 return;
2869
2870 intel_crtc->active = true;
2871 intel_update_watermarks(dev);
2872
2873 intel_enable_pll(dev_priv, pipe);
2874 intel_enable_pipe(dev_priv, pipe, false);
2875 intel_enable_plane(dev_priv, plane, pipe);
2876
2877 intel_crtc_load_lut(crtc);
2878 intel_update_fbc(dev);
2879
2880 /* Give the overlay scaler a chance to enable if it's on this pipe */
2881 intel_crtc_dpms_overlay(intel_crtc, true);
2882 intel_crtc_update_cursor(crtc, true);
2883 }
2884
2885 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2886 {
2887 struct drm_device *dev = crtc->dev;
2888 struct drm_i915_private *dev_priv = dev->dev_private;
2889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2890 int pipe = intel_crtc->pipe;
2891 int plane = intel_crtc->plane;
2892
2893 if (!intel_crtc->active)
2894 return;
2895
2896 /* Give the overlay scaler a chance to disable if it's on this pipe */
2897 intel_crtc_wait_for_pending_flips(crtc);
2898 drm_vblank_off(dev, pipe);
2899 intel_crtc_dpms_overlay(intel_crtc, false);
2900 intel_crtc_update_cursor(crtc, false);
2901
2902 if (dev_priv->cfb_plane == plane &&
2903 dev_priv->display.disable_fbc)
2904 dev_priv->display.disable_fbc(dev);
2905
2906 intel_disable_plane(dev_priv, plane, pipe);
2907 intel_disable_pipe(dev_priv, pipe);
2908 intel_disable_pll(dev_priv, pipe);
2909
2910 intel_crtc->active = false;
2911 intel_update_fbc(dev);
2912 intel_update_watermarks(dev);
2913 intel_clear_scanline_wait(dev);
2914 }
2915
2916 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2917 {
2918 /* XXX: When our outputs are all unaware of DPMS modes other than off
2919 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2920 */
2921 switch (mode) {
2922 case DRM_MODE_DPMS_ON:
2923 case DRM_MODE_DPMS_STANDBY:
2924 case DRM_MODE_DPMS_SUSPEND:
2925 i9xx_crtc_enable(crtc);
2926 break;
2927 case DRM_MODE_DPMS_OFF:
2928 i9xx_crtc_disable(crtc);
2929 break;
2930 }
2931 }
2932
2933 /**
2934 * Sets the power management mode of the pipe and plane.
2935 */
2936 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2937 {
2938 struct drm_device *dev = crtc->dev;
2939 struct drm_i915_private *dev_priv = dev->dev_private;
2940 struct drm_i915_master_private *master_priv;
2941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2942 int pipe = intel_crtc->pipe;
2943 bool enabled;
2944
2945 if (intel_crtc->dpms_mode == mode)
2946 return;
2947
2948 intel_crtc->dpms_mode = mode;
2949
2950 dev_priv->display.dpms(crtc, mode);
2951
2952 if (!dev->primary->master)
2953 return;
2954
2955 master_priv = dev->primary->master->driver_priv;
2956 if (!master_priv->sarea_priv)
2957 return;
2958
2959 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2960
2961 switch (pipe) {
2962 case 0:
2963 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2964 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2965 break;
2966 case 1:
2967 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2968 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2969 break;
2970 default:
2971 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
2972 break;
2973 }
2974 }
2975
2976 static void intel_crtc_disable(struct drm_crtc *crtc)
2977 {
2978 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2979 struct drm_device *dev = crtc->dev;
2980
2981 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2982
2983 if (crtc->fb) {
2984 mutex_lock(&dev->struct_mutex);
2985 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2986 mutex_unlock(&dev->struct_mutex);
2987 }
2988 }
2989
2990 /* Prepare for a mode set.
2991 *
2992 * Note we could be a lot smarter here. We need to figure out which outputs
2993 * will be enabled, which disabled (in short, how the config will changes)
2994 * and perform the minimum necessary steps to accomplish that, e.g. updating
2995 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2996 * panel fitting is in the proper state, etc.
2997 */
2998 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2999 {
3000 i9xx_crtc_disable(crtc);
3001 }
3002
3003 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3004 {
3005 i9xx_crtc_enable(crtc);
3006 }
3007
3008 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3009 {
3010 ironlake_crtc_disable(crtc);
3011 }
3012
3013 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3014 {
3015 ironlake_crtc_enable(crtc);
3016 }
3017
3018 void intel_encoder_prepare (struct drm_encoder *encoder)
3019 {
3020 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3021 /* lvds has its own version of prepare see intel_lvds_prepare */
3022 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3023 }
3024
3025 void intel_encoder_commit (struct drm_encoder *encoder)
3026 {
3027 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3028 /* lvds has its own version of commit see intel_lvds_commit */
3029 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3030 }
3031
3032 void intel_encoder_destroy(struct drm_encoder *encoder)
3033 {
3034 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3035
3036 drm_encoder_cleanup(encoder);
3037 kfree(intel_encoder);
3038 }
3039
3040 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3041 struct drm_display_mode *mode,
3042 struct drm_display_mode *adjusted_mode)
3043 {
3044 struct drm_device *dev = crtc->dev;
3045
3046 if (HAS_PCH_SPLIT(dev)) {
3047 /* FDI link clock is fixed at 2.7G */
3048 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3049 return false;
3050 }
3051
3052 /* XXX some encoders set the crtcinfo, others don't.
3053 * Obviously we need some form of conflict resolution here...
3054 */
3055 if (adjusted_mode->crtc_htotal == 0)
3056 drm_mode_set_crtcinfo(adjusted_mode, 0);
3057
3058 return true;
3059 }
3060
3061 static int i945_get_display_clock_speed(struct drm_device *dev)
3062 {
3063 return 400000;
3064 }
3065
3066 static int i915_get_display_clock_speed(struct drm_device *dev)
3067 {
3068 return 333000;
3069 }
3070
3071 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3072 {
3073 return 200000;
3074 }
3075
3076 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3077 {
3078 u16 gcfgc = 0;
3079
3080 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3081
3082 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3083 return 133000;
3084 else {
3085 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3086 case GC_DISPLAY_CLOCK_333_MHZ:
3087 return 333000;
3088 default:
3089 case GC_DISPLAY_CLOCK_190_200_MHZ:
3090 return 190000;
3091 }
3092 }
3093 }
3094
3095 static int i865_get_display_clock_speed(struct drm_device *dev)
3096 {
3097 return 266000;
3098 }
3099
3100 static int i855_get_display_clock_speed(struct drm_device *dev)
3101 {
3102 u16 hpllcc = 0;
3103 /* Assume that the hardware is in the high speed state. This
3104 * should be the default.
3105 */
3106 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3107 case GC_CLOCK_133_200:
3108 case GC_CLOCK_100_200:
3109 return 200000;
3110 case GC_CLOCK_166_250:
3111 return 250000;
3112 case GC_CLOCK_100_133:
3113 return 133000;
3114 }
3115
3116 /* Shouldn't happen */
3117 return 0;
3118 }
3119
3120 static int i830_get_display_clock_speed(struct drm_device *dev)
3121 {
3122 return 133000;
3123 }
3124
3125 struct fdi_m_n {
3126 u32 tu;
3127 u32 gmch_m;
3128 u32 gmch_n;
3129 u32 link_m;
3130 u32 link_n;
3131 };
3132
3133 static void
3134 fdi_reduce_ratio(u32 *num, u32 *den)
3135 {
3136 while (*num > 0xffffff || *den > 0xffffff) {
3137 *num >>= 1;
3138 *den >>= 1;
3139 }
3140 }
3141
3142 static void
3143 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3144 int link_clock, struct fdi_m_n *m_n)
3145 {
3146 m_n->tu = 64; /* default size */
3147
3148 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3149 m_n->gmch_m = bits_per_pixel * pixel_clock;
3150 m_n->gmch_n = link_clock * nlanes * 8;
3151 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3152
3153 m_n->link_m = pixel_clock;
3154 m_n->link_n = link_clock;
3155 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3156 }
3157
3158
3159 struct intel_watermark_params {
3160 unsigned long fifo_size;
3161 unsigned long max_wm;
3162 unsigned long default_wm;
3163 unsigned long guard_size;
3164 unsigned long cacheline_size;
3165 };
3166
3167 /* Pineview has different values for various configs */
3168 static const struct intel_watermark_params pineview_display_wm = {
3169 PINEVIEW_DISPLAY_FIFO,
3170 PINEVIEW_MAX_WM,
3171 PINEVIEW_DFT_WM,
3172 PINEVIEW_GUARD_WM,
3173 PINEVIEW_FIFO_LINE_SIZE
3174 };
3175 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3176 PINEVIEW_DISPLAY_FIFO,
3177 PINEVIEW_MAX_WM,
3178 PINEVIEW_DFT_HPLLOFF_WM,
3179 PINEVIEW_GUARD_WM,
3180 PINEVIEW_FIFO_LINE_SIZE
3181 };
3182 static const struct intel_watermark_params pineview_cursor_wm = {
3183 PINEVIEW_CURSOR_FIFO,
3184 PINEVIEW_CURSOR_MAX_WM,
3185 PINEVIEW_CURSOR_DFT_WM,
3186 PINEVIEW_CURSOR_GUARD_WM,
3187 PINEVIEW_FIFO_LINE_SIZE,
3188 };
3189 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3190 PINEVIEW_CURSOR_FIFO,
3191 PINEVIEW_CURSOR_MAX_WM,
3192 PINEVIEW_CURSOR_DFT_WM,
3193 PINEVIEW_CURSOR_GUARD_WM,
3194 PINEVIEW_FIFO_LINE_SIZE
3195 };
3196 static const struct intel_watermark_params g4x_wm_info = {
3197 G4X_FIFO_SIZE,
3198 G4X_MAX_WM,
3199 G4X_MAX_WM,
3200 2,
3201 G4X_FIFO_LINE_SIZE,
3202 };
3203 static const struct intel_watermark_params g4x_cursor_wm_info = {
3204 I965_CURSOR_FIFO,
3205 I965_CURSOR_MAX_WM,
3206 I965_CURSOR_DFT_WM,
3207 2,
3208 G4X_FIFO_LINE_SIZE,
3209 };
3210 static const struct intel_watermark_params i965_cursor_wm_info = {
3211 I965_CURSOR_FIFO,
3212 I965_CURSOR_MAX_WM,
3213 I965_CURSOR_DFT_WM,
3214 2,
3215 I915_FIFO_LINE_SIZE,
3216 };
3217 static const struct intel_watermark_params i945_wm_info = {
3218 I945_FIFO_SIZE,
3219 I915_MAX_WM,
3220 1,
3221 2,
3222 I915_FIFO_LINE_SIZE
3223 };
3224 static const struct intel_watermark_params i915_wm_info = {
3225 I915_FIFO_SIZE,
3226 I915_MAX_WM,
3227 1,
3228 2,
3229 I915_FIFO_LINE_SIZE
3230 };
3231 static const struct intel_watermark_params i855_wm_info = {
3232 I855GM_FIFO_SIZE,
3233 I915_MAX_WM,
3234 1,
3235 2,
3236 I830_FIFO_LINE_SIZE
3237 };
3238 static const struct intel_watermark_params i830_wm_info = {
3239 I830_FIFO_SIZE,
3240 I915_MAX_WM,
3241 1,
3242 2,
3243 I830_FIFO_LINE_SIZE
3244 };
3245
3246 static const struct intel_watermark_params ironlake_display_wm_info = {
3247 ILK_DISPLAY_FIFO,
3248 ILK_DISPLAY_MAXWM,
3249 ILK_DISPLAY_DFTWM,
3250 2,
3251 ILK_FIFO_LINE_SIZE
3252 };
3253 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3254 ILK_CURSOR_FIFO,
3255 ILK_CURSOR_MAXWM,
3256 ILK_CURSOR_DFTWM,
3257 2,
3258 ILK_FIFO_LINE_SIZE
3259 };
3260 static const struct intel_watermark_params ironlake_display_srwm_info = {
3261 ILK_DISPLAY_SR_FIFO,
3262 ILK_DISPLAY_MAX_SRWM,
3263 ILK_DISPLAY_DFT_SRWM,
3264 2,
3265 ILK_FIFO_LINE_SIZE
3266 };
3267 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3268 ILK_CURSOR_SR_FIFO,
3269 ILK_CURSOR_MAX_SRWM,
3270 ILK_CURSOR_DFT_SRWM,
3271 2,
3272 ILK_FIFO_LINE_SIZE
3273 };
3274
3275 static const struct intel_watermark_params sandybridge_display_wm_info = {
3276 SNB_DISPLAY_FIFO,
3277 SNB_DISPLAY_MAXWM,
3278 SNB_DISPLAY_DFTWM,
3279 2,
3280 SNB_FIFO_LINE_SIZE
3281 };
3282 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3283 SNB_CURSOR_FIFO,
3284 SNB_CURSOR_MAXWM,
3285 SNB_CURSOR_DFTWM,
3286 2,
3287 SNB_FIFO_LINE_SIZE
3288 };
3289 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3290 SNB_DISPLAY_SR_FIFO,
3291 SNB_DISPLAY_MAX_SRWM,
3292 SNB_DISPLAY_DFT_SRWM,
3293 2,
3294 SNB_FIFO_LINE_SIZE
3295 };
3296 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3297 SNB_CURSOR_SR_FIFO,
3298 SNB_CURSOR_MAX_SRWM,
3299 SNB_CURSOR_DFT_SRWM,
3300 2,
3301 SNB_FIFO_LINE_SIZE
3302 };
3303
3304
3305 /**
3306 * intel_calculate_wm - calculate watermark level
3307 * @clock_in_khz: pixel clock
3308 * @wm: chip FIFO params
3309 * @pixel_size: display pixel size
3310 * @latency_ns: memory latency for the platform
3311 *
3312 * Calculate the watermark level (the level at which the display plane will
3313 * start fetching from memory again). Each chip has a different display
3314 * FIFO size and allocation, so the caller needs to figure that out and pass
3315 * in the correct intel_watermark_params structure.
3316 *
3317 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3318 * on the pixel size. When it reaches the watermark level, it'll start
3319 * fetching FIFO line sized based chunks from memory until the FIFO fills
3320 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3321 * will occur, and a display engine hang could result.
3322 */
3323 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3324 const struct intel_watermark_params *wm,
3325 int fifo_size,
3326 int pixel_size,
3327 unsigned long latency_ns)
3328 {
3329 long entries_required, wm_size;
3330
3331 /*
3332 * Note: we need to make sure we don't overflow for various clock &
3333 * latency values.
3334 * clocks go from a few thousand to several hundred thousand.
3335 * latency is usually a few thousand
3336 */
3337 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3338 1000;
3339 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3340
3341 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3342
3343 wm_size = fifo_size - (entries_required + wm->guard_size);
3344
3345 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3346
3347 /* Don't promote wm_size to unsigned... */
3348 if (wm_size > (long)wm->max_wm)
3349 wm_size = wm->max_wm;
3350 if (wm_size <= 0)
3351 wm_size = wm->default_wm;
3352 return wm_size;
3353 }
3354
3355 struct cxsr_latency {
3356 int is_desktop;
3357 int is_ddr3;
3358 unsigned long fsb_freq;
3359 unsigned long mem_freq;
3360 unsigned long display_sr;
3361 unsigned long display_hpll_disable;
3362 unsigned long cursor_sr;
3363 unsigned long cursor_hpll_disable;
3364 };
3365
3366 static const struct cxsr_latency cxsr_latency_table[] = {
3367 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3368 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3369 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3370 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3371 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3372
3373 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3374 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3375 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3376 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3377 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3378
3379 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3380 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3381 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3382 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3383 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3384
3385 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3386 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3387 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3388 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3389 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3390
3391 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3392 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3393 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3394 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3395 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3396
3397 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3398 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3399 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3400 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3401 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3402 };
3403
3404 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3405 int is_ddr3,
3406 int fsb,
3407 int mem)
3408 {
3409 const struct cxsr_latency *latency;
3410 int i;
3411
3412 if (fsb == 0 || mem == 0)
3413 return NULL;
3414
3415 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3416 latency = &cxsr_latency_table[i];
3417 if (is_desktop == latency->is_desktop &&
3418 is_ddr3 == latency->is_ddr3 &&
3419 fsb == latency->fsb_freq && mem == latency->mem_freq)
3420 return latency;
3421 }
3422
3423 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3424
3425 return NULL;
3426 }
3427
3428 static void pineview_disable_cxsr(struct drm_device *dev)
3429 {
3430 struct drm_i915_private *dev_priv = dev->dev_private;
3431
3432 /* deactivate cxsr */
3433 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3434 }
3435
3436 /*
3437 * Latency for FIFO fetches is dependent on several factors:
3438 * - memory configuration (speed, channels)
3439 * - chipset
3440 * - current MCH state
3441 * It can be fairly high in some situations, so here we assume a fairly
3442 * pessimal value. It's a tradeoff between extra memory fetches (if we
3443 * set this value too high, the FIFO will fetch frequently to stay full)
3444 * and power consumption (set it too low to save power and we might see
3445 * FIFO underruns and display "flicker").
3446 *
3447 * A value of 5us seems to be a good balance; safe for very low end
3448 * platforms but not overly aggressive on lower latency configs.
3449 */
3450 static const int latency_ns = 5000;
3451
3452 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3453 {
3454 struct drm_i915_private *dev_priv = dev->dev_private;
3455 uint32_t dsparb = I915_READ(DSPARB);
3456 int size;
3457
3458 size = dsparb & 0x7f;
3459 if (plane)
3460 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3461
3462 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3463 plane ? "B" : "A", size);
3464
3465 return size;
3466 }
3467
3468 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3469 {
3470 struct drm_i915_private *dev_priv = dev->dev_private;
3471 uint32_t dsparb = I915_READ(DSPARB);
3472 int size;
3473
3474 size = dsparb & 0x1ff;
3475 if (plane)
3476 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3477 size >>= 1; /* Convert to cachelines */
3478
3479 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3480 plane ? "B" : "A", size);
3481
3482 return size;
3483 }
3484
3485 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3486 {
3487 struct drm_i915_private *dev_priv = dev->dev_private;
3488 uint32_t dsparb = I915_READ(DSPARB);
3489 int size;
3490
3491 size = dsparb & 0x7f;
3492 size >>= 2; /* Convert to cachelines */
3493
3494 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3495 plane ? "B" : "A",
3496 size);
3497
3498 return size;
3499 }
3500
3501 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3502 {
3503 struct drm_i915_private *dev_priv = dev->dev_private;
3504 uint32_t dsparb = I915_READ(DSPARB);
3505 int size;
3506
3507 size = dsparb & 0x7f;
3508 size >>= 1; /* Convert to cachelines */
3509
3510 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3511 plane ? "B" : "A", size);
3512
3513 return size;
3514 }
3515
3516 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3517 {
3518 struct drm_crtc *crtc, *enabled = NULL;
3519
3520 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3521 if (crtc->enabled && crtc->fb) {
3522 if (enabled)
3523 return NULL;
3524 enabled = crtc;
3525 }
3526 }
3527
3528 return enabled;
3529 }
3530
3531 static void pineview_update_wm(struct drm_device *dev)
3532 {
3533 struct drm_i915_private *dev_priv = dev->dev_private;
3534 struct drm_crtc *crtc;
3535 const struct cxsr_latency *latency;
3536 u32 reg;
3537 unsigned long wm;
3538
3539 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3540 dev_priv->fsb_freq, dev_priv->mem_freq);
3541 if (!latency) {
3542 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3543 pineview_disable_cxsr(dev);
3544 return;
3545 }
3546
3547 crtc = single_enabled_crtc(dev);
3548 if (crtc) {
3549 int clock = crtc->mode.clock;
3550 int pixel_size = crtc->fb->bits_per_pixel / 8;
3551
3552 /* Display SR */
3553 wm = intel_calculate_wm(clock, &pineview_display_wm,
3554 pineview_display_wm.fifo_size,
3555 pixel_size, latency->display_sr);
3556 reg = I915_READ(DSPFW1);
3557 reg &= ~DSPFW_SR_MASK;
3558 reg |= wm << DSPFW_SR_SHIFT;
3559 I915_WRITE(DSPFW1, reg);
3560 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3561
3562 /* cursor SR */
3563 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3564 pineview_display_wm.fifo_size,
3565 pixel_size, latency->cursor_sr);
3566 reg = I915_READ(DSPFW3);
3567 reg &= ~DSPFW_CURSOR_SR_MASK;
3568 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3569 I915_WRITE(DSPFW3, reg);
3570
3571 /* Display HPLL off SR */
3572 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3573 pineview_display_hplloff_wm.fifo_size,
3574 pixel_size, latency->display_hpll_disable);
3575 reg = I915_READ(DSPFW3);
3576 reg &= ~DSPFW_HPLL_SR_MASK;
3577 reg |= wm & DSPFW_HPLL_SR_MASK;
3578 I915_WRITE(DSPFW3, reg);
3579
3580 /* cursor HPLL off SR */
3581 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3582 pineview_display_hplloff_wm.fifo_size,
3583 pixel_size, latency->cursor_hpll_disable);
3584 reg = I915_READ(DSPFW3);
3585 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3586 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3587 I915_WRITE(DSPFW3, reg);
3588 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3589
3590 /* activate cxsr */
3591 I915_WRITE(DSPFW3,
3592 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3593 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3594 } else {
3595 pineview_disable_cxsr(dev);
3596 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3597 }
3598 }
3599
3600 static bool g4x_compute_wm0(struct drm_device *dev,
3601 int plane,
3602 const struct intel_watermark_params *display,
3603 int display_latency_ns,
3604 const struct intel_watermark_params *cursor,
3605 int cursor_latency_ns,
3606 int *plane_wm,
3607 int *cursor_wm)
3608 {
3609 struct drm_crtc *crtc;
3610 int htotal, hdisplay, clock, pixel_size;
3611 int line_time_us, line_count;
3612 int entries, tlb_miss;
3613
3614 crtc = intel_get_crtc_for_plane(dev, plane);
3615 if (crtc->fb == NULL || !crtc->enabled) {
3616 *cursor_wm = cursor->guard_size;
3617 *plane_wm = display->guard_size;
3618 return false;
3619 }
3620
3621 htotal = crtc->mode.htotal;
3622 hdisplay = crtc->mode.hdisplay;
3623 clock = crtc->mode.clock;
3624 pixel_size = crtc->fb->bits_per_pixel / 8;
3625
3626 /* Use the small buffer method to calculate plane watermark */
3627 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3628 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3629 if (tlb_miss > 0)
3630 entries += tlb_miss;
3631 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3632 *plane_wm = entries + display->guard_size;
3633 if (*plane_wm > (int)display->max_wm)
3634 *plane_wm = display->max_wm;
3635
3636 /* Use the large buffer method to calculate cursor watermark */
3637 line_time_us = ((htotal * 1000) / clock);
3638 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3639 entries = line_count * 64 * pixel_size;
3640 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3641 if (tlb_miss > 0)
3642 entries += tlb_miss;
3643 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3644 *cursor_wm = entries + cursor->guard_size;
3645 if (*cursor_wm > (int)cursor->max_wm)
3646 *cursor_wm = (int)cursor->max_wm;
3647
3648 return true;
3649 }
3650
3651 /*
3652 * Check the wm result.
3653 *
3654 * If any calculated watermark values is larger than the maximum value that
3655 * can be programmed into the associated watermark register, that watermark
3656 * must be disabled.
3657 */
3658 static bool g4x_check_srwm(struct drm_device *dev,
3659 int display_wm, int cursor_wm,
3660 const struct intel_watermark_params *display,
3661 const struct intel_watermark_params *cursor)
3662 {
3663 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3664 display_wm, cursor_wm);
3665
3666 if (display_wm > display->max_wm) {
3667 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3668 display_wm, display->max_wm);
3669 return false;
3670 }
3671
3672 if (cursor_wm > cursor->max_wm) {
3673 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3674 cursor_wm, cursor->max_wm);
3675 return false;
3676 }
3677
3678 if (!(display_wm || cursor_wm)) {
3679 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3680 return false;
3681 }
3682
3683 return true;
3684 }
3685
3686 static bool g4x_compute_srwm(struct drm_device *dev,
3687 int plane,
3688 int latency_ns,
3689 const struct intel_watermark_params *display,
3690 const struct intel_watermark_params *cursor,
3691 int *display_wm, int *cursor_wm)
3692 {
3693 struct drm_crtc *crtc;
3694 int hdisplay, htotal, pixel_size, clock;
3695 unsigned long line_time_us;
3696 int line_count, line_size;
3697 int small, large;
3698 int entries;
3699
3700 if (!latency_ns) {
3701 *display_wm = *cursor_wm = 0;
3702 return false;
3703 }
3704
3705 crtc = intel_get_crtc_for_plane(dev, plane);
3706 hdisplay = crtc->mode.hdisplay;
3707 htotal = crtc->mode.htotal;
3708 clock = crtc->mode.clock;
3709 pixel_size = crtc->fb->bits_per_pixel / 8;
3710
3711 line_time_us = (htotal * 1000) / clock;
3712 line_count = (latency_ns / line_time_us + 1000) / 1000;
3713 line_size = hdisplay * pixel_size;
3714
3715 /* Use the minimum of the small and large buffer method for primary */
3716 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3717 large = line_count * line_size;
3718
3719 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3720 *display_wm = entries + display->guard_size;
3721
3722 /* calculate the self-refresh watermark for display cursor */
3723 entries = line_count * pixel_size * 64;
3724 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3725 *cursor_wm = entries + cursor->guard_size;
3726
3727 return g4x_check_srwm(dev,
3728 *display_wm, *cursor_wm,
3729 display, cursor);
3730 }
3731
3732 #define single_plane_enabled(mask) is_power_of_2(mask)
3733
3734 static void g4x_update_wm(struct drm_device *dev)
3735 {
3736 static const int sr_latency_ns = 12000;
3737 struct drm_i915_private *dev_priv = dev->dev_private;
3738 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3739 int plane_sr, cursor_sr;
3740 unsigned int enabled = 0;
3741
3742 if (g4x_compute_wm0(dev, 0,
3743 &g4x_wm_info, latency_ns,
3744 &g4x_cursor_wm_info, latency_ns,
3745 &planea_wm, &cursora_wm))
3746 enabled |= 1;
3747
3748 if (g4x_compute_wm0(dev, 1,
3749 &g4x_wm_info, latency_ns,
3750 &g4x_cursor_wm_info, latency_ns,
3751 &planeb_wm, &cursorb_wm))
3752 enabled |= 2;
3753
3754 plane_sr = cursor_sr = 0;
3755 if (single_plane_enabled(enabled) &&
3756 g4x_compute_srwm(dev, ffs(enabled) - 1,
3757 sr_latency_ns,
3758 &g4x_wm_info,
3759 &g4x_cursor_wm_info,
3760 &plane_sr, &cursor_sr))
3761 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3762 else
3763 I915_WRITE(FW_BLC_SELF,
3764 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
3765
3766 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3767 planea_wm, cursora_wm,
3768 planeb_wm, cursorb_wm,
3769 plane_sr, cursor_sr);
3770
3771 I915_WRITE(DSPFW1,
3772 (plane_sr << DSPFW_SR_SHIFT) |
3773 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3774 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3775 planea_wm);
3776 I915_WRITE(DSPFW2,
3777 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3778 (cursora_wm << DSPFW_CURSORA_SHIFT));
3779 /* HPLL off in SR has some issues on G4x... disable it */
3780 I915_WRITE(DSPFW3,
3781 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3782 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3783 }
3784
3785 static void i965_update_wm(struct drm_device *dev)
3786 {
3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788 struct drm_crtc *crtc;
3789 int srwm = 1;
3790 int cursor_sr = 16;
3791
3792 /* Calc sr entries for one plane configs */
3793 crtc = single_enabled_crtc(dev);
3794 if (crtc) {
3795 /* self-refresh has much higher latency */
3796 static const int sr_latency_ns = 12000;
3797 int clock = crtc->mode.clock;
3798 int htotal = crtc->mode.htotal;
3799 int hdisplay = crtc->mode.hdisplay;
3800 int pixel_size = crtc->fb->bits_per_pixel / 8;
3801 unsigned long line_time_us;
3802 int entries;
3803
3804 line_time_us = ((htotal * 1000) / clock);
3805
3806 /* Use ns/us then divide to preserve precision */
3807 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3808 pixel_size * hdisplay;
3809 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
3810 srwm = I965_FIFO_SIZE - entries;
3811 if (srwm < 0)
3812 srwm = 1;
3813 srwm &= 0x1ff;
3814 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3815 entries, srwm);
3816
3817 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3818 pixel_size * 64;
3819 entries = DIV_ROUND_UP(entries,
3820 i965_cursor_wm_info.cacheline_size);
3821 cursor_sr = i965_cursor_wm_info.fifo_size -
3822 (entries + i965_cursor_wm_info.guard_size);
3823
3824 if (cursor_sr > i965_cursor_wm_info.max_wm)
3825 cursor_sr = i965_cursor_wm_info.max_wm;
3826
3827 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3828 "cursor %d\n", srwm, cursor_sr);
3829
3830 if (IS_CRESTLINE(dev))
3831 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3832 } else {
3833 /* Turn off self refresh if both pipes are enabled */
3834 if (IS_CRESTLINE(dev))
3835 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3836 & ~FW_BLC_SELF_EN);
3837 }
3838
3839 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3840 srwm);
3841
3842 /* 965 has limitations... */
3843 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3844 (8 << 16) | (8 << 8) | (8 << 0));
3845 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3846 /* update cursor SR watermark */
3847 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3848 }
3849
3850 static void i9xx_update_wm(struct drm_device *dev)
3851 {
3852 struct drm_i915_private *dev_priv = dev->dev_private;
3853 const struct intel_watermark_params *wm_info;
3854 uint32_t fwater_lo;
3855 uint32_t fwater_hi;
3856 int cwm, srwm = 1;
3857 int fifo_size;
3858 int planea_wm, planeb_wm;
3859 struct drm_crtc *crtc, *enabled = NULL;
3860
3861 if (IS_I945GM(dev))
3862 wm_info = &i945_wm_info;
3863 else if (!IS_GEN2(dev))
3864 wm_info = &i915_wm_info;
3865 else
3866 wm_info = &i855_wm_info;
3867
3868 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3869 crtc = intel_get_crtc_for_plane(dev, 0);
3870 if (crtc->enabled && crtc->fb) {
3871 planea_wm = intel_calculate_wm(crtc->mode.clock,
3872 wm_info, fifo_size,
3873 crtc->fb->bits_per_pixel / 8,
3874 latency_ns);
3875 enabled = crtc;
3876 } else
3877 planea_wm = fifo_size - wm_info->guard_size;
3878
3879 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3880 crtc = intel_get_crtc_for_plane(dev, 1);
3881 if (crtc->enabled && crtc->fb) {
3882 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3883 wm_info, fifo_size,
3884 crtc->fb->bits_per_pixel / 8,
3885 latency_ns);
3886 if (enabled == NULL)
3887 enabled = crtc;
3888 else
3889 enabled = NULL;
3890 } else
3891 planeb_wm = fifo_size - wm_info->guard_size;
3892
3893 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3894
3895 /*
3896 * Overlay gets an aggressive default since video jitter is bad.
3897 */
3898 cwm = 2;
3899
3900 /* Play safe and disable self-refresh before adjusting watermarks. */
3901 if (IS_I945G(dev) || IS_I945GM(dev))
3902 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3903 else if (IS_I915GM(dev))
3904 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3905
3906 /* Calc sr entries for one plane configs */
3907 if (HAS_FW_BLC(dev) && enabled) {
3908 /* self-refresh has much higher latency */
3909 static const int sr_latency_ns = 6000;
3910 int clock = enabled->mode.clock;
3911 int htotal = enabled->mode.htotal;
3912 int hdisplay = enabled->mode.hdisplay;
3913 int pixel_size = enabled->fb->bits_per_pixel / 8;
3914 unsigned long line_time_us;
3915 int entries;
3916
3917 line_time_us = (htotal * 1000) / clock;
3918
3919 /* Use ns/us then divide to preserve precision */
3920 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3921 pixel_size * hdisplay;
3922 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3923 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3924 srwm = wm_info->fifo_size - entries;
3925 if (srwm < 0)
3926 srwm = 1;
3927
3928 if (IS_I945G(dev) || IS_I945GM(dev))
3929 I915_WRITE(FW_BLC_SELF,
3930 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3931 else if (IS_I915GM(dev))
3932 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3933 }
3934
3935 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3936 planea_wm, planeb_wm, cwm, srwm);
3937
3938 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3939 fwater_hi = (cwm & 0x1f);
3940
3941 /* Set request length to 8 cachelines per fetch */
3942 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3943 fwater_hi = fwater_hi | (1 << 8);
3944
3945 I915_WRITE(FW_BLC, fwater_lo);
3946 I915_WRITE(FW_BLC2, fwater_hi);
3947
3948 if (HAS_FW_BLC(dev)) {
3949 if (enabled) {
3950 if (IS_I945G(dev) || IS_I945GM(dev))
3951 I915_WRITE(FW_BLC_SELF,
3952 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3953 else if (IS_I915GM(dev))
3954 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3955 DRM_DEBUG_KMS("memory self refresh enabled\n");
3956 } else
3957 DRM_DEBUG_KMS("memory self refresh disabled\n");
3958 }
3959 }
3960
3961 static void i830_update_wm(struct drm_device *dev)
3962 {
3963 struct drm_i915_private *dev_priv = dev->dev_private;
3964 struct drm_crtc *crtc;
3965 uint32_t fwater_lo;
3966 int planea_wm;
3967
3968 crtc = single_enabled_crtc(dev);
3969 if (crtc == NULL)
3970 return;
3971
3972 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3973 dev_priv->display.get_fifo_size(dev, 0),
3974 crtc->fb->bits_per_pixel / 8,
3975 latency_ns);
3976 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3977 fwater_lo |= (3<<8) | planea_wm;
3978
3979 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3980
3981 I915_WRITE(FW_BLC, fwater_lo);
3982 }
3983
3984 #define ILK_LP0_PLANE_LATENCY 700
3985 #define ILK_LP0_CURSOR_LATENCY 1300
3986
3987 /*
3988 * Check the wm result.
3989 *
3990 * If any calculated watermark values is larger than the maximum value that
3991 * can be programmed into the associated watermark register, that watermark
3992 * must be disabled.
3993 */
3994 static bool ironlake_check_srwm(struct drm_device *dev, int level,
3995 int fbc_wm, int display_wm, int cursor_wm,
3996 const struct intel_watermark_params *display,
3997 const struct intel_watermark_params *cursor)
3998 {
3999 struct drm_i915_private *dev_priv = dev->dev_private;
4000
4001 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4002 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4003
4004 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4005 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4006 fbc_wm, SNB_FBC_MAX_SRWM, level);
4007
4008 /* fbc has it's own way to disable FBC WM */
4009 I915_WRITE(DISP_ARB_CTL,
4010 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4011 return false;
4012 }
4013
4014 if (display_wm > display->max_wm) {
4015 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4016 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4017 return false;
4018 }
4019
4020 if (cursor_wm > cursor->max_wm) {
4021 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4022 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4023 return false;
4024 }
4025
4026 if (!(fbc_wm || display_wm || cursor_wm)) {
4027 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4028 return false;
4029 }
4030
4031 return true;
4032 }
4033
4034 /*
4035 * Compute watermark values of WM[1-3],
4036 */
4037 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4038 int latency_ns,
4039 const struct intel_watermark_params *display,
4040 const struct intel_watermark_params *cursor,
4041 int *fbc_wm, int *display_wm, int *cursor_wm)
4042 {
4043 struct drm_crtc *crtc;
4044 unsigned long line_time_us;
4045 int hdisplay, htotal, pixel_size, clock;
4046 int line_count, line_size;
4047 int small, large;
4048 int entries;
4049
4050 if (!latency_ns) {
4051 *fbc_wm = *display_wm = *cursor_wm = 0;
4052 return false;
4053 }
4054
4055 crtc = intel_get_crtc_for_plane(dev, plane);
4056 hdisplay = crtc->mode.hdisplay;
4057 htotal = crtc->mode.htotal;
4058 clock = crtc->mode.clock;
4059 pixel_size = crtc->fb->bits_per_pixel / 8;
4060
4061 line_time_us = (htotal * 1000) / clock;
4062 line_count = (latency_ns / line_time_us + 1000) / 1000;
4063 line_size = hdisplay * pixel_size;
4064
4065 /* Use the minimum of the small and large buffer method for primary */
4066 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4067 large = line_count * line_size;
4068
4069 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4070 *display_wm = entries + display->guard_size;
4071
4072 /*
4073 * Spec says:
4074 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4075 */
4076 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4077
4078 /* calculate the self-refresh watermark for display cursor */
4079 entries = line_count * pixel_size * 64;
4080 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4081 *cursor_wm = entries + cursor->guard_size;
4082
4083 return ironlake_check_srwm(dev, level,
4084 *fbc_wm, *display_wm, *cursor_wm,
4085 display, cursor);
4086 }
4087
4088 static void ironlake_update_wm(struct drm_device *dev)
4089 {
4090 struct drm_i915_private *dev_priv = dev->dev_private;
4091 int fbc_wm, plane_wm, cursor_wm;
4092 unsigned int enabled;
4093
4094 enabled = 0;
4095 if (g4x_compute_wm0(dev, 0,
4096 &ironlake_display_wm_info,
4097 ILK_LP0_PLANE_LATENCY,
4098 &ironlake_cursor_wm_info,
4099 ILK_LP0_CURSOR_LATENCY,
4100 &plane_wm, &cursor_wm)) {
4101 I915_WRITE(WM0_PIPEA_ILK,
4102 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4103 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4104 " plane %d, " "cursor: %d\n",
4105 plane_wm, cursor_wm);
4106 enabled |= 1;
4107 }
4108
4109 if (g4x_compute_wm0(dev, 1,
4110 &ironlake_display_wm_info,
4111 ILK_LP0_PLANE_LATENCY,
4112 &ironlake_cursor_wm_info,
4113 ILK_LP0_CURSOR_LATENCY,
4114 &plane_wm, &cursor_wm)) {
4115 I915_WRITE(WM0_PIPEB_ILK,
4116 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4117 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4118 " plane %d, cursor: %d\n",
4119 plane_wm, cursor_wm);
4120 enabled |= 2;
4121 }
4122
4123 /*
4124 * Calculate and update the self-refresh watermark only when one
4125 * display plane is used.
4126 */
4127 I915_WRITE(WM3_LP_ILK, 0);
4128 I915_WRITE(WM2_LP_ILK, 0);
4129 I915_WRITE(WM1_LP_ILK, 0);
4130
4131 if (!single_plane_enabled(enabled))
4132 return;
4133 enabled = ffs(enabled) - 1;
4134
4135 /* WM1 */
4136 if (!ironlake_compute_srwm(dev, 1, enabled,
4137 ILK_READ_WM1_LATENCY() * 500,
4138 &ironlake_display_srwm_info,
4139 &ironlake_cursor_srwm_info,
4140 &fbc_wm, &plane_wm, &cursor_wm))
4141 return;
4142
4143 I915_WRITE(WM1_LP_ILK,
4144 WM1_LP_SR_EN |
4145 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4146 (fbc_wm << WM1_LP_FBC_SHIFT) |
4147 (plane_wm << WM1_LP_SR_SHIFT) |
4148 cursor_wm);
4149
4150 /* WM2 */
4151 if (!ironlake_compute_srwm(dev, 2, enabled,
4152 ILK_READ_WM2_LATENCY() * 500,
4153 &ironlake_display_srwm_info,
4154 &ironlake_cursor_srwm_info,
4155 &fbc_wm, &plane_wm, &cursor_wm))
4156 return;
4157
4158 I915_WRITE(WM2_LP_ILK,
4159 WM2_LP_EN |
4160 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4161 (fbc_wm << WM1_LP_FBC_SHIFT) |
4162 (plane_wm << WM1_LP_SR_SHIFT) |
4163 cursor_wm);
4164
4165 /*
4166 * WM3 is unsupported on ILK, probably because we don't have latency
4167 * data for that power state
4168 */
4169 }
4170
4171 static void sandybridge_update_wm(struct drm_device *dev)
4172 {
4173 struct drm_i915_private *dev_priv = dev->dev_private;
4174 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4175 int fbc_wm, plane_wm, cursor_wm;
4176 unsigned int enabled;
4177
4178 enabled = 0;
4179 if (g4x_compute_wm0(dev, 0,
4180 &sandybridge_display_wm_info, latency,
4181 &sandybridge_cursor_wm_info, latency,
4182 &plane_wm, &cursor_wm)) {
4183 I915_WRITE(WM0_PIPEA_ILK,
4184 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4185 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4186 " plane %d, " "cursor: %d\n",
4187 plane_wm, cursor_wm);
4188 enabled |= 1;
4189 }
4190
4191 if (g4x_compute_wm0(dev, 1,
4192 &sandybridge_display_wm_info, latency,
4193 &sandybridge_cursor_wm_info, latency,
4194 &plane_wm, &cursor_wm)) {
4195 I915_WRITE(WM0_PIPEB_ILK,
4196 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4197 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4198 " plane %d, cursor: %d\n",
4199 plane_wm, cursor_wm);
4200 enabled |= 2;
4201 }
4202
4203 /*
4204 * Calculate and update the self-refresh watermark only when one
4205 * display plane is used.
4206 *
4207 * SNB support 3 levels of watermark.
4208 *
4209 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4210 * and disabled in the descending order
4211 *
4212 */
4213 I915_WRITE(WM3_LP_ILK, 0);
4214 I915_WRITE(WM2_LP_ILK, 0);
4215 I915_WRITE(WM1_LP_ILK, 0);
4216
4217 if (!single_plane_enabled(enabled))
4218 return;
4219 enabled = ffs(enabled) - 1;
4220
4221 /* WM1 */
4222 if (!ironlake_compute_srwm(dev, 1, enabled,
4223 SNB_READ_WM1_LATENCY() * 500,
4224 &sandybridge_display_srwm_info,
4225 &sandybridge_cursor_srwm_info,
4226 &fbc_wm, &plane_wm, &cursor_wm))
4227 return;
4228
4229 I915_WRITE(WM1_LP_ILK,
4230 WM1_LP_SR_EN |
4231 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4232 (fbc_wm << WM1_LP_FBC_SHIFT) |
4233 (plane_wm << WM1_LP_SR_SHIFT) |
4234 cursor_wm);
4235
4236 /* WM2 */
4237 if (!ironlake_compute_srwm(dev, 2, enabled,
4238 SNB_READ_WM2_LATENCY() * 500,
4239 &sandybridge_display_srwm_info,
4240 &sandybridge_cursor_srwm_info,
4241 &fbc_wm, &plane_wm, &cursor_wm))
4242 return;
4243
4244 I915_WRITE(WM2_LP_ILK,
4245 WM2_LP_EN |
4246 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4247 (fbc_wm << WM1_LP_FBC_SHIFT) |
4248 (plane_wm << WM1_LP_SR_SHIFT) |
4249 cursor_wm);
4250
4251 /* WM3 */
4252 if (!ironlake_compute_srwm(dev, 3, enabled,
4253 SNB_READ_WM3_LATENCY() * 500,
4254 &sandybridge_display_srwm_info,
4255 &sandybridge_cursor_srwm_info,
4256 &fbc_wm, &plane_wm, &cursor_wm))
4257 return;
4258
4259 I915_WRITE(WM3_LP_ILK,
4260 WM3_LP_EN |
4261 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4262 (fbc_wm << WM1_LP_FBC_SHIFT) |
4263 (plane_wm << WM1_LP_SR_SHIFT) |
4264 cursor_wm);
4265 }
4266
4267 /**
4268 * intel_update_watermarks - update FIFO watermark values based on current modes
4269 *
4270 * Calculate watermark values for the various WM regs based on current mode
4271 * and plane configuration.
4272 *
4273 * There are several cases to deal with here:
4274 * - normal (i.e. non-self-refresh)
4275 * - self-refresh (SR) mode
4276 * - lines are large relative to FIFO size (buffer can hold up to 2)
4277 * - lines are small relative to FIFO size (buffer can hold more than 2
4278 * lines), so need to account for TLB latency
4279 *
4280 * The normal calculation is:
4281 * watermark = dotclock * bytes per pixel * latency
4282 * where latency is platform & configuration dependent (we assume pessimal
4283 * values here).
4284 *
4285 * The SR calculation is:
4286 * watermark = (trunc(latency/line time)+1) * surface width *
4287 * bytes per pixel
4288 * where
4289 * line time = htotal / dotclock
4290 * surface width = hdisplay for normal plane and 64 for cursor
4291 * and latency is assumed to be high, as above.
4292 *
4293 * The final value programmed to the register should always be rounded up,
4294 * and include an extra 2 entries to account for clock crossings.
4295 *
4296 * We don't use the sprite, so we can ignore that. And on Crestline we have
4297 * to set the non-SR watermarks to 8.
4298 */
4299 static void intel_update_watermarks(struct drm_device *dev)
4300 {
4301 struct drm_i915_private *dev_priv = dev->dev_private;
4302
4303 if (dev_priv->display.update_wm)
4304 dev_priv->display.update_wm(dev);
4305 }
4306
4307 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4308 {
4309 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4310 }
4311
4312 /**
4313 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4314 * @crtc: CRTC structure
4315 *
4316 * A pipe may be connected to one or more outputs. Based on the depth of the
4317 * attached framebuffer, choose a good color depth to use on the pipe.
4318 *
4319 * If possible, match the pipe depth to the fb depth. In some cases, this
4320 * isn't ideal, because the connected output supports a lesser or restricted
4321 * set of depths. Resolve that here:
4322 * LVDS typically supports only 6bpc, so clamp down in that case
4323 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4324 * Displays may support a restricted set as well, check EDID and clamp as
4325 * appropriate.
4326 *
4327 * RETURNS:
4328 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4329 * true if they don't match).
4330 */
4331 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4332 unsigned int *pipe_bpp)
4333 {
4334 struct drm_device *dev = crtc->dev;
4335 struct drm_i915_private *dev_priv = dev->dev_private;
4336 struct drm_encoder *encoder;
4337 struct drm_connector *connector;
4338 unsigned int display_bpc = UINT_MAX, bpc;
4339
4340 /* Walk the encoders & connectors on this crtc, get min bpc */
4341 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4342 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4343
4344 if (encoder->crtc != crtc)
4345 continue;
4346
4347 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4348 unsigned int lvds_bpc;
4349
4350 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4351 LVDS_A3_POWER_UP)
4352 lvds_bpc = 8;
4353 else
4354 lvds_bpc = 6;
4355
4356 if (lvds_bpc < display_bpc) {
4357 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4358 display_bpc = lvds_bpc;
4359 }
4360 continue;
4361 }
4362
4363 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4364 /* Use VBT settings if we have an eDP panel */
4365 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4366
4367 if (edp_bpc < display_bpc) {
4368 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4369 display_bpc = edp_bpc;
4370 }
4371 continue;
4372 }
4373
4374 /* Not one of the known troublemakers, check the EDID */
4375 list_for_each_entry(connector, &dev->mode_config.connector_list,
4376 head) {
4377 if (connector->encoder != encoder)
4378 continue;
4379
4380 if (connector->display_info.bpc < display_bpc) {
4381 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4382 display_bpc = connector->display_info.bpc;
4383 }
4384 }
4385
4386 /*
4387 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4388 * through, clamp it down. (Note: >12bpc will be caught below.)
4389 */
4390 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4391 if (display_bpc > 8 && display_bpc < 12) {
4392 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4393 display_bpc = 12;
4394 } else {
4395 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4396 display_bpc = 8;
4397 }
4398 }
4399 }
4400
4401 /*
4402 * We could just drive the pipe at the highest bpc all the time and
4403 * enable dithering as needed, but that costs bandwidth. So choose
4404 * the minimum value that expresses the full color range of the fb but
4405 * also stays within the max display bpc discovered above.
4406 */
4407
4408 switch (crtc->fb->depth) {
4409 case 8:
4410 bpc = 8; /* since we go through a colormap */
4411 break;
4412 case 15:
4413 case 16:
4414 bpc = 6; /* min is 18bpp */
4415 break;
4416 case 24:
4417 bpc = min((unsigned int)8, display_bpc);
4418 break;
4419 case 30:
4420 bpc = min((unsigned int)10, display_bpc);
4421 break;
4422 case 48:
4423 bpc = min((unsigned int)12, display_bpc);
4424 break;
4425 default:
4426 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4427 bpc = min((unsigned int)8, display_bpc);
4428 break;
4429 }
4430
4431 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4432 bpc, display_bpc);
4433
4434 *pipe_bpp = bpc * 3;
4435
4436 return display_bpc != bpc;
4437 }
4438
4439 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4440 struct drm_display_mode *mode,
4441 struct drm_display_mode *adjusted_mode,
4442 int x, int y,
4443 struct drm_framebuffer *old_fb)
4444 {
4445 struct drm_device *dev = crtc->dev;
4446 struct drm_i915_private *dev_priv = dev->dev_private;
4447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4448 int pipe = intel_crtc->pipe;
4449 int plane = intel_crtc->plane;
4450 int refclk, num_connectors = 0;
4451 intel_clock_t clock, reduced_clock;
4452 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4453 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4454 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4455 struct drm_mode_config *mode_config = &dev->mode_config;
4456 struct intel_encoder *encoder;
4457 const intel_limit_t *limit;
4458 int ret;
4459 u32 temp;
4460 u32 lvds_sync = 0;
4461
4462 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4463 if (encoder->base.crtc != crtc)
4464 continue;
4465
4466 switch (encoder->type) {
4467 case INTEL_OUTPUT_LVDS:
4468 is_lvds = true;
4469 break;
4470 case INTEL_OUTPUT_SDVO:
4471 case INTEL_OUTPUT_HDMI:
4472 is_sdvo = true;
4473 if (encoder->needs_tv_clock)
4474 is_tv = true;
4475 break;
4476 case INTEL_OUTPUT_DVO:
4477 is_dvo = true;
4478 break;
4479 case INTEL_OUTPUT_TVOUT:
4480 is_tv = true;
4481 break;
4482 case INTEL_OUTPUT_ANALOG:
4483 is_crt = true;
4484 break;
4485 case INTEL_OUTPUT_DISPLAYPORT:
4486 is_dp = true;
4487 break;
4488 }
4489
4490 num_connectors++;
4491 }
4492
4493 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4494 refclk = dev_priv->lvds_ssc_freq * 1000;
4495 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4496 refclk / 1000);
4497 } else if (!IS_GEN2(dev)) {
4498 refclk = 96000;
4499 } else {
4500 refclk = 48000;
4501 }
4502
4503 /*
4504 * Returns a set of divisors for the desired target clock with the given
4505 * refclk, or FALSE. The returned values represent the clock equation:
4506 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4507 */
4508 limit = intel_limit(crtc, refclk);
4509 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4510 if (!ok) {
4511 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4512 return -EINVAL;
4513 }
4514
4515 /* Ensure that the cursor is valid for the new mode before changing... */
4516 intel_crtc_update_cursor(crtc, true);
4517
4518 if (is_lvds && dev_priv->lvds_downclock_avail) {
4519 has_reduced_clock = limit->find_pll(limit, crtc,
4520 dev_priv->lvds_downclock,
4521 refclk,
4522 &reduced_clock);
4523 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4524 /*
4525 * If the different P is found, it means that we can't
4526 * switch the display clock by using the FP0/FP1.
4527 * In such case we will disable the LVDS downclock
4528 * feature.
4529 */
4530 DRM_DEBUG_KMS("Different P is found for "
4531 "LVDS clock/downclock\n");
4532 has_reduced_clock = 0;
4533 }
4534 }
4535 /* SDVO TV has fixed PLL values depend on its clock range,
4536 this mirrors vbios setting. */
4537 if (is_sdvo && is_tv) {
4538 if (adjusted_mode->clock >= 100000
4539 && adjusted_mode->clock < 140500) {
4540 clock.p1 = 2;
4541 clock.p2 = 10;
4542 clock.n = 3;
4543 clock.m1 = 16;
4544 clock.m2 = 8;
4545 } else if (adjusted_mode->clock >= 140500
4546 && adjusted_mode->clock <= 200000) {
4547 clock.p1 = 1;
4548 clock.p2 = 10;
4549 clock.n = 6;
4550 clock.m1 = 12;
4551 clock.m2 = 8;
4552 }
4553 }
4554
4555 if (IS_PINEVIEW(dev)) {
4556 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4557 if (has_reduced_clock)
4558 fp2 = (1 << reduced_clock.n) << 16 |
4559 reduced_clock.m1 << 8 | reduced_clock.m2;
4560 } else {
4561 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4562 if (has_reduced_clock)
4563 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4564 reduced_clock.m2;
4565 }
4566
4567 dpll = DPLL_VGA_MODE_DIS;
4568
4569 if (!IS_GEN2(dev)) {
4570 if (is_lvds)
4571 dpll |= DPLLB_MODE_LVDS;
4572 else
4573 dpll |= DPLLB_MODE_DAC_SERIAL;
4574 if (is_sdvo) {
4575 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4576 if (pixel_multiplier > 1) {
4577 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4578 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4579 }
4580 dpll |= DPLL_DVO_HIGH_SPEED;
4581 }
4582 if (is_dp)
4583 dpll |= DPLL_DVO_HIGH_SPEED;
4584
4585 /* compute bitmask from p1 value */
4586 if (IS_PINEVIEW(dev))
4587 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4588 else {
4589 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4590 if (IS_G4X(dev) && has_reduced_clock)
4591 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4592 }
4593 switch (clock.p2) {
4594 case 5:
4595 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4596 break;
4597 case 7:
4598 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4599 break;
4600 case 10:
4601 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4602 break;
4603 case 14:
4604 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4605 break;
4606 }
4607 if (INTEL_INFO(dev)->gen >= 4)
4608 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4609 } else {
4610 if (is_lvds) {
4611 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4612 } else {
4613 if (clock.p1 == 2)
4614 dpll |= PLL_P1_DIVIDE_BY_TWO;
4615 else
4616 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4617 if (clock.p2 == 4)
4618 dpll |= PLL_P2_DIVIDE_BY_4;
4619 }
4620 }
4621
4622 if (is_sdvo && is_tv)
4623 dpll |= PLL_REF_INPUT_TVCLKINBC;
4624 else if (is_tv)
4625 /* XXX: just matching BIOS for now */
4626 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4627 dpll |= 3;
4628 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4629 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4630 else
4631 dpll |= PLL_REF_INPUT_DREFCLK;
4632
4633 /* setup pipeconf */
4634 pipeconf = I915_READ(PIPECONF(pipe));
4635
4636 /* Set up the display plane register */
4637 dspcntr = DISPPLANE_GAMMA_ENABLE;
4638
4639 /* Ironlake's plane is forced to pipe, bit 24 is to
4640 enable color space conversion */
4641 if (pipe == 0)
4642 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4643 else
4644 dspcntr |= DISPPLANE_SEL_PIPE_B;
4645
4646 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4647 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4648 * core speed.
4649 *
4650 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4651 * pipe == 0 check?
4652 */
4653 if (mode->clock >
4654 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4655 pipeconf |= PIPECONF_DOUBLE_WIDE;
4656 else
4657 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4658 }
4659
4660 dpll |= DPLL_VCO_ENABLE;
4661
4662 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4663 drm_mode_debug_printmodeline(mode);
4664
4665 I915_WRITE(FP0(pipe), fp);
4666 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4667
4668 POSTING_READ(DPLL(pipe));
4669 udelay(150);
4670
4671 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4672 * This is an exception to the general rule that mode_set doesn't turn
4673 * things on.
4674 */
4675 if (is_lvds) {
4676 temp = I915_READ(LVDS);
4677 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4678 if (pipe == 1) {
4679 temp |= LVDS_PIPEB_SELECT;
4680 } else {
4681 temp &= ~LVDS_PIPEB_SELECT;
4682 }
4683 /* set the corresponsding LVDS_BORDER bit */
4684 temp |= dev_priv->lvds_border_bits;
4685 /* Set the B0-B3 data pairs corresponding to whether we're going to
4686 * set the DPLLs for dual-channel mode or not.
4687 */
4688 if (clock.p2 == 7)
4689 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4690 else
4691 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4692
4693 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4694 * appropriately here, but we need to look more thoroughly into how
4695 * panels behave in the two modes.
4696 */
4697 /* set the dithering flag on LVDS as needed */
4698 if (INTEL_INFO(dev)->gen >= 4) {
4699 if (dev_priv->lvds_dither)
4700 temp |= LVDS_ENABLE_DITHER;
4701 else
4702 temp &= ~LVDS_ENABLE_DITHER;
4703 }
4704 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4705 lvds_sync |= LVDS_HSYNC_POLARITY;
4706 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4707 lvds_sync |= LVDS_VSYNC_POLARITY;
4708 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4709 != lvds_sync) {
4710 char flags[2] = "-+";
4711 DRM_INFO("Changing LVDS panel from "
4712 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4713 flags[!(temp & LVDS_HSYNC_POLARITY)],
4714 flags[!(temp & LVDS_VSYNC_POLARITY)],
4715 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4716 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4717 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4718 temp |= lvds_sync;
4719 }
4720 I915_WRITE(LVDS, temp);
4721 }
4722
4723 if (is_dp) {
4724 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4725 }
4726
4727 I915_WRITE(DPLL(pipe), dpll);
4728
4729 /* Wait for the clocks to stabilize. */
4730 POSTING_READ(DPLL(pipe));
4731 udelay(150);
4732
4733 if (INTEL_INFO(dev)->gen >= 4) {
4734 temp = 0;
4735 if (is_sdvo) {
4736 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4737 if (temp > 1)
4738 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4739 else
4740 temp = 0;
4741 }
4742 I915_WRITE(DPLL_MD(pipe), temp);
4743 } else {
4744 /* The pixel multiplier can only be updated once the
4745 * DPLL is enabled and the clocks are stable.
4746 *
4747 * So write it again.
4748 */
4749 I915_WRITE(DPLL(pipe), dpll);
4750 }
4751
4752 intel_crtc->lowfreq_avail = false;
4753 if (is_lvds && has_reduced_clock && i915_powersave) {
4754 I915_WRITE(FP1(pipe), fp2);
4755 intel_crtc->lowfreq_avail = true;
4756 if (HAS_PIPE_CXSR(dev)) {
4757 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4758 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4759 }
4760 } else {
4761 I915_WRITE(FP1(pipe), fp);
4762 if (HAS_PIPE_CXSR(dev)) {
4763 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4764 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4765 }
4766 }
4767
4768 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4769 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4770 /* the chip adds 2 halflines automatically */
4771 adjusted_mode->crtc_vdisplay -= 1;
4772 adjusted_mode->crtc_vtotal -= 1;
4773 adjusted_mode->crtc_vblank_start -= 1;
4774 adjusted_mode->crtc_vblank_end -= 1;
4775 adjusted_mode->crtc_vsync_end -= 1;
4776 adjusted_mode->crtc_vsync_start -= 1;
4777 } else
4778 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4779
4780 I915_WRITE(HTOTAL(pipe),
4781 (adjusted_mode->crtc_hdisplay - 1) |
4782 ((adjusted_mode->crtc_htotal - 1) << 16));
4783 I915_WRITE(HBLANK(pipe),
4784 (adjusted_mode->crtc_hblank_start - 1) |
4785 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4786 I915_WRITE(HSYNC(pipe),
4787 (adjusted_mode->crtc_hsync_start - 1) |
4788 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4789
4790 I915_WRITE(VTOTAL(pipe),
4791 (adjusted_mode->crtc_vdisplay - 1) |
4792 ((adjusted_mode->crtc_vtotal - 1) << 16));
4793 I915_WRITE(VBLANK(pipe),
4794 (adjusted_mode->crtc_vblank_start - 1) |
4795 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4796 I915_WRITE(VSYNC(pipe),
4797 (adjusted_mode->crtc_vsync_start - 1) |
4798 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4799
4800 /* pipesrc and dspsize control the size that is scaled from,
4801 * which should always be the user's requested size.
4802 */
4803 I915_WRITE(DSPSIZE(plane),
4804 ((mode->vdisplay - 1) << 16) |
4805 (mode->hdisplay - 1));
4806 I915_WRITE(DSPPOS(plane), 0);
4807 I915_WRITE(PIPESRC(pipe),
4808 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4809
4810 I915_WRITE(PIPECONF(pipe), pipeconf);
4811 POSTING_READ(PIPECONF(pipe));
4812 intel_enable_pipe(dev_priv, pipe, false);
4813
4814 intel_wait_for_vblank(dev, pipe);
4815
4816 I915_WRITE(DSPCNTR(plane), dspcntr);
4817 POSTING_READ(DSPCNTR(plane));
4818 intel_enable_plane(dev_priv, plane, pipe);
4819
4820 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4821
4822 intel_update_watermarks(dev);
4823
4824 return ret;
4825 }
4826
4827 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4828 struct drm_display_mode *mode,
4829 struct drm_display_mode *adjusted_mode,
4830 int x, int y,
4831 struct drm_framebuffer *old_fb)
4832 {
4833 struct drm_device *dev = crtc->dev;
4834 struct drm_i915_private *dev_priv = dev->dev_private;
4835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4836 int pipe = intel_crtc->pipe;
4837 int plane = intel_crtc->plane;
4838 int refclk, num_connectors = 0;
4839 intel_clock_t clock, reduced_clock;
4840 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4841 bool ok, has_reduced_clock = false, is_sdvo = false;
4842 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4843 struct intel_encoder *has_edp_encoder = NULL;
4844 struct drm_mode_config *mode_config = &dev->mode_config;
4845 struct intel_encoder *encoder;
4846 const intel_limit_t *limit;
4847 int ret;
4848 struct fdi_m_n m_n = {0};
4849 u32 temp;
4850 u32 lvds_sync = 0;
4851 int target_clock, pixel_multiplier, lane, link_bw, factor;
4852 unsigned int pipe_bpp;
4853 bool dither;
4854
4855 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4856 if (encoder->base.crtc != crtc)
4857 continue;
4858
4859 switch (encoder->type) {
4860 case INTEL_OUTPUT_LVDS:
4861 is_lvds = true;
4862 break;
4863 case INTEL_OUTPUT_SDVO:
4864 case INTEL_OUTPUT_HDMI:
4865 is_sdvo = true;
4866 if (encoder->needs_tv_clock)
4867 is_tv = true;
4868 break;
4869 case INTEL_OUTPUT_TVOUT:
4870 is_tv = true;
4871 break;
4872 case INTEL_OUTPUT_ANALOG:
4873 is_crt = true;
4874 break;
4875 case INTEL_OUTPUT_DISPLAYPORT:
4876 is_dp = true;
4877 break;
4878 case INTEL_OUTPUT_EDP:
4879 has_edp_encoder = encoder;
4880 break;
4881 }
4882
4883 num_connectors++;
4884 }
4885
4886 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4887 refclk = dev_priv->lvds_ssc_freq * 1000;
4888 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4889 refclk / 1000);
4890 } else {
4891 refclk = 96000;
4892 if (!has_edp_encoder ||
4893 intel_encoder_is_pch_edp(&has_edp_encoder->base))
4894 refclk = 120000; /* 120Mhz refclk */
4895 }
4896
4897 /*
4898 * Returns a set of divisors for the desired target clock with the given
4899 * refclk, or FALSE. The returned values represent the clock equation:
4900 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4901 */
4902 limit = intel_limit(crtc, refclk);
4903 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4904 if (!ok) {
4905 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4906 return -EINVAL;
4907 }
4908
4909 /* Ensure that the cursor is valid for the new mode before changing... */
4910 intel_crtc_update_cursor(crtc, true);
4911
4912 if (is_lvds && dev_priv->lvds_downclock_avail) {
4913 has_reduced_clock = limit->find_pll(limit, crtc,
4914 dev_priv->lvds_downclock,
4915 refclk,
4916 &reduced_clock);
4917 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4918 /*
4919 * If the different P is found, it means that we can't
4920 * switch the display clock by using the FP0/FP1.
4921 * In such case we will disable the LVDS downclock
4922 * feature.
4923 */
4924 DRM_DEBUG_KMS("Different P is found for "
4925 "LVDS clock/downclock\n");
4926 has_reduced_clock = 0;
4927 }
4928 }
4929 /* SDVO TV has fixed PLL values depend on its clock range,
4930 this mirrors vbios setting. */
4931 if (is_sdvo && is_tv) {
4932 if (adjusted_mode->clock >= 100000
4933 && adjusted_mode->clock < 140500) {
4934 clock.p1 = 2;
4935 clock.p2 = 10;
4936 clock.n = 3;
4937 clock.m1 = 16;
4938 clock.m2 = 8;
4939 } else if (adjusted_mode->clock >= 140500
4940 && adjusted_mode->clock <= 200000) {
4941 clock.p1 = 1;
4942 clock.p2 = 10;
4943 clock.n = 6;
4944 clock.m1 = 12;
4945 clock.m2 = 8;
4946 }
4947 }
4948
4949 /* FDI link */
4950 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4951 lane = 0;
4952 /* CPU eDP doesn't require FDI link, so just set DP M/N
4953 according to current link config */
4954 if (has_edp_encoder &&
4955 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4956 target_clock = mode->clock;
4957 intel_edp_link_config(has_edp_encoder,
4958 &lane, &link_bw);
4959 } else {
4960 /* [e]DP over FDI requires target mode clock
4961 instead of link clock */
4962 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4963 target_clock = mode->clock;
4964 else
4965 target_clock = adjusted_mode->clock;
4966
4967 /* FDI is a binary signal running at ~2.7GHz, encoding
4968 * each output octet as 10 bits. The actual frequency
4969 * is stored as a divider into a 100MHz clock, and the
4970 * mode pixel clock is stored in units of 1KHz.
4971 * Hence the bw of each lane in terms of the mode signal
4972 * is:
4973 */
4974 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4975 }
4976
4977 /* determine panel color depth */
4978 temp = I915_READ(PIPECONF(pipe));
4979 temp &= ~PIPE_BPC_MASK;
4980 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
4981 switch (pipe_bpp) {
4982 case 18:
4983 temp |= PIPE_6BPC;
4984 break;
4985 case 24:
4986 temp |= PIPE_8BPC;
4987 break;
4988 case 30:
4989 temp |= PIPE_10BPC;
4990 break;
4991 case 36:
4992 temp |= PIPE_12BPC;
4993 break;
4994 default:
4995 WARN(1, "intel_choose_pipe_bpp returned invalid value\n");
4996 temp |= PIPE_8BPC;
4997 pipe_bpp = 24;
4998 break;
4999 }
5000
5001 intel_crtc->bpp = pipe_bpp;
5002 I915_WRITE(PIPECONF(pipe), temp);
5003
5004 if (!lane) {
5005 /*
5006 * Account for spread spectrum to avoid
5007 * oversubscribing the link. Max center spread
5008 * is 2.5%; use 5% for safety's sake.
5009 */
5010 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5011 lane = bps / (link_bw * 8) + 1;
5012 }
5013
5014 intel_crtc->fdi_lanes = lane;
5015
5016 if (pixel_multiplier > 1)
5017 link_bw *= pixel_multiplier;
5018 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5019 &m_n);
5020
5021 /* Ironlake: try to setup display ref clock before DPLL
5022 * enabling. This is only under driver's control after
5023 * PCH B stepping, previous chipset stepping should be
5024 * ignoring this setting.
5025 */
5026 temp = I915_READ(PCH_DREF_CONTROL);
5027 /* Always enable nonspread source */
5028 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5029 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5030 temp &= ~DREF_SSC_SOURCE_MASK;
5031 temp |= DREF_SSC_SOURCE_ENABLE;
5032 I915_WRITE(PCH_DREF_CONTROL, temp);
5033
5034 POSTING_READ(PCH_DREF_CONTROL);
5035 udelay(200);
5036
5037 if (has_edp_encoder) {
5038 if (intel_panel_use_ssc(dev_priv)) {
5039 temp |= DREF_SSC1_ENABLE;
5040 I915_WRITE(PCH_DREF_CONTROL, temp);
5041
5042 POSTING_READ(PCH_DREF_CONTROL);
5043 udelay(200);
5044 }
5045 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5046
5047 /* Enable CPU source on CPU attached eDP */
5048 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5049 if (intel_panel_use_ssc(dev_priv))
5050 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5051 else
5052 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5053 } else {
5054 /* Enable SSC on PCH eDP if needed */
5055 if (intel_panel_use_ssc(dev_priv)) {
5056 DRM_ERROR("enabling SSC on PCH\n");
5057 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5058 }
5059 }
5060 I915_WRITE(PCH_DREF_CONTROL, temp);
5061 POSTING_READ(PCH_DREF_CONTROL);
5062 udelay(200);
5063 }
5064
5065 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5066 if (has_reduced_clock)
5067 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5068 reduced_clock.m2;
5069
5070 /* Enable autotuning of the PLL clock (if permissible) */
5071 factor = 21;
5072 if (is_lvds) {
5073 if ((intel_panel_use_ssc(dev_priv) &&
5074 dev_priv->lvds_ssc_freq == 100) ||
5075 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5076 factor = 25;
5077 } else if (is_sdvo && is_tv)
5078 factor = 20;
5079
5080 if (clock.m1 < factor * clock.n)
5081 fp |= FP_CB_TUNE;
5082
5083 dpll = 0;
5084
5085 if (is_lvds)
5086 dpll |= DPLLB_MODE_LVDS;
5087 else
5088 dpll |= DPLLB_MODE_DAC_SERIAL;
5089 if (is_sdvo) {
5090 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5091 if (pixel_multiplier > 1) {
5092 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5093 }
5094 dpll |= DPLL_DVO_HIGH_SPEED;
5095 }
5096 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5097 dpll |= DPLL_DVO_HIGH_SPEED;
5098
5099 /* compute bitmask from p1 value */
5100 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5101 /* also FPA1 */
5102 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5103
5104 switch (clock.p2) {
5105 case 5:
5106 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5107 break;
5108 case 7:
5109 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5110 break;
5111 case 10:
5112 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5113 break;
5114 case 14:
5115 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5116 break;
5117 }
5118
5119 if (is_sdvo && is_tv)
5120 dpll |= PLL_REF_INPUT_TVCLKINBC;
5121 else if (is_tv)
5122 /* XXX: just matching BIOS for now */
5123 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5124 dpll |= 3;
5125 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5126 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5127 else
5128 dpll |= PLL_REF_INPUT_DREFCLK;
5129
5130 /* setup pipeconf */
5131 pipeconf = I915_READ(PIPECONF(pipe));
5132
5133 /* Set up the display plane register */
5134 dspcntr = DISPPLANE_GAMMA_ENABLE;
5135
5136 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5137 drm_mode_debug_printmodeline(mode);
5138
5139 /* PCH eDP needs FDI, but CPU eDP does not */
5140 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5141 I915_WRITE(PCH_FP0(pipe), fp);
5142 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5143
5144 POSTING_READ(PCH_DPLL(pipe));
5145 udelay(150);
5146 }
5147
5148 /* enable transcoder DPLL */
5149 if (HAS_PCH_CPT(dev)) {
5150 temp = I915_READ(PCH_DPLL_SEL);
5151 switch (pipe) {
5152 case 0:
5153 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
5154 break;
5155 case 1:
5156 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
5157 break;
5158 case 2:
5159 /* FIXME: manage transcoder PLLs? */
5160 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5161 break;
5162 default:
5163 BUG();
5164 }
5165 I915_WRITE(PCH_DPLL_SEL, temp);
5166
5167 POSTING_READ(PCH_DPLL_SEL);
5168 udelay(150);
5169 }
5170
5171 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5172 * This is an exception to the general rule that mode_set doesn't turn
5173 * things on.
5174 */
5175 if (is_lvds) {
5176 temp = I915_READ(PCH_LVDS);
5177 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5178 if (pipe == 1) {
5179 if (HAS_PCH_CPT(dev))
5180 temp |= PORT_TRANS_B_SEL_CPT;
5181 else
5182 temp |= LVDS_PIPEB_SELECT;
5183 } else {
5184 if (HAS_PCH_CPT(dev))
5185 temp &= ~PORT_TRANS_SEL_MASK;
5186 else
5187 temp &= ~LVDS_PIPEB_SELECT;
5188 }
5189 /* set the corresponsding LVDS_BORDER bit */
5190 temp |= dev_priv->lvds_border_bits;
5191 /* Set the B0-B3 data pairs corresponding to whether we're going to
5192 * set the DPLLs for dual-channel mode or not.
5193 */
5194 if (clock.p2 == 7)
5195 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5196 else
5197 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5198
5199 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5200 * appropriately here, but we need to look more thoroughly into how
5201 * panels behave in the two modes.
5202 */
5203 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5204 lvds_sync |= LVDS_HSYNC_POLARITY;
5205 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5206 lvds_sync |= LVDS_VSYNC_POLARITY;
5207 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5208 != lvds_sync) {
5209 char flags[2] = "-+";
5210 DRM_INFO("Changing LVDS panel from "
5211 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5212 flags[!(temp & LVDS_HSYNC_POLARITY)],
5213 flags[!(temp & LVDS_VSYNC_POLARITY)],
5214 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5215 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5216 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5217 temp |= lvds_sync;
5218 }
5219 I915_WRITE(PCH_LVDS, temp);
5220 }
5221
5222 pipeconf &= ~PIPECONF_DITHER_EN;
5223 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5224 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5225 pipeconf |= PIPECONF_DITHER_EN;
5226 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5227 }
5228 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5229 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5230 } else {
5231 /* For non-DP output, clear any trans DP clock recovery setting.*/
5232 I915_WRITE(TRANSDATA_M1(pipe), 0);
5233 I915_WRITE(TRANSDATA_N1(pipe), 0);
5234 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5235 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5236 }
5237
5238 if (!has_edp_encoder ||
5239 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5240 I915_WRITE(PCH_DPLL(pipe), dpll);
5241
5242 /* Wait for the clocks to stabilize. */
5243 POSTING_READ(PCH_DPLL(pipe));
5244 udelay(150);
5245
5246 /* The pixel multiplier can only be updated once the
5247 * DPLL is enabled and the clocks are stable.
5248 *
5249 * So write it again.
5250 */
5251 I915_WRITE(PCH_DPLL(pipe), dpll);
5252 }
5253
5254 intel_crtc->lowfreq_avail = false;
5255 if (is_lvds && has_reduced_clock && i915_powersave) {
5256 I915_WRITE(PCH_FP1(pipe), fp2);
5257 intel_crtc->lowfreq_avail = true;
5258 if (HAS_PIPE_CXSR(dev)) {
5259 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5260 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5261 }
5262 } else {
5263 I915_WRITE(PCH_FP1(pipe), fp);
5264 if (HAS_PIPE_CXSR(dev)) {
5265 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5266 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5267 }
5268 }
5269
5270 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5271 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5272 /* the chip adds 2 halflines automatically */
5273 adjusted_mode->crtc_vdisplay -= 1;
5274 adjusted_mode->crtc_vtotal -= 1;
5275 adjusted_mode->crtc_vblank_start -= 1;
5276 adjusted_mode->crtc_vblank_end -= 1;
5277 adjusted_mode->crtc_vsync_end -= 1;
5278 adjusted_mode->crtc_vsync_start -= 1;
5279 } else
5280 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5281
5282 I915_WRITE(HTOTAL(pipe),
5283 (adjusted_mode->crtc_hdisplay - 1) |
5284 ((adjusted_mode->crtc_htotal - 1) << 16));
5285 I915_WRITE(HBLANK(pipe),
5286 (adjusted_mode->crtc_hblank_start - 1) |
5287 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5288 I915_WRITE(HSYNC(pipe),
5289 (adjusted_mode->crtc_hsync_start - 1) |
5290 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5291
5292 I915_WRITE(VTOTAL(pipe),
5293 (adjusted_mode->crtc_vdisplay - 1) |
5294 ((adjusted_mode->crtc_vtotal - 1) << 16));
5295 I915_WRITE(VBLANK(pipe),
5296 (adjusted_mode->crtc_vblank_start - 1) |
5297 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5298 I915_WRITE(VSYNC(pipe),
5299 (adjusted_mode->crtc_vsync_start - 1) |
5300 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5301
5302 /* pipesrc controls the size that is scaled from, which should
5303 * always be the user's requested size.
5304 */
5305 I915_WRITE(PIPESRC(pipe),
5306 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5307
5308 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5309 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5310 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5311 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5312
5313 if (has_edp_encoder &&
5314 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5315 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5316 }
5317
5318 I915_WRITE(PIPECONF(pipe), pipeconf);
5319 POSTING_READ(PIPECONF(pipe));
5320
5321 intel_wait_for_vblank(dev, pipe);
5322
5323 if (IS_GEN5(dev)) {
5324 /* enable address swizzle for tiling buffer */
5325 temp = I915_READ(DISP_ARB_CTL);
5326 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5327 }
5328
5329 I915_WRITE(DSPCNTR(plane), dspcntr);
5330 POSTING_READ(DSPCNTR(plane));
5331
5332 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5333
5334 intel_update_watermarks(dev);
5335
5336 return ret;
5337 }
5338
5339 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5340 struct drm_display_mode *mode,
5341 struct drm_display_mode *adjusted_mode,
5342 int x, int y,
5343 struct drm_framebuffer *old_fb)
5344 {
5345 struct drm_device *dev = crtc->dev;
5346 struct drm_i915_private *dev_priv = dev->dev_private;
5347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5348 int pipe = intel_crtc->pipe;
5349 int ret;
5350
5351 drm_vblank_pre_modeset(dev, pipe);
5352
5353 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5354 x, y, old_fb);
5355
5356 drm_vblank_post_modeset(dev, pipe);
5357
5358 return ret;
5359 }
5360
5361 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5362 void intel_crtc_load_lut(struct drm_crtc *crtc)
5363 {
5364 struct drm_device *dev = crtc->dev;
5365 struct drm_i915_private *dev_priv = dev->dev_private;
5366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5367 int palreg = PALETTE(intel_crtc->pipe);
5368 int i;
5369
5370 /* The clocks have to be on to load the palette. */
5371 if (!crtc->enabled)
5372 return;
5373
5374 /* use legacy palette for Ironlake */
5375 if (HAS_PCH_SPLIT(dev))
5376 palreg = LGC_PALETTE(intel_crtc->pipe);
5377
5378 for (i = 0; i < 256; i++) {
5379 I915_WRITE(palreg + 4 * i,
5380 (intel_crtc->lut_r[i] << 16) |
5381 (intel_crtc->lut_g[i] << 8) |
5382 intel_crtc->lut_b[i]);
5383 }
5384 }
5385
5386 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5387 {
5388 struct drm_device *dev = crtc->dev;
5389 struct drm_i915_private *dev_priv = dev->dev_private;
5390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5391 bool visible = base != 0;
5392 u32 cntl;
5393
5394 if (intel_crtc->cursor_visible == visible)
5395 return;
5396
5397 cntl = I915_READ(_CURACNTR);
5398 if (visible) {
5399 /* On these chipsets we can only modify the base whilst
5400 * the cursor is disabled.
5401 */
5402 I915_WRITE(_CURABASE, base);
5403
5404 cntl &= ~(CURSOR_FORMAT_MASK);
5405 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5406 cntl |= CURSOR_ENABLE |
5407 CURSOR_GAMMA_ENABLE |
5408 CURSOR_FORMAT_ARGB;
5409 } else
5410 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5411 I915_WRITE(_CURACNTR, cntl);
5412
5413 intel_crtc->cursor_visible = visible;
5414 }
5415
5416 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5417 {
5418 struct drm_device *dev = crtc->dev;
5419 struct drm_i915_private *dev_priv = dev->dev_private;
5420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5421 int pipe = intel_crtc->pipe;
5422 bool visible = base != 0;
5423
5424 if (intel_crtc->cursor_visible != visible) {
5425 uint32_t cntl = I915_READ(CURCNTR(pipe));
5426 if (base) {
5427 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5428 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5429 cntl |= pipe << 28; /* Connect to correct pipe */
5430 } else {
5431 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5432 cntl |= CURSOR_MODE_DISABLE;
5433 }
5434 I915_WRITE(CURCNTR(pipe), cntl);
5435
5436 intel_crtc->cursor_visible = visible;
5437 }
5438 /* and commit changes on next vblank */
5439 I915_WRITE(CURBASE(pipe), base);
5440 }
5441
5442 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5443 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5444 bool on)
5445 {
5446 struct drm_device *dev = crtc->dev;
5447 struct drm_i915_private *dev_priv = dev->dev_private;
5448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5449 int pipe = intel_crtc->pipe;
5450 int x = intel_crtc->cursor_x;
5451 int y = intel_crtc->cursor_y;
5452 u32 base, pos;
5453 bool visible;
5454
5455 pos = 0;
5456
5457 if (on && crtc->enabled && crtc->fb) {
5458 base = intel_crtc->cursor_addr;
5459 if (x > (int) crtc->fb->width)
5460 base = 0;
5461
5462 if (y > (int) crtc->fb->height)
5463 base = 0;
5464 } else
5465 base = 0;
5466
5467 if (x < 0) {
5468 if (x + intel_crtc->cursor_width < 0)
5469 base = 0;
5470
5471 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5472 x = -x;
5473 }
5474 pos |= x << CURSOR_X_SHIFT;
5475
5476 if (y < 0) {
5477 if (y + intel_crtc->cursor_height < 0)
5478 base = 0;
5479
5480 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5481 y = -y;
5482 }
5483 pos |= y << CURSOR_Y_SHIFT;
5484
5485 visible = base != 0;
5486 if (!visible && !intel_crtc->cursor_visible)
5487 return;
5488
5489 I915_WRITE(CURPOS(pipe), pos);
5490 if (IS_845G(dev) || IS_I865G(dev))
5491 i845_update_cursor(crtc, base);
5492 else
5493 i9xx_update_cursor(crtc, base);
5494
5495 if (visible)
5496 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5497 }
5498
5499 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5500 struct drm_file *file,
5501 uint32_t handle,
5502 uint32_t width, uint32_t height)
5503 {
5504 struct drm_device *dev = crtc->dev;
5505 struct drm_i915_private *dev_priv = dev->dev_private;
5506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5507 struct drm_i915_gem_object *obj;
5508 uint32_t addr;
5509 int ret;
5510
5511 DRM_DEBUG_KMS("\n");
5512
5513 /* if we want to turn off the cursor ignore width and height */
5514 if (!handle) {
5515 DRM_DEBUG_KMS("cursor off\n");
5516 addr = 0;
5517 obj = NULL;
5518 mutex_lock(&dev->struct_mutex);
5519 goto finish;
5520 }
5521
5522 /* Currently we only support 64x64 cursors */
5523 if (width != 64 || height != 64) {
5524 DRM_ERROR("we currently only support 64x64 cursors\n");
5525 return -EINVAL;
5526 }
5527
5528 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5529 if (&obj->base == NULL)
5530 return -ENOENT;
5531
5532 if (obj->base.size < width * height * 4) {
5533 DRM_ERROR("buffer is to small\n");
5534 ret = -ENOMEM;
5535 goto fail;
5536 }
5537
5538 /* we only need to pin inside GTT if cursor is non-phy */
5539 mutex_lock(&dev->struct_mutex);
5540 if (!dev_priv->info->cursor_needs_physical) {
5541 if (obj->tiling_mode) {
5542 DRM_ERROR("cursor cannot be tiled\n");
5543 ret = -EINVAL;
5544 goto fail_locked;
5545 }
5546
5547 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5548 if (ret) {
5549 DRM_ERROR("failed to move cursor bo into the GTT\n");
5550 goto fail_locked;
5551 }
5552
5553 ret = i915_gem_object_put_fence(obj);
5554 if (ret) {
5555 DRM_ERROR("failed to release fence for cursor");
5556 goto fail_unpin;
5557 }
5558
5559 addr = obj->gtt_offset;
5560 } else {
5561 int align = IS_I830(dev) ? 16 * 1024 : 256;
5562 ret = i915_gem_attach_phys_object(dev, obj,
5563 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5564 align);
5565 if (ret) {
5566 DRM_ERROR("failed to attach phys object\n");
5567 goto fail_locked;
5568 }
5569 addr = obj->phys_obj->handle->busaddr;
5570 }
5571
5572 if (IS_GEN2(dev))
5573 I915_WRITE(CURSIZE, (height << 12) | width);
5574
5575 finish:
5576 if (intel_crtc->cursor_bo) {
5577 if (dev_priv->info->cursor_needs_physical) {
5578 if (intel_crtc->cursor_bo != obj)
5579 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5580 } else
5581 i915_gem_object_unpin(intel_crtc->cursor_bo);
5582 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5583 }
5584
5585 mutex_unlock(&dev->struct_mutex);
5586
5587 intel_crtc->cursor_addr = addr;
5588 intel_crtc->cursor_bo = obj;
5589 intel_crtc->cursor_width = width;
5590 intel_crtc->cursor_height = height;
5591
5592 intel_crtc_update_cursor(crtc, true);
5593
5594 return 0;
5595 fail_unpin:
5596 i915_gem_object_unpin(obj);
5597 fail_locked:
5598 mutex_unlock(&dev->struct_mutex);
5599 fail:
5600 drm_gem_object_unreference_unlocked(&obj->base);
5601 return ret;
5602 }
5603
5604 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5605 {
5606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5607
5608 intel_crtc->cursor_x = x;
5609 intel_crtc->cursor_y = y;
5610
5611 intel_crtc_update_cursor(crtc, true);
5612
5613 return 0;
5614 }
5615
5616 /** Sets the color ramps on behalf of RandR */
5617 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5618 u16 blue, int regno)
5619 {
5620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5621
5622 intel_crtc->lut_r[regno] = red >> 8;
5623 intel_crtc->lut_g[regno] = green >> 8;
5624 intel_crtc->lut_b[regno] = blue >> 8;
5625 }
5626
5627 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5628 u16 *blue, int regno)
5629 {
5630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5631
5632 *red = intel_crtc->lut_r[regno] << 8;
5633 *green = intel_crtc->lut_g[regno] << 8;
5634 *blue = intel_crtc->lut_b[regno] << 8;
5635 }
5636
5637 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5638 u16 *blue, uint32_t start, uint32_t size)
5639 {
5640 int end = (start + size > 256) ? 256 : start + size, i;
5641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5642
5643 for (i = start; i < end; i++) {
5644 intel_crtc->lut_r[i] = red[i] >> 8;
5645 intel_crtc->lut_g[i] = green[i] >> 8;
5646 intel_crtc->lut_b[i] = blue[i] >> 8;
5647 }
5648
5649 intel_crtc_load_lut(crtc);
5650 }
5651
5652 /**
5653 * Get a pipe with a simple mode set on it for doing load-based monitor
5654 * detection.
5655 *
5656 * It will be up to the load-detect code to adjust the pipe as appropriate for
5657 * its requirements. The pipe will be connected to no other encoders.
5658 *
5659 * Currently this code will only succeed if there is a pipe with no encoders
5660 * configured for it. In the future, it could choose to temporarily disable
5661 * some outputs to free up a pipe for its use.
5662 *
5663 * \return crtc, or NULL if no pipes are available.
5664 */
5665
5666 /* VESA 640x480x72Hz mode to set on the pipe */
5667 static struct drm_display_mode load_detect_mode = {
5668 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5669 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5670 };
5671
5672 static struct drm_framebuffer *
5673 intel_framebuffer_create(struct drm_device *dev,
5674 struct drm_mode_fb_cmd *mode_cmd,
5675 struct drm_i915_gem_object *obj)
5676 {
5677 struct intel_framebuffer *intel_fb;
5678 int ret;
5679
5680 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5681 if (!intel_fb) {
5682 drm_gem_object_unreference_unlocked(&obj->base);
5683 return ERR_PTR(-ENOMEM);
5684 }
5685
5686 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5687 if (ret) {
5688 drm_gem_object_unreference_unlocked(&obj->base);
5689 kfree(intel_fb);
5690 return ERR_PTR(ret);
5691 }
5692
5693 return &intel_fb->base;
5694 }
5695
5696 static u32
5697 intel_framebuffer_pitch_for_width(int width, int bpp)
5698 {
5699 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5700 return ALIGN(pitch, 64);
5701 }
5702
5703 static u32
5704 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5705 {
5706 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5707 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5708 }
5709
5710 static struct drm_framebuffer *
5711 intel_framebuffer_create_for_mode(struct drm_device *dev,
5712 struct drm_display_mode *mode,
5713 int depth, int bpp)
5714 {
5715 struct drm_i915_gem_object *obj;
5716 struct drm_mode_fb_cmd mode_cmd;
5717
5718 obj = i915_gem_alloc_object(dev,
5719 intel_framebuffer_size_for_mode(mode, bpp));
5720 if (obj == NULL)
5721 return ERR_PTR(-ENOMEM);
5722
5723 mode_cmd.width = mode->hdisplay;
5724 mode_cmd.height = mode->vdisplay;
5725 mode_cmd.depth = depth;
5726 mode_cmd.bpp = bpp;
5727 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5728
5729 return intel_framebuffer_create(dev, &mode_cmd, obj);
5730 }
5731
5732 static struct drm_framebuffer *
5733 mode_fits_in_fbdev(struct drm_device *dev,
5734 struct drm_display_mode *mode)
5735 {
5736 struct drm_i915_private *dev_priv = dev->dev_private;
5737 struct drm_i915_gem_object *obj;
5738 struct drm_framebuffer *fb;
5739
5740 if (dev_priv->fbdev == NULL)
5741 return NULL;
5742
5743 obj = dev_priv->fbdev->ifb.obj;
5744 if (obj == NULL)
5745 return NULL;
5746
5747 fb = &dev_priv->fbdev->ifb.base;
5748 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5749 fb->bits_per_pixel))
5750 return NULL;
5751
5752 if (obj->base.size < mode->vdisplay * fb->pitch)
5753 return NULL;
5754
5755 return fb;
5756 }
5757
5758 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5759 struct drm_connector *connector,
5760 struct drm_display_mode *mode,
5761 struct intel_load_detect_pipe *old)
5762 {
5763 struct intel_crtc *intel_crtc;
5764 struct drm_crtc *possible_crtc;
5765 struct drm_encoder *encoder = &intel_encoder->base;
5766 struct drm_crtc *crtc = NULL;
5767 struct drm_device *dev = encoder->dev;
5768 struct drm_framebuffer *old_fb;
5769 int i = -1;
5770
5771 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5772 connector->base.id, drm_get_connector_name(connector),
5773 encoder->base.id, drm_get_encoder_name(encoder));
5774
5775 /*
5776 * Algorithm gets a little messy:
5777 *
5778 * - if the connector already has an assigned crtc, use it (but make
5779 * sure it's on first)
5780 *
5781 * - try to find the first unused crtc that can drive this connector,
5782 * and use that if we find one
5783 */
5784
5785 /* See if we already have a CRTC for this connector */
5786 if (encoder->crtc) {
5787 crtc = encoder->crtc;
5788
5789 intel_crtc = to_intel_crtc(crtc);
5790 old->dpms_mode = intel_crtc->dpms_mode;
5791 old->load_detect_temp = false;
5792
5793 /* Make sure the crtc and connector are running */
5794 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5795 struct drm_encoder_helper_funcs *encoder_funcs;
5796 struct drm_crtc_helper_funcs *crtc_funcs;
5797
5798 crtc_funcs = crtc->helper_private;
5799 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5800
5801 encoder_funcs = encoder->helper_private;
5802 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5803 }
5804
5805 return true;
5806 }
5807
5808 /* Find an unused one (if possible) */
5809 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5810 i++;
5811 if (!(encoder->possible_crtcs & (1 << i)))
5812 continue;
5813 if (!possible_crtc->enabled) {
5814 crtc = possible_crtc;
5815 break;
5816 }
5817 }
5818
5819 /*
5820 * If we didn't find an unused CRTC, don't use any.
5821 */
5822 if (!crtc) {
5823 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5824 return false;
5825 }
5826
5827 encoder->crtc = crtc;
5828 connector->encoder = encoder;
5829
5830 intel_crtc = to_intel_crtc(crtc);
5831 old->dpms_mode = intel_crtc->dpms_mode;
5832 old->load_detect_temp = true;
5833 old->release_fb = NULL;
5834
5835 if (!mode)
5836 mode = &load_detect_mode;
5837
5838 old_fb = crtc->fb;
5839
5840 /* We need a framebuffer large enough to accommodate all accesses
5841 * that the plane may generate whilst we perform load detection.
5842 * We can not rely on the fbcon either being present (we get called
5843 * during its initialisation to detect all boot displays, or it may
5844 * not even exist) or that it is large enough to satisfy the
5845 * requested mode.
5846 */
5847 crtc->fb = mode_fits_in_fbdev(dev, mode);
5848 if (crtc->fb == NULL) {
5849 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5850 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5851 old->release_fb = crtc->fb;
5852 } else
5853 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5854 if (IS_ERR(crtc->fb)) {
5855 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5856 crtc->fb = old_fb;
5857 return false;
5858 }
5859
5860 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5861 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5862 if (old->release_fb)
5863 old->release_fb->funcs->destroy(old->release_fb);
5864 crtc->fb = old_fb;
5865 return false;
5866 }
5867
5868 /* let the connector get through one full cycle before testing */
5869 intel_wait_for_vblank(dev, intel_crtc->pipe);
5870
5871 return true;
5872 }
5873
5874 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5875 struct drm_connector *connector,
5876 struct intel_load_detect_pipe *old)
5877 {
5878 struct drm_encoder *encoder = &intel_encoder->base;
5879 struct drm_device *dev = encoder->dev;
5880 struct drm_crtc *crtc = encoder->crtc;
5881 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5882 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5883
5884 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5885 connector->base.id, drm_get_connector_name(connector),
5886 encoder->base.id, drm_get_encoder_name(encoder));
5887
5888 if (old->load_detect_temp) {
5889 connector->encoder = NULL;
5890 drm_helper_disable_unused_functions(dev);
5891
5892 if (old->release_fb)
5893 old->release_fb->funcs->destroy(old->release_fb);
5894
5895 return;
5896 }
5897
5898 /* Switch crtc and encoder back off if necessary */
5899 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5900 encoder_funcs->dpms(encoder, old->dpms_mode);
5901 crtc_funcs->dpms(crtc, old->dpms_mode);
5902 }
5903 }
5904
5905 /* Returns the clock of the currently programmed mode of the given pipe. */
5906 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5907 {
5908 struct drm_i915_private *dev_priv = dev->dev_private;
5909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5910 int pipe = intel_crtc->pipe;
5911 u32 dpll = I915_READ(DPLL(pipe));
5912 u32 fp;
5913 intel_clock_t clock;
5914
5915 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5916 fp = I915_READ(FP0(pipe));
5917 else
5918 fp = I915_READ(FP1(pipe));
5919
5920 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5921 if (IS_PINEVIEW(dev)) {
5922 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5923 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5924 } else {
5925 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5926 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5927 }
5928
5929 if (!IS_GEN2(dev)) {
5930 if (IS_PINEVIEW(dev))
5931 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5932 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5933 else
5934 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5935 DPLL_FPA01_P1_POST_DIV_SHIFT);
5936
5937 switch (dpll & DPLL_MODE_MASK) {
5938 case DPLLB_MODE_DAC_SERIAL:
5939 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5940 5 : 10;
5941 break;
5942 case DPLLB_MODE_LVDS:
5943 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5944 7 : 14;
5945 break;
5946 default:
5947 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5948 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5949 return 0;
5950 }
5951
5952 /* XXX: Handle the 100Mhz refclk */
5953 intel_clock(dev, 96000, &clock);
5954 } else {
5955 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5956
5957 if (is_lvds) {
5958 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5959 DPLL_FPA01_P1_POST_DIV_SHIFT);
5960 clock.p2 = 14;
5961
5962 if ((dpll & PLL_REF_INPUT_MASK) ==
5963 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5964 /* XXX: might not be 66MHz */
5965 intel_clock(dev, 66000, &clock);
5966 } else
5967 intel_clock(dev, 48000, &clock);
5968 } else {
5969 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5970 clock.p1 = 2;
5971 else {
5972 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5973 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5974 }
5975 if (dpll & PLL_P2_DIVIDE_BY_4)
5976 clock.p2 = 4;
5977 else
5978 clock.p2 = 2;
5979
5980 intel_clock(dev, 48000, &clock);
5981 }
5982 }
5983
5984 /* XXX: It would be nice to validate the clocks, but we can't reuse
5985 * i830PllIsValid() because it relies on the xf86_config connector
5986 * configuration being accurate, which it isn't necessarily.
5987 */
5988
5989 return clock.dot;
5990 }
5991
5992 /** Returns the currently programmed mode of the given pipe. */
5993 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5994 struct drm_crtc *crtc)
5995 {
5996 struct drm_i915_private *dev_priv = dev->dev_private;
5997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5998 int pipe = intel_crtc->pipe;
5999 struct drm_display_mode *mode;
6000 int htot = I915_READ(HTOTAL(pipe));
6001 int hsync = I915_READ(HSYNC(pipe));
6002 int vtot = I915_READ(VTOTAL(pipe));
6003 int vsync = I915_READ(VSYNC(pipe));
6004
6005 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6006 if (!mode)
6007 return NULL;
6008
6009 mode->clock = intel_crtc_clock_get(dev, crtc);
6010 mode->hdisplay = (htot & 0xffff) + 1;
6011 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6012 mode->hsync_start = (hsync & 0xffff) + 1;
6013 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6014 mode->vdisplay = (vtot & 0xffff) + 1;
6015 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6016 mode->vsync_start = (vsync & 0xffff) + 1;
6017 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6018
6019 drm_mode_set_name(mode);
6020 drm_mode_set_crtcinfo(mode, 0);
6021
6022 return mode;
6023 }
6024
6025 #define GPU_IDLE_TIMEOUT 500 /* ms */
6026
6027 /* When this timer fires, we've been idle for awhile */
6028 static void intel_gpu_idle_timer(unsigned long arg)
6029 {
6030 struct drm_device *dev = (struct drm_device *)arg;
6031 drm_i915_private_t *dev_priv = dev->dev_private;
6032
6033 if (!list_empty(&dev_priv->mm.active_list)) {
6034 /* Still processing requests, so just re-arm the timer. */
6035 mod_timer(&dev_priv->idle_timer, jiffies +
6036 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6037 return;
6038 }
6039
6040 dev_priv->busy = false;
6041 queue_work(dev_priv->wq, &dev_priv->idle_work);
6042 }
6043
6044 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6045
6046 static void intel_crtc_idle_timer(unsigned long arg)
6047 {
6048 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6049 struct drm_crtc *crtc = &intel_crtc->base;
6050 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6051 struct intel_framebuffer *intel_fb;
6052
6053 intel_fb = to_intel_framebuffer(crtc->fb);
6054 if (intel_fb && intel_fb->obj->active) {
6055 /* The framebuffer is still being accessed by the GPU. */
6056 mod_timer(&intel_crtc->idle_timer, jiffies +
6057 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6058 return;
6059 }
6060
6061 intel_crtc->busy = false;
6062 queue_work(dev_priv->wq, &dev_priv->idle_work);
6063 }
6064
6065 static void intel_increase_pllclock(struct drm_crtc *crtc)
6066 {
6067 struct drm_device *dev = crtc->dev;
6068 drm_i915_private_t *dev_priv = dev->dev_private;
6069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6070 int pipe = intel_crtc->pipe;
6071 int dpll_reg = DPLL(pipe);
6072 int dpll;
6073
6074 if (HAS_PCH_SPLIT(dev))
6075 return;
6076
6077 if (!dev_priv->lvds_downclock_avail)
6078 return;
6079
6080 dpll = I915_READ(dpll_reg);
6081 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6082 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6083
6084 /* Unlock panel regs */
6085 I915_WRITE(PP_CONTROL,
6086 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6087
6088 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6089 I915_WRITE(dpll_reg, dpll);
6090 intel_wait_for_vblank(dev, pipe);
6091
6092 dpll = I915_READ(dpll_reg);
6093 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6094 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6095
6096 /* ...and lock them again */
6097 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6098 }
6099
6100 /* Schedule downclock */
6101 mod_timer(&intel_crtc->idle_timer, jiffies +
6102 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6103 }
6104
6105 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6106 {
6107 struct drm_device *dev = crtc->dev;
6108 drm_i915_private_t *dev_priv = dev->dev_private;
6109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6110 int pipe = intel_crtc->pipe;
6111 int dpll_reg = DPLL(pipe);
6112 int dpll = I915_READ(dpll_reg);
6113
6114 if (HAS_PCH_SPLIT(dev))
6115 return;
6116
6117 if (!dev_priv->lvds_downclock_avail)
6118 return;
6119
6120 /*
6121 * Since this is called by a timer, we should never get here in
6122 * the manual case.
6123 */
6124 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6125 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6126
6127 /* Unlock panel regs */
6128 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6129 PANEL_UNLOCK_REGS);
6130
6131 dpll |= DISPLAY_RATE_SELECT_FPA1;
6132 I915_WRITE(dpll_reg, dpll);
6133 intel_wait_for_vblank(dev, pipe);
6134 dpll = I915_READ(dpll_reg);
6135 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6136 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6137
6138 /* ...and lock them again */
6139 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6140 }
6141
6142 }
6143
6144 /**
6145 * intel_idle_update - adjust clocks for idleness
6146 * @work: work struct
6147 *
6148 * Either the GPU or display (or both) went idle. Check the busy status
6149 * here and adjust the CRTC and GPU clocks as necessary.
6150 */
6151 static void intel_idle_update(struct work_struct *work)
6152 {
6153 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6154 idle_work);
6155 struct drm_device *dev = dev_priv->dev;
6156 struct drm_crtc *crtc;
6157 struct intel_crtc *intel_crtc;
6158
6159 if (!i915_powersave)
6160 return;
6161
6162 mutex_lock(&dev->struct_mutex);
6163
6164 i915_update_gfx_val(dev_priv);
6165
6166 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6167 /* Skip inactive CRTCs */
6168 if (!crtc->fb)
6169 continue;
6170
6171 intel_crtc = to_intel_crtc(crtc);
6172 if (!intel_crtc->busy)
6173 intel_decrease_pllclock(crtc);
6174 }
6175
6176
6177 mutex_unlock(&dev->struct_mutex);
6178 }
6179
6180 /**
6181 * intel_mark_busy - mark the GPU and possibly the display busy
6182 * @dev: drm device
6183 * @obj: object we're operating on
6184 *
6185 * Callers can use this function to indicate that the GPU is busy processing
6186 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6187 * buffer), we'll also mark the display as busy, so we know to increase its
6188 * clock frequency.
6189 */
6190 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6191 {
6192 drm_i915_private_t *dev_priv = dev->dev_private;
6193 struct drm_crtc *crtc = NULL;
6194 struct intel_framebuffer *intel_fb;
6195 struct intel_crtc *intel_crtc;
6196
6197 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6198 return;
6199
6200 if (!dev_priv->busy)
6201 dev_priv->busy = true;
6202 else
6203 mod_timer(&dev_priv->idle_timer, jiffies +
6204 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6205
6206 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6207 if (!crtc->fb)
6208 continue;
6209
6210 intel_crtc = to_intel_crtc(crtc);
6211 intel_fb = to_intel_framebuffer(crtc->fb);
6212 if (intel_fb->obj == obj) {
6213 if (!intel_crtc->busy) {
6214 /* Non-busy -> busy, upclock */
6215 intel_increase_pllclock(crtc);
6216 intel_crtc->busy = true;
6217 } else {
6218 /* Busy -> busy, put off timer */
6219 mod_timer(&intel_crtc->idle_timer, jiffies +
6220 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6221 }
6222 }
6223 }
6224 }
6225
6226 static void intel_crtc_destroy(struct drm_crtc *crtc)
6227 {
6228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6229 struct drm_device *dev = crtc->dev;
6230 struct intel_unpin_work *work;
6231 unsigned long flags;
6232
6233 spin_lock_irqsave(&dev->event_lock, flags);
6234 work = intel_crtc->unpin_work;
6235 intel_crtc->unpin_work = NULL;
6236 spin_unlock_irqrestore(&dev->event_lock, flags);
6237
6238 if (work) {
6239 cancel_work_sync(&work->work);
6240 kfree(work);
6241 }
6242
6243 drm_crtc_cleanup(crtc);
6244
6245 kfree(intel_crtc);
6246 }
6247
6248 static void intel_unpin_work_fn(struct work_struct *__work)
6249 {
6250 struct intel_unpin_work *work =
6251 container_of(__work, struct intel_unpin_work, work);
6252
6253 mutex_lock(&work->dev->struct_mutex);
6254 i915_gem_object_unpin(work->old_fb_obj);
6255 drm_gem_object_unreference(&work->pending_flip_obj->base);
6256 drm_gem_object_unreference(&work->old_fb_obj->base);
6257
6258 mutex_unlock(&work->dev->struct_mutex);
6259 kfree(work);
6260 }
6261
6262 static void do_intel_finish_page_flip(struct drm_device *dev,
6263 struct drm_crtc *crtc)
6264 {
6265 drm_i915_private_t *dev_priv = dev->dev_private;
6266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6267 struct intel_unpin_work *work;
6268 struct drm_i915_gem_object *obj;
6269 struct drm_pending_vblank_event *e;
6270 struct timeval tnow, tvbl;
6271 unsigned long flags;
6272
6273 /* Ignore early vblank irqs */
6274 if (intel_crtc == NULL)
6275 return;
6276
6277 do_gettimeofday(&tnow);
6278
6279 spin_lock_irqsave(&dev->event_lock, flags);
6280 work = intel_crtc->unpin_work;
6281 if (work == NULL || !work->pending) {
6282 spin_unlock_irqrestore(&dev->event_lock, flags);
6283 return;
6284 }
6285
6286 intel_crtc->unpin_work = NULL;
6287
6288 if (work->event) {
6289 e = work->event;
6290 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6291
6292 /* Called before vblank count and timestamps have
6293 * been updated for the vblank interval of flip
6294 * completion? Need to increment vblank count and
6295 * add one videorefresh duration to returned timestamp
6296 * to account for this. We assume this happened if we
6297 * get called over 0.9 frame durations after the last
6298 * timestamped vblank.
6299 *
6300 * This calculation can not be used with vrefresh rates
6301 * below 5Hz (10Hz to be on the safe side) without
6302 * promoting to 64 integers.
6303 */
6304 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6305 9 * crtc->framedur_ns) {
6306 e->event.sequence++;
6307 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6308 crtc->framedur_ns);
6309 }
6310
6311 e->event.tv_sec = tvbl.tv_sec;
6312 e->event.tv_usec = tvbl.tv_usec;
6313
6314 list_add_tail(&e->base.link,
6315 &e->base.file_priv->event_list);
6316 wake_up_interruptible(&e->base.file_priv->event_wait);
6317 }
6318
6319 drm_vblank_put(dev, intel_crtc->pipe);
6320
6321 spin_unlock_irqrestore(&dev->event_lock, flags);
6322
6323 obj = work->old_fb_obj;
6324
6325 atomic_clear_mask(1 << intel_crtc->plane,
6326 &obj->pending_flip.counter);
6327 if (atomic_read(&obj->pending_flip) == 0)
6328 wake_up(&dev_priv->pending_flip_queue);
6329
6330 schedule_work(&work->work);
6331
6332 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6333 }
6334
6335 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6336 {
6337 drm_i915_private_t *dev_priv = dev->dev_private;
6338 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6339
6340 do_intel_finish_page_flip(dev, crtc);
6341 }
6342
6343 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6344 {
6345 drm_i915_private_t *dev_priv = dev->dev_private;
6346 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6347
6348 do_intel_finish_page_flip(dev, crtc);
6349 }
6350
6351 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6352 {
6353 drm_i915_private_t *dev_priv = dev->dev_private;
6354 struct intel_crtc *intel_crtc =
6355 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6356 unsigned long flags;
6357
6358 spin_lock_irqsave(&dev->event_lock, flags);
6359 if (intel_crtc->unpin_work) {
6360 if ((++intel_crtc->unpin_work->pending) > 1)
6361 DRM_ERROR("Prepared flip multiple times\n");
6362 } else {
6363 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6364 }
6365 spin_unlock_irqrestore(&dev->event_lock, flags);
6366 }
6367
6368 static int intel_gen2_queue_flip(struct drm_device *dev,
6369 struct drm_crtc *crtc,
6370 struct drm_framebuffer *fb,
6371 struct drm_i915_gem_object *obj)
6372 {
6373 struct drm_i915_private *dev_priv = dev->dev_private;
6374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6375 unsigned long offset;
6376 u32 flip_mask;
6377 int ret;
6378
6379 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6380 if (ret)
6381 goto out;
6382
6383 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6384 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6385
6386 ret = BEGIN_LP_RING(6);
6387 if (ret)
6388 goto out;
6389
6390 /* Can't queue multiple flips, so wait for the previous
6391 * one to finish before executing the next.
6392 */
6393 if (intel_crtc->plane)
6394 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6395 else
6396 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6397 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6398 OUT_RING(MI_NOOP);
6399 OUT_RING(MI_DISPLAY_FLIP |
6400 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6401 OUT_RING(fb->pitch);
6402 OUT_RING(obj->gtt_offset + offset);
6403 OUT_RING(MI_NOOP);
6404 ADVANCE_LP_RING();
6405 out:
6406 return ret;
6407 }
6408
6409 static int intel_gen3_queue_flip(struct drm_device *dev,
6410 struct drm_crtc *crtc,
6411 struct drm_framebuffer *fb,
6412 struct drm_i915_gem_object *obj)
6413 {
6414 struct drm_i915_private *dev_priv = dev->dev_private;
6415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6416 unsigned long offset;
6417 u32 flip_mask;
6418 int ret;
6419
6420 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6421 if (ret)
6422 goto out;
6423
6424 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6425 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6426
6427 ret = BEGIN_LP_RING(6);
6428 if (ret)
6429 goto out;
6430
6431 if (intel_crtc->plane)
6432 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6433 else
6434 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6435 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6436 OUT_RING(MI_NOOP);
6437 OUT_RING(MI_DISPLAY_FLIP_I915 |
6438 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6439 OUT_RING(fb->pitch);
6440 OUT_RING(obj->gtt_offset + offset);
6441 OUT_RING(MI_NOOP);
6442
6443 ADVANCE_LP_RING();
6444 out:
6445 return ret;
6446 }
6447
6448 static int intel_gen4_queue_flip(struct drm_device *dev,
6449 struct drm_crtc *crtc,
6450 struct drm_framebuffer *fb,
6451 struct drm_i915_gem_object *obj)
6452 {
6453 struct drm_i915_private *dev_priv = dev->dev_private;
6454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6455 uint32_t pf, pipesrc;
6456 int ret;
6457
6458 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6459 if (ret)
6460 goto out;
6461
6462 ret = BEGIN_LP_RING(4);
6463 if (ret)
6464 goto out;
6465
6466 /* i965+ uses the linear or tiled offsets from the
6467 * Display Registers (which do not change across a page-flip)
6468 * so we need only reprogram the base address.
6469 */
6470 OUT_RING(MI_DISPLAY_FLIP |
6471 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6472 OUT_RING(fb->pitch);
6473 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6474
6475 /* XXX Enabling the panel-fitter across page-flip is so far
6476 * untested on non-native modes, so ignore it for now.
6477 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6478 */
6479 pf = 0;
6480 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6481 OUT_RING(pf | pipesrc);
6482 ADVANCE_LP_RING();
6483 out:
6484 return ret;
6485 }
6486
6487 static int intel_gen6_queue_flip(struct drm_device *dev,
6488 struct drm_crtc *crtc,
6489 struct drm_framebuffer *fb,
6490 struct drm_i915_gem_object *obj)
6491 {
6492 struct drm_i915_private *dev_priv = dev->dev_private;
6493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6494 uint32_t pf, pipesrc;
6495 int ret;
6496
6497 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6498 if (ret)
6499 goto out;
6500
6501 ret = BEGIN_LP_RING(4);
6502 if (ret)
6503 goto out;
6504
6505 OUT_RING(MI_DISPLAY_FLIP |
6506 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6507 OUT_RING(fb->pitch | obj->tiling_mode);
6508 OUT_RING(obj->gtt_offset);
6509
6510 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6511 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6512 OUT_RING(pf | pipesrc);
6513 ADVANCE_LP_RING();
6514 out:
6515 return ret;
6516 }
6517
6518 /*
6519 * On gen7 we currently use the blit ring because (in early silicon at least)
6520 * the render ring doesn't give us interrpts for page flip completion, which
6521 * means clients will hang after the first flip is queued. Fortunately the
6522 * blit ring generates interrupts properly, so use it instead.
6523 */
6524 static int intel_gen7_queue_flip(struct drm_device *dev,
6525 struct drm_crtc *crtc,
6526 struct drm_framebuffer *fb,
6527 struct drm_i915_gem_object *obj)
6528 {
6529 struct drm_i915_private *dev_priv = dev->dev_private;
6530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6531 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6532 int ret;
6533
6534 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6535 if (ret)
6536 goto out;
6537
6538 ret = intel_ring_begin(ring, 4);
6539 if (ret)
6540 goto out;
6541
6542 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6543 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6544 intel_ring_emit(ring, (obj->gtt_offset));
6545 intel_ring_emit(ring, (MI_NOOP));
6546 intel_ring_advance(ring);
6547 out:
6548 return ret;
6549 }
6550
6551 static int intel_default_queue_flip(struct drm_device *dev,
6552 struct drm_crtc *crtc,
6553 struct drm_framebuffer *fb,
6554 struct drm_i915_gem_object *obj)
6555 {
6556 return -ENODEV;
6557 }
6558
6559 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6560 struct drm_framebuffer *fb,
6561 struct drm_pending_vblank_event *event)
6562 {
6563 struct drm_device *dev = crtc->dev;
6564 struct drm_i915_private *dev_priv = dev->dev_private;
6565 struct intel_framebuffer *intel_fb;
6566 struct drm_i915_gem_object *obj;
6567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6568 struct intel_unpin_work *work;
6569 unsigned long flags;
6570 int ret;
6571
6572 work = kzalloc(sizeof *work, GFP_KERNEL);
6573 if (work == NULL)
6574 return -ENOMEM;
6575
6576 work->event = event;
6577 work->dev = crtc->dev;
6578 intel_fb = to_intel_framebuffer(crtc->fb);
6579 work->old_fb_obj = intel_fb->obj;
6580 INIT_WORK(&work->work, intel_unpin_work_fn);
6581
6582 /* We borrow the event spin lock for protecting unpin_work */
6583 spin_lock_irqsave(&dev->event_lock, flags);
6584 if (intel_crtc->unpin_work) {
6585 spin_unlock_irqrestore(&dev->event_lock, flags);
6586 kfree(work);
6587
6588 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6589 return -EBUSY;
6590 }
6591 intel_crtc->unpin_work = work;
6592 spin_unlock_irqrestore(&dev->event_lock, flags);
6593
6594 intel_fb = to_intel_framebuffer(fb);
6595 obj = intel_fb->obj;
6596
6597 mutex_lock(&dev->struct_mutex);
6598
6599 /* Reference the objects for the scheduled work. */
6600 drm_gem_object_reference(&work->old_fb_obj->base);
6601 drm_gem_object_reference(&obj->base);
6602
6603 crtc->fb = fb;
6604
6605 ret = drm_vblank_get(dev, intel_crtc->pipe);
6606 if (ret)
6607 goto cleanup_objs;
6608
6609 work->pending_flip_obj = obj;
6610
6611 work->enable_stall_check = true;
6612
6613 /* Block clients from rendering to the new back buffer until
6614 * the flip occurs and the object is no longer visible.
6615 */
6616 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6617
6618 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6619 if (ret)
6620 goto cleanup_pending;
6621
6622 mutex_unlock(&dev->struct_mutex);
6623
6624 trace_i915_flip_request(intel_crtc->plane, obj);
6625
6626 return 0;
6627
6628 cleanup_pending:
6629 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6630 cleanup_objs:
6631 drm_gem_object_unreference(&work->old_fb_obj->base);
6632 drm_gem_object_unreference(&obj->base);
6633 mutex_unlock(&dev->struct_mutex);
6634
6635 spin_lock_irqsave(&dev->event_lock, flags);
6636 intel_crtc->unpin_work = NULL;
6637 spin_unlock_irqrestore(&dev->event_lock, flags);
6638
6639 kfree(work);
6640
6641 return ret;
6642 }
6643
6644 static void intel_sanitize_modesetting(struct drm_device *dev,
6645 int pipe, int plane)
6646 {
6647 struct drm_i915_private *dev_priv = dev->dev_private;
6648 u32 reg, val;
6649
6650 if (HAS_PCH_SPLIT(dev))
6651 return;
6652
6653 /* Who knows what state these registers were left in by the BIOS or
6654 * grub?
6655 *
6656 * If we leave the registers in a conflicting state (e.g. with the
6657 * display plane reading from the other pipe than the one we intend
6658 * to use) then when we attempt to teardown the active mode, we will
6659 * not disable the pipes and planes in the correct order -- leaving
6660 * a plane reading from a disabled pipe and possibly leading to
6661 * undefined behaviour.
6662 */
6663
6664 reg = DSPCNTR(plane);
6665 val = I915_READ(reg);
6666
6667 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6668 return;
6669 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6670 return;
6671
6672 /* This display plane is active and attached to the other CPU pipe. */
6673 pipe = !pipe;
6674
6675 /* Disable the plane and wait for it to stop reading from the pipe. */
6676 intel_disable_plane(dev_priv, plane, pipe);
6677 intel_disable_pipe(dev_priv, pipe);
6678 }
6679
6680 static void intel_crtc_reset(struct drm_crtc *crtc)
6681 {
6682 struct drm_device *dev = crtc->dev;
6683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6684
6685 /* Reset flags back to the 'unknown' status so that they
6686 * will be correctly set on the initial modeset.
6687 */
6688 intel_crtc->dpms_mode = -1;
6689
6690 /* We need to fix up any BIOS configuration that conflicts with
6691 * our expectations.
6692 */
6693 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6694 }
6695
6696 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6697 .dpms = intel_crtc_dpms,
6698 .mode_fixup = intel_crtc_mode_fixup,
6699 .mode_set = intel_crtc_mode_set,
6700 .mode_set_base = intel_pipe_set_base,
6701 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6702 .load_lut = intel_crtc_load_lut,
6703 .disable = intel_crtc_disable,
6704 };
6705
6706 static const struct drm_crtc_funcs intel_crtc_funcs = {
6707 .reset = intel_crtc_reset,
6708 .cursor_set = intel_crtc_cursor_set,
6709 .cursor_move = intel_crtc_cursor_move,
6710 .gamma_set = intel_crtc_gamma_set,
6711 .set_config = drm_crtc_helper_set_config,
6712 .destroy = intel_crtc_destroy,
6713 .page_flip = intel_crtc_page_flip,
6714 };
6715
6716 static void intel_crtc_init(struct drm_device *dev, int pipe)
6717 {
6718 drm_i915_private_t *dev_priv = dev->dev_private;
6719 struct intel_crtc *intel_crtc;
6720 int i;
6721
6722 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6723 if (intel_crtc == NULL)
6724 return;
6725
6726 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6727
6728 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6729 for (i = 0; i < 256; i++) {
6730 intel_crtc->lut_r[i] = i;
6731 intel_crtc->lut_g[i] = i;
6732 intel_crtc->lut_b[i] = i;
6733 }
6734
6735 /* Swap pipes & planes for FBC on pre-965 */
6736 intel_crtc->pipe = pipe;
6737 intel_crtc->plane = pipe;
6738 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6739 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6740 intel_crtc->plane = !pipe;
6741 }
6742
6743 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6744 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6745 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6746 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6747
6748 intel_crtc_reset(&intel_crtc->base);
6749 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6750 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6751
6752 if (HAS_PCH_SPLIT(dev)) {
6753 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6754 intel_helper_funcs.commit = ironlake_crtc_commit;
6755 } else {
6756 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6757 intel_helper_funcs.commit = i9xx_crtc_commit;
6758 }
6759
6760 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6761
6762 intel_crtc->busy = false;
6763
6764 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6765 (unsigned long)intel_crtc);
6766 }
6767
6768 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6769 struct drm_file *file)
6770 {
6771 drm_i915_private_t *dev_priv = dev->dev_private;
6772 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6773 struct drm_mode_object *drmmode_obj;
6774 struct intel_crtc *crtc;
6775
6776 if (!dev_priv) {
6777 DRM_ERROR("called with no initialization\n");
6778 return -EINVAL;
6779 }
6780
6781 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6782 DRM_MODE_OBJECT_CRTC);
6783
6784 if (!drmmode_obj) {
6785 DRM_ERROR("no such CRTC id\n");
6786 return -EINVAL;
6787 }
6788
6789 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6790 pipe_from_crtc_id->pipe = crtc->pipe;
6791
6792 return 0;
6793 }
6794
6795 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6796 {
6797 struct intel_encoder *encoder;
6798 int index_mask = 0;
6799 int entry = 0;
6800
6801 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6802 if (type_mask & encoder->clone_mask)
6803 index_mask |= (1 << entry);
6804 entry++;
6805 }
6806
6807 return index_mask;
6808 }
6809
6810 static bool has_edp_a(struct drm_device *dev)
6811 {
6812 struct drm_i915_private *dev_priv = dev->dev_private;
6813
6814 if (!IS_MOBILE(dev))
6815 return false;
6816
6817 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6818 return false;
6819
6820 if (IS_GEN5(dev) &&
6821 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6822 return false;
6823
6824 return true;
6825 }
6826
6827 static void intel_setup_outputs(struct drm_device *dev)
6828 {
6829 struct drm_i915_private *dev_priv = dev->dev_private;
6830 struct intel_encoder *encoder;
6831 bool dpd_is_edp = false;
6832 bool has_lvds = false;
6833
6834 if (IS_MOBILE(dev) && !IS_I830(dev))
6835 has_lvds = intel_lvds_init(dev);
6836 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6837 /* disable the panel fitter on everything but LVDS */
6838 I915_WRITE(PFIT_CONTROL, 0);
6839 }
6840
6841 if (HAS_PCH_SPLIT(dev)) {
6842 dpd_is_edp = intel_dpd_is_edp(dev);
6843
6844 if (has_edp_a(dev))
6845 intel_dp_init(dev, DP_A);
6846
6847 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6848 intel_dp_init(dev, PCH_DP_D);
6849 }
6850
6851 intel_crt_init(dev);
6852
6853 if (HAS_PCH_SPLIT(dev)) {
6854 int found;
6855
6856 if (I915_READ(HDMIB) & PORT_DETECTED) {
6857 /* PCH SDVOB multiplex with HDMIB */
6858 found = intel_sdvo_init(dev, PCH_SDVOB);
6859 if (!found)
6860 intel_hdmi_init(dev, HDMIB);
6861 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6862 intel_dp_init(dev, PCH_DP_B);
6863 }
6864
6865 if (I915_READ(HDMIC) & PORT_DETECTED)
6866 intel_hdmi_init(dev, HDMIC);
6867
6868 if (I915_READ(HDMID) & PORT_DETECTED)
6869 intel_hdmi_init(dev, HDMID);
6870
6871 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6872 intel_dp_init(dev, PCH_DP_C);
6873
6874 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6875 intel_dp_init(dev, PCH_DP_D);
6876
6877 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6878 bool found = false;
6879
6880 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6881 DRM_DEBUG_KMS("probing SDVOB\n");
6882 found = intel_sdvo_init(dev, SDVOB);
6883 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6884 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6885 intel_hdmi_init(dev, SDVOB);
6886 }
6887
6888 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6889 DRM_DEBUG_KMS("probing DP_B\n");
6890 intel_dp_init(dev, DP_B);
6891 }
6892 }
6893
6894 /* Before G4X SDVOC doesn't have its own detect register */
6895
6896 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6897 DRM_DEBUG_KMS("probing SDVOC\n");
6898 found = intel_sdvo_init(dev, SDVOC);
6899 }
6900
6901 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6902
6903 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6904 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6905 intel_hdmi_init(dev, SDVOC);
6906 }
6907 if (SUPPORTS_INTEGRATED_DP(dev)) {
6908 DRM_DEBUG_KMS("probing DP_C\n");
6909 intel_dp_init(dev, DP_C);
6910 }
6911 }
6912
6913 if (SUPPORTS_INTEGRATED_DP(dev) &&
6914 (I915_READ(DP_D) & DP_DETECTED)) {
6915 DRM_DEBUG_KMS("probing DP_D\n");
6916 intel_dp_init(dev, DP_D);
6917 }
6918 } else if (IS_GEN2(dev))
6919 intel_dvo_init(dev);
6920
6921 if (SUPPORTS_TV(dev))
6922 intel_tv_init(dev);
6923
6924 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6925 encoder->base.possible_crtcs = encoder->crtc_mask;
6926 encoder->base.possible_clones =
6927 intel_encoder_clones(dev, encoder->clone_mask);
6928 }
6929
6930 intel_panel_setup_backlight(dev);
6931
6932 /* disable all the possible outputs/crtcs before entering KMS mode */
6933 drm_helper_disable_unused_functions(dev);
6934 }
6935
6936 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6937 {
6938 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6939
6940 drm_framebuffer_cleanup(fb);
6941 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6942
6943 kfree(intel_fb);
6944 }
6945
6946 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6947 struct drm_file *file,
6948 unsigned int *handle)
6949 {
6950 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6951 struct drm_i915_gem_object *obj = intel_fb->obj;
6952
6953 return drm_gem_handle_create(file, &obj->base, handle);
6954 }
6955
6956 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6957 .destroy = intel_user_framebuffer_destroy,
6958 .create_handle = intel_user_framebuffer_create_handle,
6959 };
6960
6961 int intel_framebuffer_init(struct drm_device *dev,
6962 struct intel_framebuffer *intel_fb,
6963 struct drm_mode_fb_cmd *mode_cmd,
6964 struct drm_i915_gem_object *obj)
6965 {
6966 int ret;
6967
6968 if (obj->tiling_mode == I915_TILING_Y)
6969 return -EINVAL;
6970
6971 if (mode_cmd->pitch & 63)
6972 return -EINVAL;
6973
6974 switch (mode_cmd->bpp) {
6975 case 8:
6976 case 16:
6977 case 24:
6978 case 32:
6979 break;
6980 default:
6981 return -EINVAL;
6982 }
6983
6984 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6985 if (ret) {
6986 DRM_ERROR("framebuffer init failed %d\n", ret);
6987 return ret;
6988 }
6989
6990 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6991 intel_fb->obj = obj;
6992 return 0;
6993 }
6994
6995 static struct drm_framebuffer *
6996 intel_user_framebuffer_create(struct drm_device *dev,
6997 struct drm_file *filp,
6998 struct drm_mode_fb_cmd *mode_cmd)
6999 {
7000 struct drm_i915_gem_object *obj;
7001
7002 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7003 if (&obj->base == NULL)
7004 return ERR_PTR(-ENOENT);
7005
7006 return intel_framebuffer_create(dev, mode_cmd, obj);
7007 }
7008
7009 static const struct drm_mode_config_funcs intel_mode_funcs = {
7010 .fb_create = intel_user_framebuffer_create,
7011 .output_poll_changed = intel_fb_output_poll_changed,
7012 };
7013
7014 static struct drm_i915_gem_object *
7015 intel_alloc_context_page(struct drm_device *dev)
7016 {
7017 struct drm_i915_gem_object *ctx;
7018 int ret;
7019
7020 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7021
7022 ctx = i915_gem_alloc_object(dev, 4096);
7023 if (!ctx) {
7024 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7025 return NULL;
7026 }
7027
7028 ret = i915_gem_object_pin(ctx, 4096, true);
7029 if (ret) {
7030 DRM_ERROR("failed to pin power context: %d\n", ret);
7031 goto err_unref;
7032 }
7033
7034 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7035 if (ret) {
7036 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7037 goto err_unpin;
7038 }
7039
7040 return ctx;
7041
7042 err_unpin:
7043 i915_gem_object_unpin(ctx);
7044 err_unref:
7045 drm_gem_object_unreference(&ctx->base);
7046 mutex_unlock(&dev->struct_mutex);
7047 return NULL;
7048 }
7049
7050 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7051 {
7052 struct drm_i915_private *dev_priv = dev->dev_private;
7053 u16 rgvswctl;
7054
7055 rgvswctl = I915_READ16(MEMSWCTL);
7056 if (rgvswctl & MEMCTL_CMD_STS) {
7057 DRM_DEBUG("gpu busy, RCS change rejected\n");
7058 return false; /* still busy with another command */
7059 }
7060
7061 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7062 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7063 I915_WRITE16(MEMSWCTL, rgvswctl);
7064 POSTING_READ16(MEMSWCTL);
7065
7066 rgvswctl |= MEMCTL_CMD_STS;
7067 I915_WRITE16(MEMSWCTL, rgvswctl);
7068
7069 return true;
7070 }
7071
7072 void ironlake_enable_drps(struct drm_device *dev)
7073 {
7074 struct drm_i915_private *dev_priv = dev->dev_private;
7075 u32 rgvmodectl = I915_READ(MEMMODECTL);
7076 u8 fmax, fmin, fstart, vstart;
7077
7078 /* Enable temp reporting */
7079 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7080 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7081
7082 /* 100ms RC evaluation intervals */
7083 I915_WRITE(RCUPEI, 100000);
7084 I915_WRITE(RCDNEI, 100000);
7085
7086 /* Set max/min thresholds to 90ms and 80ms respectively */
7087 I915_WRITE(RCBMAXAVG, 90000);
7088 I915_WRITE(RCBMINAVG, 80000);
7089
7090 I915_WRITE(MEMIHYST, 1);
7091
7092 /* Set up min, max, and cur for interrupt handling */
7093 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7094 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7095 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7096 MEMMODE_FSTART_SHIFT;
7097
7098 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7099 PXVFREQ_PX_SHIFT;
7100
7101 dev_priv->fmax = fmax; /* IPS callback will increase this */
7102 dev_priv->fstart = fstart;
7103
7104 dev_priv->max_delay = fstart;
7105 dev_priv->min_delay = fmin;
7106 dev_priv->cur_delay = fstart;
7107
7108 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7109 fmax, fmin, fstart);
7110
7111 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7112
7113 /*
7114 * Interrupts will be enabled in ironlake_irq_postinstall
7115 */
7116
7117 I915_WRITE(VIDSTART, vstart);
7118 POSTING_READ(VIDSTART);
7119
7120 rgvmodectl |= MEMMODE_SWMODE_EN;
7121 I915_WRITE(MEMMODECTL, rgvmodectl);
7122
7123 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7124 DRM_ERROR("stuck trying to change perf mode\n");
7125 msleep(1);
7126
7127 ironlake_set_drps(dev, fstart);
7128
7129 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7130 I915_READ(0x112e0);
7131 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7132 dev_priv->last_count2 = I915_READ(0x112f4);
7133 getrawmonotonic(&dev_priv->last_time2);
7134 }
7135
7136 void ironlake_disable_drps(struct drm_device *dev)
7137 {
7138 struct drm_i915_private *dev_priv = dev->dev_private;
7139 u16 rgvswctl = I915_READ16(MEMSWCTL);
7140
7141 /* Ack interrupts, disable EFC interrupt */
7142 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7143 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7144 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7145 I915_WRITE(DEIIR, DE_PCU_EVENT);
7146 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7147
7148 /* Go back to the starting frequency */
7149 ironlake_set_drps(dev, dev_priv->fstart);
7150 msleep(1);
7151 rgvswctl |= MEMCTL_CMD_STS;
7152 I915_WRITE(MEMSWCTL, rgvswctl);
7153 msleep(1);
7154
7155 }
7156
7157 void gen6_set_rps(struct drm_device *dev, u8 val)
7158 {
7159 struct drm_i915_private *dev_priv = dev->dev_private;
7160 u32 swreq;
7161
7162 swreq = (val & 0x3ff) << 25;
7163 I915_WRITE(GEN6_RPNSWREQ, swreq);
7164 }
7165
7166 void gen6_disable_rps(struct drm_device *dev)
7167 {
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169
7170 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7171 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7172 I915_WRITE(GEN6_PMIER, 0);
7173
7174 spin_lock_irq(&dev_priv->rps_lock);
7175 dev_priv->pm_iir = 0;
7176 spin_unlock_irq(&dev_priv->rps_lock);
7177
7178 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7179 }
7180
7181 static unsigned long intel_pxfreq(u32 vidfreq)
7182 {
7183 unsigned long freq;
7184 int div = (vidfreq & 0x3f0000) >> 16;
7185 int post = (vidfreq & 0x3000) >> 12;
7186 int pre = (vidfreq & 0x7);
7187
7188 if (!pre)
7189 return 0;
7190
7191 freq = ((div * 133333) / ((1<<post) * pre));
7192
7193 return freq;
7194 }
7195
7196 void intel_init_emon(struct drm_device *dev)
7197 {
7198 struct drm_i915_private *dev_priv = dev->dev_private;
7199 u32 lcfuse;
7200 u8 pxw[16];
7201 int i;
7202
7203 /* Disable to program */
7204 I915_WRITE(ECR, 0);
7205 POSTING_READ(ECR);
7206
7207 /* Program energy weights for various events */
7208 I915_WRITE(SDEW, 0x15040d00);
7209 I915_WRITE(CSIEW0, 0x007f0000);
7210 I915_WRITE(CSIEW1, 0x1e220004);
7211 I915_WRITE(CSIEW2, 0x04000004);
7212
7213 for (i = 0; i < 5; i++)
7214 I915_WRITE(PEW + (i * 4), 0);
7215 for (i = 0; i < 3; i++)
7216 I915_WRITE(DEW + (i * 4), 0);
7217
7218 /* Program P-state weights to account for frequency power adjustment */
7219 for (i = 0; i < 16; i++) {
7220 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7221 unsigned long freq = intel_pxfreq(pxvidfreq);
7222 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7223 PXVFREQ_PX_SHIFT;
7224 unsigned long val;
7225
7226 val = vid * vid;
7227 val *= (freq / 1000);
7228 val *= 255;
7229 val /= (127*127*900);
7230 if (val > 0xff)
7231 DRM_ERROR("bad pxval: %ld\n", val);
7232 pxw[i] = val;
7233 }
7234 /* Render standby states get 0 weight */
7235 pxw[14] = 0;
7236 pxw[15] = 0;
7237
7238 for (i = 0; i < 4; i++) {
7239 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7240 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7241 I915_WRITE(PXW + (i * 4), val);
7242 }
7243
7244 /* Adjust magic regs to magic values (more experimental results) */
7245 I915_WRITE(OGW0, 0);
7246 I915_WRITE(OGW1, 0);
7247 I915_WRITE(EG0, 0x00007f00);
7248 I915_WRITE(EG1, 0x0000000e);
7249 I915_WRITE(EG2, 0x000e0000);
7250 I915_WRITE(EG3, 0x68000300);
7251 I915_WRITE(EG4, 0x42000000);
7252 I915_WRITE(EG5, 0x00140031);
7253 I915_WRITE(EG6, 0);
7254 I915_WRITE(EG7, 0);
7255
7256 for (i = 0; i < 8; i++)
7257 I915_WRITE(PXWL + (i * 4), 0);
7258
7259 /* Enable PMON + select events */
7260 I915_WRITE(ECR, 0x80000019);
7261
7262 lcfuse = I915_READ(LCFUSE02);
7263
7264 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7265 }
7266
7267 void gen6_enable_rps(struct drm_i915_private *dev_priv)
7268 {
7269 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7270 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7271 u32 pcu_mbox, rc6_mask = 0;
7272 int cur_freq, min_freq, max_freq;
7273 int i;
7274
7275 /* Here begins a magic sequence of register writes to enable
7276 * auto-downclocking.
7277 *
7278 * Perhaps there might be some value in exposing these to
7279 * userspace...
7280 */
7281 I915_WRITE(GEN6_RC_STATE, 0);
7282 mutex_lock(&dev_priv->dev->struct_mutex);
7283 gen6_gt_force_wake_get(dev_priv);
7284
7285 /* disable the counters and set deterministic thresholds */
7286 I915_WRITE(GEN6_RC_CONTROL, 0);
7287
7288 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7289 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7290 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7291 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7292 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7293
7294 for (i = 0; i < I915_NUM_RINGS; i++)
7295 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7296
7297 I915_WRITE(GEN6_RC_SLEEP, 0);
7298 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7299 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7300 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7301 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7302
7303 if (i915_enable_rc6)
7304 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7305 GEN6_RC_CTL_RC6_ENABLE;
7306
7307 I915_WRITE(GEN6_RC_CONTROL,
7308 rc6_mask |
7309 GEN6_RC_CTL_EI_MODE(1) |
7310 GEN6_RC_CTL_HW_ENABLE);
7311
7312 I915_WRITE(GEN6_RPNSWREQ,
7313 GEN6_FREQUENCY(10) |
7314 GEN6_OFFSET(0) |
7315 GEN6_AGGRESSIVE_TURBO);
7316 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7317 GEN6_FREQUENCY(12));
7318
7319 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7320 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7321 18 << 24 |
7322 6 << 16);
7323 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7324 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
7325 I915_WRITE(GEN6_RP_UP_EI, 100000);
7326 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
7327 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7328 I915_WRITE(GEN6_RP_CONTROL,
7329 GEN6_RP_MEDIA_TURBO |
7330 GEN6_RP_USE_NORMAL_FREQ |
7331 GEN6_RP_MEDIA_IS_GFX |
7332 GEN6_RP_ENABLE |
7333 GEN6_RP_UP_BUSY_AVG |
7334 GEN6_RP_DOWN_IDLE_CONT);
7335
7336 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7337 500))
7338 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7339
7340 I915_WRITE(GEN6_PCODE_DATA, 0);
7341 I915_WRITE(GEN6_PCODE_MAILBOX,
7342 GEN6_PCODE_READY |
7343 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7344 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7345 500))
7346 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7347
7348 min_freq = (rp_state_cap & 0xff0000) >> 16;
7349 max_freq = rp_state_cap & 0xff;
7350 cur_freq = (gt_perf_status & 0xff00) >> 8;
7351
7352 /* Check for overclock support */
7353 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7354 500))
7355 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7356 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7357 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7358 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7359 500))
7360 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7361 if (pcu_mbox & (1<<31)) { /* OC supported */
7362 max_freq = pcu_mbox & 0xff;
7363 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
7364 }
7365
7366 /* In units of 100MHz */
7367 dev_priv->max_delay = max_freq;
7368 dev_priv->min_delay = min_freq;
7369 dev_priv->cur_delay = cur_freq;
7370
7371 /* requires MSI enabled */
7372 I915_WRITE(GEN6_PMIER,
7373 GEN6_PM_MBOX_EVENT |
7374 GEN6_PM_THERMAL_EVENT |
7375 GEN6_PM_RP_DOWN_TIMEOUT |
7376 GEN6_PM_RP_UP_THRESHOLD |
7377 GEN6_PM_RP_DOWN_THRESHOLD |
7378 GEN6_PM_RP_UP_EI_EXPIRED |
7379 GEN6_PM_RP_DOWN_EI_EXPIRED);
7380 spin_lock_irq(&dev_priv->rps_lock);
7381 WARN_ON(dev_priv->pm_iir != 0);
7382 I915_WRITE(GEN6_PMIMR, 0);
7383 spin_unlock_irq(&dev_priv->rps_lock);
7384 /* enable all PM interrupts */
7385 I915_WRITE(GEN6_PMINTRMSK, 0);
7386
7387 gen6_gt_force_wake_put(dev_priv);
7388 mutex_unlock(&dev_priv->dev->struct_mutex);
7389 }
7390
7391 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7392 {
7393 int min_freq = 15;
7394 int gpu_freq, ia_freq, max_ia_freq;
7395 int scaling_factor = 180;
7396
7397 max_ia_freq = cpufreq_quick_get_max(0);
7398 /*
7399 * Default to measured freq if none found, PCU will ensure we don't go
7400 * over
7401 */
7402 if (!max_ia_freq)
7403 max_ia_freq = tsc_khz;
7404
7405 /* Convert from kHz to MHz */
7406 max_ia_freq /= 1000;
7407
7408 mutex_lock(&dev_priv->dev->struct_mutex);
7409
7410 /*
7411 * For each potential GPU frequency, load a ring frequency we'd like
7412 * to use for memory access. We do this by specifying the IA frequency
7413 * the PCU should use as a reference to determine the ring frequency.
7414 */
7415 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7416 gpu_freq--) {
7417 int diff = dev_priv->max_delay - gpu_freq;
7418
7419 /*
7420 * For GPU frequencies less than 750MHz, just use the lowest
7421 * ring freq.
7422 */
7423 if (gpu_freq < min_freq)
7424 ia_freq = 800;
7425 else
7426 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7427 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7428
7429 I915_WRITE(GEN6_PCODE_DATA,
7430 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7431 gpu_freq);
7432 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7433 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7434 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7435 GEN6_PCODE_READY) == 0, 10)) {
7436 DRM_ERROR("pcode write of freq table timed out\n");
7437 continue;
7438 }
7439 }
7440
7441 mutex_unlock(&dev_priv->dev->struct_mutex);
7442 }
7443
7444 static void ironlake_init_clock_gating(struct drm_device *dev)
7445 {
7446 struct drm_i915_private *dev_priv = dev->dev_private;
7447 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7448
7449 /* Required for FBC */
7450 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7451 DPFCRUNIT_CLOCK_GATE_DISABLE |
7452 DPFDUNIT_CLOCK_GATE_DISABLE;
7453 /* Required for CxSR */
7454 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7455
7456 I915_WRITE(PCH_3DCGDIS0,
7457 MARIUNIT_CLOCK_GATE_DISABLE |
7458 SVSMUNIT_CLOCK_GATE_DISABLE);
7459 I915_WRITE(PCH_3DCGDIS1,
7460 VFMUNIT_CLOCK_GATE_DISABLE);
7461
7462 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7463
7464 /*
7465 * According to the spec the following bits should be set in
7466 * order to enable memory self-refresh
7467 * The bit 22/21 of 0x42004
7468 * The bit 5 of 0x42020
7469 * The bit 15 of 0x45000
7470 */
7471 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7472 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7473 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7474 I915_WRITE(ILK_DSPCLK_GATE,
7475 (I915_READ(ILK_DSPCLK_GATE) |
7476 ILK_DPARB_CLK_GATE));
7477 I915_WRITE(DISP_ARB_CTL,
7478 (I915_READ(DISP_ARB_CTL) |
7479 DISP_FBC_WM_DIS));
7480 I915_WRITE(WM3_LP_ILK, 0);
7481 I915_WRITE(WM2_LP_ILK, 0);
7482 I915_WRITE(WM1_LP_ILK, 0);
7483
7484 /*
7485 * Based on the document from hardware guys the following bits
7486 * should be set unconditionally in order to enable FBC.
7487 * The bit 22 of 0x42000
7488 * The bit 22 of 0x42004
7489 * The bit 7,8,9 of 0x42020.
7490 */
7491 if (IS_IRONLAKE_M(dev)) {
7492 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7493 I915_READ(ILK_DISPLAY_CHICKEN1) |
7494 ILK_FBCQ_DIS);
7495 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7496 I915_READ(ILK_DISPLAY_CHICKEN2) |
7497 ILK_DPARB_GATE);
7498 I915_WRITE(ILK_DSPCLK_GATE,
7499 I915_READ(ILK_DSPCLK_GATE) |
7500 ILK_DPFC_DIS1 |
7501 ILK_DPFC_DIS2 |
7502 ILK_CLK_FBC);
7503 }
7504
7505 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7506 I915_READ(ILK_DISPLAY_CHICKEN2) |
7507 ILK_ELPIN_409_SELECT);
7508 I915_WRITE(_3D_CHICKEN2,
7509 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7510 _3D_CHICKEN2_WM_READ_PIPELINED);
7511 }
7512
7513 static void gen6_init_clock_gating(struct drm_device *dev)
7514 {
7515 struct drm_i915_private *dev_priv = dev->dev_private;
7516 int pipe;
7517 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7518
7519 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7520
7521 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7522 I915_READ(ILK_DISPLAY_CHICKEN2) |
7523 ILK_ELPIN_409_SELECT);
7524
7525 I915_WRITE(WM3_LP_ILK, 0);
7526 I915_WRITE(WM2_LP_ILK, 0);
7527 I915_WRITE(WM1_LP_ILK, 0);
7528
7529 /*
7530 * According to the spec the following bits should be
7531 * set in order to enable memory self-refresh and fbc:
7532 * The bit21 and bit22 of 0x42000
7533 * The bit21 and bit22 of 0x42004
7534 * The bit5 and bit7 of 0x42020
7535 * The bit14 of 0x70180
7536 * The bit14 of 0x71180
7537 */
7538 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7539 I915_READ(ILK_DISPLAY_CHICKEN1) |
7540 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7541 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7542 I915_READ(ILK_DISPLAY_CHICKEN2) |
7543 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7544 I915_WRITE(ILK_DSPCLK_GATE,
7545 I915_READ(ILK_DSPCLK_GATE) |
7546 ILK_DPARB_CLK_GATE |
7547 ILK_DPFD_CLK_GATE);
7548
7549 for_each_pipe(pipe)
7550 I915_WRITE(DSPCNTR(pipe),
7551 I915_READ(DSPCNTR(pipe)) |
7552 DISPPLANE_TRICKLE_FEED_DISABLE);
7553 }
7554
7555 static void ivybridge_init_clock_gating(struct drm_device *dev)
7556 {
7557 struct drm_i915_private *dev_priv = dev->dev_private;
7558 int pipe;
7559 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7560
7561 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7562
7563 I915_WRITE(WM3_LP_ILK, 0);
7564 I915_WRITE(WM2_LP_ILK, 0);
7565 I915_WRITE(WM1_LP_ILK, 0);
7566
7567 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7568
7569 for_each_pipe(pipe)
7570 I915_WRITE(DSPCNTR(pipe),
7571 I915_READ(DSPCNTR(pipe)) |
7572 DISPPLANE_TRICKLE_FEED_DISABLE);
7573 }
7574
7575 static void g4x_init_clock_gating(struct drm_device *dev)
7576 {
7577 struct drm_i915_private *dev_priv = dev->dev_private;
7578 uint32_t dspclk_gate;
7579
7580 I915_WRITE(RENCLK_GATE_D1, 0);
7581 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7582 GS_UNIT_CLOCK_GATE_DISABLE |
7583 CL_UNIT_CLOCK_GATE_DISABLE);
7584 I915_WRITE(RAMCLK_GATE_D, 0);
7585 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7586 OVRUNIT_CLOCK_GATE_DISABLE |
7587 OVCUNIT_CLOCK_GATE_DISABLE;
7588 if (IS_GM45(dev))
7589 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7590 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7591 }
7592
7593 static void crestline_init_clock_gating(struct drm_device *dev)
7594 {
7595 struct drm_i915_private *dev_priv = dev->dev_private;
7596
7597 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7598 I915_WRITE(RENCLK_GATE_D2, 0);
7599 I915_WRITE(DSPCLK_GATE_D, 0);
7600 I915_WRITE(RAMCLK_GATE_D, 0);
7601 I915_WRITE16(DEUC, 0);
7602 }
7603
7604 static void broadwater_init_clock_gating(struct drm_device *dev)
7605 {
7606 struct drm_i915_private *dev_priv = dev->dev_private;
7607
7608 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7609 I965_RCC_CLOCK_GATE_DISABLE |
7610 I965_RCPB_CLOCK_GATE_DISABLE |
7611 I965_ISC_CLOCK_GATE_DISABLE |
7612 I965_FBC_CLOCK_GATE_DISABLE);
7613 I915_WRITE(RENCLK_GATE_D2, 0);
7614 }
7615
7616 static void gen3_init_clock_gating(struct drm_device *dev)
7617 {
7618 struct drm_i915_private *dev_priv = dev->dev_private;
7619 u32 dstate = I915_READ(D_STATE);
7620
7621 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7622 DSTATE_DOT_CLOCK_GATING;
7623 I915_WRITE(D_STATE, dstate);
7624 }
7625
7626 static void i85x_init_clock_gating(struct drm_device *dev)
7627 {
7628 struct drm_i915_private *dev_priv = dev->dev_private;
7629
7630 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7631 }
7632
7633 static void i830_init_clock_gating(struct drm_device *dev)
7634 {
7635 struct drm_i915_private *dev_priv = dev->dev_private;
7636
7637 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7638 }
7639
7640 static void ibx_init_clock_gating(struct drm_device *dev)
7641 {
7642 struct drm_i915_private *dev_priv = dev->dev_private;
7643
7644 /*
7645 * On Ibex Peak and Cougar Point, we need to disable clock
7646 * gating for the panel power sequencer or it will fail to
7647 * start up when no ports are active.
7648 */
7649 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7650 }
7651
7652 static void cpt_init_clock_gating(struct drm_device *dev)
7653 {
7654 struct drm_i915_private *dev_priv = dev->dev_private;
7655
7656 /*
7657 * On Ibex Peak and Cougar Point, we need to disable clock
7658 * gating for the panel power sequencer or it will fail to
7659 * start up when no ports are active.
7660 */
7661 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7662 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7663 DPLS_EDP_PPS_FIX_DIS);
7664 }
7665
7666 static void ironlake_teardown_rc6(struct drm_device *dev)
7667 {
7668 struct drm_i915_private *dev_priv = dev->dev_private;
7669
7670 if (dev_priv->renderctx) {
7671 i915_gem_object_unpin(dev_priv->renderctx);
7672 drm_gem_object_unreference(&dev_priv->renderctx->base);
7673 dev_priv->renderctx = NULL;
7674 }
7675
7676 if (dev_priv->pwrctx) {
7677 i915_gem_object_unpin(dev_priv->pwrctx);
7678 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7679 dev_priv->pwrctx = NULL;
7680 }
7681 }
7682
7683 static void ironlake_disable_rc6(struct drm_device *dev)
7684 {
7685 struct drm_i915_private *dev_priv = dev->dev_private;
7686
7687 if (I915_READ(PWRCTXA)) {
7688 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7689 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7690 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7691 50);
7692
7693 I915_WRITE(PWRCTXA, 0);
7694 POSTING_READ(PWRCTXA);
7695
7696 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7697 POSTING_READ(RSTDBYCTL);
7698 }
7699
7700 ironlake_teardown_rc6(dev);
7701 }
7702
7703 static int ironlake_setup_rc6(struct drm_device *dev)
7704 {
7705 struct drm_i915_private *dev_priv = dev->dev_private;
7706
7707 if (dev_priv->renderctx == NULL)
7708 dev_priv->renderctx = intel_alloc_context_page(dev);
7709 if (!dev_priv->renderctx)
7710 return -ENOMEM;
7711
7712 if (dev_priv->pwrctx == NULL)
7713 dev_priv->pwrctx = intel_alloc_context_page(dev);
7714 if (!dev_priv->pwrctx) {
7715 ironlake_teardown_rc6(dev);
7716 return -ENOMEM;
7717 }
7718
7719 return 0;
7720 }
7721
7722 void ironlake_enable_rc6(struct drm_device *dev)
7723 {
7724 struct drm_i915_private *dev_priv = dev->dev_private;
7725 int ret;
7726
7727 /* rc6 disabled by default due to repeated reports of hanging during
7728 * boot and resume.
7729 */
7730 if (!i915_enable_rc6)
7731 return;
7732
7733 mutex_lock(&dev->struct_mutex);
7734 ret = ironlake_setup_rc6(dev);
7735 if (ret) {
7736 mutex_unlock(&dev->struct_mutex);
7737 return;
7738 }
7739
7740 /*
7741 * GPU can automatically power down the render unit if given a page
7742 * to save state.
7743 */
7744 ret = BEGIN_LP_RING(6);
7745 if (ret) {
7746 ironlake_teardown_rc6(dev);
7747 mutex_unlock(&dev->struct_mutex);
7748 return;
7749 }
7750
7751 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7752 OUT_RING(MI_SET_CONTEXT);
7753 OUT_RING(dev_priv->renderctx->gtt_offset |
7754 MI_MM_SPACE_GTT |
7755 MI_SAVE_EXT_STATE_EN |
7756 MI_RESTORE_EXT_STATE_EN |
7757 MI_RESTORE_INHIBIT);
7758 OUT_RING(MI_SUSPEND_FLUSH);
7759 OUT_RING(MI_NOOP);
7760 OUT_RING(MI_FLUSH);
7761 ADVANCE_LP_RING();
7762
7763 /*
7764 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7765 * does an implicit flush, combined with MI_FLUSH above, it should be
7766 * safe to assume that renderctx is valid
7767 */
7768 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7769 if (ret) {
7770 DRM_ERROR("failed to enable ironlake power power savings\n");
7771 ironlake_teardown_rc6(dev);
7772 mutex_unlock(&dev->struct_mutex);
7773 return;
7774 }
7775
7776 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7777 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7778 mutex_unlock(&dev->struct_mutex);
7779 }
7780
7781 void intel_init_clock_gating(struct drm_device *dev)
7782 {
7783 struct drm_i915_private *dev_priv = dev->dev_private;
7784
7785 dev_priv->display.init_clock_gating(dev);
7786
7787 if (dev_priv->display.init_pch_clock_gating)
7788 dev_priv->display.init_pch_clock_gating(dev);
7789 }
7790
7791 /* Set up chip specific display functions */
7792 static void intel_init_display(struct drm_device *dev)
7793 {
7794 struct drm_i915_private *dev_priv = dev->dev_private;
7795
7796 /* We always want a DPMS function */
7797 if (HAS_PCH_SPLIT(dev)) {
7798 dev_priv->display.dpms = ironlake_crtc_dpms;
7799 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7800 } else {
7801 dev_priv->display.dpms = i9xx_crtc_dpms;
7802 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7803 }
7804
7805 if (I915_HAS_FBC(dev)) {
7806 if (HAS_PCH_SPLIT(dev)) {
7807 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7808 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7809 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7810 } else if (IS_GM45(dev)) {
7811 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7812 dev_priv->display.enable_fbc = g4x_enable_fbc;
7813 dev_priv->display.disable_fbc = g4x_disable_fbc;
7814 } else if (IS_CRESTLINE(dev)) {
7815 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7816 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7817 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7818 }
7819 /* 855GM needs testing */
7820 }
7821
7822 /* Returns the core display clock speed */
7823 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
7824 dev_priv->display.get_display_clock_speed =
7825 i945_get_display_clock_speed;
7826 else if (IS_I915G(dev))
7827 dev_priv->display.get_display_clock_speed =
7828 i915_get_display_clock_speed;
7829 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7830 dev_priv->display.get_display_clock_speed =
7831 i9xx_misc_get_display_clock_speed;
7832 else if (IS_I915GM(dev))
7833 dev_priv->display.get_display_clock_speed =
7834 i915gm_get_display_clock_speed;
7835 else if (IS_I865G(dev))
7836 dev_priv->display.get_display_clock_speed =
7837 i865_get_display_clock_speed;
7838 else if (IS_I85X(dev))
7839 dev_priv->display.get_display_clock_speed =
7840 i855_get_display_clock_speed;
7841 else /* 852, 830 */
7842 dev_priv->display.get_display_clock_speed =
7843 i830_get_display_clock_speed;
7844
7845 /* For FIFO watermark updates */
7846 if (HAS_PCH_SPLIT(dev)) {
7847 if (HAS_PCH_IBX(dev))
7848 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7849 else if (HAS_PCH_CPT(dev))
7850 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7851
7852 if (IS_GEN5(dev)) {
7853 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7854 dev_priv->display.update_wm = ironlake_update_wm;
7855 else {
7856 DRM_DEBUG_KMS("Failed to get proper latency. "
7857 "Disable CxSR\n");
7858 dev_priv->display.update_wm = NULL;
7859 }
7860 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7861 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7862 } else if (IS_GEN6(dev)) {
7863 if (SNB_READ_WM0_LATENCY()) {
7864 dev_priv->display.update_wm = sandybridge_update_wm;
7865 } else {
7866 DRM_DEBUG_KMS("Failed to read display plane latency. "
7867 "Disable CxSR\n");
7868 dev_priv->display.update_wm = NULL;
7869 }
7870 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7871 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7872 } else if (IS_IVYBRIDGE(dev)) {
7873 /* FIXME: detect B0+ stepping and use auto training */
7874 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7875 if (SNB_READ_WM0_LATENCY()) {
7876 dev_priv->display.update_wm = sandybridge_update_wm;
7877 } else {
7878 DRM_DEBUG_KMS("Failed to read display plane latency. "
7879 "Disable CxSR\n");
7880 dev_priv->display.update_wm = NULL;
7881 }
7882 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7883
7884 } else
7885 dev_priv->display.update_wm = NULL;
7886 } else if (IS_PINEVIEW(dev)) {
7887 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7888 dev_priv->is_ddr3,
7889 dev_priv->fsb_freq,
7890 dev_priv->mem_freq)) {
7891 DRM_INFO("failed to find known CxSR latency "
7892 "(found ddr%s fsb freq %d, mem freq %d), "
7893 "disabling CxSR\n",
7894 (dev_priv->is_ddr3 == 1) ? "3": "2",
7895 dev_priv->fsb_freq, dev_priv->mem_freq);
7896 /* Disable CxSR and never update its watermark again */
7897 pineview_disable_cxsr(dev);
7898 dev_priv->display.update_wm = NULL;
7899 } else
7900 dev_priv->display.update_wm = pineview_update_wm;
7901 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7902 } else if (IS_G4X(dev)) {
7903 dev_priv->display.update_wm = g4x_update_wm;
7904 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7905 } else if (IS_GEN4(dev)) {
7906 dev_priv->display.update_wm = i965_update_wm;
7907 if (IS_CRESTLINE(dev))
7908 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7909 else if (IS_BROADWATER(dev))
7910 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7911 } else if (IS_GEN3(dev)) {
7912 dev_priv->display.update_wm = i9xx_update_wm;
7913 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7914 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7915 } else if (IS_I865G(dev)) {
7916 dev_priv->display.update_wm = i830_update_wm;
7917 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7918 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7919 } else if (IS_I85X(dev)) {
7920 dev_priv->display.update_wm = i9xx_update_wm;
7921 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7922 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7923 } else {
7924 dev_priv->display.update_wm = i830_update_wm;
7925 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7926 if (IS_845G(dev))
7927 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7928 else
7929 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7930 }
7931
7932 /* Default just returns -ENODEV to indicate unsupported */
7933 dev_priv->display.queue_flip = intel_default_queue_flip;
7934
7935 switch (INTEL_INFO(dev)->gen) {
7936 case 2:
7937 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7938 break;
7939
7940 case 3:
7941 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7942 break;
7943
7944 case 4:
7945 case 5:
7946 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7947 break;
7948
7949 case 6:
7950 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7951 break;
7952 case 7:
7953 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7954 break;
7955 }
7956 }
7957
7958 /*
7959 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7960 * resume, or other times. This quirk makes sure that's the case for
7961 * affected systems.
7962 */
7963 static void quirk_pipea_force (struct drm_device *dev)
7964 {
7965 struct drm_i915_private *dev_priv = dev->dev_private;
7966
7967 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7968 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7969 }
7970
7971 struct intel_quirk {
7972 int device;
7973 int subsystem_vendor;
7974 int subsystem_device;
7975 void (*hook)(struct drm_device *dev);
7976 };
7977
7978 struct intel_quirk intel_quirks[] = {
7979 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7980 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7981 /* HP Mini needs pipe A force quirk (LP: #322104) */
7982 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7983
7984 /* Thinkpad R31 needs pipe A force quirk */
7985 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7986 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7987 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7988
7989 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7990 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7991 /* ThinkPad X40 needs pipe A force quirk */
7992
7993 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7994 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7995
7996 /* 855 & before need to leave pipe A & dpll A up */
7997 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7998 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7999 };
8000
8001 static void intel_init_quirks(struct drm_device *dev)
8002 {
8003 struct pci_dev *d = dev->pdev;
8004 int i;
8005
8006 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8007 struct intel_quirk *q = &intel_quirks[i];
8008
8009 if (d->device == q->device &&
8010 (d->subsystem_vendor == q->subsystem_vendor ||
8011 q->subsystem_vendor == PCI_ANY_ID) &&
8012 (d->subsystem_device == q->subsystem_device ||
8013 q->subsystem_device == PCI_ANY_ID))
8014 q->hook(dev);
8015 }
8016 }
8017
8018 /* Disable the VGA plane that we never use */
8019 static void i915_disable_vga(struct drm_device *dev)
8020 {
8021 struct drm_i915_private *dev_priv = dev->dev_private;
8022 u8 sr1;
8023 u32 vga_reg;
8024
8025 if (HAS_PCH_SPLIT(dev))
8026 vga_reg = CPU_VGACNTRL;
8027 else
8028 vga_reg = VGACNTRL;
8029
8030 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8031 outb(1, VGA_SR_INDEX);
8032 sr1 = inb(VGA_SR_DATA);
8033 outb(sr1 | 1<<5, VGA_SR_DATA);
8034 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8035 udelay(300);
8036
8037 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8038 POSTING_READ(vga_reg);
8039 }
8040
8041 void intel_modeset_init(struct drm_device *dev)
8042 {
8043 struct drm_i915_private *dev_priv = dev->dev_private;
8044 int i;
8045
8046 drm_mode_config_init(dev);
8047
8048 dev->mode_config.min_width = 0;
8049 dev->mode_config.min_height = 0;
8050
8051 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8052
8053 intel_init_quirks(dev);
8054
8055 intel_init_display(dev);
8056
8057 if (IS_GEN2(dev)) {
8058 dev->mode_config.max_width = 2048;
8059 dev->mode_config.max_height = 2048;
8060 } else if (IS_GEN3(dev)) {
8061 dev->mode_config.max_width = 4096;
8062 dev->mode_config.max_height = 4096;
8063 } else {
8064 dev->mode_config.max_width = 8192;
8065 dev->mode_config.max_height = 8192;
8066 }
8067 dev->mode_config.fb_base = dev->agp->base;
8068
8069 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8070 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8071
8072 for (i = 0; i < dev_priv->num_pipe; i++) {
8073 intel_crtc_init(dev, i);
8074 }
8075
8076 /* Just disable it once at startup */
8077 i915_disable_vga(dev);
8078 intel_setup_outputs(dev);
8079
8080 intel_init_clock_gating(dev);
8081
8082 if (IS_IRONLAKE_M(dev)) {
8083 ironlake_enable_drps(dev);
8084 intel_init_emon(dev);
8085 }
8086
8087 if (IS_GEN6(dev) || IS_GEN7(dev)) {
8088 gen6_enable_rps(dev_priv);
8089 gen6_update_ring_freq(dev_priv);
8090 }
8091
8092 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8093 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8094 (unsigned long)dev);
8095 }
8096
8097 void intel_modeset_gem_init(struct drm_device *dev)
8098 {
8099 if (IS_IRONLAKE_M(dev))
8100 ironlake_enable_rc6(dev);
8101
8102 intel_setup_overlay(dev);
8103 }
8104
8105 void intel_modeset_cleanup(struct drm_device *dev)
8106 {
8107 struct drm_i915_private *dev_priv = dev->dev_private;
8108 struct drm_crtc *crtc;
8109 struct intel_crtc *intel_crtc;
8110
8111 drm_kms_helper_poll_fini(dev);
8112 mutex_lock(&dev->struct_mutex);
8113
8114 intel_unregister_dsm_handler();
8115
8116
8117 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8118 /* Skip inactive CRTCs */
8119 if (!crtc->fb)
8120 continue;
8121
8122 intel_crtc = to_intel_crtc(crtc);
8123 intel_increase_pllclock(crtc);
8124 }
8125
8126 if (dev_priv->display.disable_fbc)
8127 dev_priv->display.disable_fbc(dev);
8128
8129 if (IS_IRONLAKE_M(dev))
8130 ironlake_disable_drps(dev);
8131 if (IS_GEN6(dev) || IS_GEN7(dev))
8132 gen6_disable_rps(dev);
8133
8134 if (IS_IRONLAKE_M(dev))
8135 ironlake_disable_rc6(dev);
8136
8137 mutex_unlock(&dev->struct_mutex);
8138
8139 /* Disable the irq before mode object teardown, for the irq might
8140 * enqueue unpin/hotplug work. */
8141 drm_irq_uninstall(dev);
8142 cancel_work_sync(&dev_priv->hotplug_work);
8143
8144 /* Shut off idle work before the crtcs get freed. */
8145 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8146 intel_crtc = to_intel_crtc(crtc);
8147 del_timer_sync(&intel_crtc->idle_timer);
8148 }
8149 del_timer_sync(&dev_priv->idle_timer);
8150 cancel_work_sync(&dev_priv->idle_work);
8151
8152 drm_mode_config_cleanup(dev);
8153 }
8154
8155 /*
8156 * Return which encoder is currently attached for connector.
8157 */
8158 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8159 {
8160 return &intel_attached_encoder(connector)->base;
8161 }
8162
8163 void intel_connector_attach_encoder(struct intel_connector *connector,
8164 struct intel_encoder *encoder)
8165 {
8166 connector->encoder = encoder;
8167 drm_mode_connector_attach_encoder(&connector->base,
8168 &encoder->base);
8169 }
8170
8171 /*
8172 * set vga decode state - true == enable VGA decode
8173 */
8174 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8175 {
8176 struct drm_i915_private *dev_priv = dev->dev_private;
8177 u16 gmch_ctrl;
8178
8179 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8180 if (state)
8181 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8182 else
8183 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8184 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8185 return 0;
8186 }
8187
8188 #ifdef CONFIG_DEBUG_FS
8189 #include <linux/seq_file.h>
8190
8191 struct intel_display_error_state {
8192 struct intel_cursor_error_state {
8193 u32 control;
8194 u32 position;
8195 u32 base;
8196 u32 size;
8197 } cursor[2];
8198
8199 struct intel_pipe_error_state {
8200 u32 conf;
8201 u32 source;
8202
8203 u32 htotal;
8204 u32 hblank;
8205 u32 hsync;
8206 u32 vtotal;
8207 u32 vblank;
8208 u32 vsync;
8209 } pipe[2];
8210
8211 struct intel_plane_error_state {
8212 u32 control;
8213 u32 stride;
8214 u32 size;
8215 u32 pos;
8216 u32 addr;
8217 u32 surface;
8218 u32 tile_offset;
8219 } plane[2];
8220 };
8221
8222 struct intel_display_error_state *
8223 intel_display_capture_error_state(struct drm_device *dev)
8224 {
8225 drm_i915_private_t *dev_priv = dev->dev_private;
8226 struct intel_display_error_state *error;
8227 int i;
8228
8229 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8230 if (error == NULL)
8231 return NULL;
8232
8233 for (i = 0; i < 2; i++) {
8234 error->cursor[i].control = I915_READ(CURCNTR(i));
8235 error->cursor[i].position = I915_READ(CURPOS(i));
8236 error->cursor[i].base = I915_READ(CURBASE(i));
8237
8238 error->plane[i].control = I915_READ(DSPCNTR(i));
8239 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8240 error->plane[i].size = I915_READ(DSPSIZE(i));
8241 error->plane[i].pos= I915_READ(DSPPOS(i));
8242 error->plane[i].addr = I915_READ(DSPADDR(i));
8243 if (INTEL_INFO(dev)->gen >= 4) {
8244 error->plane[i].surface = I915_READ(DSPSURF(i));
8245 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8246 }
8247
8248 error->pipe[i].conf = I915_READ(PIPECONF(i));
8249 error->pipe[i].source = I915_READ(PIPESRC(i));
8250 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8251 error->pipe[i].hblank = I915_READ(HBLANK(i));
8252 error->pipe[i].hsync = I915_READ(HSYNC(i));
8253 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8254 error->pipe[i].vblank = I915_READ(VBLANK(i));
8255 error->pipe[i].vsync = I915_READ(VSYNC(i));
8256 }
8257
8258 return error;
8259 }
8260
8261 void
8262 intel_display_print_error_state(struct seq_file *m,
8263 struct drm_device *dev,
8264 struct intel_display_error_state *error)
8265 {
8266 int i;
8267
8268 for (i = 0; i < 2; i++) {
8269 seq_printf(m, "Pipe [%d]:\n", i);
8270 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8271 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8272 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8273 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8274 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8275 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8276 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8277 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8278
8279 seq_printf(m, "Plane [%d]:\n", i);
8280 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8281 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8282 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8283 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8284 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8285 if (INTEL_INFO(dev)->gen >= 4) {
8286 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8287 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8288 }
8289
8290 seq_printf(m, "Cursor [%d]:\n", i);
8291 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8292 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8293 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8294 }
8295 }
8296 #endif
kernel source for telekom puls (alcatel/mediatek)