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Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
347 {
348 if (IS_GEN5(dev)) {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351 } else
352 return 27;
353 }
354
355 static const intel_limit_t intel_limits_i8xx_dvo = {
356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
366 .find_pll = intel_find_best_PLL,
367 };
368
369 static const intel_limit_t intel_limits_i8xx_lvds = {
370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
380 .find_pll = intel_find_best_PLL,
381 };
382
383 static const intel_limit_t intel_limits_i9xx_sdvo = {
384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
394 .find_pll = intel_find_best_PLL,
395 };
396
397 static const intel_limit_t intel_limits_i9xx_lvds = {
398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
408 */
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
411 .find_pll = intel_find_best_PLL,
412 };
413
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo = {
416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
427 },
428 .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_hdmi = {
432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
443 },
444 .find_pll = intel_g4x_find_best_PLL,
445 };
446
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467 },
468 .find_pll = intel_g4x_find_best_PLL,
469 };
470
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491 },
492 .find_pll = intel_g4x_find_best_PLL,
493 };
494
495 static const intel_limit_t intel_limits_g4x_display_port = {
496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
499 .max = G4X_VCO_MAX},
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
516 };
517
518 static const intel_limit_t intel_limits_pineview_sdvo = {
519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
529 .find_pll = intel_find_best_PLL,
530 };
531
532 static const intel_limit_t intel_limits_pineview_lvds = {
533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
541 /* Pineview only supports single-channel mode. */
542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
544 .find_pll = intel_find_best_PLL,
545 };
546
547 static const intel_limit_t intel_limits_ironlake_dac = {
548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
559 .find_pll = intel_g4x_find_best_PLL,
560 };
561
562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
575 };
576
577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
590 };
591
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
605 };
606
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619 .find_pll = intel_g4x_find_best_PLL,
620 };
621
622 static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
642 .find_pll = intel_find_pll_ironlake_dp,
643 };
644
645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
646 int refclk)
647 {
648 struct drm_device *dev = crtc->dev;
649 struct drm_i915_private *dev_priv = dev->dev_private;
650 const intel_limit_t *limit;
651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
656 if (refclk == 100000)
657 limit = &intel_limits_ironlake_dual_lvds_100m;
658 else
659 limit = &intel_limits_ironlake_dual_lvds;
660 } else {
661 if (refclk == 100000)
662 limit = &intel_limits_ironlake_single_lvds_100m;
663 else
664 limit = &intel_limits_ironlake_single_lvds;
665 }
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
667 HAS_eDP)
668 limit = &intel_limits_ironlake_display_port;
669 else
670 limit = &intel_limits_ironlake_dac;
671
672 return limit;
673 }
674
675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
676 {
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
680
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
683 LVDS_CLKB_POWER_UP)
684 /* LVDS with dual channel */
685 limit = &intel_limits_g4x_dual_channel_lvds;
686 else
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_single_channel_lvds;
689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
691 limit = &intel_limits_g4x_hdmi;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
693 limit = &intel_limits_g4x_sdvo;
694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
695 limit = &intel_limits_g4x_display_port;
696 } else /* The option is for other outputs */
697 limit = &intel_limits_i9xx_sdvo;
698
699 return limit;
700 }
701
702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
703 {
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
706
707 if (HAS_PCH_SPLIT(dev))
708 limit = intel_ironlake_limit(crtc, refclk);
709 else if (IS_G4X(dev)) {
710 limit = intel_g4x_limit(crtc);
711 } else if (IS_PINEVIEW(dev)) {
712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
713 limit = &intel_limits_pineview_lvds;
714 else
715 limit = &intel_limits_pineview_sdvo;
716 } else if (!IS_GEN2(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_i9xx_lvds;
719 else
720 limit = &intel_limits_i9xx_sdvo;
721 } else {
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
723 limit = &intel_limits_i8xx_lvds;
724 else
725 limit = &intel_limits_i8xx_dvo;
726 }
727 return limit;
728 }
729
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk, intel_clock_t *clock)
732 {
733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
737 }
738
739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
740 {
741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
743 return;
744 }
745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
749 }
750
751 /**
752 * Returns whether any output on the specified pipe is of the specified type
753 */
754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
755 {
756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
759
760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
762 return true;
763
764 return false;
765 }
766
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
768 /**
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
771 */
772
773 static bool intel_PLL_is_valid(struct drm_device *dev,
774 const intel_limit_t *limit,
775 const intel_clock_t *clock)
776 {
777 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
778 INTELPllInvalid ("p1 out of range\n");
779 if (clock->p < limit->p.min || limit->p.max < clock->p)
780 INTELPllInvalid ("p out of range\n");
781 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
782 INTELPllInvalid ("m2 out of range\n");
783 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
784 INTELPllInvalid ("m1 out of range\n");
785 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
786 INTELPllInvalid ("m1 <= m2\n");
787 if (clock->m < limit->m.min || limit->m.max < clock->m)
788 INTELPllInvalid ("m out of range\n");
789 if (clock->n < limit->n.min || limit->n.max < clock->n)
790 INTELPllInvalid ("n out of range\n");
791 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
792 INTELPllInvalid ("vco out of range\n");
793 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794 * connector, etc., rather than just a single range.
795 */
796 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
797 INTELPllInvalid ("dot out of range\n");
798
799 return true;
800 }
801
802 static bool
803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
804 int target, int refclk, intel_clock_t *best_clock)
805
806 {
807 struct drm_device *dev = crtc->dev;
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 intel_clock_t clock;
810 int err = target;
811
812 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
813 (I915_READ(LVDS)) != 0) {
814 /*
815 * For LVDS, if the panel is on, just rely on its current
816 * settings for dual-channel. We haven't figured out how to
817 * reliably set up different single/dual channel state, if we
818 * even can.
819 */
820 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
821 LVDS_CLKB_POWER_UP)
822 clock.p2 = limit->p2.p2_fast;
823 else
824 clock.p2 = limit->p2.p2_slow;
825 } else {
826 if (target < limit->p2.dot_limit)
827 clock.p2 = limit->p2.p2_slow;
828 else
829 clock.p2 = limit->p2.p2_fast;
830 }
831
832 memset (best_clock, 0, sizeof (*best_clock));
833
834 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
835 clock.m1++) {
836 for (clock.m2 = limit->m2.min;
837 clock.m2 <= limit->m2.max; clock.m2++) {
838 /* m1 is always 0 in Pineview */
839 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
840 break;
841 for (clock.n = limit->n.min;
842 clock.n <= limit->n.max; clock.n++) {
843 for (clock.p1 = limit->p1.min;
844 clock.p1 <= limit->p1.max; clock.p1++) {
845 int this_err;
846
847 intel_clock(dev, refclk, &clock);
848 if (!intel_PLL_is_valid(dev, limit,
849 &clock))
850 continue;
851
852 this_err = abs(clock.dot - target);
853 if (this_err < err) {
854 *best_clock = clock;
855 err = this_err;
856 }
857 }
858 }
859 }
860 }
861
862 return (err != target);
863 }
864
865 static bool
866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
867 int target, int refclk, intel_clock_t *best_clock)
868 {
869 struct drm_device *dev = crtc->dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
871 intel_clock_t clock;
872 int max_n;
873 bool found;
874 /* approximately equals target * 0.00585 */
875 int err_most = (target >> 8) + (target >> 9);
876 found = false;
877
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
879 int lvds_reg;
880
881 if (HAS_PCH_SPLIT(dev))
882 lvds_reg = PCH_LVDS;
883 else
884 lvds_reg = LVDS;
885 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
886 LVDS_CLKB_POWER_UP)
887 clock.p2 = limit->p2.p2_fast;
888 else
889 clock.p2 = limit->p2.p2_slow;
890 } else {
891 if (target < limit->p2.dot_limit)
892 clock.p2 = limit->p2.p2_slow;
893 else
894 clock.p2 = limit->p2.p2_fast;
895 }
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 max_n = limit->n.max;
899 /* based on hardware requirement, prefer smaller n to precision */
900 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
901 /* based on hardware requirement, prefere larger m1,m2 */
902 for (clock.m1 = limit->m1.max;
903 clock.m1 >= limit->m1.min; clock.m1--) {
904 for (clock.m2 = limit->m2.max;
905 clock.m2 >= limit->m2.min; clock.m2--) {
906 for (clock.p1 = limit->p1.max;
907 clock.p1 >= limit->p1.min; clock.p1--) {
908 int this_err;
909
910 intel_clock(dev, refclk, &clock);
911 if (!intel_PLL_is_valid(dev, limit,
912 &clock))
913 continue;
914
915 this_err = abs(clock.dot - target);
916 if (this_err < err_most) {
917 *best_clock = clock;
918 err_most = this_err;
919 max_n = clock.n;
920 found = true;
921 }
922 }
923 }
924 }
925 }
926 return found;
927 }
928
929 static bool
930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
931 int target, int refclk, intel_clock_t *best_clock)
932 {
933 struct drm_device *dev = crtc->dev;
934 intel_clock_t clock;
935
936 if (target < 200000) {
937 clock.n = 1;
938 clock.p1 = 2;
939 clock.p2 = 10;
940 clock.m1 = 12;
941 clock.m2 = 9;
942 } else {
943 clock.n = 2;
944 clock.p1 = 1;
945 clock.p2 = 10;
946 clock.m1 = 14;
947 clock.m2 = 8;
948 }
949 intel_clock(dev, refclk, &clock);
950 memcpy(best_clock, &clock, sizeof(intel_clock_t));
951 return true;
952 }
953
954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
955 static bool
956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
957 int target, int refclk, intel_clock_t *best_clock)
958 {
959 intel_clock_t clock;
960 if (target < 200000) {
961 clock.p1 = 2;
962 clock.p2 = 10;
963 clock.n = 2;
964 clock.m1 = 23;
965 clock.m2 = 8;
966 } else {
967 clock.p1 = 1;
968 clock.p2 = 10;
969 clock.n = 1;
970 clock.m1 = 14;
971 clock.m2 = 2;
972 }
973 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
974 clock.p = (clock.p1 * clock.p2);
975 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
976 clock.vco = 0;
977 memcpy(best_clock, &clock, sizeof(intel_clock_t));
978 return true;
979 }
980
981 /**
982 * intel_wait_for_vblank - wait for vblank on a given pipe
983 * @dev: drm device
984 * @pipe: pipe to wait for
985 *
986 * Wait for vblank to occur on a given pipe. Needed for various bits of
987 * mode setting code.
988 */
989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
990 {
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
993
994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well.
996 *
997 * This races with i915_driver_irq_handler() with the result
998 * that either function could miss a vblank event. Here it is not
999 * fatal, as we will either wait upon the next vblank interrupt or
1000 * timeout. Generally speaking intel_wait_for_vblank() is only
1001 * called during modeset at which time the GPU should be idle and
1002 * should *not* be performing page flips and thus not waiting on
1003 * vblanks...
1004 * Currently, the result of us stealing a vblank from the irq
1005 * handler is that a single frame will be skipped during swapbuffers.
1006 */
1007 I915_WRITE(pipestat_reg,
1008 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
1010 /* Wait for vblank interrupt bit to set */
1011 if (wait_for(I915_READ(pipestat_reg) &
1012 PIPE_VBLANK_INTERRUPT_STATUS,
1013 50))
1014 DRM_DEBUG_KMS("vblank wait timed out\n");
1015 }
1016
1017 /*
1018 * intel_wait_for_pipe_off - wait for pipe to turn off
1019 * @dev: drm device
1020 * @pipe: pipe to wait for
1021 *
1022 * After disabling a pipe, we can't wait for vblank in the usual way,
1023 * spinning on the vblank interrupt status bit, since we won't actually
1024 * see an interrupt when the pipe is disabled.
1025 *
1026 * On Gen4 and above:
1027 * wait for the pipe register state bit to turn off
1028 *
1029 * Otherwise:
1030 * wait for the display line value to settle (it usually
1031 * ends up stopping at the start of the next frame).
1032 *
1033 */
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035 {
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038 if (INTEL_INFO(dev)->gen >= 4) {
1039 int reg = PIPECONF(pipe);
1040
1041 /* Wait for the Pipe State to go off */
1042 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043 100))
1044 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045 } else {
1046 u32 last_line;
1047 int reg = PIPEDSL(pipe);
1048 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050 /* Wait for the display line to settle */
1051 do {
1052 last_line = I915_READ(reg) & DSL_LINEMASK;
1053 mdelay(5);
1054 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055 time_after(timeout, jiffies));
1056 if (time_after(jiffies, timeout))
1057 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058 }
1059 }
1060
1061 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1062 {
1063 struct drm_device *dev = crtc->dev;
1064 struct drm_i915_private *dev_priv = dev->dev_private;
1065 struct drm_framebuffer *fb = crtc->fb;
1066 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1067 struct drm_i915_gem_object *obj = intel_fb->obj;
1068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1069 int plane, i;
1070 u32 fbc_ctl, fbc_ctl2;
1071
1072 if (fb->pitch == dev_priv->cfb_pitch &&
1073 obj->fence_reg == dev_priv->cfb_fence &&
1074 intel_crtc->plane == dev_priv->cfb_plane &&
1075 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1076 return;
1077
1078 i8xx_disable_fbc(dev);
1079
1080 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1081
1082 if (fb->pitch < dev_priv->cfb_pitch)
1083 dev_priv->cfb_pitch = fb->pitch;
1084
1085 /* FBC_CTL wants 64B units */
1086 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1087 dev_priv->cfb_fence = obj->fence_reg;
1088 dev_priv->cfb_plane = intel_crtc->plane;
1089 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1090
1091 /* Clear old tags */
1092 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1093 I915_WRITE(FBC_TAG + (i * 4), 0);
1094
1095 /* Set it up... */
1096 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1097 if (obj->tiling_mode != I915_TILING_NONE)
1098 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1099 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1100 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1101
1102 /* enable it... */
1103 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1104 if (IS_I945GM(dev))
1105 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1106 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1107 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1108 if (obj->tiling_mode != I915_TILING_NONE)
1109 fbc_ctl |= dev_priv->cfb_fence;
1110 I915_WRITE(FBC_CONTROL, fbc_ctl);
1111
1112 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1113 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1114 }
1115
1116 void i8xx_disable_fbc(struct drm_device *dev)
1117 {
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119 u32 fbc_ctl;
1120
1121 /* Disable compression */
1122 fbc_ctl = I915_READ(FBC_CONTROL);
1123 if ((fbc_ctl & FBC_CTL_EN) == 0)
1124 return;
1125
1126 fbc_ctl &= ~FBC_CTL_EN;
1127 I915_WRITE(FBC_CONTROL, fbc_ctl);
1128
1129 /* Wait for compressing bit to clear */
1130 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1131 DRM_DEBUG_KMS("FBC idle timed out\n");
1132 return;
1133 }
1134
1135 DRM_DEBUG_KMS("disabled FBC\n");
1136 }
1137
1138 static bool i8xx_fbc_enabled(struct drm_device *dev)
1139 {
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141
1142 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1143 }
1144
1145 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1146 {
1147 struct drm_device *dev = crtc->dev;
1148 struct drm_i915_private *dev_priv = dev->dev_private;
1149 struct drm_framebuffer *fb = crtc->fb;
1150 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1151 struct drm_i915_gem_object *obj = intel_fb->obj;
1152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1153 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1154 unsigned long stall_watermark = 200;
1155 u32 dpfc_ctl;
1156
1157 dpfc_ctl = I915_READ(DPFC_CONTROL);
1158 if (dpfc_ctl & DPFC_CTL_EN) {
1159 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1160 dev_priv->cfb_fence == obj->fence_reg &&
1161 dev_priv->cfb_plane == intel_crtc->plane &&
1162 dev_priv->cfb_y == crtc->y)
1163 return;
1164
1165 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1166 POSTING_READ(DPFC_CONTROL);
1167 intel_wait_for_vblank(dev, intel_crtc->pipe);
1168 }
1169
1170 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1171 dev_priv->cfb_fence = obj->fence_reg;
1172 dev_priv->cfb_plane = intel_crtc->plane;
1173 dev_priv->cfb_y = crtc->y;
1174
1175 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1176 if (obj->tiling_mode != I915_TILING_NONE) {
1177 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1178 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1179 } else {
1180 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1181 }
1182
1183 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1184 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1185 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1186 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1187
1188 /* enable it... */
1189 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1190
1191 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1192 }
1193
1194 void g4x_disable_fbc(struct drm_device *dev)
1195 {
1196 struct drm_i915_private *dev_priv = dev->dev_private;
1197 u32 dpfc_ctl;
1198
1199 /* Disable compression */
1200 dpfc_ctl = I915_READ(DPFC_CONTROL);
1201 if (dpfc_ctl & DPFC_CTL_EN) {
1202 dpfc_ctl &= ~DPFC_CTL_EN;
1203 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1204
1205 DRM_DEBUG_KMS("disabled FBC\n");
1206 }
1207 }
1208
1209 static bool g4x_fbc_enabled(struct drm_device *dev)
1210 {
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212
1213 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1214 }
1215
1216 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1217 {
1218 struct drm_device *dev = crtc->dev;
1219 struct drm_i915_private *dev_priv = dev->dev_private;
1220 struct drm_framebuffer *fb = crtc->fb;
1221 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1222 struct drm_i915_gem_object *obj = intel_fb->obj;
1223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1224 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1225 unsigned long stall_watermark = 200;
1226 u32 dpfc_ctl;
1227
1228 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1229 if (dpfc_ctl & DPFC_CTL_EN) {
1230 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1231 dev_priv->cfb_fence == obj->fence_reg &&
1232 dev_priv->cfb_plane == intel_crtc->plane &&
1233 dev_priv->cfb_offset == obj->gtt_offset &&
1234 dev_priv->cfb_y == crtc->y)
1235 return;
1236
1237 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1238 POSTING_READ(ILK_DPFC_CONTROL);
1239 intel_wait_for_vblank(dev, intel_crtc->pipe);
1240 }
1241
1242 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1243 dev_priv->cfb_fence = obj->fence_reg;
1244 dev_priv->cfb_plane = intel_crtc->plane;
1245 dev_priv->cfb_offset = obj->gtt_offset;
1246 dev_priv->cfb_y = crtc->y;
1247
1248 dpfc_ctl &= DPFC_RESERVED;
1249 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1250 if (obj->tiling_mode != I915_TILING_NONE) {
1251 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1252 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1253 } else {
1254 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1255 }
1256
1257 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1258 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1259 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1260 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1261 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1262 /* enable it... */
1263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1264
1265 if (IS_GEN6(dev)) {
1266 I915_WRITE(SNB_DPFC_CTL_SA,
1267 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1268 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1269 }
1270
1271 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1272 }
1273
1274 void ironlake_disable_fbc(struct drm_device *dev)
1275 {
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 u32 dpfc_ctl;
1278
1279 /* Disable compression */
1280 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1281 if (dpfc_ctl & DPFC_CTL_EN) {
1282 dpfc_ctl &= ~DPFC_CTL_EN;
1283 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1284
1285 DRM_DEBUG_KMS("disabled FBC\n");
1286 }
1287 }
1288
1289 static bool ironlake_fbc_enabled(struct drm_device *dev)
1290 {
1291 struct drm_i915_private *dev_priv = dev->dev_private;
1292
1293 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1294 }
1295
1296 bool intel_fbc_enabled(struct drm_device *dev)
1297 {
1298 struct drm_i915_private *dev_priv = dev->dev_private;
1299
1300 if (!dev_priv->display.fbc_enabled)
1301 return false;
1302
1303 return dev_priv->display.fbc_enabled(dev);
1304 }
1305
1306 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1307 {
1308 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1309
1310 if (!dev_priv->display.enable_fbc)
1311 return;
1312
1313 dev_priv->display.enable_fbc(crtc, interval);
1314 }
1315
1316 void intel_disable_fbc(struct drm_device *dev)
1317 {
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319
1320 if (!dev_priv->display.disable_fbc)
1321 return;
1322
1323 dev_priv->display.disable_fbc(dev);
1324 }
1325
1326 /**
1327 * intel_update_fbc - enable/disable FBC as needed
1328 * @dev: the drm_device
1329 *
1330 * Set up the framebuffer compression hardware at mode set time. We
1331 * enable it if possible:
1332 * - plane A only (on pre-965)
1333 * - no pixel mulitply/line duplication
1334 * - no alpha buffer discard
1335 * - no dual wide
1336 * - framebuffer <= 2048 in width, 1536 in height
1337 *
1338 * We can't assume that any compression will take place (worst case),
1339 * so the compressed buffer has to be the same size as the uncompressed
1340 * one. It also must reside (along with the line length buffer) in
1341 * stolen memory.
1342 *
1343 * We need to enable/disable FBC on a global basis.
1344 */
1345 static void intel_update_fbc(struct drm_device *dev)
1346 {
1347 struct drm_i915_private *dev_priv = dev->dev_private;
1348 struct drm_crtc *crtc = NULL, *tmp_crtc;
1349 struct intel_crtc *intel_crtc;
1350 struct drm_framebuffer *fb;
1351 struct intel_framebuffer *intel_fb;
1352 struct drm_i915_gem_object *obj;
1353
1354 DRM_DEBUG_KMS("\n");
1355
1356 if (!i915_powersave)
1357 return;
1358
1359 if (!I915_HAS_FBC(dev))
1360 return;
1361
1362 /*
1363 * If FBC is already on, we just have to verify that we can
1364 * keep it that way...
1365 * Need to disable if:
1366 * - more than one pipe is active
1367 * - changing FBC params (stride, fence, mode)
1368 * - new fb is too large to fit in compressed buffer
1369 * - going to an unsupported config (interlace, pixel multiply, etc.)
1370 */
1371 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1372 if (tmp_crtc->enabled) {
1373 if (crtc) {
1374 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1375 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1376 goto out_disable;
1377 }
1378 crtc = tmp_crtc;
1379 }
1380 }
1381
1382 if (!crtc || crtc->fb == NULL) {
1383 DRM_DEBUG_KMS("no output, disabling\n");
1384 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1385 goto out_disable;
1386 }
1387
1388 intel_crtc = to_intel_crtc(crtc);
1389 fb = crtc->fb;
1390 intel_fb = to_intel_framebuffer(fb);
1391 obj = intel_fb->obj;
1392
1393 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1394 DRM_DEBUG_KMS("framebuffer too large, disabling "
1395 "compression\n");
1396 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1397 goto out_disable;
1398 }
1399 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1400 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1401 DRM_DEBUG_KMS("mode incompatible with compression, "
1402 "disabling\n");
1403 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1404 goto out_disable;
1405 }
1406 if ((crtc->mode.hdisplay > 2048) ||
1407 (crtc->mode.vdisplay > 1536)) {
1408 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1409 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1410 goto out_disable;
1411 }
1412 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1413 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1414 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1415 goto out_disable;
1416 }
1417 if (obj->tiling_mode != I915_TILING_X) {
1418 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1419 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1420 goto out_disable;
1421 }
1422
1423 /* If the kernel debugger is active, always disable compression */
1424 if (in_dbg_master())
1425 goto out_disable;
1426
1427 intel_enable_fbc(crtc, 500);
1428 return;
1429
1430 out_disable:
1431 /* Multiple disables should be harmless */
1432 if (intel_fbc_enabled(dev)) {
1433 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1434 intel_disable_fbc(dev);
1435 }
1436 }
1437
1438 int
1439 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1440 struct drm_i915_gem_object *obj,
1441 struct intel_ring_buffer *pipelined)
1442 {
1443 u32 alignment;
1444 int ret;
1445
1446 switch (obj->tiling_mode) {
1447 case I915_TILING_NONE:
1448 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1449 alignment = 128 * 1024;
1450 else if (INTEL_INFO(dev)->gen >= 4)
1451 alignment = 4 * 1024;
1452 else
1453 alignment = 64 * 1024;
1454 break;
1455 case I915_TILING_X:
1456 /* pin() will align the object as required by fence */
1457 alignment = 0;
1458 break;
1459 case I915_TILING_Y:
1460 /* FIXME: Is this true? */
1461 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1462 return -EINVAL;
1463 default:
1464 BUG();
1465 }
1466
1467 ret = i915_gem_object_pin(obj, alignment, true);
1468 if (ret)
1469 return ret;
1470
1471 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1472 if (ret)
1473 goto err_unpin;
1474
1475 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1476 * fence, whereas 965+ only requires a fence if using
1477 * framebuffer compression. For simplicity, we always install
1478 * a fence as the cost is not that onerous.
1479 */
1480 if (obj->tiling_mode != I915_TILING_NONE) {
1481 ret = i915_gem_object_get_fence(obj, pipelined, false);
1482 if (ret)
1483 goto err_unpin;
1484 }
1485
1486 return 0;
1487
1488 err_unpin:
1489 i915_gem_object_unpin(obj);
1490 return ret;
1491 }
1492
1493 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1494 static int
1495 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1496 int x, int y, enum mode_set_atomic state)
1497 {
1498 struct drm_device *dev = crtc->dev;
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1501 struct intel_framebuffer *intel_fb;
1502 struct drm_i915_gem_object *obj;
1503 int plane = intel_crtc->plane;
1504 unsigned long Start, Offset;
1505 u32 dspcntr;
1506 u32 reg;
1507
1508 switch (plane) {
1509 case 0:
1510 case 1:
1511 break;
1512 default:
1513 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1514 return -EINVAL;
1515 }
1516
1517 intel_fb = to_intel_framebuffer(fb);
1518 obj = intel_fb->obj;
1519
1520 reg = DSPCNTR(plane);
1521 dspcntr = I915_READ(reg);
1522 /* Mask out pixel format bits in case we change it */
1523 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1524 switch (fb->bits_per_pixel) {
1525 case 8:
1526 dspcntr |= DISPPLANE_8BPP;
1527 break;
1528 case 16:
1529 if (fb->depth == 15)
1530 dspcntr |= DISPPLANE_15_16BPP;
1531 else
1532 dspcntr |= DISPPLANE_16BPP;
1533 break;
1534 case 24:
1535 case 32:
1536 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1537 break;
1538 default:
1539 DRM_ERROR("Unknown color depth\n");
1540 return -EINVAL;
1541 }
1542 if (INTEL_INFO(dev)->gen >= 4) {
1543 if (obj->tiling_mode != I915_TILING_NONE)
1544 dspcntr |= DISPPLANE_TILED;
1545 else
1546 dspcntr &= ~DISPPLANE_TILED;
1547 }
1548
1549 if (HAS_PCH_SPLIT(dev))
1550 /* must disable */
1551 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1552
1553 I915_WRITE(reg, dspcntr);
1554
1555 Start = obj->gtt_offset;
1556 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1557
1558 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1559 Start, Offset, x, y, fb->pitch);
1560 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1561 if (INTEL_INFO(dev)->gen >= 4) {
1562 I915_WRITE(DSPSURF(plane), Start);
1563 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1564 I915_WRITE(DSPADDR(plane), Offset);
1565 } else
1566 I915_WRITE(DSPADDR(plane), Start + Offset);
1567 POSTING_READ(reg);
1568
1569 intel_update_fbc(dev);
1570 intel_increase_pllclock(crtc);
1571
1572 return 0;
1573 }
1574
1575 static int
1576 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1577 struct drm_framebuffer *old_fb)
1578 {
1579 struct drm_device *dev = crtc->dev;
1580 struct drm_i915_master_private *master_priv;
1581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1582 int ret;
1583
1584 /* no fb bound */
1585 if (!crtc->fb) {
1586 DRM_DEBUG_KMS("No FB bound\n");
1587 return 0;
1588 }
1589
1590 switch (intel_crtc->plane) {
1591 case 0:
1592 case 1:
1593 break;
1594 default:
1595 return -EINVAL;
1596 }
1597
1598 mutex_lock(&dev->struct_mutex);
1599 ret = intel_pin_and_fence_fb_obj(dev,
1600 to_intel_framebuffer(crtc->fb)->obj,
1601 NULL);
1602 if (ret != 0) {
1603 mutex_unlock(&dev->struct_mutex);
1604 return ret;
1605 }
1606
1607 if (old_fb) {
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1610
1611 wait_event(dev_priv->pending_flip_queue,
1612 atomic_read(&obj->pending_flip) == 0);
1613
1614 /* Big Hammer, we also need to ensure that any pending
1615 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1616 * current scanout is retired before unpinning the old
1617 * framebuffer.
1618 */
1619 ret = i915_gem_object_flush_gpu(obj, false);
1620 if (ret) {
1621 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1622 mutex_unlock(&dev->struct_mutex);
1623 return ret;
1624 }
1625 }
1626
1627 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1628 LEAVE_ATOMIC_MODE_SET);
1629 if (ret) {
1630 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1631 mutex_unlock(&dev->struct_mutex);
1632 return ret;
1633 }
1634
1635 if (old_fb) {
1636 intel_wait_for_vblank(dev, intel_crtc->pipe);
1637 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1638 }
1639
1640 mutex_unlock(&dev->struct_mutex);
1641
1642 if (!dev->primary->master)
1643 return 0;
1644
1645 master_priv = dev->primary->master->driver_priv;
1646 if (!master_priv->sarea_priv)
1647 return 0;
1648
1649 if (intel_crtc->pipe) {
1650 master_priv->sarea_priv->pipeB_x = x;
1651 master_priv->sarea_priv->pipeB_y = y;
1652 } else {
1653 master_priv->sarea_priv->pipeA_x = x;
1654 master_priv->sarea_priv->pipeA_y = y;
1655 }
1656
1657 return 0;
1658 }
1659
1660 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1661 {
1662 struct drm_device *dev = crtc->dev;
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 u32 dpa_ctl;
1665
1666 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1667 dpa_ctl = I915_READ(DP_A);
1668 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1669
1670 if (clock < 200000) {
1671 u32 temp;
1672 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1673 /* workaround for 160Mhz:
1674 1) program 0x4600c bits 15:0 = 0x8124
1675 2) program 0x46010 bit 0 = 1
1676 3) program 0x46034 bit 24 = 1
1677 4) program 0x64000 bit 14 = 1
1678 */
1679 temp = I915_READ(0x4600c);
1680 temp &= 0xffff0000;
1681 I915_WRITE(0x4600c, temp | 0x8124);
1682
1683 temp = I915_READ(0x46010);
1684 I915_WRITE(0x46010, temp | 1);
1685
1686 temp = I915_READ(0x46034);
1687 I915_WRITE(0x46034, temp | (1 << 24));
1688 } else {
1689 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1690 }
1691 I915_WRITE(DP_A, dpa_ctl);
1692
1693 POSTING_READ(DP_A);
1694 udelay(500);
1695 }
1696
1697 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1698 {
1699 struct drm_device *dev = crtc->dev;
1700 struct drm_i915_private *dev_priv = dev->dev_private;
1701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1702 int pipe = intel_crtc->pipe;
1703 u32 reg, temp;
1704
1705 /* enable normal train */
1706 reg = FDI_TX_CTL(pipe);
1707 temp = I915_READ(reg);
1708 temp &= ~FDI_LINK_TRAIN_NONE;
1709 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1710 I915_WRITE(reg, temp);
1711
1712 reg = FDI_RX_CTL(pipe);
1713 temp = I915_READ(reg);
1714 if (HAS_PCH_CPT(dev)) {
1715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1716 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1717 } else {
1718 temp &= ~FDI_LINK_TRAIN_NONE;
1719 temp |= FDI_LINK_TRAIN_NONE;
1720 }
1721 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1722
1723 /* wait one idle pattern time */
1724 POSTING_READ(reg);
1725 udelay(1000);
1726 }
1727
1728 /* The FDI link training functions for ILK/Ibexpeak. */
1729 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1730 {
1731 struct drm_device *dev = crtc->dev;
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1734 int pipe = intel_crtc->pipe;
1735 u32 reg, temp, tries;
1736
1737 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1738 for train result */
1739 reg = FDI_RX_IMR(pipe);
1740 temp = I915_READ(reg);
1741 temp &= ~FDI_RX_SYMBOL_LOCK;
1742 temp &= ~FDI_RX_BIT_LOCK;
1743 I915_WRITE(reg, temp);
1744 I915_READ(reg);
1745 udelay(150);
1746
1747 /* enable CPU FDI TX and PCH FDI RX */
1748 reg = FDI_TX_CTL(pipe);
1749 temp = I915_READ(reg);
1750 temp &= ~(7 << 19);
1751 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1752 temp &= ~FDI_LINK_TRAIN_NONE;
1753 temp |= FDI_LINK_TRAIN_PATTERN_1;
1754 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1755
1756 reg = FDI_RX_CTL(pipe);
1757 temp = I915_READ(reg);
1758 temp &= ~FDI_LINK_TRAIN_NONE;
1759 temp |= FDI_LINK_TRAIN_PATTERN_1;
1760 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1761
1762 POSTING_READ(reg);
1763 udelay(150);
1764
1765 /* Ironlake workaround, enable clock pointer after FDI enable*/
1766 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1767
1768 reg = FDI_RX_IIR(pipe);
1769 for (tries = 0; tries < 5; tries++) {
1770 temp = I915_READ(reg);
1771 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1772
1773 if ((temp & FDI_RX_BIT_LOCK)) {
1774 DRM_DEBUG_KMS("FDI train 1 done.\n");
1775 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1776 break;
1777 }
1778 }
1779 if (tries == 5)
1780 DRM_ERROR("FDI train 1 fail!\n");
1781
1782 /* Train 2 */
1783 reg = FDI_TX_CTL(pipe);
1784 temp = I915_READ(reg);
1785 temp &= ~FDI_LINK_TRAIN_NONE;
1786 temp |= FDI_LINK_TRAIN_PATTERN_2;
1787 I915_WRITE(reg, temp);
1788
1789 reg = FDI_RX_CTL(pipe);
1790 temp = I915_READ(reg);
1791 temp &= ~FDI_LINK_TRAIN_NONE;
1792 temp |= FDI_LINK_TRAIN_PATTERN_2;
1793 I915_WRITE(reg, temp);
1794
1795 POSTING_READ(reg);
1796 udelay(150);
1797
1798 reg = FDI_RX_IIR(pipe);
1799 for (tries = 0; tries < 5; tries++) {
1800 temp = I915_READ(reg);
1801 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1802
1803 if (temp & FDI_RX_SYMBOL_LOCK) {
1804 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1805 DRM_DEBUG_KMS("FDI train 2 done.\n");
1806 break;
1807 }
1808 }
1809 if (tries == 5)
1810 DRM_ERROR("FDI train 2 fail!\n");
1811
1812 DRM_DEBUG_KMS("FDI train done\n");
1813
1814 }
1815
1816 static const int const snb_b_fdi_train_param [] = {
1817 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1818 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1819 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1820 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1821 };
1822
1823 /* The FDI link training functions for SNB/Cougarpoint. */
1824 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1825 {
1826 struct drm_device *dev = crtc->dev;
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1829 int pipe = intel_crtc->pipe;
1830 u32 reg, temp, i;
1831
1832 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1833 for train result */
1834 reg = FDI_RX_IMR(pipe);
1835 temp = I915_READ(reg);
1836 temp &= ~FDI_RX_SYMBOL_LOCK;
1837 temp &= ~FDI_RX_BIT_LOCK;
1838 I915_WRITE(reg, temp);
1839
1840 POSTING_READ(reg);
1841 udelay(150);
1842
1843 /* enable CPU FDI TX and PCH FDI RX */
1844 reg = FDI_TX_CTL(pipe);
1845 temp = I915_READ(reg);
1846 temp &= ~(7 << 19);
1847 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1848 temp &= ~FDI_LINK_TRAIN_NONE;
1849 temp |= FDI_LINK_TRAIN_PATTERN_1;
1850 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1851 /* SNB-B */
1852 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1853 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1854
1855 reg = FDI_RX_CTL(pipe);
1856 temp = I915_READ(reg);
1857 if (HAS_PCH_CPT(dev)) {
1858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1859 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1860 } else {
1861 temp &= ~FDI_LINK_TRAIN_NONE;
1862 temp |= FDI_LINK_TRAIN_PATTERN_1;
1863 }
1864 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1865
1866 POSTING_READ(reg);
1867 udelay(150);
1868
1869 for (i = 0; i < 4; i++ ) {
1870 reg = FDI_TX_CTL(pipe);
1871 temp = I915_READ(reg);
1872 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1873 temp |= snb_b_fdi_train_param[i];
1874 I915_WRITE(reg, temp);
1875
1876 POSTING_READ(reg);
1877 udelay(500);
1878
1879 reg = FDI_RX_IIR(pipe);
1880 temp = I915_READ(reg);
1881 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1882
1883 if (temp & FDI_RX_BIT_LOCK) {
1884 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1885 DRM_DEBUG_KMS("FDI train 1 done.\n");
1886 break;
1887 }
1888 }
1889 if (i == 4)
1890 DRM_ERROR("FDI train 1 fail!\n");
1891
1892 /* Train 2 */
1893 reg = FDI_TX_CTL(pipe);
1894 temp = I915_READ(reg);
1895 temp &= ~FDI_LINK_TRAIN_NONE;
1896 temp |= FDI_LINK_TRAIN_PATTERN_2;
1897 if (IS_GEN6(dev)) {
1898 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1899 /* SNB-B */
1900 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1901 }
1902 I915_WRITE(reg, temp);
1903
1904 reg = FDI_RX_CTL(pipe);
1905 temp = I915_READ(reg);
1906 if (HAS_PCH_CPT(dev)) {
1907 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1908 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1909 } else {
1910 temp &= ~FDI_LINK_TRAIN_NONE;
1911 temp |= FDI_LINK_TRAIN_PATTERN_2;
1912 }
1913 I915_WRITE(reg, temp);
1914
1915 POSTING_READ(reg);
1916 udelay(150);
1917
1918 for (i = 0; i < 4; i++ ) {
1919 reg = FDI_TX_CTL(pipe);
1920 temp = I915_READ(reg);
1921 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1922 temp |= snb_b_fdi_train_param[i];
1923 I915_WRITE(reg, temp);
1924
1925 POSTING_READ(reg);
1926 udelay(500);
1927
1928 reg = FDI_RX_IIR(pipe);
1929 temp = I915_READ(reg);
1930 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1931
1932 if (temp & FDI_RX_SYMBOL_LOCK) {
1933 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1934 DRM_DEBUG_KMS("FDI train 2 done.\n");
1935 break;
1936 }
1937 }
1938 if (i == 4)
1939 DRM_ERROR("FDI train 2 fail!\n");
1940
1941 DRM_DEBUG_KMS("FDI train done.\n");
1942 }
1943
1944 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1945 {
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 int pipe = intel_crtc->pipe;
1950 u32 reg, temp;
1951
1952 /* Write the TU size bits so error detection works */
1953 I915_WRITE(FDI_RX_TUSIZE1(pipe),
1954 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1955
1956 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1957 reg = FDI_RX_CTL(pipe);
1958 temp = I915_READ(reg);
1959 temp &= ~((0x7 << 19) | (0x7 << 16));
1960 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1961 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1962 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1963
1964 POSTING_READ(reg);
1965 udelay(200);
1966
1967 /* Switch from Rawclk to PCDclk */
1968 temp = I915_READ(reg);
1969 I915_WRITE(reg, temp | FDI_PCDCLK);
1970
1971 POSTING_READ(reg);
1972 udelay(200);
1973
1974 /* Enable CPU FDI TX PLL, always on for Ironlake */
1975 reg = FDI_TX_CTL(pipe);
1976 temp = I915_READ(reg);
1977 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1978 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1979
1980 POSTING_READ(reg);
1981 udelay(100);
1982 }
1983 }
1984
1985 static void intel_flush_display_plane(struct drm_device *dev,
1986 int plane)
1987 {
1988 struct drm_i915_private *dev_priv = dev->dev_private;
1989 u32 reg = DSPADDR(plane);
1990 I915_WRITE(reg, I915_READ(reg));
1991 }
1992
1993 /*
1994 * When we disable a pipe, we need to clear any pending scanline wait events
1995 * to avoid hanging the ring, which we assume we are waiting on.
1996 */
1997 static void intel_clear_scanline_wait(struct drm_device *dev)
1998 {
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 struct intel_ring_buffer *ring;
2001 u32 tmp;
2002
2003 if (IS_GEN2(dev))
2004 /* Can't break the hang on i8xx */
2005 return;
2006
2007 ring = LP_RING(dev_priv);
2008 tmp = I915_READ_CTL(ring);
2009 if (tmp & RING_WAIT)
2010 I915_WRITE_CTL(ring, tmp);
2011 }
2012
2013 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2014 {
2015 struct drm_i915_gem_object *obj;
2016 struct drm_i915_private *dev_priv;
2017
2018 if (crtc->fb == NULL)
2019 return;
2020
2021 obj = to_intel_framebuffer(crtc->fb)->obj;
2022 dev_priv = crtc->dev->dev_private;
2023 wait_event(dev_priv->pending_flip_queue,
2024 atomic_read(&obj->pending_flip) == 0);
2025 }
2026
2027 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2028 {
2029 struct drm_device *dev = crtc->dev;
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032 int pipe = intel_crtc->pipe;
2033 int plane = intel_crtc->plane;
2034 u32 reg, temp;
2035
2036 if (intel_crtc->active)
2037 return;
2038
2039 intel_crtc->active = true;
2040 intel_update_watermarks(dev);
2041
2042 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2043 temp = I915_READ(PCH_LVDS);
2044 if ((temp & LVDS_PORT_EN) == 0)
2045 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2046 }
2047
2048 ironlake_fdi_enable(crtc);
2049
2050 /* Enable panel fitting for LVDS */
2051 if (dev_priv->pch_pf_size &&
2052 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2053 /* Force use of hard-coded filter coefficients
2054 * as some pre-programmed values are broken,
2055 * e.g. x201.
2056 */
2057 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2058 PF_ENABLE | PF_FILTER_MED_3x3);
2059 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2060 dev_priv->pch_pf_pos);
2061 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2062 dev_priv->pch_pf_size);
2063 }
2064
2065 /* Enable CPU pipe */
2066 reg = PIPECONF(pipe);
2067 temp = I915_READ(reg);
2068 if ((temp & PIPECONF_ENABLE) == 0) {
2069 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2070 POSTING_READ(reg);
2071 intel_wait_for_vblank(dev, intel_crtc->pipe);
2072 }
2073
2074 /* configure and enable CPU plane */
2075 reg = DSPCNTR(plane);
2076 temp = I915_READ(reg);
2077 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2078 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2079 intel_flush_display_plane(dev, plane);
2080 }
2081
2082 /* For PCH output, training FDI link */
2083 if (IS_GEN6(dev))
2084 gen6_fdi_link_train(crtc);
2085 else
2086 ironlake_fdi_link_train(crtc);
2087
2088 /* enable PCH DPLL */
2089 reg = PCH_DPLL(pipe);
2090 temp = I915_READ(reg);
2091 if ((temp & DPLL_VCO_ENABLE) == 0) {
2092 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2093 POSTING_READ(reg);
2094 udelay(200);
2095 }
2096
2097 if (HAS_PCH_CPT(dev)) {
2098 /* Be sure PCH DPLL SEL is set */
2099 temp = I915_READ(PCH_DPLL_SEL);
2100 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2101 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2102 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2103 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2104 I915_WRITE(PCH_DPLL_SEL, temp);
2105 }
2106
2107 /* set transcoder timing */
2108 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2109 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2110 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2111
2112 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2113 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2114 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2115
2116 intel_fdi_normal_train(crtc);
2117
2118 /* For PCH DP, enable TRANS_DP_CTL */
2119 if (HAS_PCH_CPT(dev) &&
2120 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2121 reg = TRANS_DP_CTL(pipe);
2122 temp = I915_READ(reg);
2123 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2124 TRANS_DP_SYNC_MASK |
2125 TRANS_DP_BPC_MASK);
2126 temp |= (TRANS_DP_OUTPUT_ENABLE |
2127 TRANS_DP_ENH_FRAMING);
2128 temp |= TRANS_DP_8BPC;
2129
2130 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2131 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2132 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2133 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2134
2135 switch (intel_trans_dp_port_sel(crtc)) {
2136 case PCH_DP_B:
2137 temp |= TRANS_DP_PORT_SEL_B;
2138 break;
2139 case PCH_DP_C:
2140 temp |= TRANS_DP_PORT_SEL_C;
2141 break;
2142 case PCH_DP_D:
2143 temp |= TRANS_DP_PORT_SEL_D;
2144 break;
2145 default:
2146 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2147 temp |= TRANS_DP_PORT_SEL_B;
2148 break;
2149 }
2150
2151 I915_WRITE(reg, temp);
2152 }
2153
2154 /* enable PCH transcoder */
2155 reg = TRANSCONF(pipe);
2156 temp = I915_READ(reg);
2157 /*
2158 * make the BPC in transcoder be consistent with
2159 * that in pipeconf reg.
2160 */
2161 temp &= ~PIPE_BPC_MASK;
2162 temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2163 I915_WRITE(reg, temp | TRANS_ENABLE);
2164 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2165 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2166
2167 intel_crtc_load_lut(crtc);
2168 intel_update_fbc(dev);
2169 intel_crtc_update_cursor(crtc, true);
2170 }
2171
2172 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2173 {
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
2176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2177 int pipe = intel_crtc->pipe;
2178 int plane = intel_crtc->plane;
2179 u32 reg, temp;
2180
2181 if (!intel_crtc->active)
2182 return;
2183
2184 intel_crtc_wait_for_pending_flips(crtc);
2185 drm_vblank_off(dev, pipe);
2186 intel_crtc_update_cursor(crtc, false);
2187
2188 /* Disable display plane */
2189 reg = DSPCNTR(plane);
2190 temp = I915_READ(reg);
2191 if (temp & DISPLAY_PLANE_ENABLE) {
2192 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2193 intel_flush_display_plane(dev, plane);
2194 }
2195
2196 if (dev_priv->cfb_plane == plane &&
2197 dev_priv->display.disable_fbc)
2198 dev_priv->display.disable_fbc(dev);
2199
2200 /* disable cpu pipe, disable after all planes disabled */
2201 reg = PIPECONF(pipe);
2202 temp = I915_READ(reg);
2203 if (temp & PIPECONF_ENABLE) {
2204 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2205 POSTING_READ(reg);
2206 /* wait for cpu pipe off, pipe state */
2207 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2208 }
2209
2210 /* Disable PF */
2211 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2212 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2213
2214 /* disable CPU FDI tx and PCH FDI rx */
2215 reg = FDI_TX_CTL(pipe);
2216 temp = I915_READ(reg);
2217 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2218 POSTING_READ(reg);
2219
2220 reg = FDI_RX_CTL(pipe);
2221 temp = I915_READ(reg);
2222 temp &= ~(0x7 << 16);
2223 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2224 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2225
2226 POSTING_READ(reg);
2227 udelay(100);
2228
2229 /* Ironlake workaround, disable clock pointer after downing FDI */
2230 if (HAS_PCH_IBX(dev))
2231 I915_WRITE(FDI_RX_CHICKEN(pipe),
2232 I915_READ(FDI_RX_CHICKEN(pipe) &
2233 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2234
2235 /* still set train pattern 1 */
2236 reg = FDI_TX_CTL(pipe);
2237 temp = I915_READ(reg);
2238 temp &= ~FDI_LINK_TRAIN_NONE;
2239 temp |= FDI_LINK_TRAIN_PATTERN_1;
2240 I915_WRITE(reg, temp);
2241
2242 reg = FDI_RX_CTL(pipe);
2243 temp = I915_READ(reg);
2244 if (HAS_PCH_CPT(dev)) {
2245 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2246 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2247 } else {
2248 temp &= ~FDI_LINK_TRAIN_NONE;
2249 temp |= FDI_LINK_TRAIN_PATTERN_1;
2250 }
2251 /* BPC in FDI rx is consistent with that in PIPECONF */
2252 temp &= ~(0x07 << 16);
2253 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2254 I915_WRITE(reg, temp);
2255
2256 POSTING_READ(reg);
2257 udelay(100);
2258
2259 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2260 temp = I915_READ(PCH_LVDS);
2261 if (temp & LVDS_PORT_EN) {
2262 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2263 POSTING_READ(PCH_LVDS);
2264 udelay(100);
2265 }
2266 }
2267
2268 /* disable PCH transcoder */
2269 reg = TRANSCONF(plane);
2270 temp = I915_READ(reg);
2271 if (temp & TRANS_ENABLE) {
2272 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2273 /* wait for PCH transcoder off, transcoder state */
2274 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2275 DRM_ERROR("failed to disable transcoder\n");
2276 }
2277
2278 if (HAS_PCH_CPT(dev)) {
2279 /* disable TRANS_DP_CTL */
2280 reg = TRANS_DP_CTL(pipe);
2281 temp = I915_READ(reg);
2282 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2283 I915_WRITE(reg, temp);
2284
2285 /* disable DPLL_SEL */
2286 temp = I915_READ(PCH_DPLL_SEL);
2287 if (pipe == 0)
2288 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2289 else
2290 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2291 I915_WRITE(PCH_DPLL_SEL, temp);
2292 }
2293
2294 /* disable PCH DPLL */
2295 reg = PCH_DPLL(pipe);
2296 temp = I915_READ(reg);
2297 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2298
2299 /* Switch from PCDclk to Rawclk */
2300 reg = FDI_RX_CTL(pipe);
2301 temp = I915_READ(reg);
2302 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2303
2304 /* Disable CPU FDI TX PLL */
2305 reg = FDI_TX_CTL(pipe);
2306 temp = I915_READ(reg);
2307 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2308
2309 POSTING_READ(reg);
2310 udelay(100);
2311
2312 reg = FDI_RX_CTL(pipe);
2313 temp = I915_READ(reg);
2314 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2315
2316 /* Wait for the clocks to turn off. */
2317 POSTING_READ(reg);
2318 udelay(100);
2319
2320 intel_crtc->active = false;
2321 intel_update_watermarks(dev);
2322 intel_update_fbc(dev);
2323 intel_clear_scanline_wait(dev);
2324 }
2325
2326 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2327 {
2328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2329 int pipe = intel_crtc->pipe;
2330 int plane = intel_crtc->plane;
2331
2332 /* XXX: When our outputs are all unaware of DPMS modes other than off
2333 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2334 */
2335 switch (mode) {
2336 case DRM_MODE_DPMS_ON:
2337 case DRM_MODE_DPMS_STANDBY:
2338 case DRM_MODE_DPMS_SUSPEND:
2339 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2340 ironlake_crtc_enable(crtc);
2341 break;
2342
2343 case DRM_MODE_DPMS_OFF:
2344 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2345 ironlake_crtc_disable(crtc);
2346 break;
2347 }
2348 }
2349
2350 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2351 {
2352 if (!enable && intel_crtc->overlay) {
2353 struct drm_device *dev = intel_crtc->base.dev;
2354
2355 mutex_lock(&dev->struct_mutex);
2356 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2357 mutex_unlock(&dev->struct_mutex);
2358 }
2359
2360 /* Let userspace switch the overlay on again. In most cases userspace
2361 * has to recompute where to put it anyway.
2362 */
2363 }
2364
2365 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2366 {
2367 struct drm_device *dev = crtc->dev;
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2370 int pipe = intel_crtc->pipe;
2371 int plane = intel_crtc->plane;
2372 u32 reg, temp;
2373
2374 if (intel_crtc->active)
2375 return;
2376
2377 intel_crtc->active = true;
2378 intel_update_watermarks(dev);
2379
2380 /* Enable the DPLL */
2381 reg = DPLL(pipe);
2382 temp = I915_READ(reg);
2383 if ((temp & DPLL_VCO_ENABLE) == 0) {
2384 I915_WRITE(reg, temp);
2385
2386 /* Wait for the clocks to stabilize. */
2387 POSTING_READ(reg);
2388 udelay(150);
2389
2390 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2391
2392 /* Wait for the clocks to stabilize. */
2393 POSTING_READ(reg);
2394 udelay(150);
2395
2396 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2397
2398 /* Wait for the clocks to stabilize. */
2399 POSTING_READ(reg);
2400 udelay(150);
2401 }
2402
2403 /* Enable the pipe */
2404 reg = PIPECONF(pipe);
2405 temp = I915_READ(reg);
2406 if ((temp & PIPECONF_ENABLE) == 0)
2407 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2408
2409 /* Enable the plane */
2410 reg = DSPCNTR(plane);
2411 temp = I915_READ(reg);
2412 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2413 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2414 intel_flush_display_plane(dev, plane);
2415 }
2416
2417 intel_crtc_load_lut(crtc);
2418 intel_update_fbc(dev);
2419
2420 /* Give the overlay scaler a chance to enable if it's on this pipe */
2421 intel_crtc_dpms_overlay(intel_crtc, true);
2422 intel_crtc_update_cursor(crtc, true);
2423 }
2424
2425 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2426 {
2427 struct drm_device *dev = crtc->dev;
2428 struct drm_i915_private *dev_priv = dev->dev_private;
2429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430 int pipe = intel_crtc->pipe;
2431 int plane = intel_crtc->plane;
2432 u32 reg, temp;
2433
2434 if (!intel_crtc->active)
2435 return;
2436
2437 /* Give the overlay scaler a chance to disable if it's on this pipe */
2438 intel_crtc_wait_for_pending_flips(crtc);
2439 drm_vblank_off(dev, pipe);
2440 intel_crtc_dpms_overlay(intel_crtc, false);
2441 intel_crtc_update_cursor(crtc, false);
2442
2443 if (dev_priv->cfb_plane == plane &&
2444 dev_priv->display.disable_fbc)
2445 dev_priv->display.disable_fbc(dev);
2446
2447 /* Disable display plane */
2448 reg = DSPCNTR(plane);
2449 temp = I915_READ(reg);
2450 if (temp & DISPLAY_PLANE_ENABLE) {
2451 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2452 /* Flush the plane changes */
2453 intel_flush_display_plane(dev, plane);
2454
2455 /* Wait for vblank for the disable to take effect */
2456 if (IS_GEN2(dev))
2457 intel_wait_for_vblank(dev, pipe);
2458 }
2459
2460 /* Don't disable pipe A or pipe A PLLs if needed */
2461 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2462 goto done;
2463
2464 /* Next, disable display pipes */
2465 reg = PIPECONF(pipe);
2466 temp = I915_READ(reg);
2467 if (temp & PIPECONF_ENABLE) {
2468 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2469
2470 /* Wait for the pipe to turn off */
2471 POSTING_READ(reg);
2472 intel_wait_for_pipe_off(dev, pipe);
2473 }
2474
2475 reg = DPLL(pipe);
2476 temp = I915_READ(reg);
2477 if (temp & DPLL_VCO_ENABLE) {
2478 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2479
2480 /* Wait for the clocks to turn off. */
2481 POSTING_READ(reg);
2482 udelay(150);
2483 }
2484
2485 done:
2486 intel_crtc->active = false;
2487 intel_update_fbc(dev);
2488 intel_update_watermarks(dev);
2489 intel_clear_scanline_wait(dev);
2490 }
2491
2492 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2493 {
2494 /* XXX: When our outputs are all unaware of DPMS modes other than off
2495 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2496 */
2497 switch (mode) {
2498 case DRM_MODE_DPMS_ON:
2499 case DRM_MODE_DPMS_STANDBY:
2500 case DRM_MODE_DPMS_SUSPEND:
2501 i9xx_crtc_enable(crtc);
2502 break;
2503 case DRM_MODE_DPMS_OFF:
2504 i9xx_crtc_disable(crtc);
2505 break;
2506 }
2507 }
2508
2509 /**
2510 * Sets the power management mode of the pipe and plane.
2511 */
2512 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2513 {
2514 struct drm_device *dev = crtc->dev;
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2516 struct drm_i915_master_private *master_priv;
2517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2518 int pipe = intel_crtc->pipe;
2519 bool enabled;
2520
2521 if (intel_crtc->dpms_mode == mode)
2522 return;
2523
2524 intel_crtc->dpms_mode = mode;
2525
2526 dev_priv->display.dpms(crtc, mode);
2527
2528 if (!dev->primary->master)
2529 return;
2530
2531 master_priv = dev->primary->master->driver_priv;
2532 if (!master_priv->sarea_priv)
2533 return;
2534
2535 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2536
2537 switch (pipe) {
2538 case 0:
2539 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2540 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2541 break;
2542 case 1:
2543 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2544 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2545 break;
2546 default:
2547 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2548 break;
2549 }
2550 }
2551
2552 static void intel_crtc_disable(struct drm_crtc *crtc)
2553 {
2554 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2555 struct drm_device *dev = crtc->dev;
2556
2557 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2558
2559 if (crtc->fb) {
2560 mutex_lock(&dev->struct_mutex);
2561 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2562 mutex_unlock(&dev->struct_mutex);
2563 }
2564 }
2565
2566 /* Prepare for a mode set.
2567 *
2568 * Note we could be a lot smarter here. We need to figure out which outputs
2569 * will be enabled, which disabled (in short, how the config will changes)
2570 * and perform the minimum necessary steps to accomplish that, e.g. updating
2571 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2572 * panel fitting is in the proper state, etc.
2573 */
2574 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2575 {
2576 i9xx_crtc_disable(crtc);
2577 }
2578
2579 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2580 {
2581 i9xx_crtc_enable(crtc);
2582 }
2583
2584 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2585 {
2586 ironlake_crtc_disable(crtc);
2587 }
2588
2589 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2590 {
2591 ironlake_crtc_enable(crtc);
2592 }
2593
2594 void intel_encoder_prepare (struct drm_encoder *encoder)
2595 {
2596 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2597 /* lvds has its own version of prepare see intel_lvds_prepare */
2598 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2599 }
2600
2601 void intel_encoder_commit (struct drm_encoder *encoder)
2602 {
2603 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2604 /* lvds has its own version of commit see intel_lvds_commit */
2605 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2606 }
2607
2608 void intel_encoder_destroy(struct drm_encoder *encoder)
2609 {
2610 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2611
2612 drm_encoder_cleanup(encoder);
2613 kfree(intel_encoder);
2614 }
2615
2616 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2617 struct drm_display_mode *mode,
2618 struct drm_display_mode *adjusted_mode)
2619 {
2620 struct drm_device *dev = crtc->dev;
2621
2622 if (HAS_PCH_SPLIT(dev)) {
2623 /* FDI link clock is fixed at 2.7G */
2624 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2625 return false;
2626 }
2627
2628 /* XXX some encoders set the crtcinfo, others don't.
2629 * Obviously we need some form of conflict resolution here...
2630 */
2631 if (adjusted_mode->crtc_htotal == 0)
2632 drm_mode_set_crtcinfo(adjusted_mode, 0);
2633
2634 return true;
2635 }
2636
2637 static int i945_get_display_clock_speed(struct drm_device *dev)
2638 {
2639 return 400000;
2640 }
2641
2642 static int i915_get_display_clock_speed(struct drm_device *dev)
2643 {
2644 return 333000;
2645 }
2646
2647 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2648 {
2649 return 200000;
2650 }
2651
2652 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2653 {
2654 u16 gcfgc = 0;
2655
2656 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2657
2658 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2659 return 133000;
2660 else {
2661 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2662 case GC_DISPLAY_CLOCK_333_MHZ:
2663 return 333000;
2664 default:
2665 case GC_DISPLAY_CLOCK_190_200_MHZ:
2666 return 190000;
2667 }
2668 }
2669 }
2670
2671 static int i865_get_display_clock_speed(struct drm_device *dev)
2672 {
2673 return 266000;
2674 }
2675
2676 static int i855_get_display_clock_speed(struct drm_device *dev)
2677 {
2678 u16 hpllcc = 0;
2679 /* Assume that the hardware is in the high speed state. This
2680 * should be the default.
2681 */
2682 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2683 case GC_CLOCK_133_200:
2684 case GC_CLOCK_100_200:
2685 return 200000;
2686 case GC_CLOCK_166_250:
2687 return 250000;
2688 case GC_CLOCK_100_133:
2689 return 133000;
2690 }
2691
2692 /* Shouldn't happen */
2693 return 0;
2694 }
2695
2696 static int i830_get_display_clock_speed(struct drm_device *dev)
2697 {
2698 return 133000;
2699 }
2700
2701 struct fdi_m_n {
2702 u32 tu;
2703 u32 gmch_m;
2704 u32 gmch_n;
2705 u32 link_m;
2706 u32 link_n;
2707 };
2708
2709 static void
2710 fdi_reduce_ratio(u32 *num, u32 *den)
2711 {
2712 while (*num > 0xffffff || *den > 0xffffff) {
2713 *num >>= 1;
2714 *den >>= 1;
2715 }
2716 }
2717
2718 static void
2719 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2720 int link_clock, struct fdi_m_n *m_n)
2721 {
2722 m_n->tu = 64; /* default size */
2723
2724 /* BUG_ON(pixel_clock > INT_MAX / 36); */
2725 m_n->gmch_m = bits_per_pixel * pixel_clock;
2726 m_n->gmch_n = link_clock * nlanes * 8;
2727 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2728
2729 m_n->link_m = pixel_clock;
2730 m_n->link_n = link_clock;
2731 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2732 }
2733
2734
2735 struct intel_watermark_params {
2736 unsigned long fifo_size;
2737 unsigned long max_wm;
2738 unsigned long default_wm;
2739 unsigned long guard_size;
2740 unsigned long cacheline_size;
2741 };
2742
2743 /* Pineview has different values for various configs */
2744 static struct intel_watermark_params pineview_display_wm = {
2745 PINEVIEW_DISPLAY_FIFO,
2746 PINEVIEW_MAX_WM,
2747 PINEVIEW_DFT_WM,
2748 PINEVIEW_GUARD_WM,
2749 PINEVIEW_FIFO_LINE_SIZE
2750 };
2751 static struct intel_watermark_params pineview_display_hplloff_wm = {
2752 PINEVIEW_DISPLAY_FIFO,
2753 PINEVIEW_MAX_WM,
2754 PINEVIEW_DFT_HPLLOFF_WM,
2755 PINEVIEW_GUARD_WM,
2756 PINEVIEW_FIFO_LINE_SIZE
2757 };
2758 static struct intel_watermark_params pineview_cursor_wm = {
2759 PINEVIEW_CURSOR_FIFO,
2760 PINEVIEW_CURSOR_MAX_WM,
2761 PINEVIEW_CURSOR_DFT_WM,
2762 PINEVIEW_CURSOR_GUARD_WM,
2763 PINEVIEW_FIFO_LINE_SIZE,
2764 };
2765 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2766 PINEVIEW_CURSOR_FIFO,
2767 PINEVIEW_CURSOR_MAX_WM,
2768 PINEVIEW_CURSOR_DFT_WM,
2769 PINEVIEW_CURSOR_GUARD_WM,
2770 PINEVIEW_FIFO_LINE_SIZE
2771 };
2772 static struct intel_watermark_params g4x_wm_info = {
2773 G4X_FIFO_SIZE,
2774 G4X_MAX_WM,
2775 G4X_MAX_WM,
2776 2,
2777 G4X_FIFO_LINE_SIZE,
2778 };
2779 static struct intel_watermark_params g4x_cursor_wm_info = {
2780 I965_CURSOR_FIFO,
2781 I965_CURSOR_MAX_WM,
2782 I965_CURSOR_DFT_WM,
2783 2,
2784 G4X_FIFO_LINE_SIZE,
2785 };
2786 static struct intel_watermark_params i965_cursor_wm_info = {
2787 I965_CURSOR_FIFO,
2788 I965_CURSOR_MAX_WM,
2789 I965_CURSOR_DFT_WM,
2790 2,
2791 I915_FIFO_LINE_SIZE,
2792 };
2793 static struct intel_watermark_params i945_wm_info = {
2794 I945_FIFO_SIZE,
2795 I915_MAX_WM,
2796 1,
2797 2,
2798 I915_FIFO_LINE_SIZE
2799 };
2800 static struct intel_watermark_params i915_wm_info = {
2801 I915_FIFO_SIZE,
2802 I915_MAX_WM,
2803 1,
2804 2,
2805 I915_FIFO_LINE_SIZE
2806 };
2807 static struct intel_watermark_params i855_wm_info = {
2808 I855GM_FIFO_SIZE,
2809 I915_MAX_WM,
2810 1,
2811 2,
2812 I830_FIFO_LINE_SIZE
2813 };
2814 static struct intel_watermark_params i830_wm_info = {
2815 I830_FIFO_SIZE,
2816 I915_MAX_WM,
2817 1,
2818 2,
2819 I830_FIFO_LINE_SIZE
2820 };
2821
2822 static struct intel_watermark_params ironlake_display_wm_info = {
2823 ILK_DISPLAY_FIFO,
2824 ILK_DISPLAY_MAXWM,
2825 ILK_DISPLAY_DFTWM,
2826 2,
2827 ILK_FIFO_LINE_SIZE
2828 };
2829
2830 static struct intel_watermark_params ironlake_cursor_wm_info = {
2831 ILK_CURSOR_FIFO,
2832 ILK_CURSOR_MAXWM,
2833 ILK_CURSOR_DFTWM,
2834 2,
2835 ILK_FIFO_LINE_SIZE
2836 };
2837
2838 static struct intel_watermark_params ironlake_display_srwm_info = {
2839 ILK_DISPLAY_SR_FIFO,
2840 ILK_DISPLAY_MAX_SRWM,
2841 ILK_DISPLAY_DFT_SRWM,
2842 2,
2843 ILK_FIFO_LINE_SIZE
2844 };
2845
2846 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2847 ILK_CURSOR_SR_FIFO,
2848 ILK_CURSOR_MAX_SRWM,
2849 ILK_CURSOR_DFT_SRWM,
2850 2,
2851 ILK_FIFO_LINE_SIZE
2852 };
2853
2854 static struct intel_watermark_params sandybridge_display_wm_info = {
2855 SNB_DISPLAY_FIFO,
2856 SNB_DISPLAY_MAXWM,
2857 SNB_DISPLAY_DFTWM,
2858 2,
2859 SNB_FIFO_LINE_SIZE
2860 };
2861
2862 static struct intel_watermark_params sandybridge_cursor_wm_info = {
2863 SNB_CURSOR_FIFO,
2864 SNB_CURSOR_MAXWM,
2865 SNB_CURSOR_DFTWM,
2866 2,
2867 SNB_FIFO_LINE_SIZE
2868 };
2869
2870 static struct intel_watermark_params sandybridge_display_srwm_info = {
2871 SNB_DISPLAY_SR_FIFO,
2872 SNB_DISPLAY_MAX_SRWM,
2873 SNB_DISPLAY_DFT_SRWM,
2874 2,
2875 SNB_FIFO_LINE_SIZE
2876 };
2877
2878 static struct intel_watermark_params sandybridge_cursor_srwm_info = {
2879 SNB_CURSOR_SR_FIFO,
2880 SNB_CURSOR_MAX_SRWM,
2881 SNB_CURSOR_DFT_SRWM,
2882 2,
2883 SNB_FIFO_LINE_SIZE
2884 };
2885
2886
2887 /**
2888 * intel_calculate_wm - calculate watermark level
2889 * @clock_in_khz: pixel clock
2890 * @wm: chip FIFO params
2891 * @pixel_size: display pixel size
2892 * @latency_ns: memory latency for the platform
2893 *
2894 * Calculate the watermark level (the level at which the display plane will
2895 * start fetching from memory again). Each chip has a different display
2896 * FIFO size and allocation, so the caller needs to figure that out and pass
2897 * in the correct intel_watermark_params structure.
2898 *
2899 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2900 * on the pixel size. When it reaches the watermark level, it'll start
2901 * fetching FIFO line sized based chunks from memory until the FIFO fills
2902 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2903 * will occur, and a display engine hang could result.
2904 */
2905 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2906 struct intel_watermark_params *wm,
2907 int pixel_size,
2908 unsigned long latency_ns)
2909 {
2910 long entries_required, wm_size;
2911
2912 /*
2913 * Note: we need to make sure we don't overflow for various clock &
2914 * latency values.
2915 * clocks go from a few thousand to several hundred thousand.
2916 * latency is usually a few thousand
2917 */
2918 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2919 1000;
2920 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2921
2922 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2923
2924 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2925
2926 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2927
2928 /* Don't promote wm_size to unsigned... */
2929 if (wm_size > (long)wm->max_wm)
2930 wm_size = wm->max_wm;
2931 if (wm_size <= 0)
2932 wm_size = wm->default_wm;
2933 return wm_size;
2934 }
2935
2936 struct cxsr_latency {
2937 int is_desktop;
2938 int is_ddr3;
2939 unsigned long fsb_freq;
2940 unsigned long mem_freq;
2941 unsigned long display_sr;
2942 unsigned long display_hpll_disable;
2943 unsigned long cursor_sr;
2944 unsigned long cursor_hpll_disable;
2945 };
2946
2947 static const struct cxsr_latency cxsr_latency_table[] = {
2948 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2949 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2950 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2951 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2952 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2953
2954 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2955 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2956 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2957 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2958 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2959
2960 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2961 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2962 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2963 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2964 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2965
2966 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2967 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2968 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2969 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2970 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2971
2972 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2973 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2974 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2975 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2976 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2977
2978 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2979 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2980 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2981 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2982 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2983 };
2984
2985 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2986 int is_ddr3,
2987 int fsb,
2988 int mem)
2989 {
2990 const struct cxsr_latency *latency;
2991 int i;
2992
2993 if (fsb == 0 || mem == 0)
2994 return NULL;
2995
2996 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2997 latency = &cxsr_latency_table[i];
2998 if (is_desktop == latency->is_desktop &&
2999 is_ddr3 == latency->is_ddr3 &&
3000 fsb == latency->fsb_freq && mem == latency->mem_freq)
3001 return latency;
3002 }
3003
3004 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3005
3006 return NULL;
3007 }
3008
3009 static void pineview_disable_cxsr(struct drm_device *dev)
3010 {
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012
3013 /* deactivate cxsr */
3014 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3015 }
3016
3017 /*
3018 * Latency for FIFO fetches is dependent on several factors:
3019 * - memory configuration (speed, channels)
3020 * - chipset
3021 * - current MCH state
3022 * It can be fairly high in some situations, so here we assume a fairly
3023 * pessimal value. It's a tradeoff between extra memory fetches (if we
3024 * set this value too high, the FIFO will fetch frequently to stay full)
3025 * and power consumption (set it too low to save power and we might see
3026 * FIFO underruns and display "flicker").
3027 *
3028 * A value of 5us seems to be a good balance; safe for very low end
3029 * platforms but not overly aggressive on lower latency configs.
3030 */
3031 static const int latency_ns = 5000;
3032
3033 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3034 {
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 uint32_t dsparb = I915_READ(DSPARB);
3037 int size;
3038
3039 size = dsparb & 0x7f;
3040 if (plane)
3041 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3042
3043 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3044 plane ? "B" : "A", size);
3045
3046 return size;
3047 }
3048
3049 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3050 {
3051 struct drm_i915_private *dev_priv = dev->dev_private;
3052 uint32_t dsparb = I915_READ(DSPARB);
3053 int size;
3054
3055 size = dsparb & 0x1ff;
3056 if (plane)
3057 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3058 size >>= 1; /* Convert to cachelines */
3059
3060 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3061 plane ? "B" : "A", size);
3062
3063 return size;
3064 }
3065
3066 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3067 {
3068 struct drm_i915_private *dev_priv = dev->dev_private;
3069 uint32_t dsparb = I915_READ(DSPARB);
3070 int size;
3071
3072 size = dsparb & 0x7f;
3073 size >>= 2; /* Convert to cachelines */
3074
3075 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3076 plane ? "B" : "A",
3077 size);
3078
3079 return size;
3080 }
3081
3082 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3083 {
3084 struct drm_i915_private *dev_priv = dev->dev_private;
3085 uint32_t dsparb = I915_READ(DSPARB);
3086 int size;
3087
3088 size = dsparb & 0x7f;
3089 size >>= 1; /* Convert to cachelines */
3090
3091 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3092 plane ? "B" : "A", size);
3093
3094 return size;
3095 }
3096
3097 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3098 int planeb_clock, int sr_hdisplay, int unused,
3099 int pixel_size)
3100 {
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102 const struct cxsr_latency *latency;
3103 u32 reg;
3104 unsigned long wm;
3105 int sr_clock;
3106
3107 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3108 dev_priv->fsb_freq, dev_priv->mem_freq);
3109 if (!latency) {
3110 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3111 pineview_disable_cxsr(dev);
3112 return;
3113 }
3114
3115 if (!planea_clock || !planeb_clock) {
3116 sr_clock = planea_clock ? planea_clock : planeb_clock;
3117
3118 /* Display SR */
3119 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3120 pixel_size, latency->display_sr);
3121 reg = I915_READ(DSPFW1);
3122 reg &= ~DSPFW_SR_MASK;
3123 reg |= wm << DSPFW_SR_SHIFT;
3124 I915_WRITE(DSPFW1, reg);
3125 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3126
3127 /* cursor SR */
3128 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3129 pixel_size, latency->cursor_sr);
3130 reg = I915_READ(DSPFW3);
3131 reg &= ~DSPFW_CURSOR_SR_MASK;
3132 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3133 I915_WRITE(DSPFW3, reg);
3134
3135 /* Display HPLL off SR */
3136 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3137 pixel_size, latency->display_hpll_disable);
3138 reg = I915_READ(DSPFW3);
3139 reg &= ~DSPFW_HPLL_SR_MASK;
3140 reg |= wm & DSPFW_HPLL_SR_MASK;
3141 I915_WRITE(DSPFW3, reg);
3142
3143 /* cursor HPLL off SR */
3144 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3145 pixel_size, latency->cursor_hpll_disable);
3146 reg = I915_READ(DSPFW3);
3147 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3148 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3149 I915_WRITE(DSPFW3, reg);
3150 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3151
3152 /* activate cxsr */
3153 I915_WRITE(DSPFW3,
3154 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3155 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3156 } else {
3157 pineview_disable_cxsr(dev);
3158 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3159 }
3160 }
3161
3162 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3163 int planeb_clock, int sr_hdisplay, int sr_htotal,
3164 int pixel_size)
3165 {
3166 struct drm_i915_private *dev_priv = dev->dev_private;
3167 int total_size, cacheline_size;
3168 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3169 struct intel_watermark_params planea_params, planeb_params;
3170 unsigned long line_time_us;
3171 int sr_clock, sr_entries = 0, entries_required;
3172
3173 /* Create copies of the base settings for each pipe */
3174 planea_params = planeb_params = g4x_wm_info;
3175
3176 /* Grab a couple of global values before we overwrite them */
3177 total_size = planea_params.fifo_size;
3178 cacheline_size = planea_params.cacheline_size;
3179
3180 /*
3181 * Note: we need to make sure we don't overflow for various clock &
3182 * latency values.
3183 * clocks go from a few thousand to several hundred thousand.
3184 * latency is usually a few thousand
3185 */
3186 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3187 1000;
3188 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3189 planea_wm = entries_required + planea_params.guard_size;
3190
3191 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3192 1000;
3193 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3194 planeb_wm = entries_required + planeb_params.guard_size;
3195
3196 cursora_wm = cursorb_wm = 16;
3197 cursor_sr = 32;
3198
3199 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3200
3201 /* Calc sr entries for one plane configs */
3202 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3203 /* self-refresh has much higher latency */
3204 static const int sr_latency_ns = 12000;
3205
3206 sr_clock = planea_clock ? planea_clock : planeb_clock;
3207 line_time_us = ((sr_htotal * 1000) / sr_clock);
3208
3209 /* Use ns/us then divide to preserve precision */
3210 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3211 pixel_size * sr_hdisplay;
3212 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3213
3214 entries_required = (((sr_latency_ns / line_time_us) +
3215 1000) / 1000) * pixel_size * 64;
3216 entries_required = DIV_ROUND_UP(entries_required,
3217 g4x_cursor_wm_info.cacheline_size);
3218 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3219
3220 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3221 cursor_sr = g4x_cursor_wm_info.max_wm;
3222 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3223 "cursor %d\n", sr_entries, cursor_sr);
3224
3225 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3226 } else {
3227 /* Turn off self refresh if both pipes are enabled */
3228 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3229 & ~FW_BLC_SELF_EN);
3230 }
3231
3232 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3233 planea_wm, planeb_wm, sr_entries);
3234
3235 planea_wm &= 0x3f;
3236 planeb_wm &= 0x3f;
3237
3238 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3239 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3240 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3241 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3242 (cursora_wm << DSPFW_CURSORA_SHIFT));
3243 /* HPLL off in SR has some issues on G4x... disable it */
3244 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3245 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3246 }
3247
3248 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3249 int planeb_clock, int sr_hdisplay, int sr_htotal,
3250 int pixel_size)
3251 {
3252 struct drm_i915_private *dev_priv = dev->dev_private;
3253 unsigned long line_time_us;
3254 int sr_clock, sr_entries, srwm = 1;
3255 int cursor_sr = 16;
3256
3257 /* Calc sr entries for one plane configs */
3258 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3259 /* self-refresh has much higher latency */
3260 static const int sr_latency_ns = 12000;
3261
3262 sr_clock = planea_clock ? planea_clock : planeb_clock;
3263 line_time_us = ((sr_htotal * 1000) / sr_clock);
3264
3265 /* Use ns/us then divide to preserve precision */
3266 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3267 pixel_size * sr_hdisplay;
3268 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3269 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3270 srwm = I965_FIFO_SIZE - sr_entries;
3271 if (srwm < 0)
3272 srwm = 1;
3273 srwm &= 0x1ff;
3274
3275 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3276 pixel_size * 64;
3277 sr_entries = DIV_ROUND_UP(sr_entries,
3278 i965_cursor_wm_info.cacheline_size);
3279 cursor_sr = i965_cursor_wm_info.fifo_size -
3280 (sr_entries + i965_cursor_wm_info.guard_size);
3281
3282 if (cursor_sr > i965_cursor_wm_info.max_wm)
3283 cursor_sr = i965_cursor_wm_info.max_wm;
3284
3285 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3286 "cursor %d\n", srwm, cursor_sr);
3287
3288 if (IS_CRESTLINE(dev))
3289 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3290 } else {
3291 /* Turn off self refresh if both pipes are enabled */
3292 if (IS_CRESTLINE(dev))
3293 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3294 & ~FW_BLC_SELF_EN);
3295 }
3296
3297 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3298 srwm);
3299
3300 /* 965 has limitations... */
3301 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3302 (8 << 0));
3303 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3304 /* update cursor SR watermark */
3305 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3306 }
3307
3308 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3309 int planeb_clock, int sr_hdisplay, int sr_htotal,
3310 int pixel_size)
3311 {
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 uint32_t fwater_lo;
3314 uint32_t fwater_hi;
3315 int total_size, cacheline_size, cwm, srwm = 1;
3316 int planea_wm, planeb_wm;
3317 struct intel_watermark_params planea_params, planeb_params;
3318 unsigned long line_time_us;
3319 int sr_clock, sr_entries = 0;
3320
3321 /* Create copies of the base settings for each pipe */
3322 if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3323 planea_params = planeb_params = i945_wm_info;
3324 else if (!IS_GEN2(dev))
3325 planea_params = planeb_params = i915_wm_info;
3326 else
3327 planea_params = planeb_params = i855_wm_info;
3328
3329 /* Grab a couple of global values before we overwrite them */
3330 total_size = planea_params.fifo_size;
3331 cacheline_size = planea_params.cacheline_size;
3332
3333 /* Update per-plane FIFO sizes */
3334 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3335 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3336
3337 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3338 pixel_size, latency_ns);
3339 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3340 pixel_size, latency_ns);
3341 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3342
3343 /*
3344 * Overlay gets an aggressive default since video jitter is bad.
3345 */
3346 cwm = 2;
3347
3348 /* Calc sr entries for one plane configs */
3349 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3350 (!planea_clock || !planeb_clock)) {
3351 /* self-refresh has much higher latency */
3352 static const int sr_latency_ns = 6000;
3353
3354 sr_clock = planea_clock ? planea_clock : planeb_clock;
3355 line_time_us = ((sr_htotal * 1000) / sr_clock);
3356
3357 /* Use ns/us then divide to preserve precision */
3358 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3359 pixel_size * sr_hdisplay;
3360 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3361 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3362 srwm = total_size - sr_entries;
3363 if (srwm < 0)
3364 srwm = 1;
3365
3366 if (IS_I945G(dev) || IS_I945GM(dev))
3367 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3368 else if (IS_I915GM(dev)) {
3369 /* 915M has a smaller SRWM field */
3370 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3371 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3372 }
3373 } else {
3374 /* Turn off self refresh if both pipes are enabled */
3375 if (IS_I945G(dev) || IS_I945GM(dev)) {
3376 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3377 & ~FW_BLC_SELF_EN);
3378 } else if (IS_I915GM(dev)) {
3379 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3380 }
3381 }
3382
3383 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3384 planea_wm, planeb_wm, cwm, srwm);
3385
3386 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3387 fwater_hi = (cwm & 0x1f);
3388
3389 /* Set request length to 8 cachelines per fetch */
3390 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3391 fwater_hi = fwater_hi | (1 << 8);
3392
3393 I915_WRITE(FW_BLC, fwater_lo);
3394 I915_WRITE(FW_BLC2, fwater_hi);
3395 }
3396
3397 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3398 int unused2, int unused3, int pixel_size)
3399 {
3400 struct drm_i915_private *dev_priv = dev->dev_private;
3401 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3402 int planea_wm;
3403
3404 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3405
3406 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3407 pixel_size, latency_ns);
3408 fwater_lo |= (3<<8) | planea_wm;
3409
3410 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3411
3412 I915_WRITE(FW_BLC, fwater_lo);
3413 }
3414
3415 #define ILK_LP0_PLANE_LATENCY 700
3416 #define ILK_LP0_CURSOR_LATENCY 1300
3417
3418 static bool ironlake_compute_wm0(struct drm_device *dev,
3419 int pipe,
3420 const struct intel_watermark_params *display,
3421 int display_latency_ns,
3422 const struct intel_watermark_params *cursor,
3423 int cursor_latency_ns,
3424 int *plane_wm,
3425 int *cursor_wm)
3426 {
3427 struct drm_crtc *crtc;
3428 int htotal, hdisplay, clock, pixel_size;
3429 int line_time_us, line_count;
3430 int entries, tlb_miss;
3431
3432 crtc = intel_get_crtc_for_pipe(dev, pipe);
3433 if (crtc->fb == NULL || !crtc->enabled)
3434 return false;
3435
3436 htotal = crtc->mode.htotal;
3437 hdisplay = crtc->mode.hdisplay;
3438 clock = crtc->mode.clock;
3439 pixel_size = crtc->fb->bits_per_pixel / 8;
3440
3441 /* Use the small buffer method to calculate plane watermark */
3442 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3443 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3444 if (tlb_miss > 0)
3445 entries += tlb_miss;
3446 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3447 *plane_wm = entries + display->guard_size;
3448 if (*plane_wm > (int)display->max_wm)
3449 *plane_wm = display->max_wm;
3450
3451 /* Use the large buffer method to calculate cursor watermark */
3452 line_time_us = ((htotal * 1000) / clock);
3453 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3454 entries = line_count * 64 * pixel_size;
3455 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3456 if (tlb_miss > 0)
3457 entries += tlb_miss;
3458 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3459 *cursor_wm = entries + cursor->guard_size;
3460 if (*cursor_wm > (int)cursor->max_wm)
3461 *cursor_wm = (int)cursor->max_wm;
3462
3463 return true;
3464 }
3465
3466 /*
3467 * Check the wm result.
3468 *
3469 * If any calculated watermark values is larger than the maximum value that
3470 * can be programmed into the associated watermark register, that watermark
3471 * must be disabled.
3472 */
3473 static bool ironlake_check_srwm(struct drm_device *dev, int level,
3474 int fbc_wm, int display_wm, int cursor_wm,
3475 const struct intel_watermark_params *display,
3476 const struct intel_watermark_params *cursor)
3477 {
3478 struct drm_i915_private *dev_priv = dev->dev_private;
3479
3480 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3481 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3482
3483 if (fbc_wm > SNB_FBC_MAX_SRWM) {
3484 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
3485 fbc_wm, SNB_FBC_MAX_SRWM, level);
3486
3487 /* fbc has it's own way to disable FBC WM */
3488 I915_WRITE(DISP_ARB_CTL,
3489 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3490 return false;
3491 }
3492
3493 if (display_wm > display->max_wm) {
3494 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
3495 display_wm, SNB_DISPLAY_MAX_SRWM, level);
3496 return false;
3497 }
3498
3499 if (cursor_wm > cursor->max_wm) {
3500 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
3501 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
3502 return false;
3503 }
3504
3505 if (!(fbc_wm || display_wm || cursor_wm)) {
3506 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3507 return false;
3508 }
3509
3510 return true;
3511 }
3512
3513 /*
3514 * Compute watermark values of WM[1-3],
3515 */
3516 static bool ironlake_compute_srwm(struct drm_device *dev, int level,
3517 int hdisplay, int htotal,
3518 int pixel_size, int clock, int latency_ns,
3519 const struct intel_watermark_params *display,
3520 const struct intel_watermark_params *cursor,
3521 int *fbc_wm, int *display_wm, int *cursor_wm)
3522 {
3523
3524 unsigned long line_time_us;
3525 int line_count, line_size;
3526 int small, large;
3527 int entries;
3528
3529 if (!latency_ns) {
3530 *fbc_wm = *display_wm = *cursor_wm = 0;
3531 return false;
3532 }
3533
3534 line_time_us = (htotal * 1000) / clock;
3535 line_count = (latency_ns / line_time_us + 1000) / 1000;
3536 line_size = hdisplay * pixel_size;
3537
3538 /* Use the minimum of the small and large buffer method for primary */
3539 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3540 large = line_count * line_size;
3541
3542 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3543 *display_wm = entries + display->guard_size;
3544
3545 /*
3546 * Spec says:
3547 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
3548 */
3549 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
3550
3551 /* calculate the self-refresh watermark for display cursor */
3552 entries = line_count * pixel_size * 64;
3553 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3554 *cursor_wm = entries + cursor->guard_size;
3555
3556 return ironlake_check_srwm(dev, level,
3557 *fbc_wm, *display_wm, *cursor_wm,
3558 display, cursor);
3559 }
3560
3561 static void ironlake_update_wm(struct drm_device *dev,
3562 int planea_clock, int planeb_clock,
3563 int hdisplay, int htotal,
3564 int pixel_size)
3565 {
3566 struct drm_i915_private *dev_priv = dev->dev_private;
3567 int fbc_wm, plane_wm, cursor_wm, enabled;
3568 int clock;
3569
3570 enabled = 0;
3571 if (ironlake_compute_wm0(dev, 0,
3572 &ironlake_display_wm_info,
3573 ILK_LP0_PLANE_LATENCY,
3574 &ironlake_cursor_wm_info,
3575 ILK_LP0_CURSOR_LATENCY,
3576 &plane_wm, &cursor_wm)) {
3577 I915_WRITE(WM0_PIPEA_ILK,
3578 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3579 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3580 " plane %d, " "cursor: %d\n",
3581 plane_wm, cursor_wm);
3582 enabled++;
3583 }
3584
3585 if (ironlake_compute_wm0(dev, 1,
3586 &ironlake_display_wm_info,
3587 ILK_LP0_PLANE_LATENCY,
3588 &ironlake_cursor_wm_info,
3589 ILK_LP0_CURSOR_LATENCY,
3590 &plane_wm, &cursor_wm)) {
3591 I915_WRITE(WM0_PIPEB_ILK,
3592 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3593 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3594 " plane %d, cursor: %d\n",
3595 plane_wm, cursor_wm);
3596 enabled++;
3597 }
3598
3599 /*
3600 * Calculate and update the self-refresh watermark only when one
3601 * display plane is used.
3602 */
3603 I915_WRITE(WM3_LP_ILK, 0);
3604 I915_WRITE(WM2_LP_ILK, 0);
3605 I915_WRITE(WM1_LP_ILK, 0);
3606
3607 if (enabled != 1)
3608 return;
3609
3610 clock = planea_clock ? planea_clock : planeb_clock;
3611
3612 /* WM1 */
3613 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3614 clock, ILK_READ_WM1_LATENCY() * 500,
3615 &ironlake_display_srwm_info,
3616 &ironlake_cursor_srwm_info,
3617 &fbc_wm, &plane_wm, &cursor_wm))
3618 return;
3619
3620 I915_WRITE(WM1_LP_ILK,
3621 WM1_LP_SR_EN |
3622 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3623 (fbc_wm << WM1_LP_FBC_SHIFT) |
3624 (plane_wm << WM1_LP_SR_SHIFT) |
3625 cursor_wm);
3626
3627 /* WM2 */
3628 if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size,
3629 clock, ILK_READ_WM2_LATENCY() * 500,
3630 &ironlake_display_srwm_info,
3631 &ironlake_cursor_srwm_info,
3632 &fbc_wm, &plane_wm, &cursor_wm))
3633 return;
3634
3635 I915_WRITE(WM2_LP_ILK,
3636 WM2_LP_EN |
3637 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3638 (fbc_wm << WM1_LP_FBC_SHIFT) |
3639 (plane_wm << WM1_LP_SR_SHIFT) |
3640 cursor_wm);
3641
3642 /*
3643 * WM3 is unsupported on ILK, probably because we don't have latency
3644 * data for that power state
3645 */
3646 }
3647
3648 static void sandybridge_update_wm(struct drm_device *dev,
3649 int planea_clock, int planeb_clock,
3650 int hdisplay, int htotal,
3651 int pixel_size)
3652 {
3653 struct drm_i915_private *dev_priv = dev->dev_private;
3654 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
3655 int fbc_wm, plane_wm, cursor_wm, enabled;
3656 int clock;
3657
3658 enabled = 0;
3659 if (ironlake_compute_wm0(dev, 0,
3660 &sandybridge_display_wm_info, latency,
3661 &sandybridge_cursor_wm_info, latency,
3662 &plane_wm, &cursor_wm)) {
3663 I915_WRITE(WM0_PIPEA_ILK,
3664 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3665 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3666 " plane %d, " "cursor: %d\n",
3667 plane_wm, cursor_wm);
3668 enabled++;
3669 }
3670
3671 if (ironlake_compute_wm0(dev, 1,
3672 &sandybridge_display_wm_info, latency,
3673 &sandybridge_cursor_wm_info, latency,
3674 &plane_wm, &cursor_wm)) {
3675 I915_WRITE(WM0_PIPEB_ILK,
3676 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3677 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3678 " plane %d, cursor: %d\n",
3679 plane_wm, cursor_wm);
3680 enabled++;
3681 }
3682
3683 /*
3684 * Calculate and update the self-refresh watermark only when one
3685 * display plane is used.
3686 *
3687 * SNB support 3 levels of watermark.
3688 *
3689 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
3690 * and disabled in the descending order
3691 *
3692 */
3693 I915_WRITE(WM3_LP_ILK, 0);
3694 I915_WRITE(WM2_LP_ILK, 0);
3695 I915_WRITE(WM1_LP_ILK, 0);
3696
3697 if (enabled != 1)
3698 return;
3699
3700 clock = planea_clock ? planea_clock : planeb_clock;
3701
3702 /* WM1 */
3703 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3704 clock, SNB_READ_WM1_LATENCY() * 500,
3705 &sandybridge_display_srwm_info,
3706 &sandybridge_cursor_srwm_info,
3707 &fbc_wm, &plane_wm, &cursor_wm))
3708 return;
3709
3710 I915_WRITE(WM1_LP_ILK,
3711 WM1_LP_SR_EN |
3712 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3713 (fbc_wm << WM1_LP_FBC_SHIFT) |
3714 (plane_wm << WM1_LP_SR_SHIFT) |
3715 cursor_wm);
3716
3717 /* WM2 */
3718 if (!ironlake_compute_srwm(dev, 2,
3719 hdisplay, htotal, pixel_size,
3720 clock, SNB_READ_WM2_LATENCY() * 500,
3721 &sandybridge_display_srwm_info,
3722 &sandybridge_cursor_srwm_info,
3723 &fbc_wm, &plane_wm, &cursor_wm))
3724 return;
3725
3726 I915_WRITE(WM2_LP_ILK,
3727 WM2_LP_EN |
3728 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3729 (fbc_wm << WM1_LP_FBC_SHIFT) |
3730 (plane_wm << WM1_LP_SR_SHIFT) |
3731 cursor_wm);
3732
3733 /* WM3 */
3734 if (!ironlake_compute_srwm(dev, 3,
3735 hdisplay, htotal, pixel_size,
3736 clock, SNB_READ_WM3_LATENCY() * 500,
3737 &sandybridge_display_srwm_info,
3738 &sandybridge_cursor_srwm_info,
3739 &fbc_wm, &plane_wm, &cursor_wm))
3740 return;
3741
3742 I915_WRITE(WM3_LP_ILK,
3743 WM3_LP_EN |
3744 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3745 (fbc_wm << WM1_LP_FBC_SHIFT) |
3746 (plane_wm << WM1_LP_SR_SHIFT) |
3747 cursor_wm);
3748 }
3749
3750 /**
3751 * intel_update_watermarks - update FIFO watermark values based on current modes
3752 *
3753 * Calculate watermark values for the various WM regs based on current mode
3754 * and plane configuration.
3755 *
3756 * There are several cases to deal with here:
3757 * - normal (i.e. non-self-refresh)
3758 * - self-refresh (SR) mode
3759 * - lines are large relative to FIFO size (buffer can hold up to 2)
3760 * - lines are small relative to FIFO size (buffer can hold more than 2
3761 * lines), so need to account for TLB latency
3762 *
3763 * The normal calculation is:
3764 * watermark = dotclock * bytes per pixel * latency
3765 * where latency is platform & configuration dependent (we assume pessimal
3766 * values here).
3767 *
3768 * The SR calculation is:
3769 * watermark = (trunc(latency/line time)+1) * surface width *
3770 * bytes per pixel
3771 * where
3772 * line time = htotal / dotclock
3773 * surface width = hdisplay for normal plane and 64 for cursor
3774 * and latency is assumed to be high, as above.
3775 *
3776 * The final value programmed to the register should always be rounded up,
3777 * and include an extra 2 entries to account for clock crossings.
3778 *
3779 * We don't use the sprite, so we can ignore that. And on Crestline we have
3780 * to set the non-SR watermarks to 8.
3781 */
3782 static void intel_update_watermarks(struct drm_device *dev)
3783 {
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 struct drm_crtc *crtc;
3786 int sr_hdisplay = 0;
3787 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3788 int enabled = 0, pixel_size = 0;
3789 int sr_htotal = 0;
3790
3791 if (!dev_priv->display.update_wm)
3792 return;
3793
3794 /* Get the clock config from both planes */
3795 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3797 if (intel_crtc->active) {
3798 enabled++;
3799 if (intel_crtc->plane == 0) {
3800 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3801 intel_crtc->pipe, crtc->mode.clock);
3802 planea_clock = crtc->mode.clock;
3803 } else {
3804 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3805 intel_crtc->pipe, crtc->mode.clock);
3806 planeb_clock = crtc->mode.clock;
3807 }
3808 sr_hdisplay = crtc->mode.hdisplay;
3809 sr_clock = crtc->mode.clock;
3810 sr_htotal = crtc->mode.htotal;
3811 if (crtc->fb)
3812 pixel_size = crtc->fb->bits_per_pixel / 8;
3813 else
3814 pixel_size = 4; /* by default */
3815 }
3816 }
3817
3818 if (enabled <= 0)
3819 return;
3820
3821 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3822 sr_hdisplay, sr_htotal, pixel_size);
3823 }
3824
3825 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3826 struct drm_display_mode *mode,
3827 struct drm_display_mode *adjusted_mode,
3828 int x, int y,
3829 struct drm_framebuffer *old_fb)
3830 {
3831 struct drm_device *dev = crtc->dev;
3832 struct drm_i915_private *dev_priv = dev->dev_private;
3833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3834 int pipe = intel_crtc->pipe;
3835 int plane = intel_crtc->plane;
3836 u32 fp_reg, dpll_reg;
3837 int refclk, num_connectors = 0;
3838 intel_clock_t clock, reduced_clock;
3839 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3840 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3841 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3842 struct intel_encoder *has_edp_encoder = NULL;
3843 struct drm_mode_config *mode_config = &dev->mode_config;
3844 struct intel_encoder *encoder;
3845 const intel_limit_t *limit;
3846 int ret;
3847 struct fdi_m_n m_n = {0};
3848 u32 reg, temp;
3849 int target_clock;
3850
3851 drm_vblank_pre_modeset(dev, pipe);
3852
3853 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3854 if (encoder->base.crtc != crtc)
3855 continue;
3856
3857 switch (encoder->type) {
3858 case INTEL_OUTPUT_LVDS:
3859 is_lvds = true;
3860 break;
3861 case INTEL_OUTPUT_SDVO:
3862 case INTEL_OUTPUT_HDMI:
3863 is_sdvo = true;
3864 if (encoder->needs_tv_clock)
3865 is_tv = true;
3866 break;
3867 case INTEL_OUTPUT_DVO:
3868 is_dvo = true;
3869 break;
3870 case INTEL_OUTPUT_TVOUT:
3871 is_tv = true;
3872 break;
3873 case INTEL_OUTPUT_ANALOG:
3874 is_crt = true;
3875 break;
3876 case INTEL_OUTPUT_DISPLAYPORT:
3877 is_dp = true;
3878 break;
3879 case INTEL_OUTPUT_EDP:
3880 has_edp_encoder = encoder;
3881 break;
3882 }
3883
3884 num_connectors++;
3885 }
3886
3887 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3888 refclk = dev_priv->lvds_ssc_freq * 1000;
3889 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3890 refclk / 1000);
3891 } else if (!IS_GEN2(dev)) {
3892 refclk = 96000;
3893 if (HAS_PCH_SPLIT(dev) &&
3894 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3895 refclk = 120000; /* 120Mhz refclk */
3896 } else {
3897 refclk = 48000;
3898 }
3899
3900 /*
3901 * Returns a set of divisors for the desired target clock with the given
3902 * refclk, or FALSE. The returned values represent the clock equation:
3903 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3904 */
3905 limit = intel_limit(crtc, refclk);
3906 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3907 if (!ok) {
3908 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3909 drm_vblank_post_modeset(dev, pipe);
3910 return -EINVAL;
3911 }
3912
3913 /* Ensure that the cursor is valid for the new mode before changing... */
3914 intel_crtc_update_cursor(crtc, true);
3915
3916 if (is_lvds && dev_priv->lvds_downclock_avail) {
3917 has_reduced_clock = limit->find_pll(limit, crtc,
3918 dev_priv->lvds_downclock,
3919 refclk,
3920 &reduced_clock);
3921 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3922 /*
3923 * If the different P is found, it means that we can't
3924 * switch the display clock by using the FP0/FP1.
3925 * In such case we will disable the LVDS downclock
3926 * feature.
3927 */
3928 DRM_DEBUG_KMS("Different P is found for "
3929 "LVDS clock/downclock\n");
3930 has_reduced_clock = 0;
3931 }
3932 }
3933 /* SDVO TV has fixed PLL values depend on its clock range,
3934 this mirrors vbios setting. */
3935 if (is_sdvo && is_tv) {
3936 if (adjusted_mode->clock >= 100000
3937 && adjusted_mode->clock < 140500) {
3938 clock.p1 = 2;
3939 clock.p2 = 10;
3940 clock.n = 3;
3941 clock.m1 = 16;
3942 clock.m2 = 8;
3943 } else if (adjusted_mode->clock >= 140500
3944 && adjusted_mode->clock <= 200000) {
3945 clock.p1 = 1;
3946 clock.p2 = 10;
3947 clock.n = 6;
3948 clock.m1 = 12;
3949 clock.m2 = 8;
3950 }
3951 }
3952
3953 /* FDI link */
3954 if (HAS_PCH_SPLIT(dev)) {
3955 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3956 int lane = 0, link_bw, bpp;
3957 /* CPU eDP doesn't require FDI link, so just set DP M/N
3958 according to current link config */
3959 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3960 target_clock = mode->clock;
3961 intel_edp_link_config(has_edp_encoder,
3962 &lane, &link_bw);
3963 } else {
3964 /* [e]DP over FDI requires target mode clock
3965 instead of link clock */
3966 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3967 target_clock = mode->clock;
3968 else
3969 target_clock = adjusted_mode->clock;
3970
3971 /* FDI is a binary signal running at ~2.7GHz, encoding
3972 * each output octet as 10 bits. The actual frequency
3973 * is stored as a divider into a 100MHz clock, and the
3974 * mode pixel clock is stored in units of 1KHz.
3975 * Hence the bw of each lane in terms of the mode signal
3976 * is:
3977 */
3978 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3979 }
3980
3981 /* determine panel color depth */
3982 temp = I915_READ(PIPECONF(pipe));
3983 temp &= ~PIPE_BPC_MASK;
3984 if (is_lvds) {
3985 /* the BPC will be 6 if it is 18-bit LVDS panel */
3986 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3987 temp |= PIPE_8BPC;
3988 else
3989 temp |= PIPE_6BPC;
3990 } else if (has_edp_encoder) {
3991 switch (dev_priv->edp.bpp/3) {
3992 case 8:
3993 temp |= PIPE_8BPC;
3994 break;
3995 case 10:
3996 temp |= PIPE_10BPC;
3997 break;
3998 case 6:
3999 temp |= PIPE_6BPC;
4000 break;
4001 case 12:
4002 temp |= PIPE_12BPC;
4003 break;
4004 }
4005 } else
4006 temp |= PIPE_8BPC;
4007 I915_WRITE(PIPECONF(pipe), temp);
4008
4009 switch (temp & PIPE_BPC_MASK) {
4010 case PIPE_8BPC:
4011 bpp = 24;
4012 break;
4013 case PIPE_10BPC:
4014 bpp = 30;
4015 break;
4016 case PIPE_6BPC:
4017 bpp = 18;
4018 break;
4019 case PIPE_12BPC:
4020 bpp = 36;
4021 break;
4022 default:
4023 DRM_ERROR("unknown pipe bpc value\n");
4024 bpp = 24;
4025 }
4026
4027 if (!lane) {
4028 /*
4029 * Account for spread spectrum to avoid
4030 * oversubscribing the link. Max center spread
4031 * is 2.5%; use 5% for safety's sake.
4032 */
4033 u32 bps = target_clock * bpp * 21 / 20;
4034 lane = bps / (link_bw * 8) + 1;
4035 }
4036
4037 intel_crtc->fdi_lanes = lane;
4038
4039 if (pixel_multiplier > 1)
4040 link_bw *= pixel_multiplier;
4041 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4042 }
4043
4044 /* Ironlake: try to setup display ref clock before DPLL
4045 * enabling. This is only under driver's control after
4046 * PCH B stepping, previous chipset stepping should be
4047 * ignoring this setting.
4048 */
4049 if (HAS_PCH_SPLIT(dev)) {
4050 temp = I915_READ(PCH_DREF_CONTROL);
4051 /* Always enable nonspread source */
4052 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4053 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4054 temp &= ~DREF_SSC_SOURCE_MASK;
4055 temp |= DREF_SSC_SOURCE_ENABLE;
4056 I915_WRITE(PCH_DREF_CONTROL, temp);
4057
4058 POSTING_READ(PCH_DREF_CONTROL);
4059 udelay(200);
4060
4061 if (has_edp_encoder) {
4062 if (dev_priv->lvds_use_ssc) {
4063 temp |= DREF_SSC1_ENABLE;
4064 I915_WRITE(PCH_DREF_CONTROL, temp);
4065
4066 POSTING_READ(PCH_DREF_CONTROL);
4067 udelay(200);
4068 }
4069 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4070
4071 /* Enable CPU source on CPU attached eDP */
4072 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4073 if (dev_priv->lvds_use_ssc)
4074 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4075 else
4076 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4077 } else {
4078 /* Enable SSC on PCH eDP if needed */
4079 if (dev_priv->lvds_use_ssc) {
4080 DRM_ERROR("enabling SSC on PCH\n");
4081 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4082 }
4083 }
4084 I915_WRITE(PCH_DREF_CONTROL, temp);
4085 POSTING_READ(PCH_DREF_CONTROL);
4086 udelay(200);
4087 }
4088 }
4089
4090 if (IS_PINEVIEW(dev)) {
4091 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4092 if (has_reduced_clock)
4093 fp2 = (1 << reduced_clock.n) << 16 |
4094 reduced_clock.m1 << 8 | reduced_clock.m2;
4095 } else {
4096 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4097 if (has_reduced_clock)
4098 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4099 reduced_clock.m2;
4100 }
4101
4102 /* Enable autotuning of the PLL clock (if permissible) */
4103 if (HAS_PCH_SPLIT(dev)) {
4104 int factor = 21;
4105
4106 if (is_lvds) {
4107 if ((dev_priv->lvds_use_ssc &&
4108 dev_priv->lvds_ssc_freq == 100) ||
4109 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4110 factor = 25;
4111 } else if (is_sdvo && is_tv)
4112 factor = 20;
4113
4114 if (clock.m1 < factor * clock.n)
4115 fp |= FP_CB_TUNE;
4116 }
4117
4118 dpll = 0;
4119 if (!HAS_PCH_SPLIT(dev))
4120 dpll = DPLL_VGA_MODE_DIS;
4121
4122 if (!IS_GEN2(dev)) {
4123 if (is_lvds)
4124 dpll |= DPLLB_MODE_LVDS;
4125 else
4126 dpll |= DPLLB_MODE_DAC_SERIAL;
4127 if (is_sdvo) {
4128 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4129 if (pixel_multiplier > 1) {
4130 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4131 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4132 else if (HAS_PCH_SPLIT(dev))
4133 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4134 }
4135 dpll |= DPLL_DVO_HIGH_SPEED;
4136 }
4137 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4138 dpll |= DPLL_DVO_HIGH_SPEED;
4139
4140 /* compute bitmask from p1 value */
4141 if (IS_PINEVIEW(dev))
4142 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4143 else {
4144 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4145 /* also FPA1 */
4146 if (HAS_PCH_SPLIT(dev))
4147 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4148 if (IS_G4X(dev) && has_reduced_clock)
4149 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4150 }
4151 switch (clock.p2) {
4152 case 5:
4153 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4154 break;
4155 case 7:
4156 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4157 break;
4158 case 10:
4159 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4160 break;
4161 case 14:
4162 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4163 break;
4164 }
4165 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4166 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4167 } else {
4168 if (is_lvds) {
4169 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4170 } else {
4171 if (clock.p1 == 2)
4172 dpll |= PLL_P1_DIVIDE_BY_TWO;
4173 else
4174 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4175 if (clock.p2 == 4)
4176 dpll |= PLL_P2_DIVIDE_BY_4;
4177 }
4178 }
4179
4180 if (is_sdvo && is_tv)
4181 dpll |= PLL_REF_INPUT_TVCLKINBC;
4182 else if (is_tv)
4183 /* XXX: just matching BIOS for now */
4184 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4185 dpll |= 3;
4186 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
4187 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4188 else
4189 dpll |= PLL_REF_INPUT_DREFCLK;
4190
4191 /* setup pipeconf */
4192 pipeconf = I915_READ(PIPECONF(pipe));
4193
4194 /* Set up the display plane register */
4195 dspcntr = DISPPLANE_GAMMA_ENABLE;
4196
4197 /* Ironlake's plane is forced to pipe, bit 24 is to
4198 enable color space conversion */
4199 if (!HAS_PCH_SPLIT(dev)) {
4200 if (pipe == 0)
4201 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4202 else
4203 dspcntr |= DISPPLANE_SEL_PIPE_B;
4204 }
4205
4206 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4207 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4208 * core speed.
4209 *
4210 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4211 * pipe == 0 check?
4212 */
4213 if (mode->clock >
4214 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4215 pipeconf |= PIPECONF_DOUBLE_WIDE;
4216 else
4217 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4218 }
4219
4220 dspcntr |= DISPLAY_PLANE_ENABLE;
4221 pipeconf |= PIPECONF_ENABLE;
4222 dpll |= DPLL_VCO_ENABLE;
4223
4224 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4225 drm_mode_debug_printmodeline(mode);
4226
4227 /* assign to Ironlake registers */
4228 if (HAS_PCH_SPLIT(dev)) {
4229 fp_reg = PCH_FP0(pipe);
4230 dpll_reg = PCH_DPLL(pipe);
4231 } else {
4232 fp_reg = FP0(pipe);
4233 dpll_reg = DPLL(pipe);
4234 }
4235
4236 /* PCH eDP needs FDI, but CPU eDP does not */
4237 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4238 I915_WRITE(fp_reg, fp);
4239 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4240
4241 POSTING_READ(dpll_reg);
4242 udelay(150);
4243 }
4244
4245 /* enable transcoder DPLL */
4246 if (HAS_PCH_CPT(dev)) {
4247 temp = I915_READ(PCH_DPLL_SEL);
4248 if (pipe == 0)
4249 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4250 else
4251 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4252 I915_WRITE(PCH_DPLL_SEL, temp);
4253
4254 POSTING_READ(PCH_DPLL_SEL);
4255 udelay(150);
4256 }
4257
4258 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4259 * This is an exception to the general rule that mode_set doesn't turn
4260 * things on.
4261 */
4262 if (is_lvds) {
4263 reg = LVDS;
4264 if (HAS_PCH_SPLIT(dev))
4265 reg = PCH_LVDS;
4266
4267 temp = I915_READ(reg);
4268 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4269 if (pipe == 1) {
4270 if (HAS_PCH_CPT(dev))
4271 temp |= PORT_TRANS_B_SEL_CPT;
4272 else
4273 temp |= LVDS_PIPEB_SELECT;
4274 } else {
4275 if (HAS_PCH_CPT(dev))
4276 temp &= ~PORT_TRANS_SEL_MASK;
4277 else
4278 temp &= ~LVDS_PIPEB_SELECT;
4279 }
4280 /* set the corresponsding LVDS_BORDER bit */
4281 temp |= dev_priv->lvds_border_bits;
4282 /* Set the B0-B3 data pairs corresponding to whether we're going to
4283 * set the DPLLs for dual-channel mode or not.
4284 */
4285 if (clock.p2 == 7)
4286 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4287 else
4288 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4289
4290 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4291 * appropriately here, but we need to look more thoroughly into how
4292 * panels behave in the two modes.
4293 */
4294 /* set the dithering flag on non-PCH LVDS as needed */
4295 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4296 if (dev_priv->lvds_dither)
4297 temp |= LVDS_ENABLE_DITHER;
4298 else
4299 temp &= ~LVDS_ENABLE_DITHER;
4300 }
4301 I915_WRITE(reg, temp);
4302 }
4303
4304 /* set the dithering flag and clear for anything other than a panel. */
4305 if (HAS_PCH_SPLIT(dev)) {
4306 pipeconf &= ~PIPECONF_DITHER_EN;
4307 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4308 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4309 pipeconf |= PIPECONF_DITHER_EN;
4310 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4311 }
4312 }
4313
4314 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4315 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4316 } else if (HAS_PCH_SPLIT(dev)) {
4317 /* For non-DP output, clear any trans DP clock recovery setting.*/
4318 if (pipe == 0) {
4319 I915_WRITE(TRANSA_DATA_M1, 0);
4320 I915_WRITE(TRANSA_DATA_N1, 0);
4321 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4322 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4323 } else {
4324 I915_WRITE(TRANSB_DATA_M1, 0);
4325 I915_WRITE(TRANSB_DATA_N1, 0);
4326 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4327 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4328 }
4329 }
4330
4331 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4332 I915_WRITE(dpll_reg, dpll);
4333
4334 /* Wait for the clocks to stabilize. */
4335 POSTING_READ(dpll_reg);
4336 udelay(150);
4337
4338 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4339 temp = 0;
4340 if (is_sdvo) {
4341 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4342 if (temp > 1)
4343 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4344 else
4345 temp = 0;
4346 }
4347 I915_WRITE(DPLL_MD(pipe), temp);
4348 } else {
4349 /* The pixel multiplier can only be updated once the
4350 * DPLL is enabled and the clocks are stable.
4351 *
4352 * So write it again.
4353 */
4354 I915_WRITE(dpll_reg, dpll);
4355 }
4356 }
4357
4358 intel_crtc->lowfreq_avail = false;
4359 if (is_lvds && has_reduced_clock && i915_powersave) {
4360 I915_WRITE(fp_reg + 4, fp2);
4361 intel_crtc->lowfreq_avail = true;
4362 if (HAS_PIPE_CXSR(dev)) {
4363 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4364 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4365 }
4366 } else {
4367 I915_WRITE(fp_reg + 4, fp);
4368 if (HAS_PIPE_CXSR(dev)) {
4369 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4370 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4371 }
4372 }
4373
4374 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4375 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4376 /* the chip adds 2 halflines automatically */
4377 adjusted_mode->crtc_vdisplay -= 1;
4378 adjusted_mode->crtc_vtotal -= 1;
4379 adjusted_mode->crtc_vblank_start -= 1;
4380 adjusted_mode->crtc_vblank_end -= 1;
4381 adjusted_mode->crtc_vsync_end -= 1;
4382 adjusted_mode->crtc_vsync_start -= 1;
4383 } else
4384 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4385
4386 I915_WRITE(HTOTAL(pipe),
4387 (adjusted_mode->crtc_hdisplay - 1) |
4388 ((adjusted_mode->crtc_htotal - 1) << 16));
4389 I915_WRITE(HBLANK(pipe),
4390 (adjusted_mode->crtc_hblank_start - 1) |
4391 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4392 I915_WRITE(HSYNC(pipe),
4393 (adjusted_mode->crtc_hsync_start - 1) |
4394 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4395
4396 I915_WRITE(VTOTAL(pipe),
4397 (adjusted_mode->crtc_vdisplay - 1) |
4398 ((adjusted_mode->crtc_vtotal - 1) << 16));
4399 I915_WRITE(VBLANK(pipe),
4400 (adjusted_mode->crtc_vblank_start - 1) |
4401 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4402 I915_WRITE(VSYNC(pipe),
4403 (adjusted_mode->crtc_vsync_start - 1) |
4404 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4405
4406 /* pipesrc and dspsize control the size that is scaled from,
4407 * which should always be the user's requested size.
4408 */
4409 if (!HAS_PCH_SPLIT(dev)) {
4410 I915_WRITE(DSPSIZE(plane),
4411 ((mode->vdisplay - 1) << 16) |
4412 (mode->hdisplay - 1));
4413 I915_WRITE(DSPPOS(plane), 0);
4414 }
4415 I915_WRITE(PIPESRC(pipe),
4416 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4417
4418 if (HAS_PCH_SPLIT(dev)) {
4419 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4420 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4421 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4422 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4423
4424 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4425 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4426 }
4427 }
4428
4429 I915_WRITE(PIPECONF(pipe), pipeconf);
4430 POSTING_READ(PIPECONF(pipe));
4431
4432 intel_wait_for_vblank(dev, pipe);
4433
4434 if (IS_GEN5(dev)) {
4435 /* enable address swizzle for tiling buffer */
4436 temp = I915_READ(DISP_ARB_CTL);
4437 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4438 }
4439
4440 I915_WRITE(DSPCNTR(plane), dspcntr);
4441
4442 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4443
4444 intel_update_watermarks(dev);
4445
4446 drm_vblank_post_modeset(dev, pipe);
4447
4448 return ret;
4449 }
4450
4451 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4452 void intel_crtc_load_lut(struct drm_crtc *crtc)
4453 {
4454 struct drm_device *dev = crtc->dev;
4455 struct drm_i915_private *dev_priv = dev->dev_private;
4456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4457 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4458 int i;
4459
4460 /* The clocks have to be on to load the palette. */
4461 if (!crtc->enabled)
4462 return;
4463
4464 /* use legacy palette for Ironlake */
4465 if (HAS_PCH_SPLIT(dev))
4466 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4467 LGC_PALETTE_B;
4468
4469 for (i = 0; i < 256; i++) {
4470 I915_WRITE(palreg + 4 * i,
4471 (intel_crtc->lut_r[i] << 16) |
4472 (intel_crtc->lut_g[i] << 8) |
4473 intel_crtc->lut_b[i]);
4474 }
4475 }
4476
4477 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4478 {
4479 struct drm_device *dev = crtc->dev;
4480 struct drm_i915_private *dev_priv = dev->dev_private;
4481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4482 bool visible = base != 0;
4483 u32 cntl;
4484
4485 if (intel_crtc->cursor_visible == visible)
4486 return;
4487
4488 cntl = I915_READ(CURACNTR);
4489 if (visible) {
4490 /* On these chipsets we can only modify the base whilst
4491 * the cursor is disabled.
4492 */
4493 I915_WRITE(CURABASE, base);
4494
4495 cntl &= ~(CURSOR_FORMAT_MASK);
4496 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4497 cntl |= CURSOR_ENABLE |
4498 CURSOR_GAMMA_ENABLE |
4499 CURSOR_FORMAT_ARGB;
4500 } else
4501 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4502 I915_WRITE(CURACNTR, cntl);
4503
4504 intel_crtc->cursor_visible = visible;
4505 }
4506
4507 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4508 {
4509 struct drm_device *dev = crtc->dev;
4510 struct drm_i915_private *dev_priv = dev->dev_private;
4511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4512 int pipe = intel_crtc->pipe;
4513 bool visible = base != 0;
4514
4515 if (intel_crtc->cursor_visible != visible) {
4516 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4517 if (base) {
4518 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4519 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4520 cntl |= pipe << 28; /* Connect to correct pipe */
4521 } else {
4522 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4523 cntl |= CURSOR_MODE_DISABLE;
4524 }
4525 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4526
4527 intel_crtc->cursor_visible = visible;
4528 }
4529 /* and commit changes on next vblank */
4530 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4531 }
4532
4533 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4534 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4535 bool on)
4536 {
4537 struct drm_device *dev = crtc->dev;
4538 struct drm_i915_private *dev_priv = dev->dev_private;
4539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4540 int pipe = intel_crtc->pipe;
4541 int x = intel_crtc->cursor_x;
4542 int y = intel_crtc->cursor_y;
4543 u32 base, pos;
4544 bool visible;
4545
4546 pos = 0;
4547
4548 if (on && crtc->enabled && crtc->fb) {
4549 base = intel_crtc->cursor_addr;
4550 if (x > (int) crtc->fb->width)
4551 base = 0;
4552
4553 if (y > (int) crtc->fb->height)
4554 base = 0;
4555 } else
4556 base = 0;
4557
4558 if (x < 0) {
4559 if (x + intel_crtc->cursor_width < 0)
4560 base = 0;
4561
4562 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4563 x = -x;
4564 }
4565 pos |= x << CURSOR_X_SHIFT;
4566
4567 if (y < 0) {
4568 if (y + intel_crtc->cursor_height < 0)
4569 base = 0;
4570
4571 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4572 y = -y;
4573 }
4574 pos |= y << CURSOR_Y_SHIFT;
4575
4576 visible = base != 0;
4577 if (!visible && !intel_crtc->cursor_visible)
4578 return;
4579
4580 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4581 if (IS_845G(dev) || IS_I865G(dev))
4582 i845_update_cursor(crtc, base);
4583 else
4584 i9xx_update_cursor(crtc, base);
4585
4586 if (visible)
4587 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4588 }
4589
4590 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4591 struct drm_file *file,
4592 uint32_t handle,
4593 uint32_t width, uint32_t height)
4594 {
4595 struct drm_device *dev = crtc->dev;
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598 struct drm_i915_gem_object *obj;
4599 uint32_t addr;
4600 int ret;
4601
4602 DRM_DEBUG_KMS("\n");
4603
4604 /* if we want to turn off the cursor ignore width and height */
4605 if (!handle) {
4606 DRM_DEBUG_KMS("cursor off\n");
4607 addr = 0;
4608 obj = NULL;
4609 mutex_lock(&dev->struct_mutex);
4610 goto finish;
4611 }
4612
4613 /* Currently we only support 64x64 cursors */
4614 if (width != 64 || height != 64) {
4615 DRM_ERROR("we currently only support 64x64 cursors\n");
4616 return -EINVAL;
4617 }
4618
4619 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4620 if (!obj)
4621 return -ENOENT;
4622
4623 if (obj->base.size < width * height * 4) {
4624 DRM_ERROR("buffer is to small\n");
4625 ret = -ENOMEM;
4626 goto fail;
4627 }
4628
4629 /* we only need to pin inside GTT if cursor is non-phy */
4630 mutex_lock(&dev->struct_mutex);
4631 if (!dev_priv->info->cursor_needs_physical) {
4632 if (obj->tiling_mode) {
4633 DRM_ERROR("cursor cannot be tiled\n");
4634 ret = -EINVAL;
4635 goto fail_locked;
4636 }
4637
4638 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
4639 if (ret) {
4640 DRM_ERROR("failed to pin cursor bo\n");
4641 goto fail_locked;
4642 }
4643
4644 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
4645 if (ret) {
4646 DRM_ERROR("failed to move cursor bo into the GTT\n");
4647 goto fail_unpin;
4648 }
4649
4650 ret = i915_gem_object_put_fence(obj);
4651 if (ret) {
4652 DRM_ERROR("failed to move cursor bo into the GTT\n");
4653 goto fail_unpin;
4654 }
4655
4656 addr = obj->gtt_offset;
4657 } else {
4658 int align = IS_I830(dev) ? 16 * 1024 : 256;
4659 ret = i915_gem_attach_phys_object(dev, obj,
4660 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4661 align);
4662 if (ret) {
4663 DRM_ERROR("failed to attach phys object\n");
4664 goto fail_locked;
4665 }
4666 addr = obj->phys_obj->handle->busaddr;
4667 }
4668
4669 if (IS_GEN2(dev))
4670 I915_WRITE(CURSIZE, (height << 12) | width);
4671
4672 finish:
4673 if (intel_crtc->cursor_bo) {
4674 if (dev_priv->info->cursor_needs_physical) {
4675 if (intel_crtc->cursor_bo != obj)
4676 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4677 } else
4678 i915_gem_object_unpin(intel_crtc->cursor_bo);
4679 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4680 }
4681
4682 mutex_unlock(&dev->struct_mutex);
4683
4684 intel_crtc->cursor_addr = addr;
4685 intel_crtc->cursor_bo = obj;
4686 intel_crtc->cursor_width = width;
4687 intel_crtc->cursor_height = height;
4688
4689 intel_crtc_update_cursor(crtc, true);
4690
4691 return 0;
4692 fail_unpin:
4693 i915_gem_object_unpin(obj);
4694 fail_locked:
4695 mutex_unlock(&dev->struct_mutex);
4696 fail:
4697 drm_gem_object_unreference_unlocked(&obj->base);
4698 return ret;
4699 }
4700
4701 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4702 {
4703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4704
4705 intel_crtc->cursor_x = x;
4706 intel_crtc->cursor_y = y;
4707
4708 intel_crtc_update_cursor(crtc, true);
4709
4710 return 0;
4711 }
4712
4713 /** Sets the color ramps on behalf of RandR */
4714 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4715 u16 blue, int regno)
4716 {
4717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4718
4719 intel_crtc->lut_r[regno] = red >> 8;
4720 intel_crtc->lut_g[regno] = green >> 8;
4721 intel_crtc->lut_b[regno] = blue >> 8;
4722 }
4723
4724 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4725 u16 *blue, int regno)
4726 {
4727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4728
4729 *red = intel_crtc->lut_r[regno] << 8;
4730 *green = intel_crtc->lut_g[regno] << 8;
4731 *blue = intel_crtc->lut_b[regno] << 8;
4732 }
4733
4734 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4735 u16 *blue, uint32_t start, uint32_t size)
4736 {
4737 int end = (start + size > 256) ? 256 : start + size, i;
4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739
4740 for (i = start; i < end; i++) {
4741 intel_crtc->lut_r[i] = red[i] >> 8;
4742 intel_crtc->lut_g[i] = green[i] >> 8;
4743 intel_crtc->lut_b[i] = blue[i] >> 8;
4744 }
4745
4746 intel_crtc_load_lut(crtc);
4747 }
4748
4749 /**
4750 * Get a pipe with a simple mode set on it for doing load-based monitor
4751 * detection.
4752 *
4753 * It will be up to the load-detect code to adjust the pipe as appropriate for
4754 * its requirements. The pipe will be connected to no other encoders.
4755 *
4756 * Currently this code will only succeed if there is a pipe with no encoders
4757 * configured for it. In the future, it could choose to temporarily disable
4758 * some outputs to free up a pipe for its use.
4759 *
4760 * \return crtc, or NULL if no pipes are available.
4761 */
4762
4763 /* VESA 640x480x72Hz mode to set on the pipe */
4764 static struct drm_display_mode load_detect_mode = {
4765 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4766 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4767 };
4768
4769 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4770 struct drm_connector *connector,
4771 struct drm_display_mode *mode,
4772 int *dpms_mode)
4773 {
4774 struct intel_crtc *intel_crtc;
4775 struct drm_crtc *possible_crtc;
4776 struct drm_crtc *supported_crtc =NULL;
4777 struct drm_encoder *encoder = &intel_encoder->base;
4778 struct drm_crtc *crtc = NULL;
4779 struct drm_device *dev = encoder->dev;
4780 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4781 struct drm_crtc_helper_funcs *crtc_funcs;
4782 int i = -1;
4783
4784 /*
4785 * Algorithm gets a little messy:
4786 * - if the connector already has an assigned crtc, use it (but make
4787 * sure it's on first)
4788 * - try to find the first unused crtc that can drive this connector,
4789 * and use that if we find one
4790 * - if there are no unused crtcs available, try to use the first
4791 * one we found that supports the connector
4792 */
4793
4794 /* See if we already have a CRTC for this connector */
4795 if (encoder->crtc) {
4796 crtc = encoder->crtc;
4797 /* Make sure the crtc and connector are running */
4798 intel_crtc = to_intel_crtc(crtc);
4799 *dpms_mode = intel_crtc->dpms_mode;
4800 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4801 crtc_funcs = crtc->helper_private;
4802 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4803 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4804 }
4805 return crtc;
4806 }
4807
4808 /* Find an unused one (if possible) */
4809 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4810 i++;
4811 if (!(encoder->possible_crtcs & (1 << i)))
4812 continue;
4813 if (!possible_crtc->enabled) {
4814 crtc = possible_crtc;
4815 break;
4816 }
4817 if (!supported_crtc)
4818 supported_crtc = possible_crtc;
4819 }
4820
4821 /*
4822 * If we didn't find an unused CRTC, don't use any.
4823 */
4824 if (!crtc) {
4825 return NULL;
4826 }
4827
4828 encoder->crtc = crtc;
4829 connector->encoder = encoder;
4830 intel_encoder->load_detect_temp = true;
4831
4832 intel_crtc = to_intel_crtc(crtc);
4833 *dpms_mode = intel_crtc->dpms_mode;
4834
4835 if (!crtc->enabled) {
4836 if (!mode)
4837 mode = &load_detect_mode;
4838 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4839 } else {
4840 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4841 crtc_funcs = crtc->helper_private;
4842 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4843 }
4844
4845 /* Add this connector to the crtc */
4846 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4847 encoder_funcs->commit(encoder);
4848 }
4849 /* let the connector get through one full cycle before testing */
4850 intel_wait_for_vblank(dev, intel_crtc->pipe);
4851
4852 return crtc;
4853 }
4854
4855 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4856 struct drm_connector *connector, int dpms_mode)
4857 {
4858 struct drm_encoder *encoder = &intel_encoder->base;
4859 struct drm_device *dev = encoder->dev;
4860 struct drm_crtc *crtc = encoder->crtc;
4861 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4862 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4863
4864 if (intel_encoder->load_detect_temp) {
4865 encoder->crtc = NULL;
4866 connector->encoder = NULL;
4867 intel_encoder->load_detect_temp = false;
4868 crtc->enabled = drm_helper_crtc_in_use(crtc);
4869 drm_helper_disable_unused_functions(dev);
4870 }
4871
4872 /* Switch crtc and encoder back off if necessary */
4873 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4874 if (encoder->crtc == crtc)
4875 encoder_funcs->dpms(encoder, dpms_mode);
4876 crtc_funcs->dpms(crtc, dpms_mode);
4877 }
4878 }
4879
4880 /* Returns the clock of the currently programmed mode of the given pipe. */
4881 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4882 {
4883 struct drm_i915_private *dev_priv = dev->dev_private;
4884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4885 int pipe = intel_crtc->pipe;
4886 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4887 u32 fp;
4888 intel_clock_t clock;
4889
4890 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4891 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4892 else
4893 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4894
4895 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4896 if (IS_PINEVIEW(dev)) {
4897 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4898 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4899 } else {
4900 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4901 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4902 }
4903
4904 if (!IS_GEN2(dev)) {
4905 if (IS_PINEVIEW(dev))
4906 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4907 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4908 else
4909 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4910 DPLL_FPA01_P1_POST_DIV_SHIFT);
4911
4912 switch (dpll & DPLL_MODE_MASK) {
4913 case DPLLB_MODE_DAC_SERIAL:
4914 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4915 5 : 10;
4916 break;
4917 case DPLLB_MODE_LVDS:
4918 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4919 7 : 14;
4920 break;
4921 default:
4922 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4923 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4924 return 0;
4925 }
4926
4927 /* XXX: Handle the 100Mhz refclk */
4928 intel_clock(dev, 96000, &clock);
4929 } else {
4930 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4931
4932 if (is_lvds) {
4933 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4934 DPLL_FPA01_P1_POST_DIV_SHIFT);
4935 clock.p2 = 14;
4936
4937 if ((dpll & PLL_REF_INPUT_MASK) ==
4938 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4939 /* XXX: might not be 66MHz */
4940 intel_clock(dev, 66000, &clock);
4941 } else
4942 intel_clock(dev, 48000, &clock);
4943 } else {
4944 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4945 clock.p1 = 2;
4946 else {
4947 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4948 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4949 }
4950 if (dpll & PLL_P2_DIVIDE_BY_4)
4951 clock.p2 = 4;
4952 else
4953 clock.p2 = 2;
4954
4955 intel_clock(dev, 48000, &clock);
4956 }
4957 }
4958
4959 /* XXX: It would be nice to validate the clocks, but we can't reuse
4960 * i830PllIsValid() because it relies on the xf86_config connector
4961 * configuration being accurate, which it isn't necessarily.
4962 */
4963
4964 return clock.dot;
4965 }
4966
4967 /** Returns the currently programmed mode of the given pipe. */
4968 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4969 struct drm_crtc *crtc)
4970 {
4971 struct drm_i915_private *dev_priv = dev->dev_private;
4972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4973 int pipe = intel_crtc->pipe;
4974 struct drm_display_mode *mode;
4975 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4976 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4977 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4978 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4979
4980 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4981 if (!mode)
4982 return NULL;
4983
4984 mode->clock = intel_crtc_clock_get(dev, crtc);
4985 mode->hdisplay = (htot & 0xffff) + 1;
4986 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4987 mode->hsync_start = (hsync & 0xffff) + 1;
4988 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4989 mode->vdisplay = (vtot & 0xffff) + 1;
4990 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4991 mode->vsync_start = (vsync & 0xffff) + 1;
4992 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4993
4994 drm_mode_set_name(mode);
4995 drm_mode_set_crtcinfo(mode, 0);
4996
4997 return mode;
4998 }
4999
5000 #define GPU_IDLE_TIMEOUT 500 /* ms */
5001
5002 /* When this timer fires, we've been idle for awhile */
5003 static void intel_gpu_idle_timer(unsigned long arg)
5004 {
5005 struct drm_device *dev = (struct drm_device *)arg;
5006 drm_i915_private_t *dev_priv = dev->dev_private;
5007
5008 if (!list_empty(&dev_priv->mm.active_list)) {
5009 /* Still processing requests, so just re-arm the timer. */
5010 mod_timer(&dev_priv->idle_timer, jiffies +
5011 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5012 return;
5013 }
5014
5015 dev_priv->busy = false;
5016 queue_work(dev_priv->wq, &dev_priv->idle_work);
5017 }
5018
5019 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5020
5021 static void intel_crtc_idle_timer(unsigned long arg)
5022 {
5023 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5024 struct drm_crtc *crtc = &intel_crtc->base;
5025 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5026 struct intel_framebuffer *intel_fb;
5027
5028 intel_fb = to_intel_framebuffer(crtc->fb);
5029 if (intel_fb && intel_fb->obj->active) {
5030 /* The framebuffer is still being accessed by the GPU. */
5031 mod_timer(&intel_crtc->idle_timer, jiffies +
5032 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5033 return;
5034 }
5035
5036 intel_crtc->busy = false;
5037 queue_work(dev_priv->wq, &dev_priv->idle_work);
5038 }
5039
5040 static void intel_increase_pllclock(struct drm_crtc *crtc)
5041 {
5042 struct drm_device *dev = crtc->dev;
5043 drm_i915_private_t *dev_priv = dev->dev_private;
5044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5045 int pipe = intel_crtc->pipe;
5046 int dpll_reg = DPLL(pipe);
5047 int dpll;
5048
5049 if (HAS_PCH_SPLIT(dev))
5050 return;
5051
5052 if (!dev_priv->lvds_downclock_avail)
5053 return;
5054
5055 dpll = I915_READ(dpll_reg);
5056 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5057 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5058
5059 /* Unlock panel regs */
5060 I915_WRITE(PP_CONTROL,
5061 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5062
5063 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5064 I915_WRITE(dpll_reg, dpll);
5065 POSTING_READ(dpll_reg);
5066 intel_wait_for_vblank(dev, pipe);
5067
5068 dpll = I915_READ(dpll_reg);
5069 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5070 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5071
5072 /* ...and lock them again */
5073 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5074 }
5075
5076 /* Schedule downclock */
5077 mod_timer(&intel_crtc->idle_timer, jiffies +
5078 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5079 }
5080
5081 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5082 {
5083 struct drm_device *dev = crtc->dev;
5084 drm_i915_private_t *dev_priv = dev->dev_private;
5085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5086 int pipe = intel_crtc->pipe;
5087 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
5088 int dpll = I915_READ(dpll_reg);
5089
5090 if (HAS_PCH_SPLIT(dev))
5091 return;
5092
5093 if (!dev_priv->lvds_downclock_avail)
5094 return;
5095
5096 /*
5097 * Since this is called by a timer, we should never get here in
5098 * the manual case.
5099 */
5100 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5101 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5102
5103 /* Unlock panel regs */
5104 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5105 PANEL_UNLOCK_REGS);
5106
5107 dpll |= DISPLAY_RATE_SELECT_FPA1;
5108 I915_WRITE(dpll_reg, dpll);
5109 dpll = I915_READ(dpll_reg);
5110 intel_wait_for_vblank(dev, pipe);
5111 dpll = I915_READ(dpll_reg);
5112 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5113 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5114
5115 /* ...and lock them again */
5116 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5117 }
5118
5119 }
5120
5121 /**
5122 * intel_idle_update - adjust clocks for idleness
5123 * @work: work struct
5124 *
5125 * Either the GPU or display (or both) went idle. Check the busy status
5126 * here and adjust the CRTC and GPU clocks as necessary.
5127 */
5128 static void intel_idle_update(struct work_struct *work)
5129 {
5130 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5131 idle_work);
5132 struct drm_device *dev = dev_priv->dev;
5133 struct drm_crtc *crtc;
5134 struct intel_crtc *intel_crtc;
5135 int enabled = 0;
5136
5137 if (!i915_powersave)
5138 return;
5139
5140 mutex_lock(&dev->struct_mutex);
5141
5142 i915_update_gfx_val(dev_priv);
5143
5144 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5145 /* Skip inactive CRTCs */
5146 if (!crtc->fb)
5147 continue;
5148
5149 enabled++;
5150 intel_crtc = to_intel_crtc(crtc);
5151 if (!intel_crtc->busy)
5152 intel_decrease_pllclock(crtc);
5153 }
5154
5155 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
5156 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
5157 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
5158 }
5159
5160 mutex_unlock(&dev->struct_mutex);
5161 }
5162
5163 /**
5164 * intel_mark_busy - mark the GPU and possibly the display busy
5165 * @dev: drm device
5166 * @obj: object we're operating on
5167 *
5168 * Callers can use this function to indicate that the GPU is busy processing
5169 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5170 * buffer), we'll also mark the display as busy, so we know to increase its
5171 * clock frequency.
5172 */
5173 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5174 {
5175 drm_i915_private_t *dev_priv = dev->dev_private;
5176 struct drm_crtc *crtc = NULL;
5177 struct intel_framebuffer *intel_fb;
5178 struct intel_crtc *intel_crtc;
5179
5180 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5181 return;
5182
5183 if (!dev_priv->busy) {
5184 if (IS_I945G(dev) || IS_I945GM(dev)) {
5185 u32 fw_blc_self;
5186
5187 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5188 fw_blc_self = I915_READ(FW_BLC_SELF);
5189 fw_blc_self &= ~FW_BLC_SELF_EN;
5190 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5191 }
5192 dev_priv->busy = true;
5193 } else
5194 mod_timer(&dev_priv->idle_timer, jiffies +
5195 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5196
5197 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5198 if (!crtc->fb)
5199 continue;
5200
5201 intel_crtc = to_intel_crtc(crtc);
5202 intel_fb = to_intel_framebuffer(crtc->fb);
5203 if (intel_fb->obj == obj) {
5204 if (!intel_crtc->busy) {
5205 if (IS_I945G(dev) || IS_I945GM(dev)) {
5206 u32 fw_blc_self;
5207
5208 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5209 fw_blc_self = I915_READ(FW_BLC_SELF);
5210 fw_blc_self &= ~FW_BLC_SELF_EN;
5211 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5212 }
5213 /* Non-busy -> busy, upclock */
5214 intel_increase_pllclock(crtc);
5215 intel_crtc->busy = true;
5216 } else {
5217 /* Busy -> busy, put off timer */
5218 mod_timer(&intel_crtc->idle_timer, jiffies +
5219 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5220 }
5221 }
5222 }
5223 }
5224
5225 static void intel_crtc_destroy(struct drm_crtc *crtc)
5226 {
5227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5228 struct drm_device *dev = crtc->dev;
5229 struct intel_unpin_work *work;
5230 unsigned long flags;
5231
5232 spin_lock_irqsave(&dev->event_lock, flags);
5233 work = intel_crtc->unpin_work;
5234 intel_crtc->unpin_work = NULL;
5235 spin_unlock_irqrestore(&dev->event_lock, flags);
5236
5237 if (work) {
5238 cancel_work_sync(&work->work);
5239 kfree(work);
5240 }
5241
5242 drm_crtc_cleanup(crtc);
5243
5244 kfree(intel_crtc);
5245 }
5246
5247 static void intel_unpin_work_fn(struct work_struct *__work)
5248 {
5249 struct intel_unpin_work *work =
5250 container_of(__work, struct intel_unpin_work, work);
5251
5252 mutex_lock(&work->dev->struct_mutex);
5253 i915_gem_object_unpin(work->old_fb_obj);
5254 drm_gem_object_unreference(&work->pending_flip_obj->base);
5255 drm_gem_object_unreference(&work->old_fb_obj->base);
5256
5257 mutex_unlock(&work->dev->struct_mutex);
5258 kfree(work);
5259 }
5260
5261 static void do_intel_finish_page_flip(struct drm_device *dev,
5262 struct drm_crtc *crtc)
5263 {
5264 drm_i915_private_t *dev_priv = dev->dev_private;
5265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5266 struct intel_unpin_work *work;
5267 struct drm_i915_gem_object *obj;
5268 struct drm_pending_vblank_event *e;
5269 struct timeval tnow, tvbl;
5270 unsigned long flags;
5271
5272 /* Ignore early vblank irqs */
5273 if (intel_crtc == NULL)
5274 return;
5275
5276 do_gettimeofday(&tnow);
5277
5278 spin_lock_irqsave(&dev->event_lock, flags);
5279 work = intel_crtc->unpin_work;
5280 if (work == NULL || !work->pending) {
5281 spin_unlock_irqrestore(&dev->event_lock, flags);
5282 return;
5283 }
5284
5285 intel_crtc->unpin_work = NULL;
5286
5287 if (work->event) {
5288 e = work->event;
5289 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5290
5291 /* Called before vblank count and timestamps have
5292 * been updated for the vblank interval of flip
5293 * completion? Need to increment vblank count and
5294 * add one videorefresh duration to returned timestamp
5295 * to account for this. We assume this happened if we
5296 * get called over 0.9 frame durations after the last
5297 * timestamped vblank.
5298 *
5299 * This calculation can not be used with vrefresh rates
5300 * below 5Hz (10Hz to be on the safe side) without
5301 * promoting to 64 integers.
5302 */
5303 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5304 9 * crtc->framedur_ns) {
5305 e->event.sequence++;
5306 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5307 crtc->framedur_ns);
5308 }
5309
5310 e->event.tv_sec = tvbl.tv_sec;
5311 e->event.tv_usec = tvbl.tv_usec;
5312
5313 list_add_tail(&e->base.link,
5314 &e->base.file_priv->event_list);
5315 wake_up_interruptible(&e->base.file_priv->event_wait);
5316 }
5317
5318 drm_vblank_put(dev, intel_crtc->pipe);
5319
5320 spin_unlock_irqrestore(&dev->event_lock, flags);
5321
5322 obj = work->old_fb_obj;
5323
5324 atomic_clear_mask(1 << intel_crtc->plane,
5325 &obj->pending_flip.counter);
5326 if (atomic_read(&obj->pending_flip) == 0)
5327 wake_up(&dev_priv->pending_flip_queue);
5328
5329 schedule_work(&work->work);
5330
5331 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5332 }
5333
5334 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5335 {
5336 drm_i915_private_t *dev_priv = dev->dev_private;
5337 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5338
5339 do_intel_finish_page_flip(dev, crtc);
5340 }
5341
5342 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5343 {
5344 drm_i915_private_t *dev_priv = dev->dev_private;
5345 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5346
5347 do_intel_finish_page_flip(dev, crtc);
5348 }
5349
5350 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5351 {
5352 drm_i915_private_t *dev_priv = dev->dev_private;
5353 struct intel_crtc *intel_crtc =
5354 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5355 unsigned long flags;
5356
5357 spin_lock_irqsave(&dev->event_lock, flags);
5358 if (intel_crtc->unpin_work) {
5359 if ((++intel_crtc->unpin_work->pending) > 1)
5360 DRM_ERROR("Prepared flip multiple times\n");
5361 } else {
5362 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5363 }
5364 spin_unlock_irqrestore(&dev->event_lock, flags);
5365 }
5366
5367 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5368 struct drm_framebuffer *fb,
5369 struct drm_pending_vblank_event *event)
5370 {
5371 struct drm_device *dev = crtc->dev;
5372 struct drm_i915_private *dev_priv = dev->dev_private;
5373 struct intel_framebuffer *intel_fb;
5374 struct drm_i915_gem_object *obj;
5375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376 struct intel_unpin_work *work;
5377 unsigned long flags, offset;
5378 int pipe = intel_crtc->pipe;
5379 u32 pf, pipesrc;
5380 int ret;
5381
5382 work = kzalloc(sizeof *work, GFP_KERNEL);
5383 if (work == NULL)
5384 return -ENOMEM;
5385
5386 work->event = event;
5387 work->dev = crtc->dev;
5388 intel_fb = to_intel_framebuffer(crtc->fb);
5389 work->old_fb_obj = intel_fb->obj;
5390 INIT_WORK(&work->work, intel_unpin_work_fn);
5391
5392 /* We borrow the event spin lock for protecting unpin_work */
5393 spin_lock_irqsave(&dev->event_lock, flags);
5394 if (intel_crtc->unpin_work) {
5395 spin_unlock_irqrestore(&dev->event_lock, flags);
5396 kfree(work);
5397
5398 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5399 return -EBUSY;
5400 }
5401 intel_crtc->unpin_work = work;
5402 spin_unlock_irqrestore(&dev->event_lock, flags);
5403
5404 intel_fb = to_intel_framebuffer(fb);
5405 obj = intel_fb->obj;
5406
5407 mutex_lock(&dev->struct_mutex);
5408 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5409 if (ret)
5410 goto cleanup_work;
5411
5412 /* Reference the objects for the scheduled work. */
5413 drm_gem_object_reference(&work->old_fb_obj->base);
5414 drm_gem_object_reference(&obj->base);
5415
5416 crtc->fb = fb;
5417
5418 ret = drm_vblank_get(dev, intel_crtc->pipe);
5419 if (ret)
5420 goto cleanup_objs;
5421
5422 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5423 u32 flip_mask;
5424
5425 /* Can't queue multiple flips, so wait for the previous
5426 * one to finish before executing the next.
5427 */
5428 ret = BEGIN_LP_RING(2);
5429 if (ret)
5430 goto cleanup_objs;
5431
5432 if (intel_crtc->plane)
5433 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5434 else
5435 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5436 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5437 OUT_RING(MI_NOOP);
5438 ADVANCE_LP_RING();
5439 }
5440
5441 work->pending_flip_obj = obj;
5442
5443 work->enable_stall_check = true;
5444
5445 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5446 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5447
5448 ret = BEGIN_LP_RING(4);
5449 if (ret)
5450 goto cleanup_objs;
5451
5452 /* Block clients from rendering to the new back buffer until
5453 * the flip occurs and the object is no longer visible.
5454 */
5455 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5456
5457 switch (INTEL_INFO(dev)->gen) {
5458 case 2:
5459 OUT_RING(MI_DISPLAY_FLIP |
5460 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5461 OUT_RING(fb->pitch);
5462 OUT_RING(obj->gtt_offset + offset);
5463 OUT_RING(MI_NOOP);
5464 break;
5465
5466 case 3:
5467 OUT_RING(MI_DISPLAY_FLIP_I915 |
5468 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5469 OUT_RING(fb->pitch);
5470 OUT_RING(obj->gtt_offset + offset);
5471 OUT_RING(MI_NOOP);
5472 break;
5473
5474 case 4:
5475 case 5:
5476 /* i965+ uses the linear or tiled offsets from the
5477 * Display Registers (which do not change across a page-flip)
5478 * so we need only reprogram the base address.
5479 */
5480 OUT_RING(MI_DISPLAY_FLIP |
5481 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5482 OUT_RING(fb->pitch);
5483 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5484
5485 /* XXX Enabling the panel-fitter across page-flip is so far
5486 * untested on non-native modes, so ignore it for now.
5487 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5488 */
5489 pf = 0;
5490 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5491 OUT_RING(pf | pipesrc);
5492 break;
5493
5494 case 6:
5495 OUT_RING(MI_DISPLAY_FLIP |
5496 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5497 OUT_RING(fb->pitch | obj->tiling_mode);
5498 OUT_RING(obj->gtt_offset);
5499
5500 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5501 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5502 OUT_RING(pf | pipesrc);
5503 break;
5504 }
5505 ADVANCE_LP_RING();
5506
5507 mutex_unlock(&dev->struct_mutex);
5508
5509 trace_i915_flip_request(intel_crtc->plane, obj);
5510
5511 return 0;
5512
5513 cleanup_objs:
5514 drm_gem_object_unreference(&work->old_fb_obj->base);
5515 drm_gem_object_unreference(&obj->base);
5516 cleanup_work:
5517 mutex_unlock(&dev->struct_mutex);
5518
5519 spin_lock_irqsave(&dev->event_lock, flags);
5520 intel_crtc->unpin_work = NULL;
5521 spin_unlock_irqrestore(&dev->event_lock, flags);
5522
5523 kfree(work);
5524
5525 return ret;
5526 }
5527
5528 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5529 .dpms = intel_crtc_dpms,
5530 .mode_fixup = intel_crtc_mode_fixup,
5531 .mode_set = intel_crtc_mode_set,
5532 .mode_set_base = intel_pipe_set_base,
5533 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5534 .load_lut = intel_crtc_load_lut,
5535 .disable = intel_crtc_disable,
5536 };
5537
5538 static const struct drm_crtc_funcs intel_crtc_funcs = {
5539 .cursor_set = intel_crtc_cursor_set,
5540 .cursor_move = intel_crtc_cursor_move,
5541 .gamma_set = intel_crtc_gamma_set,
5542 .set_config = drm_crtc_helper_set_config,
5543 .destroy = intel_crtc_destroy,
5544 .page_flip = intel_crtc_page_flip,
5545 };
5546
5547 static void intel_sanitize_modesetting(struct drm_device *dev,
5548 int pipe, int plane)
5549 {
5550 struct drm_i915_private *dev_priv = dev->dev_private;
5551 u32 reg, val;
5552
5553 if (HAS_PCH_SPLIT(dev))
5554 return;
5555
5556 /* Who knows what state these registers were left in by the BIOS or
5557 * grub?
5558 *
5559 * If we leave the registers in a conflicting state (e.g. with the
5560 * display plane reading from the other pipe than the one we intend
5561 * to use) then when we attempt to teardown the active mode, we will
5562 * not disable the pipes and planes in the correct order -- leaving
5563 * a plane reading from a disabled pipe and possibly leading to
5564 * undefined behaviour.
5565 */
5566
5567 reg = DSPCNTR(plane);
5568 val = I915_READ(reg);
5569
5570 if ((val & DISPLAY_PLANE_ENABLE) == 0)
5571 return;
5572 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5573 return;
5574
5575 /* This display plane is active and attached to the other CPU pipe. */
5576 pipe = !pipe;
5577
5578 /* Disable the plane and wait for it to stop reading from the pipe. */
5579 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
5580 intel_flush_display_plane(dev, plane);
5581
5582 if (IS_GEN2(dev))
5583 intel_wait_for_vblank(dev, pipe);
5584
5585 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
5586 return;
5587
5588 /* Switch off the pipe. */
5589 reg = PIPECONF(pipe);
5590 val = I915_READ(reg);
5591 if (val & PIPECONF_ENABLE) {
5592 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
5593 intel_wait_for_pipe_off(dev, pipe);
5594 }
5595 }
5596
5597 static void intel_crtc_init(struct drm_device *dev, int pipe)
5598 {
5599 drm_i915_private_t *dev_priv = dev->dev_private;
5600 struct intel_crtc *intel_crtc;
5601 int i;
5602
5603 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5604 if (intel_crtc == NULL)
5605 return;
5606
5607 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5608
5609 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5610 for (i = 0; i < 256; i++) {
5611 intel_crtc->lut_r[i] = i;
5612 intel_crtc->lut_g[i] = i;
5613 intel_crtc->lut_b[i] = i;
5614 }
5615
5616 /* Swap pipes & planes for FBC on pre-965 */
5617 intel_crtc->pipe = pipe;
5618 intel_crtc->plane = pipe;
5619 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5620 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5621 intel_crtc->plane = !pipe;
5622 }
5623
5624 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5625 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5626 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5627 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5628
5629 intel_crtc->cursor_addr = 0;
5630 intel_crtc->dpms_mode = -1;
5631 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5632
5633 if (HAS_PCH_SPLIT(dev)) {
5634 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5635 intel_helper_funcs.commit = ironlake_crtc_commit;
5636 } else {
5637 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5638 intel_helper_funcs.commit = i9xx_crtc_commit;
5639 }
5640
5641 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5642
5643 intel_crtc->busy = false;
5644
5645 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5646 (unsigned long)intel_crtc);
5647
5648 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
5649 }
5650
5651 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5652 struct drm_file *file)
5653 {
5654 drm_i915_private_t *dev_priv = dev->dev_private;
5655 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5656 struct drm_mode_object *drmmode_obj;
5657 struct intel_crtc *crtc;
5658
5659 if (!dev_priv) {
5660 DRM_ERROR("called with no initialization\n");
5661 return -EINVAL;
5662 }
5663
5664 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5665 DRM_MODE_OBJECT_CRTC);
5666
5667 if (!drmmode_obj) {
5668 DRM_ERROR("no such CRTC id\n");
5669 return -EINVAL;
5670 }
5671
5672 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5673 pipe_from_crtc_id->pipe = crtc->pipe;
5674
5675 return 0;
5676 }
5677
5678 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5679 {
5680 struct intel_encoder *encoder;
5681 int index_mask = 0;
5682 int entry = 0;
5683
5684 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5685 if (type_mask & encoder->clone_mask)
5686 index_mask |= (1 << entry);
5687 entry++;
5688 }
5689
5690 return index_mask;
5691 }
5692
5693 static bool has_edp_a(struct drm_device *dev)
5694 {
5695 struct drm_i915_private *dev_priv = dev->dev_private;
5696
5697 if (!IS_MOBILE(dev))
5698 return false;
5699
5700 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
5701 return false;
5702
5703 if (IS_GEN5(dev) &&
5704 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
5705 return false;
5706
5707 return true;
5708 }
5709
5710 static void intel_setup_outputs(struct drm_device *dev)
5711 {
5712 struct drm_i915_private *dev_priv = dev->dev_private;
5713 struct intel_encoder *encoder;
5714 bool dpd_is_edp = false;
5715 bool has_lvds = false;
5716
5717 if (IS_MOBILE(dev) && !IS_I830(dev))
5718 has_lvds = intel_lvds_init(dev);
5719 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5720 /* disable the panel fitter on everything but LVDS */
5721 I915_WRITE(PFIT_CONTROL, 0);
5722 }
5723
5724 if (HAS_PCH_SPLIT(dev)) {
5725 dpd_is_edp = intel_dpd_is_edp(dev);
5726
5727 if (has_edp_a(dev))
5728 intel_dp_init(dev, DP_A);
5729
5730 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5731 intel_dp_init(dev, PCH_DP_D);
5732 }
5733
5734 intel_crt_init(dev);
5735
5736 if (HAS_PCH_SPLIT(dev)) {
5737 int found;
5738
5739 if (I915_READ(HDMIB) & PORT_DETECTED) {
5740 /* PCH SDVOB multiplex with HDMIB */
5741 found = intel_sdvo_init(dev, PCH_SDVOB);
5742 if (!found)
5743 intel_hdmi_init(dev, HDMIB);
5744 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5745 intel_dp_init(dev, PCH_DP_B);
5746 }
5747
5748 if (I915_READ(HDMIC) & PORT_DETECTED)
5749 intel_hdmi_init(dev, HDMIC);
5750
5751 if (I915_READ(HDMID) & PORT_DETECTED)
5752 intel_hdmi_init(dev, HDMID);
5753
5754 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5755 intel_dp_init(dev, PCH_DP_C);
5756
5757 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5758 intel_dp_init(dev, PCH_DP_D);
5759
5760 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5761 bool found = false;
5762
5763 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5764 DRM_DEBUG_KMS("probing SDVOB\n");
5765 found = intel_sdvo_init(dev, SDVOB);
5766 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5767 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5768 intel_hdmi_init(dev, SDVOB);
5769 }
5770
5771 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5772 DRM_DEBUG_KMS("probing DP_B\n");
5773 intel_dp_init(dev, DP_B);
5774 }
5775 }
5776
5777 /* Before G4X SDVOC doesn't have its own detect register */
5778
5779 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5780 DRM_DEBUG_KMS("probing SDVOC\n");
5781 found = intel_sdvo_init(dev, SDVOC);
5782 }
5783
5784 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5785
5786 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5787 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5788 intel_hdmi_init(dev, SDVOC);
5789 }
5790 if (SUPPORTS_INTEGRATED_DP(dev)) {
5791 DRM_DEBUG_KMS("probing DP_C\n");
5792 intel_dp_init(dev, DP_C);
5793 }
5794 }
5795
5796 if (SUPPORTS_INTEGRATED_DP(dev) &&
5797 (I915_READ(DP_D) & DP_DETECTED)) {
5798 DRM_DEBUG_KMS("probing DP_D\n");
5799 intel_dp_init(dev, DP_D);
5800 }
5801 } else if (IS_GEN2(dev))
5802 intel_dvo_init(dev);
5803
5804 if (SUPPORTS_TV(dev))
5805 intel_tv_init(dev);
5806
5807 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5808 encoder->base.possible_crtcs = encoder->crtc_mask;
5809 encoder->base.possible_clones =
5810 intel_encoder_clones(dev, encoder->clone_mask);
5811 }
5812
5813 intel_panel_setup_backlight(dev);
5814 }
5815
5816 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5817 {
5818 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5819
5820 drm_framebuffer_cleanup(fb);
5821 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
5822
5823 kfree(intel_fb);
5824 }
5825
5826 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5827 struct drm_file *file,
5828 unsigned int *handle)
5829 {
5830 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5831 struct drm_i915_gem_object *obj = intel_fb->obj;
5832
5833 return drm_gem_handle_create(file, &obj->base, handle);
5834 }
5835
5836 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5837 .destroy = intel_user_framebuffer_destroy,
5838 .create_handle = intel_user_framebuffer_create_handle,
5839 };
5840
5841 int intel_framebuffer_init(struct drm_device *dev,
5842 struct intel_framebuffer *intel_fb,
5843 struct drm_mode_fb_cmd *mode_cmd,
5844 struct drm_i915_gem_object *obj)
5845 {
5846 int ret;
5847
5848 if (obj->tiling_mode == I915_TILING_Y)
5849 return -EINVAL;
5850
5851 if (mode_cmd->pitch & 63)
5852 return -EINVAL;
5853
5854 switch (mode_cmd->bpp) {
5855 case 8:
5856 case 16:
5857 case 24:
5858 case 32:
5859 break;
5860 default:
5861 return -EINVAL;
5862 }
5863
5864 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5865 if (ret) {
5866 DRM_ERROR("framebuffer init failed %d\n", ret);
5867 return ret;
5868 }
5869
5870 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5871 intel_fb->obj = obj;
5872 return 0;
5873 }
5874
5875 static struct drm_framebuffer *
5876 intel_user_framebuffer_create(struct drm_device *dev,
5877 struct drm_file *filp,
5878 struct drm_mode_fb_cmd *mode_cmd)
5879 {
5880 struct drm_i915_gem_object *obj;
5881 struct intel_framebuffer *intel_fb;
5882 int ret;
5883
5884 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
5885 if (!obj)
5886 return ERR_PTR(-ENOENT);
5887
5888 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5889 if (!intel_fb)
5890 return ERR_PTR(-ENOMEM);
5891
5892 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5893 if (ret) {
5894 drm_gem_object_unreference_unlocked(&obj->base);
5895 kfree(intel_fb);
5896 return ERR_PTR(ret);
5897 }
5898
5899 return &intel_fb->base;
5900 }
5901
5902 static const struct drm_mode_config_funcs intel_mode_funcs = {
5903 .fb_create = intel_user_framebuffer_create,
5904 .output_poll_changed = intel_fb_output_poll_changed,
5905 };
5906
5907 static struct drm_i915_gem_object *
5908 intel_alloc_context_page(struct drm_device *dev)
5909 {
5910 struct drm_i915_gem_object *ctx;
5911 int ret;
5912
5913 ctx = i915_gem_alloc_object(dev, 4096);
5914 if (!ctx) {
5915 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5916 return NULL;
5917 }
5918
5919 mutex_lock(&dev->struct_mutex);
5920 ret = i915_gem_object_pin(ctx, 4096, true);
5921 if (ret) {
5922 DRM_ERROR("failed to pin power context: %d\n", ret);
5923 goto err_unref;
5924 }
5925
5926 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5927 if (ret) {
5928 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5929 goto err_unpin;
5930 }
5931 mutex_unlock(&dev->struct_mutex);
5932
5933 return ctx;
5934
5935 err_unpin:
5936 i915_gem_object_unpin(ctx);
5937 err_unref:
5938 drm_gem_object_unreference(&ctx->base);
5939 mutex_unlock(&dev->struct_mutex);
5940 return NULL;
5941 }
5942
5943 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5944 {
5945 struct drm_i915_private *dev_priv = dev->dev_private;
5946 u16 rgvswctl;
5947
5948 rgvswctl = I915_READ16(MEMSWCTL);
5949 if (rgvswctl & MEMCTL_CMD_STS) {
5950 DRM_DEBUG("gpu busy, RCS change rejected\n");
5951 return false; /* still busy with another command */
5952 }
5953
5954 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5955 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5956 I915_WRITE16(MEMSWCTL, rgvswctl);
5957 POSTING_READ16(MEMSWCTL);
5958
5959 rgvswctl |= MEMCTL_CMD_STS;
5960 I915_WRITE16(MEMSWCTL, rgvswctl);
5961
5962 return true;
5963 }
5964
5965 void ironlake_enable_drps(struct drm_device *dev)
5966 {
5967 struct drm_i915_private *dev_priv = dev->dev_private;
5968 u32 rgvmodectl = I915_READ(MEMMODECTL);
5969 u8 fmax, fmin, fstart, vstart;
5970
5971 /* Enable temp reporting */
5972 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5973 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5974
5975 /* 100ms RC evaluation intervals */
5976 I915_WRITE(RCUPEI, 100000);
5977 I915_WRITE(RCDNEI, 100000);
5978
5979 /* Set max/min thresholds to 90ms and 80ms respectively */
5980 I915_WRITE(RCBMAXAVG, 90000);
5981 I915_WRITE(RCBMINAVG, 80000);
5982
5983 I915_WRITE(MEMIHYST, 1);
5984
5985 /* Set up min, max, and cur for interrupt handling */
5986 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5987 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5988 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5989 MEMMODE_FSTART_SHIFT;
5990
5991 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5992 PXVFREQ_PX_SHIFT;
5993
5994 dev_priv->fmax = fmax; /* IPS callback will increase this */
5995 dev_priv->fstart = fstart;
5996
5997 dev_priv->max_delay = fstart;
5998 dev_priv->min_delay = fmin;
5999 dev_priv->cur_delay = fstart;
6000
6001 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6002 fmax, fmin, fstart);
6003
6004 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6005
6006 /*
6007 * Interrupts will be enabled in ironlake_irq_postinstall
6008 */
6009
6010 I915_WRITE(VIDSTART, vstart);
6011 POSTING_READ(VIDSTART);
6012
6013 rgvmodectl |= MEMMODE_SWMODE_EN;
6014 I915_WRITE(MEMMODECTL, rgvmodectl);
6015
6016 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6017 DRM_ERROR("stuck trying to change perf mode\n");
6018 msleep(1);
6019
6020 ironlake_set_drps(dev, fstart);
6021
6022 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6023 I915_READ(0x112e0);
6024 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6025 dev_priv->last_count2 = I915_READ(0x112f4);
6026 getrawmonotonic(&dev_priv->last_time2);
6027 }
6028
6029 void ironlake_disable_drps(struct drm_device *dev)
6030 {
6031 struct drm_i915_private *dev_priv = dev->dev_private;
6032 u16 rgvswctl = I915_READ16(MEMSWCTL);
6033
6034 /* Ack interrupts, disable EFC interrupt */
6035 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6036 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6037 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6038 I915_WRITE(DEIIR, DE_PCU_EVENT);
6039 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6040
6041 /* Go back to the starting frequency */
6042 ironlake_set_drps(dev, dev_priv->fstart);
6043 msleep(1);
6044 rgvswctl |= MEMCTL_CMD_STS;
6045 I915_WRITE(MEMSWCTL, rgvswctl);
6046 msleep(1);
6047
6048 }
6049
6050 void gen6_set_rps(struct drm_device *dev, u8 val)
6051 {
6052 struct drm_i915_private *dev_priv = dev->dev_private;
6053 u32 swreq;
6054
6055 swreq = (val & 0x3ff) << 25;
6056 I915_WRITE(GEN6_RPNSWREQ, swreq);
6057 }
6058
6059 void gen6_disable_rps(struct drm_device *dev)
6060 {
6061 struct drm_i915_private *dev_priv = dev->dev_private;
6062
6063 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6064 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6065 I915_WRITE(GEN6_PMIER, 0);
6066 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6067 }
6068
6069 static unsigned long intel_pxfreq(u32 vidfreq)
6070 {
6071 unsigned long freq;
6072 int div = (vidfreq & 0x3f0000) >> 16;
6073 int post = (vidfreq & 0x3000) >> 12;
6074 int pre = (vidfreq & 0x7);
6075
6076 if (!pre)
6077 return 0;
6078
6079 freq = ((div * 133333) / ((1<<post) * pre));
6080
6081 return freq;
6082 }
6083
6084 void intel_init_emon(struct drm_device *dev)
6085 {
6086 struct drm_i915_private *dev_priv = dev->dev_private;
6087 u32 lcfuse;
6088 u8 pxw[16];
6089 int i;
6090
6091 /* Disable to program */
6092 I915_WRITE(ECR, 0);
6093 POSTING_READ(ECR);
6094
6095 /* Program energy weights for various events */
6096 I915_WRITE(SDEW, 0x15040d00);
6097 I915_WRITE(CSIEW0, 0x007f0000);
6098 I915_WRITE(CSIEW1, 0x1e220004);
6099 I915_WRITE(CSIEW2, 0x04000004);
6100
6101 for (i = 0; i < 5; i++)
6102 I915_WRITE(PEW + (i * 4), 0);
6103 for (i = 0; i < 3; i++)
6104 I915_WRITE(DEW + (i * 4), 0);
6105
6106 /* Program P-state weights to account for frequency power adjustment */
6107 for (i = 0; i < 16; i++) {
6108 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6109 unsigned long freq = intel_pxfreq(pxvidfreq);
6110 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6111 PXVFREQ_PX_SHIFT;
6112 unsigned long val;
6113
6114 val = vid * vid;
6115 val *= (freq / 1000);
6116 val *= 255;
6117 val /= (127*127*900);
6118 if (val > 0xff)
6119 DRM_ERROR("bad pxval: %ld\n", val);
6120 pxw[i] = val;
6121 }
6122 /* Render standby states get 0 weight */
6123 pxw[14] = 0;
6124 pxw[15] = 0;
6125
6126 for (i = 0; i < 4; i++) {
6127 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6128 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6129 I915_WRITE(PXW + (i * 4), val);
6130 }
6131
6132 /* Adjust magic regs to magic values (more experimental results) */
6133 I915_WRITE(OGW0, 0);
6134 I915_WRITE(OGW1, 0);
6135 I915_WRITE(EG0, 0x00007f00);
6136 I915_WRITE(EG1, 0x0000000e);
6137 I915_WRITE(EG2, 0x000e0000);
6138 I915_WRITE(EG3, 0x68000300);
6139 I915_WRITE(EG4, 0x42000000);
6140 I915_WRITE(EG5, 0x00140031);
6141 I915_WRITE(EG6, 0);
6142 I915_WRITE(EG7, 0);
6143
6144 for (i = 0; i < 8; i++)
6145 I915_WRITE(PXWL + (i * 4), 0);
6146
6147 /* Enable PMON + select events */
6148 I915_WRITE(ECR, 0x80000019);
6149
6150 lcfuse = I915_READ(LCFUSE02);
6151
6152 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6153 }
6154
6155 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6156 {
6157 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6158 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6159 u32 pcu_mbox;
6160 int cur_freq, min_freq, max_freq;
6161 int i;
6162
6163 /* Here begins a magic sequence of register writes to enable
6164 * auto-downclocking.
6165 *
6166 * Perhaps there might be some value in exposing these to
6167 * userspace...
6168 */
6169 I915_WRITE(GEN6_RC_STATE, 0);
6170 __gen6_force_wake_get(dev_priv);
6171
6172 /* disable the counters and set deterministic thresholds */
6173 I915_WRITE(GEN6_RC_CONTROL, 0);
6174
6175 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6176 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6177 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6178 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6179 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6180
6181 for (i = 0; i < I915_NUM_RINGS; i++)
6182 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6183
6184 I915_WRITE(GEN6_RC_SLEEP, 0);
6185 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6186 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6187 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6188 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6189
6190 I915_WRITE(GEN6_RC_CONTROL,
6191 GEN6_RC_CTL_RC6p_ENABLE |
6192 GEN6_RC_CTL_RC6_ENABLE |
6193 GEN6_RC_CTL_EI_MODE(1) |
6194 GEN6_RC_CTL_HW_ENABLE);
6195
6196 I915_WRITE(GEN6_RPNSWREQ,
6197 GEN6_FREQUENCY(10) |
6198 GEN6_OFFSET(0) |
6199 GEN6_AGGRESSIVE_TURBO);
6200 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6201 GEN6_FREQUENCY(12));
6202
6203 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6204 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6205 18 << 24 |
6206 6 << 16);
6207 I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
6208 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
6209 I915_WRITE(GEN6_RP_UP_EI, 100000);
6210 I915_WRITE(GEN6_RP_DOWN_EI, 300000);
6211 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6212 I915_WRITE(GEN6_RP_CONTROL,
6213 GEN6_RP_MEDIA_TURBO |
6214 GEN6_RP_USE_NORMAL_FREQ |
6215 GEN6_RP_MEDIA_IS_GFX |
6216 GEN6_RP_ENABLE |
6217 GEN6_RP_UP_BUSY_MAX |
6218 GEN6_RP_DOWN_BUSY_MIN);
6219
6220 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6221 500))
6222 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6223
6224 I915_WRITE(GEN6_PCODE_DATA, 0);
6225 I915_WRITE(GEN6_PCODE_MAILBOX,
6226 GEN6_PCODE_READY |
6227 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6228 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6229 500))
6230 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6231
6232 min_freq = (rp_state_cap & 0xff0000) >> 16;
6233 max_freq = rp_state_cap & 0xff;
6234 cur_freq = (gt_perf_status & 0xff00) >> 8;
6235
6236 /* Check for overclock support */
6237 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6238 500))
6239 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6240 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6241 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6242 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6243 500))
6244 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6245 if (pcu_mbox & (1<<31)) { /* OC supported */
6246 max_freq = pcu_mbox & 0xff;
6247 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6248 }
6249
6250 /* In units of 100MHz */
6251 dev_priv->max_delay = max_freq;
6252 dev_priv->min_delay = min_freq;
6253 dev_priv->cur_delay = cur_freq;
6254
6255 /* requires MSI enabled */
6256 I915_WRITE(GEN6_PMIER,
6257 GEN6_PM_MBOX_EVENT |
6258 GEN6_PM_THERMAL_EVENT |
6259 GEN6_PM_RP_DOWN_TIMEOUT |
6260 GEN6_PM_RP_UP_THRESHOLD |
6261 GEN6_PM_RP_DOWN_THRESHOLD |
6262 GEN6_PM_RP_UP_EI_EXPIRED |
6263 GEN6_PM_RP_DOWN_EI_EXPIRED);
6264 I915_WRITE(GEN6_PMIMR, 0);
6265 /* enable all PM interrupts */
6266 I915_WRITE(GEN6_PMINTRMSK, 0);
6267
6268 __gen6_force_wake_put(dev_priv);
6269 }
6270
6271 void intel_enable_clock_gating(struct drm_device *dev)
6272 {
6273 struct drm_i915_private *dev_priv = dev->dev_private;
6274
6275 /*
6276 * Disable clock gating reported to work incorrectly according to the
6277 * specs, but enable as much else as we can.
6278 */
6279 if (HAS_PCH_SPLIT(dev)) {
6280 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6281
6282 if (IS_GEN5(dev)) {
6283 /* Required for FBC */
6284 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
6285 /* Required for CxSR */
6286 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6287
6288 I915_WRITE(PCH_3DCGDIS0,
6289 MARIUNIT_CLOCK_GATE_DISABLE |
6290 SVSMUNIT_CLOCK_GATE_DISABLE);
6291 I915_WRITE(PCH_3DCGDIS1,
6292 VFMUNIT_CLOCK_GATE_DISABLE);
6293 }
6294
6295 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6296
6297 /*
6298 * On Ibex Peak and Cougar Point, we need to disable clock
6299 * gating for the panel power sequencer or it will fail to
6300 * start up when no ports are active.
6301 */
6302 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6303
6304 /*
6305 * According to the spec the following bits should be set in
6306 * order to enable memory self-refresh
6307 * The bit 22/21 of 0x42004
6308 * The bit 5 of 0x42020
6309 * The bit 15 of 0x45000
6310 */
6311 if (IS_GEN5(dev)) {
6312 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6313 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6314 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6315 I915_WRITE(ILK_DSPCLK_GATE,
6316 (I915_READ(ILK_DSPCLK_GATE) |
6317 ILK_DPARB_CLK_GATE));
6318 I915_WRITE(DISP_ARB_CTL,
6319 (I915_READ(DISP_ARB_CTL) |
6320 DISP_FBC_WM_DIS));
6321 I915_WRITE(WM3_LP_ILK, 0);
6322 I915_WRITE(WM2_LP_ILK, 0);
6323 I915_WRITE(WM1_LP_ILK, 0);
6324 }
6325 /*
6326 * Based on the document from hardware guys the following bits
6327 * should be set unconditionally in order to enable FBC.
6328 * The bit 22 of 0x42000
6329 * The bit 22 of 0x42004
6330 * The bit 7,8,9 of 0x42020.
6331 */
6332 if (IS_IRONLAKE_M(dev)) {
6333 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6334 I915_READ(ILK_DISPLAY_CHICKEN1) |
6335 ILK_FBCQ_DIS);
6336 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6337 I915_READ(ILK_DISPLAY_CHICKEN2) |
6338 ILK_DPARB_GATE);
6339 I915_WRITE(ILK_DSPCLK_GATE,
6340 I915_READ(ILK_DSPCLK_GATE) |
6341 ILK_DPFC_DIS1 |
6342 ILK_DPFC_DIS2 |
6343 ILK_CLK_FBC);
6344 }
6345
6346 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6347 I915_READ(ILK_DISPLAY_CHICKEN2) |
6348 ILK_ELPIN_409_SELECT);
6349
6350 if (IS_GEN5(dev)) {
6351 I915_WRITE(_3D_CHICKEN2,
6352 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6353 _3D_CHICKEN2_WM_READ_PIPELINED);
6354 }
6355
6356 if (IS_GEN6(dev)) {
6357 I915_WRITE(WM3_LP_ILK, 0);
6358 I915_WRITE(WM2_LP_ILK, 0);
6359 I915_WRITE(WM1_LP_ILK, 0);
6360
6361 /*
6362 * According to the spec the following bits should be
6363 * set in order to enable memory self-refresh and fbc:
6364 * The bit21 and bit22 of 0x42000
6365 * The bit21 and bit22 of 0x42004
6366 * The bit5 and bit7 of 0x42020
6367 * The bit14 of 0x70180
6368 * The bit14 of 0x71180
6369 */
6370 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6371 I915_READ(ILK_DISPLAY_CHICKEN1) |
6372 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6373 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6374 I915_READ(ILK_DISPLAY_CHICKEN2) |
6375 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6376 I915_WRITE(ILK_DSPCLK_GATE,
6377 I915_READ(ILK_DSPCLK_GATE) |
6378 ILK_DPARB_CLK_GATE |
6379 ILK_DPFD_CLK_GATE);
6380
6381 I915_WRITE(DSPACNTR,
6382 I915_READ(DSPACNTR) |
6383 DISPPLANE_TRICKLE_FEED_DISABLE);
6384 I915_WRITE(DSPBCNTR,
6385 I915_READ(DSPBCNTR) |
6386 DISPPLANE_TRICKLE_FEED_DISABLE);
6387 }
6388 } else if (IS_G4X(dev)) {
6389 uint32_t dspclk_gate;
6390 I915_WRITE(RENCLK_GATE_D1, 0);
6391 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6392 GS_UNIT_CLOCK_GATE_DISABLE |
6393 CL_UNIT_CLOCK_GATE_DISABLE);
6394 I915_WRITE(RAMCLK_GATE_D, 0);
6395 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6396 OVRUNIT_CLOCK_GATE_DISABLE |
6397 OVCUNIT_CLOCK_GATE_DISABLE;
6398 if (IS_GM45(dev))
6399 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6400 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6401 } else if (IS_CRESTLINE(dev)) {
6402 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6403 I915_WRITE(RENCLK_GATE_D2, 0);
6404 I915_WRITE(DSPCLK_GATE_D, 0);
6405 I915_WRITE(RAMCLK_GATE_D, 0);
6406 I915_WRITE16(DEUC, 0);
6407 } else if (IS_BROADWATER(dev)) {
6408 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6409 I965_RCC_CLOCK_GATE_DISABLE |
6410 I965_RCPB_CLOCK_GATE_DISABLE |
6411 I965_ISC_CLOCK_GATE_DISABLE |
6412 I965_FBC_CLOCK_GATE_DISABLE);
6413 I915_WRITE(RENCLK_GATE_D2, 0);
6414 } else if (IS_GEN3(dev)) {
6415 u32 dstate = I915_READ(D_STATE);
6416
6417 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6418 DSTATE_DOT_CLOCK_GATING;
6419 I915_WRITE(D_STATE, dstate);
6420 } else if (IS_I85X(dev) || IS_I865G(dev)) {
6421 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6422 } else if (IS_I830(dev)) {
6423 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6424 }
6425 }
6426
6427 void intel_disable_clock_gating(struct drm_device *dev)
6428 {
6429 struct drm_i915_private *dev_priv = dev->dev_private;
6430
6431 if (dev_priv->renderctx) {
6432 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6433
6434 I915_WRITE(CCID, 0);
6435 POSTING_READ(CCID);
6436
6437 i915_gem_object_unpin(obj);
6438 drm_gem_object_unreference(&obj->base);
6439 dev_priv->renderctx = NULL;
6440 }
6441
6442 if (dev_priv->pwrctx) {
6443 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6444
6445 I915_WRITE(PWRCTXA, 0);
6446 POSTING_READ(PWRCTXA);
6447
6448 i915_gem_object_unpin(obj);
6449 drm_gem_object_unreference(&obj->base);
6450 dev_priv->pwrctx = NULL;
6451 }
6452 }
6453
6454 static void ironlake_disable_rc6(struct drm_device *dev)
6455 {
6456 struct drm_i915_private *dev_priv = dev->dev_private;
6457
6458 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
6459 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
6460 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
6461 10);
6462 POSTING_READ(CCID);
6463 I915_WRITE(PWRCTXA, 0);
6464 POSTING_READ(PWRCTXA);
6465 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6466 POSTING_READ(RSTDBYCTL);
6467 i915_gem_object_unpin(dev_priv->renderctx);
6468 drm_gem_object_unreference(&dev_priv->renderctx->base);
6469 dev_priv->renderctx = NULL;
6470 i915_gem_object_unpin(dev_priv->pwrctx);
6471 drm_gem_object_unreference(&dev_priv->pwrctx->base);
6472 dev_priv->pwrctx = NULL;
6473 }
6474
6475 void ironlake_enable_rc6(struct drm_device *dev)
6476 {
6477 struct drm_i915_private *dev_priv = dev->dev_private;
6478 int ret;
6479
6480 /*
6481 * GPU can automatically power down the render unit if given a page
6482 * to save state.
6483 */
6484 ret = BEGIN_LP_RING(6);
6485 if (ret) {
6486 ironlake_disable_rc6(dev);
6487 return;
6488 }
6489 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
6490 OUT_RING(MI_SET_CONTEXT);
6491 OUT_RING(dev_priv->renderctx->gtt_offset |
6492 MI_MM_SPACE_GTT |
6493 MI_SAVE_EXT_STATE_EN |
6494 MI_RESTORE_EXT_STATE_EN |
6495 MI_RESTORE_INHIBIT);
6496 OUT_RING(MI_SUSPEND_FLUSH);
6497 OUT_RING(MI_NOOP);
6498 OUT_RING(MI_FLUSH);
6499 ADVANCE_LP_RING();
6500
6501 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
6502 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6503 }
6504
6505 /* Set up chip specific display functions */
6506 static void intel_init_display(struct drm_device *dev)
6507 {
6508 struct drm_i915_private *dev_priv = dev->dev_private;
6509
6510 /* We always want a DPMS function */
6511 if (HAS_PCH_SPLIT(dev))
6512 dev_priv->display.dpms = ironlake_crtc_dpms;
6513 else
6514 dev_priv->display.dpms = i9xx_crtc_dpms;
6515
6516 if (I915_HAS_FBC(dev)) {
6517 if (HAS_PCH_SPLIT(dev)) {
6518 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6519 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6520 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6521 } else if (IS_GM45(dev)) {
6522 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6523 dev_priv->display.enable_fbc = g4x_enable_fbc;
6524 dev_priv->display.disable_fbc = g4x_disable_fbc;
6525 } else if (IS_CRESTLINE(dev)) {
6526 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6527 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6528 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6529 }
6530 /* 855GM needs testing */
6531 }
6532
6533 /* Returns the core display clock speed */
6534 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
6535 dev_priv->display.get_display_clock_speed =
6536 i945_get_display_clock_speed;
6537 else if (IS_I915G(dev))
6538 dev_priv->display.get_display_clock_speed =
6539 i915_get_display_clock_speed;
6540 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6541 dev_priv->display.get_display_clock_speed =
6542 i9xx_misc_get_display_clock_speed;
6543 else if (IS_I915GM(dev))
6544 dev_priv->display.get_display_clock_speed =
6545 i915gm_get_display_clock_speed;
6546 else if (IS_I865G(dev))
6547 dev_priv->display.get_display_clock_speed =
6548 i865_get_display_clock_speed;
6549 else if (IS_I85X(dev))
6550 dev_priv->display.get_display_clock_speed =
6551 i855_get_display_clock_speed;
6552 else /* 852, 830 */
6553 dev_priv->display.get_display_clock_speed =
6554 i830_get_display_clock_speed;
6555
6556 /* For FIFO watermark updates */
6557 if (HAS_PCH_SPLIT(dev)) {
6558 if (IS_GEN5(dev)) {
6559 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6560 dev_priv->display.update_wm = ironlake_update_wm;
6561 else {
6562 DRM_DEBUG_KMS("Failed to get proper latency. "
6563 "Disable CxSR\n");
6564 dev_priv->display.update_wm = NULL;
6565 }
6566 } else if (IS_GEN6(dev)) {
6567 if (SNB_READ_WM0_LATENCY()) {
6568 dev_priv->display.update_wm = sandybridge_update_wm;
6569 } else {
6570 DRM_DEBUG_KMS("Failed to read display plane latency. "
6571 "Disable CxSR\n");
6572 dev_priv->display.update_wm = NULL;
6573 }
6574 } else
6575 dev_priv->display.update_wm = NULL;
6576 } else if (IS_PINEVIEW(dev)) {
6577 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6578 dev_priv->is_ddr3,
6579 dev_priv->fsb_freq,
6580 dev_priv->mem_freq)) {
6581 DRM_INFO("failed to find known CxSR latency "
6582 "(found ddr%s fsb freq %d, mem freq %d), "
6583 "disabling CxSR\n",
6584 (dev_priv->is_ddr3 == 1) ? "3": "2",
6585 dev_priv->fsb_freq, dev_priv->mem_freq);
6586 /* Disable CxSR and never update its watermark again */
6587 pineview_disable_cxsr(dev);
6588 dev_priv->display.update_wm = NULL;
6589 } else
6590 dev_priv->display.update_wm = pineview_update_wm;
6591 } else if (IS_G4X(dev))
6592 dev_priv->display.update_wm = g4x_update_wm;
6593 else if (IS_GEN4(dev))
6594 dev_priv->display.update_wm = i965_update_wm;
6595 else if (IS_GEN3(dev)) {
6596 dev_priv->display.update_wm = i9xx_update_wm;
6597 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6598 } else if (IS_I85X(dev)) {
6599 dev_priv->display.update_wm = i9xx_update_wm;
6600 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6601 } else {
6602 dev_priv->display.update_wm = i830_update_wm;
6603 if (IS_845G(dev))
6604 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6605 else
6606 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6607 }
6608 }
6609
6610 /*
6611 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6612 * resume, or other times. This quirk makes sure that's the case for
6613 * affected systems.
6614 */
6615 static void quirk_pipea_force (struct drm_device *dev)
6616 {
6617 struct drm_i915_private *dev_priv = dev->dev_private;
6618
6619 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6620 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6621 }
6622
6623 struct intel_quirk {
6624 int device;
6625 int subsystem_vendor;
6626 int subsystem_device;
6627 void (*hook)(struct drm_device *dev);
6628 };
6629
6630 struct intel_quirk intel_quirks[] = {
6631 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6632 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6633 /* HP Mini needs pipe A force quirk (LP: #322104) */
6634 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6635
6636 /* Thinkpad R31 needs pipe A force quirk */
6637 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6638 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6639 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6640
6641 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6642 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6643 /* ThinkPad X40 needs pipe A force quirk */
6644
6645 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6646 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6647
6648 /* 855 & before need to leave pipe A & dpll A up */
6649 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6650 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6651 };
6652
6653 static void intel_init_quirks(struct drm_device *dev)
6654 {
6655 struct pci_dev *d = dev->pdev;
6656 int i;
6657
6658 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6659 struct intel_quirk *q = &intel_quirks[i];
6660
6661 if (d->device == q->device &&
6662 (d->subsystem_vendor == q->subsystem_vendor ||
6663 q->subsystem_vendor == PCI_ANY_ID) &&
6664 (d->subsystem_device == q->subsystem_device ||
6665 q->subsystem_device == PCI_ANY_ID))
6666 q->hook(dev);
6667 }
6668 }
6669
6670 /* Disable the VGA plane that we never use */
6671 static void i915_disable_vga(struct drm_device *dev)
6672 {
6673 struct drm_i915_private *dev_priv = dev->dev_private;
6674 u8 sr1;
6675 u32 vga_reg;
6676
6677 if (HAS_PCH_SPLIT(dev))
6678 vga_reg = CPU_VGACNTRL;
6679 else
6680 vga_reg = VGACNTRL;
6681
6682 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6683 outb(1, VGA_SR_INDEX);
6684 sr1 = inb(VGA_SR_DATA);
6685 outb(sr1 | 1<<5, VGA_SR_DATA);
6686 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6687 udelay(300);
6688
6689 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6690 POSTING_READ(vga_reg);
6691 }
6692
6693 void intel_modeset_init(struct drm_device *dev)
6694 {
6695 struct drm_i915_private *dev_priv = dev->dev_private;
6696 int i;
6697
6698 drm_mode_config_init(dev);
6699
6700 dev->mode_config.min_width = 0;
6701 dev->mode_config.min_height = 0;
6702
6703 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6704
6705 intel_init_quirks(dev);
6706
6707 intel_init_display(dev);
6708
6709 if (IS_GEN2(dev)) {
6710 dev->mode_config.max_width = 2048;
6711 dev->mode_config.max_height = 2048;
6712 } else if (IS_GEN3(dev)) {
6713 dev->mode_config.max_width = 4096;
6714 dev->mode_config.max_height = 4096;
6715 } else {
6716 dev->mode_config.max_width = 8192;
6717 dev->mode_config.max_height = 8192;
6718 }
6719 dev->mode_config.fb_base = dev->agp->base;
6720
6721 if (IS_MOBILE(dev) || !IS_GEN2(dev))
6722 dev_priv->num_pipe = 2;
6723 else
6724 dev_priv->num_pipe = 1;
6725 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6726 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6727
6728 for (i = 0; i < dev_priv->num_pipe; i++) {
6729 intel_crtc_init(dev, i);
6730 }
6731
6732 intel_setup_outputs(dev);
6733
6734 intel_enable_clock_gating(dev);
6735
6736 /* Just disable it once at startup */
6737 i915_disable_vga(dev);
6738
6739 if (IS_IRONLAKE_M(dev)) {
6740 ironlake_enable_drps(dev);
6741 intel_init_emon(dev);
6742 }
6743
6744 if (IS_GEN6(dev))
6745 gen6_enable_rps(dev_priv);
6746
6747 if (IS_IRONLAKE_M(dev)) {
6748 dev_priv->renderctx = intel_alloc_context_page(dev);
6749 if (!dev_priv->renderctx)
6750 goto skip_rc6;
6751 dev_priv->pwrctx = intel_alloc_context_page(dev);
6752 if (!dev_priv->pwrctx) {
6753 i915_gem_object_unpin(dev_priv->renderctx);
6754 drm_gem_object_unreference(&dev_priv->renderctx->base);
6755 dev_priv->renderctx = NULL;
6756 goto skip_rc6;
6757 }
6758 ironlake_enable_rc6(dev);
6759 }
6760
6761 skip_rc6:
6762 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6763 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6764 (unsigned long)dev);
6765
6766 intel_setup_overlay(dev);
6767 }
6768
6769 void intel_modeset_cleanup(struct drm_device *dev)
6770 {
6771 struct drm_i915_private *dev_priv = dev->dev_private;
6772 struct drm_crtc *crtc;
6773 struct intel_crtc *intel_crtc;
6774
6775 drm_kms_helper_poll_fini(dev);
6776 mutex_lock(&dev->struct_mutex);
6777
6778 intel_unregister_dsm_handler();
6779
6780
6781 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6782 /* Skip inactive CRTCs */
6783 if (!crtc->fb)
6784 continue;
6785
6786 intel_crtc = to_intel_crtc(crtc);
6787 intel_increase_pllclock(crtc);
6788 }
6789
6790 if (dev_priv->display.disable_fbc)
6791 dev_priv->display.disable_fbc(dev);
6792
6793 if (IS_IRONLAKE_M(dev))
6794 ironlake_disable_drps(dev);
6795 if (IS_GEN6(dev))
6796 gen6_disable_rps(dev);
6797
6798 if (IS_IRONLAKE_M(dev))
6799 ironlake_disable_rc6(dev);
6800
6801 mutex_unlock(&dev->struct_mutex);
6802
6803 /* Disable the irq before mode object teardown, for the irq might
6804 * enqueue unpin/hotplug work. */
6805 drm_irq_uninstall(dev);
6806 cancel_work_sync(&dev_priv->hotplug_work);
6807
6808 /* Shut off idle work before the crtcs get freed. */
6809 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6810 intel_crtc = to_intel_crtc(crtc);
6811 del_timer_sync(&intel_crtc->idle_timer);
6812 }
6813 del_timer_sync(&dev_priv->idle_timer);
6814 cancel_work_sync(&dev_priv->idle_work);
6815
6816 drm_mode_config_cleanup(dev);
6817 }
6818
6819 /*
6820 * Return which encoder is currently attached for connector.
6821 */
6822 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6823 {
6824 return &intel_attached_encoder(connector)->base;
6825 }
6826
6827 void intel_connector_attach_encoder(struct intel_connector *connector,
6828 struct intel_encoder *encoder)
6829 {
6830 connector->encoder = encoder;
6831 drm_mode_connector_attach_encoder(&connector->base,
6832 &encoder->base);
6833 }
6834
6835 /*
6836 * set vga decode state - true == enable VGA decode
6837 */
6838 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6839 {
6840 struct drm_i915_private *dev_priv = dev->dev_private;
6841 u16 gmch_ctrl;
6842
6843 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6844 if (state)
6845 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6846 else
6847 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6848 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6849 return 0;
6850 }
6851
6852 #ifdef CONFIG_DEBUG_FS
6853 #include <linux/seq_file.h>
6854
6855 struct intel_display_error_state {
6856 struct intel_cursor_error_state {
6857 u32 control;
6858 u32 position;
6859 u32 base;
6860 u32 size;
6861 } cursor[2];
6862
6863 struct intel_pipe_error_state {
6864 u32 conf;
6865 u32 source;
6866
6867 u32 htotal;
6868 u32 hblank;
6869 u32 hsync;
6870 u32 vtotal;
6871 u32 vblank;
6872 u32 vsync;
6873 } pipe[2];
6874
6875 struct intel_plane_error_state {
6876 u32 control;
6877 u32 stride;
6878 u32 size;
6879 u32 pos;
6880 u32 addr;
6881 u32 surface;
6882 u32 tile_offset;
6883 } plane[2];
6884 };
6885
6886 struct intel_display_error_state *
6887 intel_display_capture_error_state(struct drm_device *dev)
6888 {
6889 drm_i915_private_t *dev_priv = dev->dev_private;
6890 struct intel_display_error_state *error;
6891 int i;
6892
6893 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6894 if (error == NULL)
6895 return NULL;
6896
6897 for (i = 0; i < 2; i++) {
6898 error->cursor[i].control = I915_READ(CURCNTR(i));
6899 error->cursor[i].position = I915_READ(CURPOS(i));
6900 error->cursor[i].base = I915_READ(CURBASE(i));
6901
6902 error->plane[i].control = I915_READ(DSPCNTR(i));
6903 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6904 error->plane[i].size = I915_READ(DSPSIZE(i));
6905 error->plane[i].pos= I915_READ(DSPPOS(i));
6906 error->plane[i].addr = I915_READ(DSPADDR(i));
6907 if (INTEL_INFO(dev)->gen >= 4) {
6908 error->plane[i].surface = I915_READ(DSPSURF(i));
6909 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6910 }
6911
6912 error->pipe[i].conf = I915_READ(PIPECONF(i));
6913 error->pipe[i].source = I915_READ(PIPESRC(i));
6914 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6915 error->pipe[i].hblank = I915_READ(HBLANK(i));
6916 error->pipe[i].hsync = I915_READ(HSYNC(i));
6917 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6918 error->pipe[i].vblank = I915_READ(VBLANK(i));
6919 error->pipe[i].vsync = I915_READ(VSYNC(i));
6920 }
6921
6922 return error;
6923 }
6924
6925 void
6926 intel_display_print_error_state(struct seq_file *m,
6927 struct drm_device *dev,
6928 struct intel_display_error_state *error)
6929 {
6930 int i;
6931
6932 for (i = 0; i < 2; i++) {
6933 seq_printf(m, "Pipe [%d]:\n", i);
6934 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6935 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6936 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6937 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6938 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6939 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6940 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6941 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6942
6943 seq_printf(m, "Plane [%d]:\n", i);
6944 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6945 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6946 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6947 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6948 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6949 if (INTEL_INFO(dev)->gen >= 4) {
6950 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6951 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6952 }
6953
6954 seq_printf(m, "Cursor [%d]:\n", i);
6955 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6956 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6957 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6958 }
6959 }
6960 #endif
kernel source for telekom puls (alcatel/mediatek)