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Merge tag 'drm-intel-next-2017-03-06' of git://anongit.freedesktop.org/git/drm-intel...
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / gpu / drm / i915 / i915_irq.c
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
34 #include <drm/drmP.h>
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "intel_drv.h"
39
40 /**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
50 };
51
52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
54 };
55
56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
58 };
59
60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
61 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
66 };
67
68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
69 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
70 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
74 };
75
76 static const u32 hpd_spt[HPD_NUM_PINS] = {
77 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
78 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
82 };
83
84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
85 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
91 };
92
93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
94 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
100 };
101
102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
109 };
110
111 /* BXT hpd list */
112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
116 };
117
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
127 } while (0)
128
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
137 } while (0)
138
139 /*
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
141 */
142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
143 i915_reg_t reg)
144 {
145 u32 val = I915_READ(reg);
146
147 if (val == 0)
148 return;
149
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg), val);
152 I915_WRITE(reg, 0xffffffff);
153 POSTING_READ(reg);
154 I915_WRITE(reg, 0xffffffff);
155 POSTING_READ(reg);
156 }
157
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
163 } while (0)
164
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
170 } while (0)
171
172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
173 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
174
175 /* For display hotplug interrupt */
176 static inline void
177 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
178 uint32_t mask,
179 uint32_t bits)
180 {
181 uint32_t val;
182
183 lockdep_assert_held(&dev_priv->irq_lock);
184 WARN_ON(bits & ~mask);
185
186 val = I915_READ(PORT_HOTPLUG_EN);
187 val &= ~mask;
188 val |= bits;
189 I915_WRITE(PORT_HOTPLUG_EN, val);
190 }
191
192 /**
193 * i915_hotplug_interrupt_update - update hotplug interrupt enable
194 * @dev_priv: driver private
195 * @mask: bits to update
196 * @bits: bits to enable
197 * NOTE: the HPD enable bits are modified both inside and outside
198 * of an interrupt context. To avoid that read-modify-write cycles
199 * interfer, these bits are protected by a spinlock. Since this
200 * function is usually not called from a context where the lock is
201 * held already, this function acquires the lock itself. A non-locking
202 * version is also available.
203 */
204 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
205 uint32_t mask,
206 uint32_t bits)
207 {
208 spin_lock_irq(&dev_priv->irq_lock);
209 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
210 spin_unlock_irq(&dev_priv->irq_lock);
211 }
212
213 /**
214 * ilk_update_display_irq - update DEIMR
215 * @dev_priv: driver private
216 * @interrupt_mask: mask of interrupt bits to update
217 * @enabled_irq_mask: mask of interrupt bits to enable
218 */
219 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
220 uint32_t interrupt_mask,
221 uint32_t enabled_irq_mask)
222 {
223 uint32_t new_val;
224
225 lockdep_assert_held(&dev_priv->irq_lock);
226
227 WARN_ON(enabled_irq_mask & ~interrupt_mask);
228
229 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
230 return;
231
232 new_val = dev_priv->irq_mask;
233 new_val &= ~interrupt_mask;
234 new_val |= (~enabled_irq_mask & interrupt_mask);
235
236 if (new_val != dev_priv->irq_mask) {
237 dev_priv->irq_mask = new_val;
238 I915_WRITE(DEIMR, dev_priv->irq_mask);
239 POSTING_READ(DEIMR);
240 }
241 }
242
243 /**
244 * ilk_update_gt_irq - update GTIMR
245 * @dev_priv: driver private
246 * @interrupt_mask: mask of interrupt bits to update
247 * @enabled_irq_mask: mask of interrupt bits to enable
248 */
249 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
250 uint32_t interrupt_mask,
251 uint32_t enabled_irq_mask)
252 {
253 lockdep_assert_held(&dev_priv->irq_lock);
254
255 WARN_ON(enabled_irq_mask & ~interrupt_mask);
256
257 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
258 return;
259
260 dev_priv->gt_irq_mask &= ~interrupt_mask;
261 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
262 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
263 }
264
265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
266 {
267 ilk_update_gt_irq(dev_priv, mask, mask);
268 POSTING_READ_FW(GTIMR);
269 }
270
271 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
272 {
273 ilk_update_gt_irq(dev_priv, mask, 0);
274 }
275
276 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
277 {
278 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
279 }
280
281 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
282 {
283 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
284 }
285
286 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
287 {
288 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
289 }
290
291 /**
292 * snb_update_pm_irq - update GEN6_PMIMR
293 * @dev_priv: driver private
294 * @interrupt_mask: mask of interrupt bits to update
295 * @enabled_irq_mask: mask of interrupt bits to enable
296 */
297 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
298 uint32_t interrupt_mask,
299 uint32_t enabled_irq_mask)
300 {
301 uint32_t new_val;
302
303 WARN_ON(enabled_irq_mask & ~interrupt_mask);
304
305 lockdep_assert_held(&dev_priv->irq_lock);
306
307 new_val = dev_priv->pm_imr;
308 new_val &= ~interrupt_mask;
309 new_val |= (~enabled_irq_mask & interrupt_mask);
310
311 if (new_val != dev_priv->pm_imr) {
312 dev_priv->pm_imr = new_val;
313 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
314 POSTING_READ(gen6_pm_imr(dev_priv));
315 }
316 }
317
318 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
319 {
320 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
321 return;
322
323 snb_update_pm_irq(dev_priv, mask, mask);
324 }
325
326 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
327 {
328 snb_update_pm_irq(dev_priv, mask, 0);
329 }
330
331 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
332 {
333 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
334 return;
335
336 __gen6_mask_pm_irq(dev_priv, mask);
337 }
338
339 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
340 {
341 i915_reg_t reg = gen6_pm_iir(dev_priv);
342
343 lockdep_assert_held(&dev_priv->irq_lock);
344
345 I915_WRITE(reg, reset_mask);
346 I915_WRITE(reg, reset_mask);
347 POSTING_READ(reg);
348 }
349
350 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
351 {
352 lockdep_assert_held(&dev_priv->irq_lock);
353
354 dev_priv->pm_ier |= enable_mask;
355 I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
356 gen6_unmask_pm_irq(dev_priv, enable_mask);
357 /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
358 }
359
360 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
361 {
362 lockdep_assert_held(&dev_priv->irq_lock);
363
364 dev_priv->pm_ier &= ~disable_mask;
365 __gen6_mask_pm_irq(dev_priv, disable_mask);
366 I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
367 /* though a barrier is missing here, but don't really need a one */
368 }
369
370 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
371 {
372 spin_lock_irq(&dev_priv->irq_lock);
373 gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
374 dev_priv->rps.pm_iir = 0;
375 spin_unlock_irq(&dev_priv->irq_lock);
376 }
377
378 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
379 {
380 if (READ_ONCE(dev_priv->rps.interrupts_enabled))
381 return;
382
383 spin_lock_irq(&dev_priv->irq_lock);
384 WARN_ON_ONCE(dev_priv->rps.pm_iir);
385 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
386 dev_priv->rps.interrupts_enabled = true;
387 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
388
389 spin_unlock_irq(&dev_priv->irq_lock);
390 }
391
392 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
393 {
394 return (mask & ~dev_priv->rps.pm_intr_keep);
395 }
396
397 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
398 {
399 if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
400 return;
401
402 spin_lock_irq(&dev_priv->irq_lock);
403 dev_priv->rps.interrupts_enabled = false;
404
405 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
406
407 gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
408
409 spin_unlock_irq(&dev_priv->irq_lock);
410 synchronize_irq(dev_priv->drm.irq);
411
412 /* Now that we will not be generating any more work, flush any
413 * outsanding tasks. As we are called on the RPS idle path,
414 * we will reset the GPU to minimum frequencies, so the current
415 * state of the worker can be discarded.
416 */
417 cancel_work_sync(&dev_priv->rps.work);
418 gen6_reset_rps_interrupts(dev_priv);
419 }
420
421 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
422 {
423 spin_lock_irq(&dev_priv->irq_lock);
424 gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
425 spin_unlock_irq(&dev_priv->irq_lock);
426 }
427
428 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
429 {
430 spin_lock_irq(&dev_priv->irq_lock);
431 if (!dev_priv->guc.interrupts_enabled) {
432 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
433 dev_priv->pm_guc_events);
434 dev_priv->guc.interrupts_enabled = true;
435 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
436 }
437 spin_unlock_irq(&dev_priv->irq_lock);
438 }
439
440 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
441 {
442 spin_lock_irq(&dev_priv->irq_lock);
443 dev_priv->guc.interrupts_enabled = false;
444
445 gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
446
447 spin_unlock_irq(&dev_priv->irq_lock);
448 synchronize_irq(dev_priv->drm.irq);
449
450 gen9_reset_guc_interrupts(dev_priv);
451 }
452
453 /**
454 * bdw_update_port_irq - update DE port interrupt
455 * @dev_priv: driver private
456 * @interrupt_mask: mask of interrupt bits to update
457 * @enabled_irq_mask: mask of interrupt bits to enable
458 */
459 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
460 uint32_t interrupt_mask,
461 uint32_t enabled_irq_mask)
462 {
463 uint32_t new_val;
464 uint32_t old_val;
465
466 lockdep_assert_held(&dev_priv->irq_lock);
467
468 WARN_ON(enabled_irq_mask & ~interrupt_mask);
469
470 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
471 return;
472
473 old_val = I915_READ(GEN8_DE_PORT_IMR);
474
475 new_val = old_val;
476 new_val &= ~interrupt_mask;
477 new_val |= (~enabled_irq_mask & interrupt_mask);
478
479 if (new_val != old_val) {
480 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
481 POSTING_READ(GEN8_DE_PORT_IMR);
482 }
483 }
484
485 /**
486 * bdw_update_pipe_irq - update DE pipe interrupt
487 * @dev_priv: driver private
488 * @pipe: pipe whose interrupt to update
489 * @interrupt_mask: mask of interrupt bits to update
490 * @enabled_irq_mask: mask of interrupt bits to enable
491 */
492 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
493 enum pipe pipe,
494 uint32_t interrupt_mask,
495 uint32_t enabled_irq_mask)
496 {
497 uint32_t new_val;
498
499 lockdep_assert_held(&dev_priv->irq_lock);
500
501 WARN_ON(enabled_irq_mask & ~interrupt_mask);
502
503 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
504 return;
505
506 new_val = dev_priv->de_irq_mask[pipe];
507 new_val &= ~interrupt_mask;
508 new_val |= (~enabled_irq_mask & interrupt_mask);
509
510 if (new_val != dev_priv->de_irq_mask[pipe]) {
511 dev_priv->de_irq_mask[pipe] = new_val;
512 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
513 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
514 }
515 }
516
517 /**
518 * ibx_display_interrupt_update - update SDEIMR
519 * @dev_priv: driver private
520 * @interrupt_mask: mask of interrupt bits to update
521 * @enabled_irq_mask: mask of interrupt bits to enable
522 */
523 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
524 uint32_t interrupt_mask,
525 uint32_t enabled_irq_mask)
526 {
527 uint32_t sdeimr = I915_READ(SDEIMR);
528 sdeimr &= ~interrupt_mask;
529 sdeimr |= (~enabled_irq_mask & interrupt_mask);
530
531 WARN_ON(enabled_irq_mask & ~interrupt_mask);
532
533 lockdep_assert_held(&dev_priv->irq_lock);
534
535 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
536 return;
537
538 I915_WRITE(SDEIMR, sdeimr);
539 POSTING_READ(SDEIMR);
540 }
541
542 static void
543 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
544 u32 enable_mask, u32 status_mask)
545 {
546 i915_reg_t reg = PIPESTAT(pipe);
547 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
548
549 lockdep_assert_held(&dev_priv->irq_lock);
550 WARN_ON(!intel_irqs_enabled(dev_priv));
551
552 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
553 status_mask & ~PIPESTAT_INT_STATUS_MASK,
554 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
555 pipe_name(pipe), enable_mask, status_mask))
556 return;
557
558 if ((pipestat & enable_mask) == enable_mask)
559 return;
560
561 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
562
563 /* Enable the interrupt, clear any pending status */
564 pipestat |= enable_mask | status_mask;
565 I915_WRITE(reg, pipestat);
566 POSTING_READ(reg);
567 }
568
569 static void
570 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
571 u32 enable_mask, u32 status_mask)
572 {
573 i915_reg_t reg = PIPESTAT(pipe);
574 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
575
576 lockdep_assert_held(&dev_priv->irq_lock);
577 WARN_ON(!intel_irqs_enabled(dev_priv));
578
579 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
580 status_mask & ~PIPESTAT_INT_STATUS_MASK,
581 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
582 pipe_name(pipe), enable_mask, status_mask))
583 return;
584
585 if ((pipestat & enable_mask) == 0)
586 return;
587
588 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
589
590 pipestat &= ~enable_mask;
591 I915_WRITE(reg, pipestat);
592 POSTING_READ(reg);
593 }
594
595 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
596 {
597 u32 enable_mask = status_mask << 16;
598
599 /*
600 * On pipe A we don't support the PSR interrupt yet,
601 * on pipe B and C the same bit MBZ.
602 */
603 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
604 return 0;
605 /*
606 * On pipe B and C we don't support the PSR interrupt yet, on pipe
607 * A the same bit is for perf counters which we don't use either.
608 */
609 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
610 return 0;
611
612 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
613 SPRITE0_FLIP_DONE_INT_EN_VLV |
614 SPRITE1_FLIP_DONE_INT_EN_VLV);
615 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
616 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
617 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
618 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
619
620 return enable_mask;
621 }
622
623 void
624 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
625 u32 status_mask)
626 {
627 u32 enable_mask;
628
629 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
630 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
631 status_mask);
632 else
633 enable_mask = status_mask << 16;
634 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
635 }
636
637 void
638 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
639 u32 status_mask)
640 {
641 u32 enable_mask;
642
643 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
644 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
645 status_mask);
646 else
647 enable_mask = status_mask << 16;
648 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
649 }
650
651 /**
652 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
653 * @dev_priv: i915 device private
654 */
655 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
656 {
657 if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
658 return;
659
660 spin_lock_irq(&dev_priv->irq_lock);
661
662 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
663 if (INTEL_GEN(dev_priv) >= 4)
664 i915_enable_pipestat(dev_priv, PIPE_A,
665 PIPE_LEGACY_BLC_EVENT_STATUS);
666
667 spin_unlock_irq(&dev_priv->irq_lock);
668 }
669
670 /*
671 * This timing diagram depicts the video signal in and
672 * around the vertical blanking period.
673 *
674 * Assumptions about the fictitious mode used in this example:
675 * vblank_start >= 3
676 * vsync_start = vblank_start + 1
677 * vsync_end = vblank_start + 2
678 * vtotal = vblank_start + 3
679 *
680 * start of vblank:
681 * latch double buffered registers
682 * increment frame counter (ctg+)
683 * generate start of vblank interrupt (gen4+)
684 * |
685 * | frame start:
686 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
687 * | may be shifted forward 1-3 extra lines via PIPECONF
688 * | |
689 * | | start of vsync:
690 * | | generate vsync interrupt
691 * | | |
692 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
693 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
694 * ----va---> <-----------------vb--------------------> <--------va-------------
695 * | | <----vs-----> |
696 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
697 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
698 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
699 * | | |
700 * last visible pixel first visible pixel
701 * | increment frame counter (gen3/4)
702 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
703 *
704 * x = horizontal active
705 * _ = horizontal blanking
706 * hs = horizontal sync
707 * va = vertical active
708 * vb = vertical blanking
709 * vs = vertical sync
710 * vbs = vblank_start (number)
711 *
712 * Summary:
713 * - most events happen at the start of horizontal sync
714 * - frame start happens at the start of horizontal blank, 1-4 lines
715 * (depending on PIPECONF settings) after the start of vblank
716 * - gen3/4 pixel and frame counter are synchronized with the start
717 * of horizontal active on the first line of vertical active
718 */
719
720 /* Called from drm generic code, passed a 'crtc', which
721 * we use as a pipe index
722 */
723 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
724 {
725 struct drm_i915_private *dev_priv = to_i915(dev);
726 i915_reg_t high_frame, low_frame;
727 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
728 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
729 pipe);
730 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
731
732 htotal = mode->crtc_htotal;
733 hsync_start = mode->crtc_hsync_start;
734 vbl_start = mode->crtc_vblank_start;
735 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
736 vbl_start = DIV_ROUND_UP(vbl_start, 2);
737
738 /* Convert to pixel count */
739 vbl_start *= htotal;
740
741 /* Start of vblank event occurs at start of hsync */
742 vbl_start -= htotal - hsync_start;
743
744 high_frame = PIPEFRAME(pipe);
745 low_frame = PIPEFRAMEPIXEL(pipe);
746
747 /*
748 * High & low register fields aren't synchronized, so make sure
749 * we get a low value that's stable across two reads of the high
750 * register.
751 */
752 do {
753 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
754 low = I915_READ(low_frame);
755 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
756 } while (high1 != high2);
757
758 high1 >>= PIPE_FRAME_HIGH_SHIFT;
759 pixel = low & PIPE_PIXEL_MASK;
760 low >>= PIPE_FRAME_LOW_SHIFT;
761
762 /*
763 * The frame counter increments at beginning of active.
764 * Cook up a vblank counter by also checking the pixel
765 * counter against vblank start.
766 */
767 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
768 }
769
770 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
771 {
772 struct drm_i915_private *dev_priv = to_i915(dev);
773
774 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
775 }
776
777 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
778 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
779 {
780 struct drm_device *dev = crtc->base.dev;
781 struct drm_i915_private *dev_priv = to_i915(dev);
782 const struct drm_display_mode *mode = &crtc->base.hwmode;
783 enum pipe pipe = crtc->pipe;
784 int position, vtotal;
785
786 if (!crtc->active)
787 return -1;
788
789 vtotal = mode->crtc_vtotal;
790 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
791 vtotal /= 2;
792
793 if (IS_GEN2(dev_priv))
794 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
795 else
796 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
797
798 /*
799 * On HSW, the DSL reg (0x70000) appears to return 0 if we
800 * read it just before the start of vblank. So try it again
801 * so we don't accidentally end up spanning a vblank frame
802 * increment, causing the pipe_update_end() code to squak at us.
803 *
804 * The nature of this problem means we can't simply check the ISR
805 * bit and return the vblank start value; nor can we use the scanline
806 * debug register in the transcoder as it appears to have the same
807 * problem. We may need to extend this to include other platforms,
808 * but so far testing only shows the problem on HSW.
809 */
810 if (HAS_DDI(dev_priv) && !position) {
811 int i, temp;
812
813 for (i = 0; i < 100; i++) {
814 udelay(1);
815 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
816 DSL_LINEMASK_GEN3;
817 if (temp != position) {
818 position = temp;
819 break;
820 }
821 }
822 }
823
824 /*
825 * See update_scanline_offset() for the details on the
826 * scanline_offset adjustment.
827 */
828 return (position + crtc->scanline_offset) % vtotal;
829 }
830
831 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
832 unsigned int flags, int *vpos, int *hpos,
833 ktime_t *stime, ktime_t *etime,
834 const struct drm_display_mode *mode)
835 {
836 struct drm_i915_private *dev_priv = to_i915(dev);
837 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
838 pipe);
839 int position;
840 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
841 bool in_vbl = true;
842 int ret = 0;
843 unsigned long irqflags;
844
845 if (WARN_ON(!mode->crtc_clock)) {
846 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
847 "pipe %c\n", pipe_name(pipe));
848 return 0;
849 }
850
851 htotal = mode->crtc_htotal;
852 hsync_start = mode->crtc_hsync_start;
853 vtotal = mode->crtc_vtotal;
854 vbl_start = mode->crtc_vblank_start;
855 vbl_end = mode->crtc_vblank_end;
856
857 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
858 vbl_start = DIV_ROUND_UP(vbl_start, 2);
859 vbl_end /= 2;
860 vtotal /= 2;
861 }
862
863 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
864
865 /*
866 * Lock uncore.lock, as we will do multiple timing critical raw
867 * register reads, potentially with preemption disabled, so the
868 * following code must not block on uncore.lock.
869 */
870 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
871
872 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
873
874 /* Get optional system timestamp before query. */
875 if (stime)
876 *stime = ktime_get();
877
878 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
879 /* No obvious pixelcount register. Only query vertical
880 * scanout position from Display scan line register.
881 */
882 position = __intel_get_crtc_scanline(intel_crtc);
883 } else {
884 /* Have access to pixelcount since start of frame.
885 * We can split this into vertical and horizontal
886 * scanout position.
887 */
888 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
889
890 /* convert to pixel counts */
891 vbl_start *= htotal;
892 vbl_end *= htotal;
893 vtotal *= htotal;
894
895 /*
896 * In interlaced modes, the pixel counter counts all pixels,
897 * so one field will have htotal more pixels. In order to avoid
898 * the reported position from jumping backwards when the pixel
899 * counter is beyond the length of the shorter field, just
900 * clamp the position the length of the shorter field. This
901 * matches how the scanline counter based position works since
902 * the scanline counter doesn't count the two half lines.
903 */
904 if (position >= vtotal)
905 position = vtotal - 1;
906
907 /*
908 * Start of vblank interrupt is triggered at start of hsync,
909 * just prior to the first active line of vblank. However we
910 * consider lines to start at the leading edge of horizontal
911 * active. So, should we get here before we've crossed into
912 * the horizontal active of the first line in vblank, we would
913 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
914 * always add htotal-hsync_start to the current pixel position.
915 */
916 position = (position + htotal - hsync_start) % vtotal;
917 }
918
919 /* Get optional system timestamp after query. */
920 if (etime)
921 *etime = ktime_get();
922
923 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
924
925 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
926
927 in_vbl = position >= vbl_start && position < vbl_end;
928
929 /*
930 * While in vblank, position will be negative
931 * counting up towards 0 at vbl_end. And outside
932 * vblank, position will be positive counting
933 * up since vbl_end.
934 */
935 if (position >= vbl_start)
936 position -= vbl_end;
937 else
938 position += vtotal - vbl_end;
939
940 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
941 *vpos = position;
942 *hpos = 0;
943 } else {
944 *vpos = position / htotal;
945 *hpos = position - (*vpos * htotal);
946 }
947
948 /* In vblank? */
949 if (in_vbl)
950 ret |= DRM_SCANOUTPOS_IN_VBLANK;
951
952 return ret;
953 }
954
955 int intel_get_crtc_scanline(struct intel_crtc *crtc)
956 {
957 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
958 unsigned long irqflags;
959 int position;
960
961 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
962 position = __intel_get_crtc_scanline(crtc);
963 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
964
965 return position;
966 }
967
968 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
969 int *max_error,
970 struct timeval *vblank_time,
971 unsigned flags)
972 {
973 struct drm_i915_private *dev_priv = to_i915(dev);
974 struct intel_crtc *crtc;
975
976 if (pipe >= INTEL_INFO(dev_priv)->num_pipes) {
977 DRM_ERROR("Invalid crtc %u\n", pipe);
978 return -EINVAL;
979 }
980
981 /* Get drm_crtc to timestamp: */
982 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
983 if (crtc == NULL) {
984 DRM_ERROR("Invalid crtc %u\n", pipe);
985 return -EINVAL;
986 }
987
988 if (!crtc->base.hwmode.crtc_clock) {
989 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
990 return -EBUSY;
991 }
992
993 /* Helper routine in DRM core does all the work: */
994 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
995 vblank_time, flags,
996 &crtc->base.hwmode);
997 }
998
999 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
1000 {
1001 u32 busy_up, busy_down, max_avg, min_avg;
1002 u8 new_delay;
1003
1004 spin_lock(&mchdev_lock);
1005
1006 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1007
1008 new_delay = dev_priv->ips.cur_delay;
1009
1010 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1011 busy_up = I915_READ(RCPREVBSYTUPAVG);
1012 busy_down = I915_READ(RCPREVBSYTDNAVG);
1013 max_avg = I915_READ(RCBMAXAVG);
1014 min_avg = I915_READ(RCBMINAVG);
1015
1016 /* Handle RCS change request from hw */
1017 if (busy_up > max_avg) {
1018 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1019 new_delay = dev_priv->ips.cur_delay - 1;
1020 if (new_delay < dev_priv->ips.max_delay)
1021 new_delay = dev_priv->ips.max_delay;
1022 } else if (busy_down < min_avg) {
1023 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1024 new_delay = dev_priv->ips.cur_delay + 1;
1025 if (new_delay > dev_priv->ips.min_delay)
1026 new_delay = dev_priv->ips.min_delay;
1027 }
1028
1029 if (ironlake_set_drps(dev_priv, new_delay))
1030 dev_priv->ips.cur_delay = new_delay;
1031
1032 spin_unlock(&mchdev_lock);
1033
1034 return;
1035 }
1036
1037 static void notify_ring(struct intel_engine_cs *engine)
1038 {
1039 struct drm_i915_gem_request *rq = NULL;
1040 struct intel_wait *wait;
1041
1042 atomic_inc(&engine->irq_count);
1043 set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
1044
1045 spin_lock(&engine->breadcrumbs.irq_lock);
1046 wait = engine->breadcrumbs.irq_wait;
1047 if (wait) {
1048 /* We use a callback from the dma-fence to submit
1049 * requests after waiting on our own requests. To
1050 * ensure minimum delay in queuing the next request to
1051 * hardware, signal the fence now rather than wait for
1052 * the signaler to be woken up. We still wake up the
1053 * waiter in order to handle the irq-seqno coherency
1054 * issues (we may receive the interrupt before the
1055 * seqno is written, see __i915_request_irq_complete())
1056 * and to handle coalescing of multiple seqno updates
1057 * and many waiters.
1058 */
1059 if (i915_seqno_passed(intel_engine_get_seqno(engine),
1060 wait->seqno))
1061 rq = i915_gem_request_get(wait->request);
1062
1063 wake_up_process(wait->tsk);
1064 } else {
1065 __intel_engine_disarm_breadcrumbs(engine);
1066 }
1067 spin_unlock(&engine->breadcrumbs.irq_lock);
1068
1069 if (rq) {
1070 dma_fence_signal(&rq->fence);
1071 i915_gem_request_put(rq);
1072 }
1073
1074 trace_intel_engine_notify(engine, wait);
1075 }
1076
1077 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1078 struct intel_rps_ei *ei)
1079 {
1080 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1081 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1082 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1083 }
1084
1085 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1086 const struct intel_rps_ei *old,
1087 const struct intel_rps_ei *now,
1088 int threshold)
1089 {
1090 u64 time, c0;
1091 unsigned int mul = 100;
1092
1093 if (old->cz_clock == 0)
1094 return false;
1095
1096 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1097 mul <<= 8;
1098
1099 time = now->cz_clock - old->cz_clock;
1100 time *= threshold * dev_priv->czclk_freq;
1101
1102 /* Workload can be split between render + media, e.g. SwapBuffers
1103 * being blitted in X after being rendered in mesa. To account for
1104 * this we need to combine both engines into our activity counter.
1105 */
1106 c0 = now->render_c0 - old->render_c0;
1107 c0 += now->media_c0 - old->media_c0;
1108 c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1109
1110 return c0 >= time;
1111 }
1112
1113 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1114 {
1115 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1116 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1117 }
1118
1119 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1120 {
1121 struct intel_rps_ei now;
1122 u32 events = 0;
1123
1124 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1125 return 0;
1126
1127 vlv_c0_read(dev_priv, &now);
1128 if (now.cz_clock == 0)
1129 return 0;
1130
1131 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1132 if (!vlv_c0_above(dev_priv,
1133 &dev_priv->rps.down_ei, &now,
1134 dev_priv->rps.down_threshold))
1135 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1136 dev_priv->rps.down_ei = now;
1137 }
1138
1139 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1140 if (vlv_c0_above(dev_priv,
1141 &dev_priv->rps.up_ei, &now,
1142 dev_priv->rps.up_threshold))
1143 events |= GEN6_PM_RP_UP_THRESHOLD;
1144 dev_priv->rps.up_ei = now;
1145 }
1146
1147 return events;
1148 }
1149
1150 static bool any_waiters(struct drm_i915_private *dev_priv)
1151 {
1152 struct intel_engine_cs *engine;
1153 enum intel_engine_id id;
1154
1155 for_each_engine(engine, dev_priv, id)
1156 if (intel_engine_has_waiter(engine))
1157 return true;
1158
1159 return false;
1160 }
1161
1162 static void gen6_pm_rps_work(struct work_struct *work)
1163 {
1164 struct drm_i915_private *dev_priv =
1165 container_of(work, struct drm_i915_private, rps.work);
1166 bool client_boost;
1167 int new_delay, adj, min, max;
1168 u32 pm_iir;
1169
1170 spin_lock_irq(&dev_priv->irq_lock);
1171 /* Speed up work cancelation during disabling rps interrupts. */
1172 if (!dev_priv->rps.interrupts_enabled) {
1173 spin_unlock_irq(&dev_priv->irq_lock);
1174 return;
1175 }
1176
1177 pm_iir = dev_priv->rps.pm_iir;
1178 dev_priv->rps.pm_iir = 0;
1179 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1180 gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1181 client_boost = dev_priv->rps.client_boost;
1182 dev_priv->rps.client_boost = false;
1183 spin_unlock_irq(&dev_priv->irq_lock);
1184
1185 /* Make sure we didn't queue anything we're not going to process. */
1186 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1187
1188 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1189 return;
1190
1191 mutex_lock(&dev_priv->rps.hw_lock);
1192
1193 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1194
1195 adj = dev_priv->rps.last_adj;
1196 new_delay = dev_priv->rps.cur_freq;
1197 min = dev_priv->rps.min_freq_softlimit;
1198 max = dev_priv->rps.max_freq_softlimit;
1199 if (client_boost || any_waiters(dev_priv))
1200 max = dev_priv->rps.max_freq;
1201 if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1202 new_delay = dev_priv->rps.boost_freq;
1203 adj = 0;
1204 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1205 if (adj > 0)
1206 adj *= 2;
1207 else /* CHV needs even encode values */
1208 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1209
1210 if (new_delay >= dev_priv->rps.max_freq_softlimit)
1211 adj = 0;
1212 } else if (client_boost || any_waiters(dev_priv)) {
1213 adj = 0;
1214 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1215 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1216 new_delay = dev_priv->rps.efficient_freq;
1217 else if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1218 new_delay = dev_priv->rps.min_freq_softlimit;
1219 adj = 0;
1220 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1221 if (adj < 0)
1222 adj *= 2;
1223 else /* CHV needs even encode values */
1224 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1225
1226 if (new_delay <= dev_priv->rps.min_freq_softlimit)
1227 adj = 0;
1228 } else { /* unknown event */
1229 adj = 0;
1230 }
1231
1232 dev_priv->rps.last_adj = adj;
1233
1234 /* sysfs frequency interfaces may have snuck in while servicing the
1235 * interrupt
1236 */
1237 new_delay += adj;
1238 new_delay = clamp_t(int, new_delay, min, max);
1239
1240 if (intel_set_rps(dev_priv, new_delay)) {
1241 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1242 dev_priv->rps.last_adj = 0;
1243 }
1244
1245 mutex_unlock(&dev_priv->rps.hw_lock);
1246 }
1247
1248
1249 /**
1250 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1251 * occurred.
1252 * @work: workqueue struct
1253 *
1254 * Doesn't actually do anything except notify userspace. As a consequence of
1255 * this event, userspace should try to remap the bad rows since statistically
1256 * it is likely the same row is more likely to go bad again.
1257 */
1258 static void ivybridge_parity_work(struct work_struct *work)
1259 {
1260 struct drm_i915_private *dev_priv =
1261 container_of(work, struct drm_i915_private, l3_parity.error_work);
1262 u32 error_status, row, bank, subbank;
1263 char *parity_event[6];
1264 uint32_t misccpctl;
1265 uint8_t slice = 0;
1266
1267 /* We must turn off DOP level clock gating to access the L3 registers.
1268 * In order to prevent a get/put style interface, acquire struct mutex
1269 * any time we access those registers.
1270 */
1271 mutex_lock(&dev_priv->drm.struct_mutex);
1272
1273 /* If we've screwed up tracking, just let the interrupt fire again */
1274 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1275 goto out;
1276
1277 misccpctl = I915_READ(GEN7_MISCCPCTL);
1278 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1279 POSTING_READ(GEN7_MISCCPCTL);
1280
1281 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1282 i915_reg_t reg;
1283
1284 slice--;
1285 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1286 break;
1287
1288 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1289
1290 reg = GEN7_L3CDERRST1(slice);
1291
1292 error_status = I915_READ(reg);
1293 row = GEN7_PARITY_ERROR_ROW(error_status);
1294 bank = GEN7_PARITY_ERROR_BANK(error_status);
1295 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1296
1297 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1298 POSTING_READ(reg);
1299
1300 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1301 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1302 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1303 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1304 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1305 parity_event[5] = NULL;
1306
1307 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1308 KOBJ_CHANGE, parity_event);
1309
1310 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1311 slice, row, bank, subbank);
1312
1313 kfree(parity_event[4]);
1314 kfree(parity_event[3]);
1315 kfree(parity_event[2]);
1316 kfree(parity_event[1]);
1317 }
1318
1319 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1320
1321 out:
1322 WARN_ON(dev_priv->l3_parity.which_slice);
1323 spin_lock_irq(&dev_priv->irq_lock);
1324 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1325 spin_unlock_irq(&dev_priv->irq_lock);
1326
1327 mutex_unlock(&dev_priv->drm.struct_mutex);
1328 }
1329
1330 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1331 u32 iir)
1332 {
1333 if (!HAS_L3_DPF(dev_priv))
1334 return;
1335
1336 spin_lock(&dev_priv->irq_lock);
1337 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1338 spin_unlock(&dev_priv->irq_lock);
1339
1340 iir &= GT_PARITY_ERROR(dev_priv);
1341 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1342 dev_priv->l3_parity.which_slice |= 1 << 1;
1343
1344 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1345 dev_priv->l3_parity.which_slice |= 1 << 0;
1346
1347 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1348 }
1349
1350 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1351 u32 gt_iir)
1352 {
1353 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1354 notify_ring(dev_priv->engine[RCS]);
1355 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1356 notify_ring(dev_priv->engine[VCS]);
1357 }
1358
1359 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1360 u32 gt_iir)
1361 {
1362 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1363 notify_ring(dev_priv->engine[RCS]);
1364 if (gt_iir & GT_BSD_USER_INTERRUPT)
1365 notify_ring(dev_priv->engine[VCS]);
1366 if (gt_iir & GT_BLT_USER_INTERRUPT)
1367 notify_ring(dev_priv->engine[BCS]);
1368
1369 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1370 GT_BSD_CS_ERROR_INTERRUPT |
1371 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1372 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1373
1374 if (gt_iir & GT_PARITY_ERROR(dev_priv))
1375 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1376 }
1377
1378 static __always_inline void
1379 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1380 {
1381 if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1382 notify_ring(engine);
1383
1384 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
1385 set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1386 tasklet_hi_schedule(&engine->irq_tasklet);
1387 }
1388 }
1389
1390 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1391 u32 master_ctl,
1392 u32 gt_iir[4])
1393 {
1394 irqreturn_t ret = IRQ_NONE;
1395
1396 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1397 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1398 if (gt_iir[0]) {
1399 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1400 ret = IRQ_HANDLED;
1401 } else
1402 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1403 }
1404
1405 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1406 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1407 if (gt_iir[1]) {
1408 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1409 ret = IRQ_HANDLED;
1410 } else
1411 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1412 }
1413
1414 if (master_ctl & GEN8_GT_VECS_IRQ) {
1415 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1416 if (gt_iir[3]) {
1417 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1418 ret = IRQ_HANDLED;
1419 } else
1420 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1421 }
1422
1423 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1424 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1425 if (gt_iir[2] & (dev_priv->pm_rps_events |
1426 dev_priv->pm_guc_events)) {
1427 I915_WRITE_FW(GEN8_GT_IIR(2),
1428 gt_iir[2] & (dev_priv->pm_rps_events |
1429 dev_priv->pm_guc_events));
1430 ret = IRQ_HANDLED;
1431 } else
1432 DRM_ERROR("The master control interrupt lied (PM)!\n");
1433 }
1434
1435 return ret;
1436 }
1437
1438 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1439 u32 gt_iir[4])
1440 {
1441 if (gt_iir[0]) {
1442 gen8_cs_irq_handler(dev_priv->engine[RCS],
1443 gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1444 gen8_cs_irq_handler(dev_priv->engine[BCS],
1445 gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1446 }
1447
1448 if (gt_iir[1]) {
1449 gen8_cs_irq_handler(dev_priv->engine[VCS],
1450 gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1451 gen8_cs_irq_handler(dev_priv->engine[VCS2],
1452 gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1453 }
1454
1455 if (gt_iir[3])
1456 gen8_cs_irq_handler(dev_priv->engine[VECS],
1457 gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1458
1459 if (gt_iir[2] & dev_priv->pm_rps_events)
1460 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1461
1462 if (gt_iir[2] & dev_priv->pm_guc_events)
1463 gen9_guc_irq_handler(dev_priv, gt_iir[2]);
1464 }
1465
1466 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1467 {
1468 switch (port) {
1469 case PORT_A:
1470 return val & PORTA_HOTPLUG_LONG_DETECT;
1471 case PORT_B:
1472 return val & PORTB_HOTPLUG_LONG_DETECT;
1473 case PORT_C:
1474 return val & PORTC_HOTPLUG_LONG_DETECT;
1475 default:
1476 return false;
1477 }
1478 }
1479
1480 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1481 {
1482 switch (port) {
1483 case PORT_E:
1484 return val & PORTE_HOTPLUG_LONG_DETECT;
1485 default:
1486 return false;
1487 }
1488 }
1489
1490 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1491 {
1492 switch (port) {
1493 case PORT_A:
1494 return val & PORTA_HOTPLUG_LONG_DETECT;
1495 case PORT_B:
1496 return val & PORTB_HOTPLUG_LONG_DETECT;
1497 case PORT_C:
1498 return val & PORTC_HOTPLUG_LONG_DETECT;
1499 case PORT_D:
1500 return val & PORTD_HOTPLUG_LONG_DETECT;
1501 default:
1502 return false;
1503 }
1504 }
1505
1506 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1507 {
1508 switch (port) {
1509 case PORT_A:
1510 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1511 default:
1512 return false;
1513 }
1514 }
1515
1516 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1517 {
1518 switch (port) {
1519 case PORT_B:
1520 return val & PORTB_HOTPLUG_LONG_DETECT;
1521 case PORT_C:
1522 return val & PORTC_HOTPLUG_LONG_DETECT;
1523 case PORT_D:
1524 return val & PORTD_HOTPLUG_LONG_DETECT;
1525 default:
1526 return false;
1527 }
1528 }
1529
1530 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1531 {
1532 switch (port) {
1533 case PORT_B:
1534 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1535 case PORT_C:
1536 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1537 case PORT_D:
1538 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1539 default:
1540 return false;
1541 }
1542 }
1543
1544 /*
1545 * Get a bit mask of pins that have triggered, and which ones may be long.
1546 * This can be called multiple times with the same masks to accumulate
1547 * hotplug detection results from several registers.
1548 *
1549 * Note that the caller is expected to zero out the masks initially.
1550 */
1551 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1552 u32 hotplug_trigger, u32 dig_hotplug_reg,
1553 const u32 hpd[HPD_NUM_PINS],
1554 bool long_pulse_detect(enum port port, u32 val))
1555 {
1556 enum port port;
1557 int i;
1558
1559 for_each_hpd_pin(i) {
1560 if ((hpd[i] & hotplug_trigger) == 0)
1561 continue;
1562
1563 *pin_mask |= BIT(i);
1564
1565 if (!intel_hpd_pin_to_port(i, &port))
1566 continue;
1567
1568 if (long_pulse_detect(port, dig_hotplug_reg))
1569 *long_mask |= BIT(i);
1570 }
1571
1572 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1573 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1574
1575 }
1576
1577 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1578 {
1579 wake_up_all(&dev_priv->gmbus_wait_queue);
1580 }
1581
1582 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1583 {
1584 wake_up_all(&dev_priv->gmbus_wait_queue);
1585 }
1586
1587 #if defined(CONFIG_DEBUG_FS)
1588 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1589 enum pipe pipe,
1590 uint32_t crc0, uint32_t crc1,
1591 uint32_t crc2, uint32_t crc3,
1592 uint32_t crc4)
1593 {
1594 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1595 struct intel_pipe_crc_entry *entry;
1596 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1597 struct drm_driver *driver = dev_priv->drm.driver;
1598 uint32_t crcs[5];
1599 int head, tail;
1600
1601 spin_lock(&pipe_crc->lock);
1602 if (pipe_crc->source) {
1603 if (!pipe_crc->entries) {
1604 spin_unlock(&pipe_crc->lock);
1605 DRM_DEBUG_KMS("spurious interrupt\n");
1606 return;
1607 }
1608
1609 head = pipe_crc->head;
1610 tail = pipe_crc->tail;
1611
1612 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1613 spin_unlock(&pipe_crc->lock);
1614 DRM_ERROR("CRC buffer overflowing\n");
1615 return;
1616 }
1617
1618 entry = &pipe_crc->entries[head];
1619
1620 entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe);
1621 entry->crc[0] = crc0;
1622 entry->crc[1] = crc1;
1623 entry->crc[2] = crc2;
1624 entry->crc[3] = crc3;
1625 entry->crc[4] = crc4;
1626
1627 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1628 pipe_crc->head = head;
1629
1630 spin_unlock(&pipe_crc->lock);
1631
1632 wake_up_interruptible(&pipe_crc->wq);
1633 } else {
1634 /*
1635 * For some not yet identified reason, the first CRC is
1636 * bonkers. So let's just wait for the next vblank and read
1637 * out the buggy result.
1638 *
1639 * On CHV sometimes the second CRC is bonkers as well, so
1640 * don't trust that one either.
1641 */
1642 if (pipe_crc->skipped == 0 ||
1643 (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
1644 pipe_crc->skipped++;
1645 spin_unlock(&pipe_crc->lock);
1646 return;
1647 }
1648 spin_unlock(&pipe_crc->lock);
1649 crcs[0] = crc0;
1650 crcs[1] = crc1;
1651 crcs[2] = crc2;
1652 crcs[3] = crc3;
1653 crcs[4] = crc4;
1654 drm_crtc_add_crc_entry(&crtc->base, true,
1655 drm_accurate_vblank_count(&crtc->base),
1656 crcs);
1657 }
1658 }
1659 #else
1660 static inline void
1661 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1662 enum pipe pipe,
1663 uint32_t crc0, uint32_t crc1,
1664 uint32_t crc2, uint32_t crc3,
1665 uint32_t crc4) {}
1666 #endif
1667
1668
1669 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1670 enum pipe pipe)
1671 {
1672 display_pipe_crc_irq_handler(dev_priv, pipe,
1673 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1674 0, 0, 0, 0);
1675 }
1676
1677 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1678 enum pipe pipe)
1679 {
1680 display_pipe_crc_irq_handler(dev_priv, pipe,
1681 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1682 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1683 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1684 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1685 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1686 }
1687
1688 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1689 enum pipe pipe)
1690 {
1691 uint32_t res1, res2;
1692
1693 if (INTEL_GEN(dev_priv) >= 3)
1694 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1695 else
1696 res1 = 0;
1697
1698 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1699 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1700 else
1701 res2 = 0;
1702
1703 display_pipe_crc_irq_handler(dev_priv, pipe,
1704 I915_READ(PIPE_CRC_RES_RED(pipe)),
1705 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1706 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1707 res1, res2);
1708 }
1709
1710 /* The RPS events need forcewake, so we add them to a work queue and mask their
1711 * IMR bits until the work is done. Other interrupts can be processed without
1712 * the work queue. */
1713 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1714 {
1715 if (pm_iir & dev_priv->pm_rps_events) {
1716 spin_lock(&dev_priv->irq_lock);
1717 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1718 if (dev_priv->rps.interrupts_enabled) {
1719 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1720 schedule_work(&dev_priv->rps.work);
1721 }
1722 spin_unlock(&dev_priv->irq_lock);
1723 }
1724
1725 if (INTEL_INFO(dev_priv)->gen >= 8)
1726 return;
1727
1728 if (HAS_VEBOX(dev_priv)) {
1729 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1730 notify_ring(dev_priv->engine[VECS]);
1731
1732 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1733 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1734 }
1735 }
1736
1737 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1738 {
1739 if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
1740 /* Sample the log buffer flush related bits & clear them out now
1741 * itself from the message identity register to minimize the
1742 * probability of losing a flush interrupt, when there are back
1743 * to back flush interrupts.
1744 * There can be a new flush interrupt, for different log buffer
1745 * type (like for ISR), whilst Host is handling one (for DPC).
1746 * Since same bit is used in message register for ISR & DPC, it
1747 * could happen that GuC sets the bit for 2nd interrupt but Host
1748 * clears out the bit on handling the 1st interrupt.
1749 */
1750 u32 msg, flush;
1751
1752 msg = I915_READ(SOFT_SCRATCH(15));
1753 flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
1754 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
1755 if (flush) {
1756 /* Clear the message bits that are handled */
1757 I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
1758
1759 /* Handle flush interrupt in bottom half */
1760 queue_work(dev_priv->guc.log.flush_wq,
1761 &dev_priv->guc.log.flush_work);
1762
1763 dev_priv->guc.log.flush_interrupt_count++;
1764 } else {
1765 /* Not clearing of unhandled event bits won't result in
1766 * re-triggering of the interrupt.
1767 */
1768 }
1769 }
1770 }
1771
1772 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1773 enum pipe pipe)
1774 {
1775 bool ret;
1776
1777 ret = drm_handle_vblank(&dev_priv->drm, pipe);
1778 if (ret)
1779 intel_finish_page_flip_mmio(dev_priv, pipe);
1780
1781 return ret;
1782 }
1783
1784 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1785 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1786 {
1787 int pipe;
1788
1789 spin_lock(&dev_priv->irq_lock);
1790
1791 if (!dev_priv->display_irqs_enabled) {
1792 spin_unlock(&dev_priv->irq_lock);
1793 return;
1794 }
1795
1796 for_each_pipe(dev_priv, pipe) {
1797 i915_reg_t reg;
1798 u32 mask, iir_bit = 0;
1799
1800 /*
1801 * PIPESTAT bits get signalled even when the interrupt is
1802 * disabled with the mask bits, and some of the status bits do
1803 * not generate interrupts at all (like the underrun bit). Hence
1804 * we need to be careful that we only handle what we want to
1805 * handle.
1806 */
1807
1808 /* fifo underruns are filterered in the underrun handler. */
1809 mask = PIPE_FIFO_UNDERRUN_STATUS;
1810
1811 switch (pipe) {
1812 case PIPE_A:
1813 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1814 break;
1815 case PIPE_B:
1816 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1817 break;
1818 case PIPE_C:
1819 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1820 break;
1821 }
1822 if (iir & iir_bit)
1823 mask |= dev_priv->pipestat_irq_mask[pipe];
1824
1825 if (!mask)
1826 continue;
1827
1828 reg = PIPESTAT(pipe);
1829 mask |= PIPESTAT_INT_ENABLE_MASK;
1830 pipe_stats[pipe] = I915_READ(reg) & mask;
1831
1832 /*
1833 * Clear the PIPE*STAT regs before the IIR
1834 */
1835 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1836 PIPESTAT_INT_STATUS_MASK))
1837 I915_WRITE(reg, pipe_stats[pipe]);
1838 }
1839 spin_unlock(&dev_priv->irq_lock);
1840 }
1841
1842 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1843 u32 pipe_stats[I915_MAX_PIPES])
1844 {
1845 enum pipe pipe;
1846
1847 for_each_pipe(dev_priv, pipe) {
1848 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1849 intel_pipe_handle_vblank(dev_priv, pipe))
1850 intel_check_page_flip(dev_priv, pipe);
1851
1852 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1853 intel_finish_page_flip_cs(dev_priv, pipe);
1854
1855 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1856 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1857
1858 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1859 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1860 }
1861
1862 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1863 gmbus_irq_handler(dev_priv);
1864 }
1865
1866 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1867 {
1868 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1869
1870 if (hotplug_status)
1871 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1872
1873 return hotplug_status;
1874 }
1875
1876 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1877 u32 hotplug_status)
1878 {
1879 u32 pin_mask = 0, long_mask = 0;
1880
1881 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1882 IS_CHERRYVIEW(dev_priv)) {
1883 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1884
1885 if (hotplug_trigger) {
1886 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1887 hotplug_trigger, hpd_status_g4x,
1888 i9xx_port_hotplug_long_detect);
1889
1890 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1891 }
1892
1893 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1894 dp_aux_irq_handler(dev_priv);
1895 } else {
1896 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1897
1898 if (hotplug_trigger) {
1899 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1900 hotplug_trigger, hpd_status_i915,
1901 i9xx_port_hotplug_long_detect);
1902 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1903 }
1904 }
1905 }
1906
1907 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1908 {
1909 struct drm_device *dev = arg;
1910 struct drm_i915_private *dev_priv = to_i915(dev);
1911 irqreturn_t ret = IRQ_NONE;
1912
1913 if (!intel_irqs_enabled(dev_priv))
1914 return IRQ_NONE;
1915
1916 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1917 disable_rpm_wakeref_asserts(dev_priv);
1918
1919 do {
1920 u32 iir, gt_iir, pm_iir;
1921 u32 pipe_stats[I915_MAX_PIPES] = {};
1922 u32 hotplug_status = 0;
1923 u32 ier = 0;
1924
1925 gt_iir = I915_READ(GTIIR);
1926 pm_iir = I915_READ(GEN6_PMIIR);
1927 iir = I915_READ(VLV_IIR);
1928
1929 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1930 break;
1931
1932 ret = IRQ_HANDLED;
1933
1934 /*
1935 * Theory on interrupt generation, based on empirical evidence:
1936 *
1937 * x = ((VLV_IIR & VLV_IER) ||
1938 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1939 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1940 *
1941 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1942 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1943 * guarantee the CPU interrupt will be raised again even if we
1944 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1945 * bits this time around.
1946 */
1947 I915_WRITE(VLV_MASTER_IER, 0);
1948 ier = I915_READ(VLV_IER);
1949 I915_WRITE(VLV_IER, 0);
1950
1951 if (gt_iir)
1952 I915_WRITE(GTIIR, gt_iir);
1953 if (pm_iir)
1954 I915_WRITE(GEN6_PMIIR, pm_iir);
1955
1956 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1957 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1958
1959 /* Call regardless, as some status bits might not be
1960 * signalled in iir */
1961 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1962
1963 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1964 I915_LPE_PIPE_B_INTERRUPT))
1965 intel_lpe_audio_irq_handler(dev_priv);
1966
1967 /*
1968 * VLV_IIR is single buffered, and reflects the level
1969 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1970 */
1971 if (iir)
1972 I915_WRITE(VLV_IIR, iir);
1973
1974 I915_WRITE(VLV_IER, ier);
1975 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1976 POSTING_READ(VLV_MASTER_IER);
1977
1978 if (gt_iir)
1979 snb_gt_irq_handler(dev_priv, gt_iir);
1980 if (pm_iir)
1981 gen6_rps_irq_handler(dev_priv, pm_iir);
1982
1983 if (hotplug_status)
1984 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1985
1986 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1987 } while (0);
1988
1989 enable_rpm_wakeref_asserts(dev_priv);
1990
1991 return ret;
1992 }
1993
1994 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1995 {
1996 struct drm_device *dev = arg;
1997 struct drm_i915_private *dev_priv = to_i915(dev);
1998 irqreturn_t ret = IRQ_NONE;
1999
2000 if (!intel_irqs_enabled(dev_priv))
2001 return IRQ_NONE;
2002
2003 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2004 disable_rpm_wakeref_asserts(dev_priv);
2005
2006 do {
2007 u32 master_ctl, iir;
2008 u32 gt_iir[4] = {};
2009 u32 pipe_stats[I915_MAX_PIPES] = {};
2010 u32 hotplug_status = 0;
2011 u32 ier = 0;
2012
2013 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
2014 iir = I915_READ(VLV_IIR);
2015
2016 if (master_ctl == 0 && iir == 0)
2017 break;
2018
2019 ret = IRQ_HANDLED;
2020
2021 /*
2022 * Theory on interrupt generation, based on empirical evidence:
2023 *
2024 * x = ((VLV_IIR & VLV_IER) ||
2025 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
2026 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
2027 *
2028 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2029 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
2030 * guarantee the CPU interrupt will be raised again even if we
2031 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2032 * bits this time around.
2033 */
2034 I915_WRITE(GEN8_MASTER_IRQ, 0);
2035 ier = I915_READ(VLV_IER);
2036 I915_WRITE(VLV_IER, 0);
2037
2038 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2039
2040 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2041 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2042
2043 /* Call regardless, as some status bits might not be
2044 * signalled in iir */
2045 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2046
2047 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2048 I915_LPE_PIPE_B_INTERRUPT |
2049 I915_LPE_PIPE_C_INTERRUPT))
2050 intel_lpe_audio_irq_handler(dev_priv);
2051
2052 /*
2053 * VLV_IIR is single buffered, and reflects the level
2054 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2055 */
2056 if (iir)
2057 I915_WRITE(VLV_IIR, iir);
2058
2059 I915_WRITE(VLV_IER, ier);
2060 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2061 POSTING_READ(GEN8_MASTER_IRQ);
2062
2063 gen8_gt_irq_handler(dev_priv, gt_iir);
2064
2065 if (hotplug_status)
2066 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2067
2068 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2069 } while (0);
2070
2071 enable_rpm_wakeref_asserts(dev_priv);
2072
2073 return ret;
2074 }
2075
2076 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2077 u32 hotplug_trigger,
2078 const u32 hpd[HPD_NUM_PINS])
2079 {
2080 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2081
2082 /*
2083 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2084 * unless we touch the hotplug register, even if hotplug_trigger is
2085 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2086 * errors.
2087 */
2088 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2089 if (!hotplug_trigger) {
2090 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2091 PORTD_HOTPLUG_STATUS_MASK |
2092 PORTC_HOTPLUG_STATUS_MASK |
2093 PORTB_HOTPLUG_STATUS_MASK;
2094 dig_hotplug_reg &= ~mask;
2095 }
2096
2097 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2098 if (!hotplug_trigger)
2099 return;
2100
2101 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2102 dig_hotplug_reg, hpd,
2103 pch_port_hotplug_long_detect);
2104
2105 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2106 }
2107
2108 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2109 {
2110 int pipe;
2111 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2112
2113 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2114
2115 if (pch_iir & SDE_AUDIO_POWER_MASK) {
2116 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2117 SDE_AUDIO_POWER_SHIFT);
2118 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2119 port_name(port));
2120 }
2121
2122 if (pch_iir & SDE_AUX_MASK)
2123 dp_aux_irq_handler(dev_priv);
2124
2125 if (pch_iir & SDE_GMBUS)
2126 gmbus_irq_handler(dev_priv);
2127
2128 if (pch_iir & SDE_AUDIO_HDCP_MASK)
2129 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2130
2131 if (pch_iir & SDE_AUDIO_TRANS_MASK)
2132 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2133
2134 if (pch_iir & SDE_POISON)
2135 DRM_ERROR("PCH poison interrupt\n");
2136
2137 if (pch_iir & SDE_FDI_MASK)
2138 for_each_pipe(dev_priv, pipe)
2139 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2140 pipe_name(pipe),
2141 I915_READ(FDI_RX_IIR(pipe)));
2142
2143 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2144 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2145
2146 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2147 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2148
2149 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2150 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2151
2152 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2153 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2154 }
2155
2156 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2157 {
2158 u32 err_int = I915_READ(GEN7_ERR_INT);
2159 enum pipe pipe;
2160
2161 if (err_int & ERR_INT_POISON)
2162 DRM_ERROR("Poison interrupt\n");
2163
2164 for_each_pipe(dev_priv, pipe) {
2165 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2166 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2167
2168 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2169 if (IS_IVYBRIDGE(dev_priv))
2170 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2171 else
2172 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2173 }
2174 }
2175
2176 I915_WRITE(GEN7_ERR_INT, err_int);
2177 }
2178
2179 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2180 {
2181 u32 serr_int = I915_READ(SERR_INT);
2182
2183 if (serr_int & SERR_INT_POISON)
2184 DRM_ERROR("PCH poison interrupt\n");
2185
2186 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2187 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2188
2189 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2190 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2191
2192 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2193 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2194
2195 I915_WRITE(SERR_INT, serr_int);
2196 }
2197
2198 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2199 {
2200 int pipe;
2201 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2202
2203 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2204
2205 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2206 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2207 SDE_AUDIO_POWER_SHIFT_CPT);
2208 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2209 port_name(port));
2210 }
2211
2212 if (pch_iir & SDE_AUX_MASK_CPT)
2213 dp_aux_irq_handler(dev_priv);
2214
2215 if (pch_iir & SDE_GMBUS_CPT)
2216 gmbus_irq_handler(dev_priv);
2217
2218 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2219 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2220
2221 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2222 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2223
2224 if (pch_iir & SDE_FDI_MASK_CPT)
2225 for_each_pipe(dev_priv, pipe)
2226 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2227 pipe_name(pipe),
2228 I915_READ(FDI_RX_IIR(pipe)));
2229
2230 if (pch_iir & SDE_ERROR_CPT)
2231 cpt_serr_int_handler(dev_priv);
2232 }
2233
2234 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2235 {
2236 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2237 ~SDE_PORTE_HOTPLUG_SPT;
2238 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2239 u32 pin_mask = 0, long_mask = 0;
2240
2241 if (hotplug_trigger) {
2242 u32 dig_hotplug_reg;
2243
2244 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2245 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2246
2247 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2248 dig_hotplug_reg, hpd_spt,
2249 spt_port_hotplug_long_detect);
2250 }
2251
2252 if (hotplug2_trigger) {
2253 u32 dig_hotplug_reg;
2254
2255 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2256 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2257
2258 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2259 dig_hotplug_reg, hpd_spt,
2260 spt_port_hotplug2_long_detect);
2261 }
2262
2263 if (pin_mask)
2264 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2265
2266 if (pch_iir & SDE_GMBUS_CPT)
2267 gmbus_irq_handler(dev_priv);
2268 }
2269
2270 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2271 u32 hotplug_trigger,
2272 const u32 hpd[HPD_NUM_PINS])
2273 {
2274 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2275
2276 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2277 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2278
2279 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2280 dig_hotplug_reg, hpd,
2281 ilk_port_hotplug_long_detect);
2282
2283 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2284 }
2285
2286 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2287 u32 de_iir)
2288 {
2289 enum pipe pipe;
2290 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2291
2292 if (hotplug_trigger)
2293 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2294
2295 if (de_iir & DE_AUX_CHANNEL_A)
2296 dp_aux_irq_handler(dev_priv);
2297
2298 if (de_iir & DE_GSE)
2299 intel_opregion_asle_intr(dev_priv);
2300
2301 if (de_iir & DE_POISON)
2302 DRM_ERROR("Poison interrupt\n");
2303
2304 for_each_pipe(dev_priv, pipe) {
2305 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2306 intel_pipe_handle_vblank(dev_priv, pipe))
2307 intel_check_page_flip(dev_priv, pipe);
2308
2309 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2310 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2311
2312 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2313 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2314
2315 /* plane/pipes map 1:1 on ilk+ */
2316 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2317 intel_finish_page_flip_cs(dev_priv, pipe);
2318 }
2319
2320 /* check event from PCH */
2321 if (de_iir & DE_PCH_EVENT) {
2322 u32 pch_iir = I915_READ(SDEIIR);
2323
2324 if (HAS_PCH_CPT(dev_priv))
2325 cpt_irq_handler(dev_priv, pch_iir);
2326 else
2327 ibx_irq_handler(dev_priv, pch_iir);
2328
2329 /* should clear PCH hotplug event before clear CPU irq */
2330 I915_WRITE(SDEIIR, pch_iir);
2331 }
2332
2333 if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2334 ironlake_rps_change_irq_handler(dev_priv);
2335 }
2336
2337 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2338 u32 de_iir)
2339 {
2340 enum pipe pipe;
2341 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2342
2343 if (hotplug_trigger)
2344 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2345
2346 if (de_iir & DE_ERR_INT_IVB)
2347 ivb_err_int_handler(dev_priv);
2348
2349 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2350 dp_aux_irq_handler(dev_priv);
2351
2352 if (de_iir & DE_GSE_IVB)
2353 intel_opregion_asle_intr(dev_priv);
2354
2355 for_each_pipe(dev_priv, pipe) {
2356 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2357 intel_pipe_handle_vblank(dev_priv, pipe))
2358 intel_check_page_flip(dev_priv, pipe);
2359
2360 /* plane/pipes map 1:1 on ilk+ */
2361 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2362 intel_finish_page_flip_cs(dev_priv, pipe);
2363 }
2364
2365 /* check event from PCH */
2366 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2367 u32 pch_iir = I915_READ(SDEIIR);
2368
2369 cpt_irq_handler(dev_priv, pch_iir);
2370
2371 /* clear PCH hotplug event before clear CPU irq */
2372 I915_WRITE(SDEIIR, pch_iir);
2373 }
2374 }
2375
2376 /*
2377 * To handle irqs with the minimum potential races with fresh interrupts, we:
2378 * 1 - Disable Master Interrupt Control.
2379 * 2 - Find the source(s) of the interrupt.
2380 * 3 - Clear the Interrupt Identity bits (IIR).
2381 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2382 * 5 - Re-enable Master Interrupt Control.
2383 */
2384 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2385 {
2386 struct drm_device *dev = arg;
2387 struct drm_i915_private *dev_priv = to_i915(dev);
2388 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2389 irqreturn_t ret = IRQ_NONE;
2390
2391 if (!intel_irqs_enabled(dev_priv))
2392 return IRQ_NONE;
2393
2394 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2395 disable_rpm_wakeref_asserts(dev_priv);
2396
2397 /* disable master interrupt before clearing iir */
2398 de_ier = I915_READ(DEIER);
2399 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2400 POSTING_READ(DEIER);
2401
2402 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2403 * interrupts will will be stored on its back queue, and then we'll be
2404 * able to process them after we restore SDEIER (as soon as we restore
2405 * it, we'll get an interrupt if SDEIIR still has something to process
2406 * due to its back queue). */
2407 if (!HAS_PCH_NOP(dev_priv)) {
2408 sde_ier = I915_READ(SDEIER);
2409 I915_WRITE(SDEIER, 0);
2410 POSTING_READ(SDEIER);
2411 }
2412
2413 /* Find, clear, then process each source of interrupt */
2414
2415 gt_iir = I915_READ(GTIIR);
2416 if (gt_iir) {
2417 I915_WRITE(GTIIR, gt_iir);
2418 ret = IRQ_HANDLED;
2419 if (INTEL_GEN(dev_priv) >= 6)
2420 snb_gt_irq_handler(dev_priv, gt_iir);
2421 else
2422 ilk_gt_irq_handler(dev_priv, gt_iir);
2423 }
2424
2425 de_iir = I915_READ(DEIIR);
2426 if (de_iir) {
2427 I915_WRITE(DEIIR, de_iir);
2428 ret = IRQ_HANDLED;
2429 if (INTEL_GEN(dev_priv) >= 7)
2430 ivb_display_irq_handler(dev_priv, de_iir);
2431 else
2432 ilk_display_irq_handler(dev_priv, de_iir);
2433 }
2434
2435 if (INTEL_GEN(dev_priv) >= 6) {
2436 u32 pm_iir = I915_READ(GEN6_PMIIR);
2437 if (pm_iir) {
2438 I915_WRITE(GEN6_PMIIR, pm_iir);
2439 ret = IRQ_HANDLED;
2440 gen6_rps_irq_handler(dev_priv, pm_iir);
2441 }
2442 }
2443
2444 I915_WRITE(DEIER, de_ier);
2445 POSTING_READ(DEIER);
2446 if (!HAS_PCH_NOP(dev_priv)) {
2447 I915_WRITE(SDEIER, sde_ier);
2448 POSTING_READ(SDEIER);
2449 }
2450
2451 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2452 enable_rpm_wakeref_asserts(dev_priv);
2453
2454 return ret;
2455 }
2456
2457 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2458 u32 hotplug_trigger,
2459 const u32 hpd[HPD_NUM_PINS])
2460 {
2461 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2462
2463 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2464 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2465
2466 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2467 dig_hotplug_reg, hpd,
2468 bxt_port_hotplug_long_detect);
2469
2470 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2471 }
2472
2473 static irqreturn_t
2474 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2475 {
2476 irqreturn_t ret = IRQ_NONE;
2477 u32 iir;
2478 enum pipe pipe;
2479
2480 if (master_ctl & GEN8_DE_MISC_IRQ) {
2481 iir = I915_READ(GEN8_DE_MISC_IIR);
2482 if (iir) {
2483 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2484 ret = IRQ_HANDLED;
2485 if (iir & GEN8_DE_MISC_GSE)
2486 intel_opregion_asle_intr(dev_priv);
2487 else
2488 DRM_ERROR("Unexpected DE Misc interrupt\n");
2489 }
2490 else
2491 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2492 }
2493
2494 if (master_ctl & GEN8_DE_PORT_IRQ) {
2495 iir = I915_READ(GEN8_DE_PORT_IIR);
2496 if (iir) {
2497 u32 tmp_mask;
2498 bool found = false;
2499
2500 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2501 ret = IRQ_HANDLED;
2502
2503 tmp_mask = GEN8_AUX_CHANNEL_A;
2504 if (INTEL_INFO(dev_priv)->gen >= 9)
2505 tmp_mask |= GEN9_AUX_CHANNEL_B |
2506 GEN9_AUX_CHANNEL_C |
2507 GEN9_AUX_CHANNEL_D;
2508
2509 if (iir & tmp_mask) {
2510 dp_aux_irq_handler(dev_priv);
2511 found = true;
2512 }
2513
2514 if (IS_GEN9_LP(dev_priv)) {
2515 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2516 if (tmp_mask) {
2517 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2518 hpd_bxt);
2519 found = true;
2520 }
2521 } else if (IS_BROADWELL(dev_priv)) {
2522 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2523 if (tmp_mask) {
2524 ilk_hpd_irq_handler(dev_priv,
2525 tmp_mask, hpd_bdw);
2526 found = true;
2527 }
2528 }
2529
2530 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2531 gmbus_irq_handler(dev_priv);
2532 found = true;
2533 }
2534
2535 if (!found)
2536 DRM_ERROR("Unexpected DE Port interrupt\n");
2537 }
2538 else
2539 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2540 }
2541
2542 for_each_pipe(dev_priv, pipe) {
2543 u32 flip_done, fault_errors;
2544
2545 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2546 continue;
2547
2548 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2549 if (!iir) {
2550 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2551 continue;
2552 }
2553
2554 ret = IRQ_HANDLED;
2555 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2556
2557 if (iir & GEN8_PIPE_VBLANK &&
2558 intel_pipe_handle_vblank(dev_priv, pipe))
2559 intel_check_page_flip(dev_priv, pipe);
2560
2561 flip_done = iir;
2562 if (INTEL_INFO(dev_priv)->gen >= 9)
2563 flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2564 else
2565 flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2566
2567 if (flip_done)
2568 intel_finish_page_flip_cs(dev_priv, pipe);
2569
2570 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2571 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2572
2573 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2574 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2575
2576 fault_errors = iir;
2577 if (INTEL_INFO(dev_priv)->gen >= 9)
2578 fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2579 else
2580 fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2581
2582 if (fault_errors)
2583 DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2584 pipe_name(pipe),
2585 fault_errors);
2586 }
2587
2588 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2589 master_ctl & GEN8_DE_PCH_IRQ) {
2590 /*
2591 * FIXME(BDW): Assume for now that the new interrupt handling
2592 * scheme also closed the SDE interrupt handling race we've seen
2593 * on older pch-split platforms. But this needs testing.
2594 */
2595 iir = I915_READ(SDEIIR);
2596 if (iir) {
2597 I915_WRITE(SDEIIR, iir);
2598 ret = IRQ_HANDLED;
2599
2600 if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2601 spt_irq_handler(dev_priv, iir);
2602 else
2603 cpt_irq_handler(dev_priv, iir);
2604 } else {
2605 /*
2606 * Like on previous PCH there seems to be something
2607 * fishy going on with forwarding PCH interrupts.
2608 */
2609 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2610 }
2611 }
2612
2613 return ret;
2614 }
2615
2616 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2617 {
2618 struct drm_device *dev = arg;
2619 struct drm_i915_private *dev_priv = to_i915(dev);
2620 u32 master_ctl;
2621 u32 gt_iir[4] = {};
2622 irqreturn_t ret;
2623
2624 if (!intel_irqs_enabled(dev_priv))
2625 return IRQ_NONE;
2626
2627 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2628 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2629 if (!master_ctl)
2630 return IRQ_NONE;
2631
2632 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2633
2634 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2635 disable_rpm_wakeref_asserts(dev_priv);
2636
2637 /* Find, clear, then process each source of interrupt */
2638 ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2639 gen8_gt_irq_handler(dev_priv, gt_iir);
2640 ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2641
2642 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2643 POSTING_READ_FW(GEN8_MASTER_IRQ);
2644
2645 enable_rpm_wakeref_asserts(dev_priv);
2646
2647 return ret;
2648 }
2649
2650 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2651 {
2652 /*
2653 * Notify all waiters for GPU completion events that reset state has
2654 * been changed, and that they need to restart their wait after
2655 * checking for potential errors (and bail out to drop locks if there is
2656 * a gpu reset pending so that i915_error_work_func can acquire them).
2657 */
2658
2659 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2660 wake_up_all(&dev_priv->gpu_error.wait_queue);
2661
2662 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2663 wake_up_all(&dev_priv->pending_flip_queue);
2664 }
2665
2666 /**
2667 * i915_reset_and_wakeup - do process context error handling work
2668 * @dev_priv: i915 device private
2669 *
2670 * Fire an error uevent so userspace can see that a hang or error
2671 * was detected.
2672 */
2673 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2674 {
2675 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2676 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2677 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2678 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2679
2680 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2681
2682 DRM_DEBUG_DRIVER("resetting chip\n");
2683 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2684
2685 /*
2686 * In most cases it's guaranteed that we get here with an RPM
2687 * reference held, for example because there is a pending GPU
2688 * request that won't finish until the reset is done. This
2689 * isn't the case at least when we get here by doing a
2690 * simulated reset via debugs, so get an RPM reference.
2691 */
2692 intel_runtime_pm_get(dev_priv);
2693 intel_prepare_reset(dev_priv);
2694
2695 do {
2696 /*
2697 * All state reset _must_ be completed before we update the
2698 * reset counter, for otherwise waiters might miss the reset
2699 * pending state and not properly drop locks, resulting in
2700 * deadlocks with the reset work.
2701 */
2702 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2703 i915_reset(dev_priv);
2704 mutex_unlock(&dev_priv->drm.struct_mutex);
2705 }
2706
2707 /* We need to wait for anyone holding the lock to wakeup */
2708 } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2709 I915_RESET_IN_PROGRESS,
2710 TASK_UNINTERRUPTIBLE,
2711 HZ));
2712
2713 intel_finish_reset(dev_priv);
2714 intel_runtime_pm_put(dev_priv);
2715
2716 if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2717 kobject_uevent_env(kobj,
2718 KOBJ_CHANGE, reset_done_event);
2719
2720 /*
2721 * Note: The wake_up also serves as a memory barrier so that
2722 * waiters see the updated value of the dev_priv->gpu_error.
2723 */
2724 wake_up_all(&dev_priv->gpu_error.reset_queue);
2725 }
2726
2727 static inline void
2728 i915_err_print_instdone(struct drm_i915_private *dev_priv,
2729 struct intel_instdone *instdone)
2730 {
2731 int slice;
2732 int subslice;
2733
2734 pr_err(" INSTDONE: 0x%08x\n", instdone->instdone);
2735
2736 if (INTEL_GEN(dev_priv) <= 3)
2737 return;
2738
2739 pr_err(" SC_INSTDONE: 0x%08x\n", instdone->slice_common);
2740
2741 if (INTEL_GEN(dev_priv) <= 6)
2742 return;
2743
2744 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2745 pr_err(" SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
2746 slice, subslice, instdone->sampler[slice][subslice]);
2747
2748 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2749 pr_err(" ROW_INSTDONE[%d][%d]: 0x%08x\n",
2750 slice, subslice, instdone->row[slice][subslice]);
2751 }
2752
2753 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
2754 {
2755 u32 eir;
2756
2757 if (!IS_GEN2(dev_priv))
2758 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
2759
2760 if (INTEL_GEN(dev_priv) < 4)
2761 I915_WRITE(IPEIR, I915_READ(IPEIR));
2762 else
2763 I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
2764
2765 I915_WRITE(EIR, I915_READ(EIR));
2766 eir = I915_READ(EIR);
2767 if (eir) {
2768 /*
2769 * some errors might have become stuck,
2770 * mask them.
2771 */
2772 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
2773 I915_WRITE(EMR, I915_READ(EMR) | eir);
2774 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2775 }
2776 }
2777
2778 /**
2779 * i915_handle_error - handle a gpu error
2780 * @dev_priv: i915 device private
2781 * @engine_mask: mask representing engines that are hung
2782 * @fmt: Error message format string
2783 *
2784 * Do some basic checking of register state at error time and
2785 * dump it to the syslog. Also call i915_capture_error_state() to make
2786 * sure we get a record and make it available in debugfs. Fire a uevent
2787 * so userspace knows something bad happened (should trigger collection
2788 * of a ring dump etc.).
2789 */
2790 void i915_handle_error(struct drm_i915_private *dev_priv,
2791 u32 engine_mask,
2792 const char *fmt, ...)
2793 {
2794 va_list args;
2795 char error_msg[80];
2796
2797 va_start(args, fmt);
2798 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2799 va_end(args);
2800
2801 i915_capture_error_state(dev_priv, engine_mask, error_msg);
2802 i915_clear_error_registers(dev_priv);
2803
2804 if (!engine_mask)
2805 return;
2806
2807 if (test_and_set_bit(I915_RESET_IN_PROGRESS,
2808 &dev_priv->gpu_error.flags))
2809 return;
2810
2811 /*
2812 * Wakeup waiting processes so that the reset function
2813 * i915_reset_and_wakeup doesn't deadlock trying to grab
2814 * various locks. By bumping the reset counter first, the woken
2815 * processes will see a reset in progress and back off,
2816 * releasing their locks and then wait for the reset completion.
2817 * We must do this for _all_ gpu waiters that might hold locks
2818 * that the reset work needs to acquire.
2819 *
2820 * Note: The wake_up also provides a memory barrier to ensure that the
2821 * waiters see the updated value of the reset flags.
2822 */
2823 i915_error_wake_up(dev_priv);
2824
2825 i915_reset_and_wakeup(dev_priv);
2826 }
2827
2828 /* Called from drm generic code, passed 'crtc' which
2829 * we use as a pipe index
2830 */
2831 static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
2832 {
2833 struct drm_i915_private *dev_priv = to_i915(dev);
2834 unsigned long irqflags;
2835
2836 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2837 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2838 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2839
2840 return 0;
2841 }
2842
2843 static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
2844 {
2845 struct drm_i915_private *dev_priv = to_i915(dev);
2846 unsigned long irqflags;
2847
2848 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2849 i915_enable_pipestat(dev_priv, pipe,
2850 PIPE_START_VBLANK_INTERRUPT_STATUS);
2851 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2852
2853 return 0;
2854 }
2855
2856 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2857 {
2858 struct drm_i915_private *dev_priv = to_i915(dev);
2859 unsigned long irqflags;
2860 uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2861 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2862
2863 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2864 ilk_enable_display_irq(dev_priv, bit);
2865 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2866
2867 return 0;
2868 }
2869
2870 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2871 {
2872 struct drm_i915_private *dev_priv = to_i915(dev);
2873 unsigned long irqflags;
2874
2875 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2876 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2877 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2878
2879 return 0;
2880 }
2881
2882 /* Called from drm generic code, passed 'crtc' which
2883 * we use as a pipe index
2884 */
2885 static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
2886 {
2887 struct drm_i915_private *dev_priv = to_i915(dev);
2888 unsigned long irqflags;
2889
2890 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2891 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2892 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2893 }
2894
2895 static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
2896 {
2897 struct drm_i915_private *dev_priv = to_i915(dev);
2898 unsigned long irqflags;
2899
2900 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2901 i915_disable_pipestat(dev_priv, pipe,
2902 PIPE_START_VBLANK_INTERRUPT_STATUS);
2903 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2904 }
2905
2906 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2907 {
2908 struct drm_i915_private *dev_priv = to_i915(dev);
2909 unsigned long irqflags;
2910 uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2911 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2912
2913 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2914 ilk_disable_display_irq(dev_priv, bit);
2915 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2916 }
2917
2918 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2919 {
2920 struct drm_i915_private *dev_priv = to_i915(dev);
2921 unsigned long irqflags;
2922
2923 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2924 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2925 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2926 }
2927
2928 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2929 {
2930 if (HAS_PCH_NOP(dev_priv))
2931 return;
2932
2933 GEN5_IRQ_RESET(SDE);
2934
2935 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2936 I915_WRITE(SERR_INT, 0xffffffff);
2937 }
2938
2939 /*
2940 * SDEIER is also touched by the interrupt handler to work around missed PCH
2941 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2942 * instead we unconditionally enable all PCH interrupt sources here, but then
2943 * only unmask them as needed with SDEIMR.
2944 *
2945 * This function needs to be called before interrupts are enabled.
2946 */
2947 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2948 {
2949 struct drm_i915_private *dev_priv = to_i915(dev);
2950
2951 if (HAS_PCH_NOP(dev_priv))
2952 return;
2953
2954 WARN_ON(I915_READ(SDEIER) != 0);
2955 I915_WRITE(SDEIER, 0xffffffff);
2956 POSTING_READ(SDEIER);
2957 }
2958
2959 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
2960 {
2961 GEN5_IRQ_RESET(GT);
2962 if (INTEL_GEN(dev_priv) >= 6)
2963 GEN5_IRQ_RESET(GEN6_PM);
2964 }
2965
2966 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2967 {
2968 enum pipe pipe;
2969
2970 if (IS_CHERRYVIEW(dev_priv))
2971 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2972 else
2973 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2974
2975 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2976 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2977
2978 for_each_pipe(dev_priv, pipe) {
2979 I915_WRITE(PIPESTAT(pipe),
2980 PIPE_FIFO_UNDERRUN_STATUS |
2981 PIPESTAT_INT_STATUS_MASK);
2982 dev_priv->pipestat_irq_mask[pipe] = 0;
2983 }
2984
2985 GEN5_IRQ_RESET(VLV_);
2986 dev_priv->irq_mask = ~0;
2987 }
2988
2989 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2990 {
2991 u32 pipestat_mask;
2992 u32 enable_mask;
2993 enum pipe pipe;
2994 u32 val;
2995
2996 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
2997 PIPE_CRC_DONE_INTERRUPT_STATUS;
2998
2999 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3000 for_each_pipe(dev_priv, pipe)
3001 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3002
3003 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3004 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3005 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3006 if (IS_CHERRYVIEW(dev_priv))
3007 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3008
3009 WARN_ON(dev_priv->irq_mask != ~0);
3010
3011 val = (I915_LPE_PIPE_A_INTERRUPT |
3012 I915_LPE_PIPE_B_INTERRUPT |
3013 I915_LPE_PIPE_C_INTERRUPT);
3014
3015 enable_mask |= val;
3016
3017 dev_priv->irq_mask = ~enable_mask;
3018
3019 GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3020 }
3021
3022 /* drm_dma.h hooks
3023 */
3024 static void ironlake_irq_reset(struct drm_device *dev)
3025 {
3026 struct drm_i915_private *dev_priv = to_i915(dev);
3027
3028 I915_WRITE(HWSTAM, 0xffffffff);
3029
3030 GEN5_IRQ_RESET(DE);
3031 if (IS_GEN7(dev_priv))
3032 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3033
3034 gen5_gt_irq_reset(dev_priv);
3035
3036 ibx_irq_reset(dev_priv);
3037 }
3038
3039 static void valleyview_irq_preinstall(struct drm_device *dev)
3040 {
3041 struct drm_i915_private *dev_priv = to_i915(dev);
3042
3043 I915_WRITE(VLV_MASTER_IER, 0);
3044 POSTING_READ(VLV_MASTER_IER);
3045
3046 gen5_gt_irq_reset(dev_priv);
3047
3048 spin_lock_irq(&dev_priv->irq_lock);
3049 if (dev_priv->display_irqs_enabled)
3050 vlv_display_irq_reset(dev_priv);
3051 spin_unlock_irq(&dev_priv->irq_lock);
3052 }
3053
3054 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3055 {
3056 GEN8_IRQ_RESET_NDX(GT, 0);
3057 GEN8_IRQ_RESET_NDX(GT, 1);
3058 GEN8_IRQ_RESET_NDX(GT, 2);
3059 GEN8_IRQ_RESET_NDX(GT, 3);
3060 }
3061
3062 static void gen8_irq_reset(struct drm_device *dev)
3063 {
3064 struct drm_i915_private *dev_priv = to_i915(dev);
3065 int pipe;
3066
3067 I915_WRITE(GEN8_MASTER_IRQ, 0);
3068 POSTING_READ(GEN8_MASTER_IRQ);
3069
3070 gen8_gt_irq_reset(dev_priv);
3071
3072 for_each_pipe(dev_priv, pipe)
3073 if (intel_display_power_is_enabled(dev_priv,
3074 POWER_DOMAIN_PIPE(pipe)))
3075 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3076
3077 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3078 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3079 GEN5_IRQ_RESET(GEN8_PCU_);
3080
3081 if (HAS_PCH_SPLIT(dev_priv))
3082 ibx_irq_reset(dev_priv);
3083 }
3084
3085 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3086 unsigned int pipe_mask)
3087 {
3088 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3089 enum pipe pipe;
3090
3091 spin_lock_irq(&dev_priv->irq_lock);
3092 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3093 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3094 dev_priv->de_irq_mask[pipe],
3095 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3096 spin_unlock_irq(&dev_priv->irq_lock);
3097 }
3098
3099 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3100 unsigned int pipe_mask)
3101 {
3102 enum pipe pipe;
3103
3104 spin_lock_irq(&dev_priv->irq_lock);
3105 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3106 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3107 spin_unlock_irq(&dev_priv->irq_lock);
3108
3109 /* make sure we're done processing display irqs */
3110 synchronize_irq(dev_priv->drm.irq);
3111 }
3112
3113 static void cherryview_irq_preinstall(struct drm_device *dev)
3114 {
3115 struct drm_i915_private *dev_priv = to_i915(dev);
3116
3117 I915_WRITE(GEN8_MASTER_IRQ, 0);
3118 POSTING_READ(GEN8_MASTER_IRQ);
3119
3120 gen8_gt_irq_reset(dev_priv);
3121
3122 GEN5_IRQ_RESET(GEN8_PCU_);
3123
3124 spin_lock_irq(&dev_priv->irq_lock);
3125 if (dev_priv->display_irqs_enabled)
3126 vlv_display_irq_reset(dev_priv);
3127 spin_unlock_irq(&dev_priv->irq_lock);
3128 }
3129
3130 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3131 const u32 hpd[HPD_NUM_PINS])
3132 {
3133 struct intel_encoder *encoder;
3134 u32 enabled_irqs = 0;
3135
3136 for_each_intel_encoder(&dev_priv->drm, encoder)
3137 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3138 enabled_irqs |= hpd[encoder->hpd_pin];
3139
3140 return enabled_irqs;
3141 }
3142
3143 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3144 {
3145 u32 hotplug;
3146
3147 /*
3148 * Enable digital hotplug on the PCH, and configure the DP short pulse
3149 * duration to 2ms (which is the minimum in the Display Port spec).
3150 * The pulse duration bits are reserved on LPT+.
3151 */
3152 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3153 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3154 PORTC_PULSE_DURATION_MASK |
3155 PORTD_PULSE_DURATION_MASK);
3156 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3157 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3158 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3159 /*
3160 * When CPU and PCH are on the same package, port A
3161 * HPD must be enabled in both north and south.
3162 */
3163 if (HAS_PCH_LPT_LP(dev_priv))
3164 hotplug |= PORTA_HOTPLUG_ENABLE;
3165 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3166 }
3167
3168 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3169 {
3170 u32 hotplug_irqs, enabled_irqs;
3171
3172 if (HAS_PCH_IBX(dev_priv)) {
3173 hotplug_irqs = SDE_HOTPLUG_MASK;
3174 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3175 } else {
3176 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3177 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3178 }
3179
3180 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3181
3182 ibx_hpd_detection_setup(dev_priv);
3183 }
3184
3185 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3186 {
3187 u32 hotplug;
3188
3189 /* Enable digital hotplug on the PCH */
3190 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3191 hotplug |= PORTA_HOTPLUG_ENABLE |
3192 PORTB_HOTPLUG_ENABLE |
3193 PORTC_HOTPLUG_ENABLE |
3194 PORTD_HOTPLUG_ENABLE;
3195 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3196
3197 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3198 hotplug |= PORTE_HOTPLUG_ENABLE;
3199 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3200 }
3201
3202 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3203 {
3204 u32 hotplug_irqs, enabled_irqs;
3205
3206 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3207 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3208
3209 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3210
3211 spt_hpd_detection_setup(dev_priv);
3212 }
3213
3214 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3215 {
3216 u32 hotplug;
3217
3218 /*
3219 * Enable digital hotplug on the CPU, and configure the DP short pulse
3220 * duration to 2ms (which is the minimum in the Display Port spec)
3221 * The pulse duration bits are reserved on HSW+.
3222 */
3223 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3224 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3225 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3226 DIGITAL_PORTA_PULSE_DURATION_2ms;
3227 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3228 }
3229
3230 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3231 {
3232 u32 hotplug_irqs, enabled_irqs;
3233
3234 if (INTEL_GEN(dev_priv) >= 8) {
3235 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3236 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3237
3238 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3239 } else if (INTEL_GEN(dev_priv) >= 7) {
3240 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3241 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3242
3243 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3244 } else {
3245 hotplug_irqs = DE_DP_A_HOTPLUG;
3246 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3247
3248 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3249 }
3250
3251 ilk_hpd_detection_setup(dev_priv);
3252
3253 ibx_hpd_irq_setup(dev_priv);
3254 }
3255
3256 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3257 u32 enabled_irqs)
3258 {
3259 u32 hotplug;
3260
3261 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3262 hotplug |= PORTA_HOTPLUG_ENABLE |
3263 PORTB_HOTPLUG_ENABLE |
3264 PORTC_HOTPLUG_ENABLE;
3265
3266 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3267 hotplug, enabled_irqs);
3268 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3269
3270 /*
3271 * For BXT invert bit has to be set based on AOB design
3272 * for HPD detection logic, update it based on VBT fields.
3273 */
3274 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3275 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3276 hotplug |= BXT_DDIA_HPD_INVERT;
3277 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3278 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3279 hotplug |= BXT_DDIB_HPD_INVERT;
3280 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3281 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3282 hotplug |= BXT_DDIC_HPD_INVERT;
3283
3284 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3285 }
3286
3287 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3288 {
3289 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3290 }
3291
3292 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3293 {
3294 u32 hotplug_irqs, enabled_irqs;
3295
3296 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3297 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3298
3299 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3300
3301 __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3302 }
3303
3304 static void ibx_irq_postinstall(struct drm_device *dev)
3305 {
3306 struct drm_i915_private *dev_priv = to_i915(dev);
3307 u32 mask;
3308
3309 if (HAS_PCH_NOP(dev_priv))
3310 return;
3311
3312 if (HAS_PCH_IBX(dev_priv))
3313 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3314 else
3315 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3316
3317 gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3318 I915_WRITE(SDEIMR, ~mask);
3319
3320 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3321 HAS_PCH_LPT(dev_priv))
3322 ibx_hpd_detection_setup(dev_priv);
3323 else
3324 spt_hpd_detection_setup(dev_priv);
3325 }
3326
3327 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3328 {
3329 struct drm_i915_private *dev_priv = to_i915(dev);
3330 u32 pm_irqs, gt_irqs;
3331
3332 pm_irqs = gt_irqs = 0;
3333
3334 dev_priv->gt_irq_mask = ~0;
3335 if (HAS_L3_DPF(dev_priv)) {
3336 /* L3 parity interrupt is always unmasked. */
3337 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3338 gt_irqs |= GT_PARITY_ERROR(dev_priv);
3339 }
3340
3341 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3342 if (IS_GEN5(dev_priv)) {
3343 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3344 } else {
3345 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3346 }
3347
3348 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3349
3350 if (INTEL_GEN(dev_priv) >= 6) {
3351 /*
3352 * RPS interrupts will get enabled/disabled on demand when RPS
3353 * itself is enabled/disabled.
3354 */
3355 if (HAS_VEBOX(dev_priv)) {
3356 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3357 dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
3358 }
3359
3360 dev_priv->pm_imr = 0xffffffff;
3361 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
3362 }
3363 }
3364
3365 static int ironlake_irq_postinstall(struct drm_device *dev)
3366 {
3367 struct drm_i915_private *dev_priv = to_i915(dev);
3368 u32 display_mask, extra_mask;
3369
3370 if (INTEL_GEN(dev_priv) >= 7) {
3371 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3372 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3373 DE_PLANEB_FLIP_DONE_IVB |
3374 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3375 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3376 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3377 DE_DP_A_HOTPLUG_IVB);
3378 } else {
3379 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3380 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3381 DE_AUX_CHANNEL_A |
3382 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3383 DE_POISON);
3384 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3385 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3386 DE_DP_A_HOTPLUG);
3387 }
3388
3389 dev_priv->irq_mask = ~display_mask;
3390
3391 I915_WRITE(HWSTAM, 0xeffe);
3392
3393 ibx_irq_pre_postinstall(dev);
3394
3395 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3396
3397 gen5_gt_irq_postinstall(dev);
3398
3399 ilk_hpd_detection_setup(dev_priv);
3400
3401 ibx_irq_postinstall(dev);
3402
3403 if (IS_IRONLAKE_M(dev_priv)) {
3404 /* Enable PCU event interrupts
3405 *
3406 * spinlocking not required here for correctness since interrupt
3407 * setup is guaranteed to run in single-threaded context. But we
3408 * need it to make the assert_spin_locked happy. */
3409 spin_lock_irq(&dev_priv->irq_lock);
3410 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3411 spin_unlock_irq(&dev_priv->irq_lock);
3412 }
3413
3414 return 0;
3415 }
3416
3417 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3418 {
3419 lockdep_assert_held(&dev_priv->irq_lock);
3420
3421 if (dev_priv->display_irqs_enabled)
3422 return;
3423
3424 dev_priv->display_irqs_enabled = true;
3425
3426 if (intel_irqs_enabled(dev_priv)) {
3427 vlv_display_irq_reset(dev_priv);
3428 vlv_display_irq_postinstall(dev_priv);
3429 }
3430 }
3431
3432 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3433 {
3434 lockdep_assert_held(&dev_priv->irq_lock);
3435
3436 if (!dev_priv->display_irqs_enabled)
3437 return;
3438
3439 dev_priv->display_irqs_enabled = false;
3440
3441 if (intel_irqs_enabled(dev_priv))
3442 vlv_display_irq_reset(dev_priv);
3443 }
3444
3445
3446 static int valleyview_irq_postinstall(struct drm_device *dev)
3447 {
3448 struct drm_i915_private *dev_priv = to_i915(dev);
3449
3450 gen5_gt_irq_postinstall(dev);
3451
3452 spin_lock_irq(&dev_priv->irq_lock);
3453 if (dev_priv->display_irqs_enabled)
3454 vlv_display_irq_postinstall(dev_priv);
3455 spin_unlock_irq(&dev_priv->irq_lock);
3456
3457 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3458 POSTING_READ(VLV_MASTER_IER);
3459
3460 return 0;
3461 }
3462
3463 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3464 {
3465 /* These are interrupts we'll toggle with the ring mask register */
3466 uint32_t gt_interrupts[] = {
3467 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3468 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3469 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3470 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3471 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3472 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3473 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3474 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3475 0,
3476 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3477 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3478 };
3479
3480 if (HAS_L3_DPF(dev_priv))
3481 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3482
3483 dev_priv->pm_ier = 0x0;
3484 dev_priv->pm_imr = ~dev_priv->pm_ier;
3485 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3486 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3487 /*
3488 * RPS interrupts will get enabled/disabled on demand when RPS itself
3489 * is enabled/disabled. Same wil be the case for GuC interrupts.
3490 */
3491 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
3492 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3493 }
3494
3495 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3496 {
3497 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3498 uint32_t de_pipe_enables;
3499 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3500 u32 de_port_enables;
3501 u32 de_misc_masked = GEN8_DE_MISC_GSE;
3502 enum pipe pipe;
3503
3504 if (INTEL_INFO(dev_priv)->gen >= 9) {
3505 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3506 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3507 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3508 GEN9_AUX_CHANNEL_D;
3509 if (IS_GEN9_LP(dev_priv))
3510 de_port_masked |= BXT_DE_PORT_GMBUS;
3511 } else {
3512 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3513 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3514 }
3515
3516 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3517 GEN8_PIPE_FIFO_UNDERRUN;
3518
3519 de_port_enables = de_port_masked;
3520 if (IS_GEN9_LP(dev_priv))
3521 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3522 else if (IS_BROADWELL(dev_priv))
3523 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3524
3525 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3526 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3527 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3528
3529 for_each_pipe(dev_priv, pipe)
3530 if (intel_display_power_is_enabled(dev_priv,
3531 POWER_DOMAIN_PIPE(pipe)))
3532 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3533 dev_priv->de_irq_mask[pipe],
3534 de_pipe_enables);
3535
3536 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3537 GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3538
3539 if (IS_GEN9_LP(dev_priv))
3540 bxt_hpd_detection_setup(dev_priv);
3541 else if (IS_BROADWELL(dev_priv))
3542 ilk_hpd_detection_setup(dev_priv);
3543 }
3544
3545 static int gen8_irq_postinstall(struct drm_device *dev)
3546 {
3547 struct drm_i915_private *dev_priv = to_i915(dev);
3548
3549 if (HAS_PCH_SPLIT(dev_priv))
3550 ibx_irq_pre_postinstall(dev);
3551
3552 gen8_gt_irq_postinstall(dev_priv);
3553 gen8_de_irq_postinstall(dev_priv);
3554
3555 if (HAS_PCH_SPLIT(dev_priv))
3556 ibx_irq_postinstall(dev);
3557
3558 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3559 POSTING_READ(GEN8_MASTER_IRQ);
3560
3561 return 0;
3562 }
3563
3564 static int cherryview_irq_postinstall(struct drm_device *dev)
3565 {
3566 struct drm_i915_private *dev_priv = to_i915(dev);
3567
3568 gen8_gt_irq_postinstall(dev_priv);
3569
3570 spin_lock_irq(&dev_priv->irq_lock);
3571 if (dev_priv->display_irqs_enabled)
3572 vlv_display_irq_postinstall(dev_priv);
3573 spin_unlock_irq(&dev_priv->irq_lock);
3574
3575 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3576 POSTING_READ(GEN8_MASTER_IRQ);
3577
3578 return 0;
3579 }
3580
3581 static void gen8_irq_uninstall(struct drm_device *dev)
3582 {
3583 struct drm_i915_private *dev_priv = to_i915(dev);
3584
3585 if (!dev_priv)
3586 return;
3587
3588 gen8_irq_reset(dev);
3589 }
3590
3591 static void valleyview_irq_uninstall(struct drm_device *dev)
3592 {
3593 struct drm_i915_private *dev_priv = to_i915(dev);
3594
3595 if (!dev_priv)
3596 return;
3597
3598 I915_WRITE(VLV_MASTER_IER, 0);
3599 POSTING_READ(VLV_MASTER_IER);
3600
3601 gen5_gt_irq_reset(dev_priv);
3602
3603 I915_WRITE(HWSTAM, 0xffffffff);
3604
3605 spin_lock_irq(&dev_priv->irq_lock);
3606 if (dev_priv->display_irqs_enabled)
3607 vlv_display_irq_reset(dev_priv);
3608 spin_unlock_irq(&dev_priv->irq_lock);
3609 }
3610
3611 static void cherryview_irq_uninstall(struct drm_device *dev)
3612 {
3613 struct drm_i915_private *dev_priv = to_i915(dev);
3614
3615 if (!dev_priv)
3616 return;
3617
3618 I915_WRITE(GEN8_MASTER_IRQ, 0);
3619 POSTING_READ(GEN8_MASTER_IRQ);
3620
3621 gen8_gt_irq_reset(dev_priv);
3622
3623 GEN5_IRQ_RESET(GEN8_PCU_);
3624
3625 spin_lock_irq(&dev_priv->irq_lock);
3626 if (dev_priv->display_irqs_enabled)
3627 vlv_display_irq_reset(dev_priv);
3628 spin_unlock_irq(&dev_priv->irq_lock);
3629 }
3630
3631 static void ironlake_irq_uninstall(struct drm_device *dev)
3632 {
3633 struct drm_i915_private *dev_priv = to_i915(dev);
3634
3635 if (!dev_priv)
3636 return;
3637
3638 ironlake_irq_reset(dev);
3639 }
3640
3641 static void i8xx_irq_preinstall(struct drm_device * dev)
3642 {
3643 struct drm_i915_private *dev_priv = to_i915(dev);
3644 int pipe;
3645
3646 for_each_pipe(dev_priv, pipe)
3647 I915_WRITE(PIPESTAT(pipe), 0);
3648 I915_WRITE16(IMR, 0xffff);
3649 I915_WRITE16(IER, 0x0);
3650 POSTING_READ16(IER);
3651 }
3652
3653 static int i8xx_irq_postinstall(struct drm_device *dev)
3654 {
3655 struct drm_i915_private *dev_priv = to_i915(dev);
3656
3657 I915_WRITE16(EMR,
3658 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3659
3660 /* Unmask the interrupts that we always want on. */
3661 dev_priv->irq_mask =
3662 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3663 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3664 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3665 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3666 I915_WRITE16(IMR, dev_priv->irq_mask);
3667
3668 I915_WRITE16(IER,
3669 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3670 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3671 I915_USER_INTERRUPT);
3672 POSTING_READ16(IER);
3673
3674 /* Interrupt setup is already guaranteed to be single-threaded, this is
3675 * just to make the assert_spin_locked check happy. */
3676 spin_lock_irq(&dev_priv->irq_lock);
3677 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3678 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3679 spin_unlock_irq(&dev_priv->irq_lock);
3680
3681 return 0;
3682 }
3683
3684 /*
3685 * Returns true when a page flip has completed.
3686 */
3687 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3688 int plane, int pipe, u32 iir)
3689 {
3690 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3691
3692 if (!intel_pipe_handle_vblank(dev_priv, pipe))
3693 return false;
3694
3695 if ((iir & flip_pending) == 0)
3696 goto check_page_flip;
3697
3698 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3699 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3700 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3701 * the flip is completed (no longer pending). Since this doesn't raise
3702 * an interrupt per se, we watch for the change at vblank.
3703 */
3704 if (I915_READ16(ISR) & flip_pending)
3705 goto check_page_flip;
3706
3707 intel_finish_page_flip_cs(dev_priv, pipe);
3708 return true;
3709
3710 check_page_flip:
3711 intel_check_page_flip(dev_priv, pipe);
3712 return false;
3713 }
3714
3715 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3716 {
3717 struct drm_device *dev = arg;
3718 struct drm_i915_private *dev_priv = to_i915(dev);
3719 u16 iir, new_iir;
3720 u32 pipe_stats[2];
3721 int pipe;
3722 u16 flip_mask =
3723 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3724 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3725 irqreturn_t ret;
3726
3727 if (!intel_irqs_enabled(dev_priv))
3728 return IRQ_NONE;
3729
3730 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3731 disable_rpm_wakeref_asserts(dev_priv);
3732
3733 ret = IRQ_NONE;
3734 iir = I915_READ16(IIR);
3735 if (iir == 0)
3736 goto out;
3737
3738 while (iir & ~flip_mask) {
3739 /* Can't rely on pipestat interrupt bit in iir as it might
3740 * have been cleared after the pipestat interrupt was received.
3741 * It doesn't set the bit in iir again, but it still produces
3742 * interrupts (for non-MSI).
3743 */
3744 spin_lock(&dev_priv->irq_lock);
3745 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3746 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3747
3748 for_each_pipe(dev_priv, pipe) {
3749 i915_reg_t reg = PIPESTAT(pipe);
3750 pipe_stats[pipe] = I915_READ(reg);
3751
3752 /*
3753 * Clear the PIPE*STAT regs before the IIR
3754 */
3755 if (pipe_stats[pipe] & 0x8000ffff)
3756 I915_WRITE(reg, pipe_stats[pipe]);
3757 }
3758 spin_unlock(&dev_priv->irq_lock);
3759
3760 I915_WRITE16(IIR, iir & ~flip_mask);
3761 new_iir = I915_READ16(IIR); /* Flush posted writes */
3762
3763 if (iir & I915_USER_INTERRUPT)
3764 notify_ring(dev_priv->engine[RCS]);
3765
3766 for_each_pipe(dev_priv, pipe) {
3767 int plane = pipe;
3768 if (HAS_FBC(dev_priv))
3769 plane = !plane;
3770
3771 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3772 i8xx_handle_vblank(dev_priv, plane, pipe, iir))
3773 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3774
3775 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3776 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3777
3778 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3779 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3780 pipe);
3781 }
3782
3783 iir = new_iir;
3784 }
3785 ret = IRQ_HANDLED;
3786
3787 out:
3788 enable_rpm_wakeref_asserts(dev_priv);
3789
3790 return ret;
3791 }
3792
3793 static void i8xx_irq_uninstall(struct drm_device * dev)
3794 {
3795 struct drm_i915_private *dev_priv = to_i915(dev);
3796 int pipe;
3797
3798 for_each_pipe(dev_priv, pipe) {
3799 /* Clear enable bits; then clear status bits */
3800 I915_WRITE(PIPESTAT(pipe), 0);
3801 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3802 }
3803 I915_WRITE16(IMR, 0xffff);
3804 I915_WRITE16(IER, 0x0);
3805 I915_WRITE16(IIR, I915_READ16(IIR));
3806 }
3807
3808 static void i915_irq_preinstall(struct drm_device * dev)
3809 {
3810 struct drm_i915_private *dev_priv = to_i915(dev);
3811 int pipe;
3812
3813 if (I915_HAS_HOTPLUG(dev_priv)) {
3814 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3815 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3816 }
3817
3818 I915_WRITE16(HWSTAM, 0xeffe);
3819 for_each_pipe(dev_priv, pipe)
3820 I915_WRITE(PIPESTAT(pipe), 0);
3821 I915_WRITE(IMR, 0xffffffff);
3822 I915_WRITE(IER, 0x0);
3823 POSTING_READ(IER);
3824 }
3825
3826 static int i915_irq_postinstall(struct drm_device *dev)
3827 {
3828 struct drm_i915_private *dev_priv = to_i915(dev);
3829 u32 enable_mask;
3830
3831 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3832
3833 /* Unmask the interrupts that we always want on. */
3834 dev_priv->irq_mask =
3835 ~(I915_ASLE_INTERRUPT |
3836 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3837 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3838 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3839 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3840
3841 enable_mask =
3842 I915_ASLE_INTERRUPT |
3843 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3844 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3845 I915_USER_INTERRUPT;
3846
3847 if (I915_HAS_HOTPLUG(dev_priv)) {
3848 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3849 POSTING_READ(PORT_HOTPLUG_EN);
3850
3851 /* Enable in IER... */
3852 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3853 /* and unmask in IMR */
3854 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3855 }
3856
3857 I915_WRITE(IMR, dev_priv->irq_mask);
3858 I915_WRITE(IER, enable_mask);
3859 POSTING_READ(IER);
3860
3861 i915_enable_asle_pipestat(dev_priv);
3862
3863 /* Interrupt setup is already guaranteed to be single-threaded, this is
3864 * just to make the assert_spin_locked check happy. */
3865 spin_lock_irq(&dev_priv->irq_lock);
3866 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3867 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3868 spin_unlock_irq(&dev_priv->irq_lock);
3869
3870 return 0;
3871 }
3872
3873 /*
3874 * Returns true when a page flip has completed.
3875 */
3876 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
3877 int plane, int pipe, u32 iir)
3878 {
3879 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3880
3881 if (!intel_pipe_handle_vblank(dev_priv, pipe))
3882 return false;
3883
3884 if ((iir & flip_pending) == 0)
3885 goto check_page_flip;
3886
3887 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3888 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3889 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3890 * the flip is completed (no longer pending). Since this doesn't raise
3891 * an interrupt per se, we watch for the change at vblank.
3892 */
3893 if (I915_READ(ISR) & flip_pending)
3894 goto check_page_flip;
3895
3896 intel_finish_page_flip_cs(dev_priv, pipe);
3897 return true;
3898
3899 check_page_flip:
3900 intel_check_page_flip(dev_priv, pipe);
3901 return false;
3902 }
3903
3904 static irqreturn_t i915_irq_handler(int irq, void *arg)
3905 {
3906 struct drm_device *dev = arg;
3907 struct drm_i915_private *dev_priv = to_i915(dev);
3908 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3909 u32 flip_mask =
3910 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3911 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3912 int pipe, ret = IRQ_NONE;
3913
3914 if (!intel_irqs_enabled(dev_priv))
3915 return IRQ_NONE;
3916
3917 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3918 disable_rpm_wakeref_asserts(dev_priv);
3919
3920 iir = I915_READ(IIR);
3921 do {
3922 bool irq_received = (iir & ~flip_mask) != 0;
3923 bool blc_event = false;
3924
3925 /* Can't rely on pipestat interrupt bit in iir as it might
3926 * have been cleared after the pipestat interrupt was received.
3927 * It doesn't set the bit in iir again, but it still produces
3928 * interrupts (for non-MSI).
3929 */
3930 spin_lock(&dev_priv->irq_lock);
3931 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3932 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3933
3934 for_each_pipe(dev_priv, pipe) {
3935 i915_reg_t reg = PIPESTAT(pipe);
3936 pipe_stats[pipe] = I915_READ(reg);
3937
3938 /* Clear the PIPE*STAT regs before the IIR */
3939 if (pipe_stats[pipe] & 0x8000ffff) {
3940 I915_WRITE(reg, pipe_stats[pipe]);
3941 irq_received = true;
3942 }
3943 }
3944 spin_unlock(&dev_priv->irq_lock);
3945
3946 if (!irq_received)
3947 break;
3948
3949 /* Consume port. Then clear IIR or we'll miss events */
3950 if (I915_HAS_HOTPLUG(dev_priv) &&
3951 iir & I915_DISPLAY_PORT_INTERRUPT) {
3952 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3953 if (hotplug_status)
3954 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3955 }
3956
3957 I915_WRITE(IIR, iir & ~flip_mask);
3958 new_iir = I915_READ(IIR); /* Flush posted writes */
3959
3960 if (iir & I915_USER_INTERRUPT)
3961 notify_ring(dev_priv->engine[RCS]);
3962
3963 for_each_pipe(dev_priv, pipe) {
3964 int plane = pipe;
3965 if (HAS_FBC(dev_priv))
3966 plane = !plane;
3967
3968 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3969 i915_handle_vblank(dev_priv, plane, pipe, iir))
3970 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3971
3972 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3973 blc_event = true;
3974
3975 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3976 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3977
3978 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3979 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3980 pipe);
3981 }
3982
3983 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3984 intel_opregion_asle_intr(dev_priv);
3985
3986 /* With MSI, interrupts are only generated when iir
3987 * transitions from zero to nonzero. If another bit got
3988 * set while we were handling the existing iir bits, then
3989 * we would never get another interrupt.
3990 *
3991 * This is fine on non-MSI as well, as if we hit this path
3992 * we avoid exiting the interrupt handler only to generate
3993 * another one.
3994 *
3995 * Note that for MSI this could cause a stray interrupt report
3996 * if an interrupt landed in the time between writing IIR and
3997 * the posting read. This should be rare enough to never
3998 * trigger the 99% of 100,000 interrupts test for disabling
3999 * stray interrupts.
4000 */
4001 ret = IRQ_HANDLED;
4002 iir = new_iir;
4003 } while (iir & ~flip_mask);
4004
4005 enable_rpm_wakeref_asserts(dev_priv);
4006
4007 return ret;
4008 }
4009
4010 static void i915_irq_uninstall(struct drm_device * dev)
4011 {
4012 struct drm_i915_private *dev_priv = to_i915(dev);
4013 int pipe;
4014
4015 if (I915_HAS_HOTPLUG(dev_priv)) {
4016 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4017 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4018 }
4019
4020 I915_WRITE16(HWSTAM, 0xffff);
4021 for_each_pipe(dev_priv, pipe) {
4022 /* Clear enable bits; then clear status bits */
4023 I915_WRITE(PIPESTAT(pipe), 0);
4024 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4025 }
4026 I915_WRITE(IMR, 0xffffffff);
4027 I915_WRITE(IER, 0x0);
4028
4029 I915_WRITE(IIR, I915_READ(IIR));
4030 }
4031
4032 static void i965_irq_preinstall(struct drm_device * dev)
4033 {
4034 struct drm_i915_private *dev_priv = to_i915(dev);
4035 int pipe;
4036
4037 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4038 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4039
4040 I915_WRITE(HWSTAM, 0xeffe);
4041 for_each_pipe(dev_priv, pipe)
4042 I915_WRITE(PIPESTAT(pipe), 0);
4043 I915_WRITE(IMR, 0xffffffff);
4044 I915_WRITE(IER, 0x0);
4045 POSTING_READ(IER);
4046 }
4047
4048 static int i965_irq_postinstall(struct drm_device *dev)
4049 {
4050 struct drm_i915_private *dev_priv = to_i915(dev);
4051 u32 enable_mask;
4052 u32 error_mask;
4053
4054 /* Unmask the interrupts that we always want on. */
4055 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4056 I915_DISPLAY_PORT_INTERRUPT |
4057 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4058 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4059 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4060 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4061 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4062
4063 enable_mask = ~dev_priv->irq_mask;
4064 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4065 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4066 enable_mask |= I915_USER_INTERRUPT;
4067
4068 if (IS_G4X(dev_priv))
4069 enable_mask |= I915_BSD_USER_INTERRUPT;
4070
4071 /* Interrupt setup is already guaranteed to be single-threaded, this is
4072 * just to make the assert_spin_locked check happy. */
4073 spin_lock_irq(&dev_priv->irq_lock);
4074 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4075 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4076 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4077 spin_unlock_irq(&dev_priv->irq_lock);
4078
4079 /*
4080 * Enable some error detection, note the instruction error mask
4081 * bit is reserved, so we leave it masked.
4082 */
4083 if (IS_G4X(dev_priv)) {
4084 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4085 GM45_ERROR_MEM_PRIV |
4086 GM45_ERROR_CP_PRIV |
4087 I915_ERROR_MEMORY_REFRESH);
4088 } else {
4089 error_mask = ~(I915_ERROR_PAGE_TABLE |
4090 I915_ERROR_MEMORY_REFRESH);
4091 }
4092 I915_WRITE(EMR, error_mask);
4093
4094 I915_WRITE(IMR, dev_priv->irq_mask);
4095 I915_WRITE(IER, enable_mask);
4096 POSTING_READ(IER);
4097
4098 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4099 POSTING_READ(PORT_HOTPLUG_EN);
4100
4101 i915_enable_asle_pipestat(dev_priv);
4102
4103 return 0;
4104 }
4105
4106 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4107 {
4108 u32 hotplug_en;
4109
4110 lockdep_assert_held(&dev_priv->irq_lock);
4111
4112 /* Note HDMI and DP share hotplug bits */
4113 /* enable bits are the same for all generations */
4114 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4115 /* Programming the CRT detection parameters tends
4116 to generate a spurious hotplug event about three
4117 seconds later. So just do it once.
4118 */
4119 if (IS_G4X(dev_priv))
4120 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4121 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4122
4123 /* Ignore TV since it's buggy */
4124 i915_hotplug_interrupt_update_locked(dev_priv,
4125 HOTPLUG_INT_EN_MASK |
4126 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4127 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4128 hotplug_en);
4129 }
4130
4131 static irqreturn_t i965_irq_handler(int irq, void *arg)
4132 {
4133 struct drm_device *dev = arg;
4134 struct drm_i915_private *dev_priv = to_i915(dev);
4135 u32 iir, new_iir;
4136 u32 pipe_stats[I915_MAX_PIPES];
4137 int ret = IRQ_NONE, pipe;
4138 u32 flip_mask =
4139 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4140 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4141
4142 if (!intel_irqs_enabled(dev_priv))
4143 return IRQ_NONE;
4144
4145 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4146 disable_rpm_wakeref_asserts(dev_priv);
4147
4148 iir = I915_READ(IIR);
4149
4150 for (;;) {
4151 bool irq_received = (iir & ~flip_mask) != 0;
4152 bool blc_event = false;
4153
4154 /* Can't rely on pipestat interrupt bit in iir as it might
4155 * have been cleared after the pipestat interrupt was received.
4156 * It doesn't set the bit in iir again, but it still produces
4157 * interrupts (for non-MSI).
4158 */
4159 spin_lock(&dev_priv->irq_lock);
4160 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4161 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4162
4163 for_each_pipe(dev_priv, pipe) {
4164 i915_reg_t reg = PIPESTAT(pipe);
4165 pipe_stats[pipe] = I915_READ(reg);
4166
4167 /*
4168 * Clear the PIPE*STAT regs before the IIR
4169 */
4170 if (pipe_stats[pipe] & 0x8000ffff) {
4171 I915_WRITE(reg, pipe_stats[pipe]);
4172 irq_received = true;
4173 }
4174 }
4175 spin_unlock(&dev_priv->irq_lock);
4176
4177 if (!irq_received)
4178 break;
4179
4180 ret = IRQ_HANDLED;
4181
4182 /* Consume port. Then clear IIR or we'll miss events */
4183 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4184 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4185 if (hotplug_status)
4186 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4187 }
4188
4189 I915_WRITE(IIR, iir & ~flip_mask);
4190 new_iir = I915_READ(IIR); /* Flush posted writes */
4191
4192 if (iir & I915_USER_INTERRUPT)
4193 notify_ring(dev_priv->engine[RCS]);
4194 if (iir & I915_BSD_USER_INTERRUPT)
4195 notify_ring(dev_priv->engine[VCS]);
4196
4197 for_each_pipe(dev_priv, pipe) {
4198 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4199 i915_handle_vblank(dev_priv, pipe, pipe, iir))
4200 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4201
4202 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4203 blc_event = true;
4204
4205 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4206 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4207
4208 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4209 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4210 }
4211
4212 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4213 intel_opregion_asle_intr(dev_priv);
4214
4215 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4216 gmbus_irq_handler(dev_priv);
4217
4218 /* With MSI, interrupts are only generated when iir
4219 * transitions from zero to nonzero. If another bit got
4220 * set while we were handling the existing iir bits, then
4221 * we would never get another interrupt.
4222 *
4223 * This is fine on non-MSI as well, as if we hit this path
4224 * we avoid exiting the interrupt handler only to generate
4225 * another one.
4226 *
4227 * Note that for MSI this could cause a stray interrupt report
4228 * if an interrupt landed in the time between writing IIR and
4229 * the posting read. This should be rare enough to never
4230 * trigger the 99% of 100,000 interrupts test for disabling
4231 * stray interrupts.
4232 */
4233 iir = new_iir;
4234 }
4235
4236 enable_rpm_wakeref_asserts(dev_priv);
4237
4238 return ret;
4239 }
4240
4241 static void i965_irq_uninstall(struct drm_device * dev)
4242 {
4243 struct drm_i915_private *dev_priv = to_i915(dev);
4244 int pipe;
4245
4246 if (!dev_priv)
4247 return;
4248
4249 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4250 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4251
4252 I915_WRITE(HWSTAM, 0xffffffff);
4253 for_each_pipe(dev_priv, pipe)
4254 I915_WRITE(PIPESTAT(pipe), 0);
4255 I915_WRITE(IMR, 0xffffffff);
4256 I915_WRITE(IER, 0x0);
4257
4258 for_each_pipe(dev_priv, pipe)
4259 I915_WRITE(PIPESTAT(pipe),
4260 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4261 I915_WRITE(IIR, I915_READ(IIR));
4262 }
4263
4264 /**
4265 * intel_irq_init - initializes irq support
4266 * @dev_priv: i915 device instance
4267 *
4268 * This function initializes all the irq support including work items, timers
4269 * and all the vtables. It does not setup the interrupt itself though.
4270 */
4271 void intel_irq_init(struct drm_i915_private *dev_priv)
4272 {
4273 struct drm_device *dev = &dev_priv->drm;
4274
4275 intel_hpd_init_work(dev_priv);
4276
4277 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4278 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4279
4280 if (HAS_GUC_SCHED(dev_priv))
4281 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4282
4283 /* Let's track the enabled rps events */
4284 if (IS_VALLEYVIEW(dev_priv))
4285 /* WaGsvRC0ResidencyMethod:vlv */
4286 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4287 else
4288 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4289
4290 dev_priv->rps.pm_intr_keep = 0;
4291
4292 /*
4293 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4294 * if GEN6_PM_UP_EI_EXPIRED is masked.
4295 *
4296 * TODO: verify if this can be reproduced on VLV,CHV.
4297 */
4298 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4299 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4300
4301 if (INTEL_INFO(dev_priv)->gen >= 8)
4302 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
4303
4304 if (IS_GEN2(dev_priv)) {
4305 /* Gen2 doesn't have a hardware frame counter */
4306 dev->max_vblank_count = 0;
4307 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4308 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4309 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4310 } else {
4311 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4312 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4313 }
4314
4315 /*
4316 * Opt out of the vblank disable timer on everything except gen2.
4317 * Gen2 doesn't have a hardware frame counter and so depends on
4318 * vblank interrupts to produce sane vblank seuquence numbers.
4319 */
4320 if (!IS_GEN2(dev_priv))
4321 dev->vblank_disable_immediate = true;
4322
4323 /* Most platforms treat the display irq block as an always-on
4324 * power domain. vlv/chv can disable it at runtime and need
4325 * special care to avoid writing any of the display block registers
4326 * outside of the power domain. We defer setting up the display irqs
4327 * in this case to the runtime pm.
4328 */
4329 dev_priv->display_irqs_enabled = true;
4330 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4331 dev_priv->display_irqs_enabled = false;
4332
4333 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4334
4335 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4336 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4337
4338 if (IS_CHERRYVIEW(dev_priv)) {
4339 dev->driver->irq_handler = cherryview_irq_handler;
4340 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4341 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4342 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4343 dev->driver->enable_vblank = i965_enable_vblank;
4344 dev->driver->disable_vblank = i965_disable_vblank;
4345 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4346 } else if (IS_VALLEYVIEW(dev_priv)) {
4347 dev->driver->irq_handler = valleyview_irq_handler;
4348 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4349 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4350 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4351 dev->driver->enable_vblank = i965_enable_vblank;
4352 dev->driver->disable_vblank = i965_disable_vblank;
4353 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4354 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4355 dev->driver->irq_handler = gen8_irq_handler;
4356 dev->driver->irq_preinstall = gen8_irq_reset;
4357 dev->driver->irq_postinstall = gen8_irq_postinstall;
4358 dev->driver->irq_uninstall = gen8_irq_uninstall;
4359 dev->driver->enable_vblank = gen8_enable_vblank;
4360 dev->driver->disable_vblank = gen8_disable_vblank;
4361 if (IS_GEN9_LP(dev_priv))
4362 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4363 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
4364 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4365 else
4366 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4367 } else if (HAS_PCH_SPLIT(dev_priv)) {
4368 dev->driver->irq_handler = ironlake_irq_handler;
4369 dev->driver->irq_preinstall = ironlake_irq_reset;
4370 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4371 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4372 dev->driver->enable_vblank = ironlake_enable_vblank;
4373 dev->driver->disable_vblank = ironlake_disable_vblank;
4374 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4375 } else {
4376 if (IS_GEN2(dev_priv)) {
4377 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4378 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4379 dev->driver->irq_handler = i8xx_irq_handler;
4380 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4381 dev->driver->enable_vblank = i8xx_enable_vblank;
4382 dev->driver->disable_vblank = i8xx_disable_vblank;
4383 } else if (IS_GEN3(dev_priv)) {
4384 dev->driver->irq_preinstall = i915_irq_preinstall;
4385 dev->driver->irq_postinstall = i915_irq_postinstall;
4386 dev->driver->irq_uninstall = i915_irq_uninstall;
4387 dev->driver->irq_handler = i915_irq_handler;
4388 dev->driver->enable_vblank = i8xx_enable_vblank;
4389 dev->driver->disable_vblank = i8xx_disable_vblank;
4390 } else {
4391 dev->driver->irq_preinstall = i965_irq_preinstall;
4392 dev->driver->irq_postinstall = i965_irq_postinstall;
4393 dev->driver->irq_uninstall = i965_irq_uninstall;
4394 dev->driver->irq_handler = i965_irq_handler;
4395 dev->driver->enable_vblank = i965_enable_vblank;
4396 dev->driver->disable_vblank = i965_disable_vblank;
4397 }
4398 if (I915_HAS_HOTPLUG(dev_priv))
4399 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4400 }
4401 }
4402
4403 /**
4404 * intel_irq_install - enables the hardware interrupt
4405 * @dev_priv: i915 device instance
4406 *
4407 * This function enables the hardware interrupt handling, but leaves the hotplug
4408 * handling still disabled. It is called after intel_irq_init().
4409 *
4410 * In the driver load and resume code we need working interrupts in a few places
4411 * but don't want to deal with the hassle of concurrent probe and hotplug
4412 * workers. Hence the split into this two-stage approach.
4413 */
4414 int intel_irq_install(struct drm_i915_private *dev_priv)
4415 {
4416 /*
4417 * We enable some interrupt sources in our postinstall hooks, so mark
4418 * interrupts as enabled _before_ actually enabling them to avoid
4419 * special cases in our ordering checks.
4420 */
4421 dev_priv->pm.irqs_enabled = true;
4422
4423 return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4424 }
4425
4426 /**
4427 * intel_irq_uninstall - finilizes all irq handling
4428 * @dev_priv: i915 device instance
4429 *
4430 * This stops interrupt and hotplug handling and unregisters and frees all
4431 * resources acquired in the init functions.
4432 */
4433 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4434 {
4435 drm_irq_uninstall(&dev_priv->drm);
4436 intel_hpd_cancel_work(dev_priv);
4437 dev_priv->pm.irqs_enabled = false;
4438 }
4439
4440 /**
4441 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4442 * @dev_priv: i915 device instance
4443 *
4444 * This function is used to disable interrupts at runtime, both in the runtime
4445 * pm and the system suspend/resume code.
4446 */
4447 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4448 {
4449 dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4450 dev_priv->pm.irqs_enabled = false;
4451 synchronize_irq(dev_priv->drm.irq);
4452 }
4453
4454 /**
4455 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4456 * @dev_priv: i915 device instance
4457 *
4458 * This function is used to enable interrupts at runtime, both in the runtime
4459 * pm and the system suspend/resume code.
4460 */
4461 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4462 {
4463 dev_priv->pm.irqs_enabled = true;
4464 dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4465 dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4466 }