2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/circ_buf.h>
28 #include <trace/events/dma_fence.h>
31 * DOC: GuC-based command submission
34 * A i915_guc_client refers to a submission path through GuC. Currently, there
35 * is only one of these (the execbuf_client) and this one is charged with all
36 * submissions to the GuC. This struct is the owner of a doorbell, a process
37 * descriptor and a workqueue (all of them inside a single gem object that
38 * contains all required pages for these elements).
40 * GuC stage descriptor:
41 * During initialization, the driver allocates a static pool of 1024 such
42 * descriptors, and shares them with the GuC.
43 * Currently, there exists a 1:1 mapping between a i915_guc_client and a
44 * guc_stage_desc (via the client's stage_id), so effectively only one
45 * gets used. This stage descriptor lets the GuC know about the doorbell,
46 * workqueue and process descriptor. Theoretically, it also lets the GuC
47 * know about our HW contexts (context ID, etc...), but we actually
48 * employ a kind of submission where the GuC uses the LRCA sent via the work
49 * item instead (the single guc_stage_desc associated to execbuf client
50 * contains information about the default kernel context only, but this is
51 * essentially unused). This is called a "proxy" submission.
53 * The Scratch registers:
54 * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
55 * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
56 * triggers an interrupt on the GuC via another register write (0xC4C8).
57 * Firmware writes a success/fail code back to the action register after
58 * processes the request. The kernel driver polls waiting for this update and
60 * See intel_guc_send()
63 * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
64 * mapped into process space.
67 * There are several types of work items that the host may place into a
68 * workqueue, each with its own requirements and limitations. Currently only
69 * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
70 * represents in-order queue. The kernel driver packs ring tail pointer and an
71 * ELSP context descriptor dword into Work Item.
72 * See guc_wq_item_append()
75 * The Additional Data Struct (ADS) has pointers for different buffers used by
76 * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
77 * scheduling policies (guc_policies), a structure describing a collection of
78 * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
79 * its internal state for sleep.
83 static inline bool is_high_priority(struct i915_guc_client
* client
)
85 return client
->priority
<= GUC_CLIENT_PRIORITY_HIGH
;
88 static int __reserve_doorbell(struct i915_guc_client
*client
)
94 GEM_BUG_ON(client
->doorbell_id
!= GUC_DOORBELL_INVALID
);
97 * The bitmap tracks which doorbell registers are currently in use.
98 * It is split into two halves; the first half is used for normal
99 * priority contexts, the second half for high-priority ones.
102 end
= GUC_NUM_DOORBELLS
/2;
103 if (is_high_priority(client
)) {
108 id
= find_next_zero_bit(client
->guc
->doorbell_bitmap
, offset
, end
);
112 __set_bit(id
, client
->guc
->doorbell_bitmap
);
113 client
->doorbell_id
= id
;
114 DRM_DEBUG_DRIVER("client %u (high prio=%s) reserved doorbell: %d\n",
115 client
->stage_id
, yesno(is_high_priority(client
)),
120 static void __unreserve_doorbell(struct i915_guc_client
*client
)
122 GEM_BUG_ON(client
->doorbell_id
== GUC_DOORBELL_INVALID
);
124 __clear_bit(client
->doorbell_id
, client
->guc
->doorbell_bitmap
);
125 client
->doorbell_id
= GUC_DOORBELL_INVALID
;
129 * Tell the GuC to allocate or deallocate a specific doorbell
132 static int __guc_allocate_doorbell(struct intel_guc
*guc
, u32 stage_id
)
135 INTEL_GUC_ACTION_ALLOCATE_DOORBELL
,
139 return intel_guc_send(guc
, action
, ARRAY_SIZE(action
));
142 static int __guc_deallocate_doorbell(struct intel_guc
*guc
, u32 stage_id
)
145 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL
,
149 return intel_guc_send(guc
, action
, ARRAY_SIZE(action
));
152 static struct guc_stage_desc
*__get_stage_desc(struct i915_guc_client
*client
)
154 struct guc_stage_desc
*base
= client
->guc
->stage_desc_pool_vaddr
;
156 return &base
[client
->stage_id
];
160 * Initialise, update, or clear doorbell data shared with the GuC
162 * These functions modify shared data and so need access to the mapped
163 * client object which contains the page being used for the doorbell
166 static void __update_doorbell_desc(struct i915_guc_client
*client
, u16 new_id
)
168 struct guc_stage_desc
*desc
;
170 /* Update the GuC's idea of the doorbell ID */
171 desc
= __get_stage_desc(client
);
172 desc
->db_id
= new_id
;
175 static struct guc_doorbell_info
*__get_doorbell(struct i915_guc_client
*client
)
177 return client
->vaddr
+ client
->doorbell_offset
;
180 static bool has_doorbell(struct i915_guc_client
*client
)
182 if (client
->doorbell_id
== GUC_DOORBELL_INVALID
)
185 return test_bit(client
->doorbell_id
, client
->guc
->doorbell_bitmap
);
188 static int __create_doorbell(struct i915_guc_client
*client
)
190 struct guc_doorbell_info
*doorbell
;
193 doorbell
= __get_doorbell(client
);
194 doorbell
->db_status
= GUC_DOORBELL_ENABLED
;
195 doorbell
->cookie
= client
->doorbell_cookie
;
197 err
= __guc_allocate_doorbell(client
->guc
, client
->stage_id
);
199 doorbell
->db_status
= GUC_DOORBELL_DISABLED
;
200 doorbell
->cookie
= 0;
205 static int __destroy_doorbell(struct i915_guc_client
*client
)
207 struct drm_i915_private
*dev_priv
= guc_to_i915(client
->guc
);
208 struct guc_doorbell_info
*doorbell
;
209 u16 db_id
= client
->doorbell_id
;
211 GEM_BUG_ON(db_id
>= GUC_DOORBELL_INVALID
);
213 doorbell
= __get_doorbell(client
);
214 doorbell
->db_status
= GUC_DOORBELL_DISABLED
;
215 doorbell
->cookie
= 0;
217 /* Doorbell release flow requires that we wait for GEN8_DRB_VALID bit
218 * to go to zero after updating db_status before we call the GuC to
219 * release the doorbell */
220 if (wait_for_us(!(I915_READ(GEN8_DRBREGL(db_id
)) & GEN8_DRB_VALID
), 10))
221 WARN_ONCE(true, "Doorbell never became invalid after disable\n");
223 return __guc_deallocate_doorbell(client
->guc
, client
->stage_id
);
226 static int create_doorbell(struct i915_guc_client
*client
)
230 ret
= __reserve_doorbell(client
);
234 __update_doorbell_desc(client
, client
->doorbell_id
);
236 ret
= __create_doorbell(client
);
243 __update_doorbell_desc(client
, GUC_DOORBELL_INVALID
);
244 __unreserve_doorbell(client
);
248 static int destroy_doorbell(struct i915_guc_client
*client
)
252 GEM_BUG_ON(!has_doorbell(client
));
254 /* XXX: wait for any interrupts */
255 /* XXX: wait for workqueue to drain */
257 err
= __destroy_doorbell(client
);
261 __update_doorbell_desc(client
, GUC_DOORBELL_INVALID
);
263 __unreserve_doorbell(client
);
268 static unsigned long __select_cacheline(struct intel_guc
* guc
)
270 unsigned long offset
;
272 /* Doorbell uses a single cache line within a page */
273 offset
= offset_in_page(guc
->db_cacheline
);
275 /* Moving to next cache line to reduce contention */
276 guc
->db_cacheline
+= cache_line_size();
278 DRM_DEBUG_DRIVER("reserved cacheline 0x%lx, next 0x%x, linesize %u\n",
279 offset
, guc
->db_cacheline
, cache_line_size());
283 static inline struct guc_process_desc
*
284 __get_process_desc(struct i915_guc_client
*client
)
286 return client
->vaddr
+ client
->proc_desc_offset
;
290 * Initialise the process descriptor shared with the GuC firmware.
292 static void guc_proc_desc_init(struct intel_guc
*guc
,
293 struct i915_guc_client
*client
)
295 struct guc_process_desc
*desc
;
297 desc
= memset(__get_process_desc(client
), 0, sizeof(*desc
));
300 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
301 * space for ring3 clients (set them as in mmap_ioctl) or kernel
302 * space for kernel clients (map on demand instead? May make debug
303 * easier to have it mapped).
305 desc
->wq_base_addr
= 0;
306 desc
->db_base_addr
= 0;
308 desc
->stage_id
= client
->stage_id
;
309 desc
->wq_size_bytes
= client
->wq_size
;
310 desc
->wq_status
= WQ_STATUS_ACTIVE
;
311 desc
->priority
= client
->priority
;
315 * Initialise/clear the stage descriptor shared with the GuC firmware.
317 * This descriptor tells the GuC where (in GGTT space) to find the important
318 * data structures relating to this client (doorbell, process descriptor,
321 static void guc_stage_desc_init(struct intel_guc
*guc
,
322 struct i915_guc_client
*client
)
324 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
325 struct intel_engine_cs
*engine
;
326 struct i915_gem_context
*ctx
= client
->owner
;
327 struct guc_stage_desc
*desc
;
331 desc
= __get_stage_desc(client
);
332 memset(desc
, 0, sizeof(*desc
));
334 desc
->attribute
= GUC_STAGE_DESC_ATTR_ACTIVE
| GUC_STAGE_DESC_ATTR_KERNEL
;
335 desc
->stage_id
= client
->stage_id
;
336 desc
->priority
= client
->priority
;
337 desc
->db_id
= client
->doorbell_id
;
339 for_each_engine_masked(engine
, dev_priv
, client
->engines
, tmp
) {
340 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
341 uint32_t guc_engine_id
= engine
->guc_id
;
342 struct guc_execlist_context
*lrc
= &desc
->lrc
[guc_engine_id
];
344 /* TODO: We have a design issue to be solved here. Only when we
345 * receive the first batch, we know which engine is used by the
346 * user. But here GuC expects the lrc and ring to be pinned. It
347 * is not an issue for default context, which is the only one
348 * for now who owns a GuC client. But for future owner of GuC
349 * client, need to make sure lrc is pinned prior to enter here.
352 break; /* XXX: continue? */
355 * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
356 * submission or, in other words, not using a direct submission
357 * model) the KMD's LRCA is not used for any work submission.
358 * Instead, the GuC uses the LRCA of the user mode context (see
359 * guc_wq_item_append below).
361 lrc
->context_desc
= lower_32_bits(ce
->lrc_desc
);
363 /* The state page is after PPHWSP */
365 guc_ggtt_offset(ce
->state
) + LRC_STATE_PN
* PAGE_SIZE
;
367 /* XXX: In direct submission, the GuC wants the HW context id
368 * here. In proxy submission, it wants the stage id */
369 lrc
->context_id
= (client
->stage_id
<< GUC_ELC_CTXID_OFFSET
) |
370 (guc_engine_id
<< GUC_ELC_ENGINE_OFFSET
);
372 lrc
->ring_begin
= guc_ggtt_offset(ce
->ring
->vma
);
373 lrc
->ring_end
= lrc
->ring_begin
+ ce
->ring
->size
- 1;
374 lrc
->ring_next_free_location
= lrc
->ring_begin
;
375 lrc
->ring_current_tail_pointer_value
= 0;
377 desc
->engines_used
|= (1 << guc_engine_id
);
380 DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
381 client
->engines
, desc
->engines_used
);
382 WARN_ON(desc
->engines_used
== 0);
385 * The doorbell, process descriptor, and workqueue are all parts
386 * of the client object, which the GuC will reference via the GGTT
388 gfx_addr
= guc_ggtt_offset(client
->vma
);
389 desc
->db_trigger_phy
= sg_dma_address(client
->vma
->pages
->sgl
) +
390 client
->doorbell_offset
;
391 desc
->db_trigger_cpu
= (uintptr_t)__get_doorbell(client
);
392 desc
->db_trigger_uk
= gfx_addr
+ client
->doorbell_offset
;
393 desc
->process_desc
= gfx_addr
+ client
->proc_desc_offset
;
394 desc
->wq_addr
= gfx_addr
+ client
->wq_offset
;
395 desc
->wq_size
= client
->wq_size
;
397 desc
->desc_private
= (uintptr_t)client
;
400 static void guc_stage_desc_fini(struct intel_guc
*guc
,
401 struct i915_guc_client
*client
)
403 struct guc_stage_desc
*desc
;
405 desc
= __get_stage_desc(client
);
406 memset(desc
, 0, sizeof(*desc
));
410 * i915_guc_wq_reserve() - reserve space in the GuC's workqueue
411 * @request: request associated with the commands
413 * Return: 0 if space is available
414 * -EAGAIN if space is not currently available
416 * This function must be called (and must return 0) before a request
417 * is submitted to the GuC via i915_guc_submit() below. Once a result
418 * of 0 has been returned, it must be balanced by a corresponding
421 * Reservation allows the caller to determine in advance that space
422 * will be available for the next submission before committing resources
423 * to it, and helps avoid late failures with complicated recovery paths.
425 int i915_guc_wq_reserve(struct drm_i915_gem_request
*request
)
427 const size_t wqi_size
= sizeof(struct guc_wq_item
);
428 struct i915_guc_client
*client
= request
->i915
->guc
.execbuf_client
;
429 struct guc_process_desc
*desc
= __get_process_desc(client
);
433 spin_lock_irq(&client
->wq_lock
);
434 freespace
= CIRC_SPACE(client
->wq_tail
, desc
->head
, client
->wq_size
);
435 freespace
-= client
->wq_rsvd
;
436 if (likely(freespace
>= wqi_size
)) {
437 client
->wq_rsvd
+= wqi_size
;
440 client
->no_wq_space
++;
443 spin_unlock_irq(&client
->wq_lock
);
448 static void guc_client_update_wq_rsvd(struct i915_guc_client
*client
, int size
)
452 spin_lock_irqsave(&client
->wq_lock
, flags
);
453 client
->wq_rsvd
+= size
;
454 spin_unlock_irqrestore(&client
->wq_lock
, flags
);
457 void i915_guc_wq_unreserve(struct drm_i915_gem_request
*request
)
459 const int wqi_size
= sizeof(struct guc_wq_item
);
460 struct i915_guc_client
*client
= request
->i915
->guc
.execbuf_client
;
462 GEM_BUG_ON(READ_ONCE(client
->wq_rsvd
) < wqi_size
);
463 guc_client_update_wq_rsvd(client
, -wqi_size
);
466 /* Construct a Work Item and append it to the GuC's Work Queue */
467 static void guc_wq_item_append(struct i915_guc_client
*client
,
468 struct drm_i915_gem_request
*rq
)
470 /* wqi_len is in DWords, and does not include the one-word header */
471 const size_t wqi_size
= sizeof(struct guc_wq_item
);
472 const u32 wqi_len
= wqi_size
/sizeof(u32
) - 1;
473 struct intel_engine_cs
*engine
= rq
->engine
;
474 struct guc_process_desc
*desc
= __get_process_desc(client
);
475 struct guc_wq_item
*wqi
;
476 u32 freespace
, tail
, wq_off
;
478 /* Free space is guaranteed, see i915_guc_wq_reserve() above */
479 freespace
= CIRC_SPACE(client
->wq_tail
, desc
->head
, client
->wq_size
);
480 GEM_BUG_ON(freespace
< wqi_size
);
482 /* The GuC firmware wants the tail index in QWords, not bytes */
484 assert_ring_tail_valid(rq
->ring
, rq
->tail
);
486 GEM_BUG_ON(tail
> WQ_RING_TAIL_MAX
);
488 /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
489 * should not have the case where structure wqi is across page, neither
490 * wrapped to the beginning. This simplifies the implementation below.
492 * XXX: if not the case, we need save data to a temp wqi and copy it to
493 * workqueue buffer dw by dw.
495 BUILD_BUG_ON(wqi_size
!= 16);
496 GEM_BUG_ON(client
->wq_rsvd
< wqi_size
);
498 /* postincrement WQ tail for next time */
499 wq_off
= client
->wq_tail
;
500 GEM_BUG_ON(wq_off
& (wqi_size
- 1));
501 client
->wq_tail
+= wqi_size
;
502 client
->wq_tail
&= client
->wq_size
- 1;
503 client
->wq_rsvd
-= wqi_size
;
505 /* WQ starts from the page after doorbell / process_desc */
506 wqi
= client
->vaddr
+ wq_off
+ GUC_DB_SIZE
;
508 /* Now fill in the 4-word work queue item */
509 wqi
->header
= WQ_TYPE_INORDER
|
510 (wqi_len
<< WQ_LEN_SHIFT
) |
511 (engine
->guc_id
<< WQ_TARGET_SHIFT
) |
514 /* The GuC wants only the low-order word of the context descriptor */
515 wqi
->context_desc
= (u32
)intel_lr_context_descriptor(rq
->ctx
, engine
);
517 wqi
->submit_element_info
= tail
<< WQ_RING_TAIL_SHIFT
;
518 wqi
->fence_id
= rq
->global_seqno
;
521 static void guc_reset_wq(struct i915_guc_client
*client
)
523 struct guc_process_desc
*desc
= __get_process_desc(client
);
531 static int guc_ring_doorbell(struct i915_guc_client
*client
)
533 struct guc_process_desc
*desc
= __get_process_desc(client
);
534 union guc_doorbell_qw db_cmp
, db_exc
, db_ret
;
535 union guc_doorbell_qw
*db
;
536 int attempt
= 2, ret
= -EAGAIN
;
538 /* Update the tail so it is visible to GuC */
539 desc
->tail
= client
->wq_tail
;
542 db_cmp
.db_status
= GUC_DOORBELL_ENABLED
;
543 db_cmp
.cookie
= client
->doorbell_cookie
;
545 /* cookie to be updated */
546 db_exc
.db_status
= GUC_DOORBELL_ENABLED
;
547 db_exc
.cookie
= client
->doorbell_cookie
+ 1;
548 if (db_exc
.cookie
== 0)
551 /* pointer of current doorbell cacheline */
552 db
= (union guc_doorbell_qw
*)__get_doorbell(client
);
555 /* lets ring the doorbell */
556 db_ret
.value_qw
= atomic64_cmpxchg((atomic64_t
*)db
,
557 db_cmp
.value_qw
, db_exc
.value_qw
);
559 /* if the exchange was successfully executed */
560 if (db_ret
.value_qw
== db_cmp
.value_qw
) {
561 /* db was successfully rung */
562 client
->doorbell_cookie
= db_exc
.cookie
;
567 /* XXX: doorbell was lost and need to acquire it again */
568 if (db_ret
.db_status
== GUC_DOORBELL_DISABLED
)
571 DRM_WARN("Cookie mismatch. Expected %d, found %d\n",
572 db_cmp
.cookie
, db_ret
.cookie
);
574 /* update the cookie to newly read cookie from GuC */
575 db_cmp
.cookie
= db_ret
.cookie
;
576 db_exc
.cookie
= db_ret
.cookie
+ 1;
577 if (db_exc
.cookie
== 0)
585 * __i915_guc_submit() - Submit commands through GuC
586 * @rq: request associated with the commands
588 * The caller must have already called i915_guc_wq_reserve() above with
589 * a result of 0 (success), guaranteeing that there is space in the work
590 * queue for the new request, so enqueuing the item cannot fail.
592 * Bad Things Will Happen if the caller violates this protocol e.g. calls
593 * submit() when _reserve() says there's no space, or calls _submit()
594 * a different number of times from (successful) calls to _reserve().
596 * The only error here arises if the doorbell hardware isn't functioning
597 * as expected, which really shouln't happen.
599 static void __i915_guc_submit(struct drm_i915_gem_request
*rq
)
601 struct drm_i915_private
*dev_priv
= rq
->i915
;
602 struct intel_engine_cs
*engine
= rq
->engine
;
603 unsigned int engine_id
= engine
->id
;
604 struct intel_guc
*guc
= &rq
->i915
->guc
;
605 struct i915_guc_client
*client
= guc
->execbuf_client
;
609 /* WA to flush out the pending GMADR writes to ring buffer. */
610 if (i915_vma_is_map_and_fenceable(rq
->ring
->vma
))
611 POSTING_READ_FW(GUC_STATUS
);
613 spin_lock_irqsave(&client
->wq_lock
, flags
);
615 guc_wq_item_append(client
, rq
);
616 b_ret
= guc_ring_doorbell(client
);
618 client
->submissions
[engine_id
] += 1;
619 client
->retcode
= b_ret
;
623 guc
->submissions
[engine_id
] += 1;
624 guc
->last_seqno
[engine_id
] = rq
->global_seqno
;
626 spin_unlock_irqrestore(&client
->wq_lock
, flags
);
629 static void i915_guc_submit(struct drm_i915_gem_request
*rq
)
631 __i915_gem_request_submit(rq
);
632 __i915_guc_submit(rq
);
635 static void nested_enable_signaling(struct drm_i915_gem_request
*rq
)
637 /* If we use dma_fence_enable_sw_signaling() directly, lockdep
638 * detects an ordering issue between the fence lockclass and the
639 * global_timeline. This circular dependency can only occur via 2
640 * different fences (but same fence lockclass), so we use the nesting
641 * annotation here to prevent the warn, equivalent to the nesting
642 * inside i915_gem_request_submit() for when we also enable the
646 if (test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT
,
650 GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT
, &rq
->fence
.flags
));
651 trace_dma_fence_enable_signal(&rq
->fence
);
653 spin_lock_nested(&rq
->lock
, SINGLE_DEPTH_NESTING
);
654 intel_engine_enable_signaling(rq
);
655 spin_unlock(&rq
->lock
);
658 static bool i915_guc_dequeue(struct intel_engine_cs
*engine
)
660 struct execlist_port
*port
= engine
->execlist_port
;
661 struct drm_i915_gem_request
*last
= port
[0].request
;
665 spin_lock_irq(&engine
->timeline
->lock
);
666 rb
= engine
->execlist_first
;
668 struct drm_i915_gem_request
*rq
=
669 rb_entry(rb
, typeof(*rq
), priotree
.node
);
671 if (last
&& rq
->ctx
!= last
->ctx
) {
672 if (port
!= engine
->execlist_port
)
675 i915_gem_request_assign(&port
->request
, last
);
676 nested_enable_signaling(last
);
681 rb_erase(&rq
->priotree
.node
, &engine
->execlist_queue
);
682 RB_CLEAR_NODE(&rq
->priotree
.node
);
683 rq
->priotree
.priority
= INT_MAX
;
686 trace_i915_gem_request_in(rq
, port
- engine
->execlist_port
);
691 i915_gem_request_assign(&port
->request
, last
);
692 nested_enable_signaling(last
);
693 engine
->execlist_first
= rb
;
695 spin_unlock_irq(&engine
->timeline
->lock
);
700 static void i915_guc_irq_handler(unsigned long data
)
702 struct intel_engine_cs
*engine
= (struct intel_engine_cs
*)data
;
703 struct execlist_port
*port
= engine
->execlist_port
;
704 struct drm_i915_gem_request
*rq
;
708 rq
= port
[0].request
;
709 while (rq
&& i915_gem_request_completed(rq
)) {
710 trace_i915_gem_request_out(rq
);
711 i915_gem_request_put(rq
);
712 port
[0].request
= port
[1].request
;
713 port
[1].request
= NULL
;
714 rq
= port
[0].request
;
718 if (!port
[1].request
)
719 submit
= i915_guc_dequeue(engine
);
724 * Everything below here is concerned with setup & teardown, and is
725 * therefore not part of the somewhat time-critical batch-submission
726 * path of i915_guc_submit() above.
730 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
732 * @size: size of area to allocate (both virtual space and memory)
734 * This is a wrapper to create an object for use with the GuC. In order to
735 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
736 * both some backing storage and a range inside the Global GTT. We must pin
737 * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
738 * range is reserved inside GuC.
740 * Return: A i915_vma if successful, otherwise an ERR_PTR.
742 struct i915_vma
*intel_guc_allocate_vma(struct intel_guc
*guc
, u32 size
)
744 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
745 struct drm_i915_gem_object
*obj
;
746 struct i915_vma
*vma
;
749 obj
= i915_gem_object_create(dev_priv
, size
);
751 return ERR_CAST(obj
);
753 vma
= i915_vma_instance(obj
, &dev_priv
->ggtt
.base
, NULL
);
757 ret
= i915_vma_pin(vma
, 0, PAGE_SIZE
,
758 PIN_GLOBAL
| PIN_OFFSET_BIAS
| GUC_WOPCM_TOP
);
767 i915_gem_object_put(obj
);
771 /* Check that a doorbell register is in the expected state */
772 static bool doorbell_ok(struct intel_guc
*guc
, u16 db_id
)
774 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
778 GEM_BUG_ON(db_id
>= GUC_DOORBELL_INVALID
);
780 drbregl
= I915_READ(GEN8_DRBREGL(db_id
));
781 valid
= drbregl
& GEN8_DRB_VALID
;
783 if (test_bit(db_id
, guc
->doorbell_bitmap
) == valid
)
786 DRM_DEBUG_DRIVER("Doorbell %d has unexpected state (0x%x): valid=%s\n",
787 db_id
, drbregl
, yesno(valid
));
793 * If the GuC thinks that the doorbell is unassigned (e.g. because we reset and
794 * reloaded the GuC FW) we can use this function to tell the GuC to reassign the
795 * doorbell to the rightful owner.
797 static int __reset_doorbell(struct i915_guc_client
* client
, u16 db_id
)
801 __update_doorbell_desc(client
, db_id
);
802 err
= __create_doorbell(client
);
804 err
= __destroy_doorbell(client
);
810 * Set up & tear down each unused doorbell in turn, to ensure that all doorbell
811 * HW is (re)initialised. For that end, we might have to borrow the first
812 * client. Also, tell GuC about all the doorbells in use by all clients.
813 * We do this because the KMD, the GuC and the doorbell HW can easily go out of
814 * sync (e.g. we can reset the GuC, but not the doorbel HW).
816 static int guc_init_doorbell_hw(struct intel_guc
*guc
)
818 struct i915_guc_client
*client
= guc
->execbuf_client
;
819 bool recreate_first_client
= false;
823 /* For unused doorbells, make sure they are disabled */
824 for_each_clear_bit(db_id
, guc
->doorbell_bitmap
, GUC_NUM_DOORBELLS
) {
825 if (doorbell_ok(guc
, db_id
))
828 if (has_doorbell(client
)) {
829 /* Borrow execbuf_client (we will recreate it later) */
830 destroy_doorbell(client
);
831 recreate_first_client
= true;
834 ret
= __reset_doorbell(client
, db_id
);
835 WARN(ret
, "Doorbell %u reset failed, err %d\n", db_id
, ret
);
838 if (recreate_first_client
) {
839 ret
= __reserve_doorbell(client
);
841 DRM_ERROR("Couldn't re-reserve first client db: %d\n", ret
);
845 __update_doorbell_desc(client
, client
->doorbell_id
);
848 /* Now for every client (and not only execbuf_client) make sure their
849 * doorbells are known by the GuC */
850 //for (client = client_list; client != NULL; client = client->next)
852 ret
= __create_doorbell(client
);
854 DRM_ERROR("Couldn't recreate client %u doorbell: %d\n",
855 client
->stage_id
, ret
);
860 /* Read back & verify all (used & unused) doorbell registers */
861 for (db_id
= 0; db_id
< GUC_NUM_DOORBELLS
; ++db_id
)
862 WARN_ON(!doorbell_ok(guc
, db_id
));
868 * guc_client_alloc() - Allocate an i915_guc_client
869 * @dev_priv: driver private data structure
870 * @engines: The set of engines to enable for this client
871 * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
872 * The kernel client to replace ExecList submission is created with
873 * NORMAL priority. Priority of a client for scheduler can be HIGH,
874 * while a preemption context can use CRITICAL.
875 * @ctx: the context that owns the client (we use the default render
878 * Return: An i915_guc_client object if success, else NULL.
880 static struct i915_guc_client
*
881 guc_client_alloc(struct drm_i915_private
*dev_priv
,
884 struct i915_gem_context
*ctx
)
886 struct i915_guc_client
*client
;
887 struct intel_guc
*guc
= &dev_priv
->guc
;
888 struct i915_vma
*vma
;
892 client
= kzalloc(sizeof(*client
), GFP_KERNEL
);
894 return ERR_PTR(-ENOMEM
);
898 client
->engines
= engines
;
899 client
->priority
= priority
;
900 client
->doorbell_id
= GUC_DOORBELL_INVALID
;
901 client
->wq_offset
= GUC_DB_SIZE
;
902 client
->wq_size
= GUC_WQ_SIZE
;
903 spin_lock_init(&client
->wq_lock
);
905 ret
= ida_simple_get(&guc
->stage_ids
, 0, GUC_MAX_STAGE_DESCRIPTORS
,
910 client
->stage_id
= ret
;
912 /* The first page is doorbell/proc_desc. Two followed pages are wq. */
913 vma
= intel_guc_allocate_vma(guc
, GUC_DB_SIZE
+ GUC_WQ_SIZE
);
919 /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
922 vaddr
= i915_gem_object_pin_map(vma
->obj
, I915_MAP_WB
);
924 ret
= PTR_ERR(vaddr
);
927 client
->vaddr
= vaddr
;
929 client
->doorbell_offset
= __select_cacheline(guc
);
932 * Since the doorbell only requires a single cacheline, we can save
933 * space by putting the application process descriptor in the same
934 * page. Use the half of the page that doesn't include the doorbell.
936 if (client
->doorbell_offset
>= (GUC_DB_SIZE
/ 2))
937 client
->proc_desc_offset
= 0;
939 client
->proc_desc_offset
= (GUC_DB_SIZE
/ 2);
941 guc_proc_desc_init(guc
, client
);
942 guc_stage_desc_init(guc
, client
);
944 ret
= create_doorbell(client
);
948 DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: stage_id %u\n",
949 priority
, client
, client
->engines
, client
->stage_id
);
950 DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n",
951 client
->doorbell_id
, client
->doorbell_offset
);
956 i915_gem_object_unpin_map(client
->vma
->obj
);
958 i915_vma_unpin_and_release(&client
->vma
);
960 ida_simple_remove(&guc
->stage_ids
, client
->stage_id
);
966 static void guc_client_free(struct i915_guc_client
*client
)
969 * XXX: wait for any outstanding submissions before freeing memory.
970 * Be sure to drop any locks
973 /* FIXME: in many cases, by the time we get here the GuC has been
974 * reset, so we cannot destroy the doorbell properly. Ignore the
975 * error message for now */
976 destroy_doorbell(client
);
977 guc_stage_desc_fini(client
->guc
, client
);
978 i915_gem_object_unpin_map(client
->vma
->obj
);
979 i915_vma_unpin_and_release(&client
->vma
);
980 ida_simple_remove(&client
->guc
->stage_ids
, client
->stage_id
);
984 static void guc_policies_init(struct guc_policies
*policies
)
986 struct guc_policy
*policy
;
989 policies
->dpc_promote_time
= 500000;
990 policies
->max_num_work_items
= POLICY_MAX_NUM_WI
;
992 for (p
= 0; p
< GUC_CLIENT_PRIORITY_NUM
; p
++) {
993 for (i
= GUC_RENDER_ENGINE
; i
< GUC_MAX_ENGINES_NUM
; i
++) {
994 policy
= &policies
->policy
[p
][i
];
996 policy
->execution_quantum
= 1000000;
997 policy
->preemption_time
= 500000;
998 policy
->fault_time
= 250000;
999 policy
->policy_flags
= 0;
1003 policies
->is_valid
= 1;
1006 static int guc_ads_create(struct intel_guc
*guc
)
1008 struct drm_i915_private
*dev_priv
= guc_to_i915(guc
);
1009 struct i915_vma
*vma
;
1011 /* The ads obj includes the struct itself and buffers passed to GuC */
1014 struct guc_policies policies
;
1015 struct guc_mmio_reg_state reg_state
;
1016 u8 reg_state_buffer
[GUC_S3_SAVE_SPACE_PAGES
* PAGE_SIZE
];
1018 struct intel_engine_cs
*engine
;
1019 enum intel_engine_id id
;
1022 GEM_BUG_ON(guc
->ads_vma
);
1024 vma
= intel_guc_allocate_vma(guc
, PAGE_ALIGN(sizeof(*blob
)));
1026 return PTR_ERR(vma
);
1030 page
= i915_vma_first_page(vma
);
1033 /* GuC scheduling policies */
1034 guc_policies_init(&blob
->policies
);
1036 /* MMIO reg state */
1037 for_each_engine(engine
, dev_priv
, id
) {
1038 blob
->reg_state
.white_list
[engine
->guc_id
].mmio_start
=
1039 engine
->mmio_base
+ GUC_MMIO_WHITE_LIST_START
;
1041 /* Nothing to be saved or restored for now. */
1042 blob
->reg_state
.white_list
[engine
->guc_id
].count
= 0;
1046 * The GuC requires a "Golden Context" when it reinitialises
1047 * engines after a reset. Here we use the Render ring default
1048 * context, which must already exist and be pinned in the GGTT,
1049 * so its address won't change after we've told the GuC where
1052 blob
->ads
.golden_context_lrca
=
1053 dev_priv
->engine
[RCS
]->status_page
.ggtt_offset
;
1055 for_each_engine(engine
, dev_priv
, id
)
1056 blob
->ads
.eng_state_size
[engine
->guc_id
] =
1057 intel_lr_context_size(engine
);
1059 base
= guc_ggtt_offset(vma
);
1060 blob
->ads
.scheduler_policies
= base
+ ptr_offset(blob
, policies
);
1061 blob
->ads
.reg_state_buffer
= base
+ ptr_offset(blob
, reg_state_buffer
);
1062 blob
->ads
.reg_state_addr
= base
+ ptr_offset(blob
, reg_state
);
1069 static void guc_ads_destroy(struct intel_guc
*guc
)
1071 i915_vma_unpin_and_release(&guc
->ads_vma
);
1075 * Set up the memory resources to be shared with the GuC (via the GGTT)
1076 * at firmware loading time.
1078 int i915_guc_submission_init(struct drm_i915_private
*dev_priv
)
1080 struct intel_guc
*guc
= &dev_priv
->guc
;
1081 struct i915_vma
*vma
;
1085 if (guc
->stage_desc_pool
)
1088 vma
= intel_guc_allocate_vma(guc
,
1089 PAGE_ALIGN(sizeof(struct guc_stage_desc
) *
1090 GUC_MAX_STAGE_DESCRIPTORS
));
1092 return PTR_ERR(vma
);
1094 guc
->stage_desc_pool
= vma
;
1096 vaddr
= i915_gem_object_pin_map(guc
->stage_desc_pool
->obj
, I915_MAP_WB
);
1097 if (IS_ERR(vaddr
)) {
1098 ret
= PTR_ERR(vaddr
);
1102 guc
->stage_desc_pool_vaddr
= vaddr
;
1104 ret
= intel_guc_log_create(guc
);
1108 ret
= guc_ads_create(guc
);
1112 ida_init(&guc
->stage_ids
);
1117 intel_guc_log_destroy(guc
);
1119 i915_gem_object_unpin_map(guc
->stage_desc_pool
->obj
);
1121 i915_vma_unpin_and_release(&guc
->stage_desc_pool
);
1125 void i915_guc_submission_fini(struct drm_i915_private
*dev_priv
)
1127 struct intel_guc
*guc
= &dev_priv
->guc
;
1129 ida_destroy(&guc
->stage_ids
);
1130 guc_ads_destroy(guc
);
1131 intel_guc_log_destroy(guc
);
1132 i915_gem_object_unpin_map(guc
->stage_desc_pool
->obj
);
1133 i915_vma_unpin_and_release(&guc
->stage_desc_pool
);
1136 static void guc_interrupts_capture(struct drm_i915_private
*dev_priv
)
1138 struct intel_engine_cs
*engine
;
1139 enum intel_engine_id id
;
1142 /* tell all command streamers to forward interrupts (but not vblank) to GuC */
1143 irqs
= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING
);
1144 for_each_engine(engine
, dev_priv
, id
)
1145 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
1147 /* route USER_INTERRUPT to Host, all others are sent to GuC. */
1148 irqs
= GT_RENDER_USER_INTERRUPT
<< GEN8_RCS_IRQ_SHIFT
|
1149 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
1150 /* These three registers have the same bit definitions */
1151 I915_WRITE(GUC_BCS_RCS_IER
, ~irqs
);
1152 I915_WRITE(GUC_VCS2_VCS1_IER
, ~irqs
);
1153 I915_WRITE(GUC_WD_VECS_IER
, ~irqs
);
1156 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
1157 * (unmasked) PM interrupts to the GuC. All other bits of this
1158 * register *disable* generation of a specific interrupt.
1160 * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when
1161 * writing to the PM interrupt mask register, i.e. interrupts
1162 * that must not be disabled.
1164 * If the GuC is handling these interrupts, then we must not let
1165 * the PM code disable ANY interrupt that the GuC is expecting.
1166 * So for each ENABLED (0) bit in this register, we must SET the
1167 * bit in pm_intrmsk_mbz so that it's left enabled for the GuC.
1168 * GuC needs ARAT expired interrupt unmasked hence it is set in
1171 * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will
1172 * result in the register bit being left SET!
1174 dev_priv
->rps
.pm_intrmsk_mbz
|= ARAT_EXPIRED_INTRMSK
;
1175 dev_priv
->rps
.pm_intrmsk_mbz
&= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC
;
1178 static void guc_interrupts_release(struct drm_i915_private
*dev_priv
)
1180 struct intel_engine_cs
*engine
;
1181 enum intel_engine_id id
;
1185 * tell all command streamers NOT to forward interrupts or vblank
1188 irqs
= _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK
, GFX_FORWARD_VBLANK_NEVER
);
1189 irqs
|= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING
);
1190 for_each_engine(engine
, dev_priv
, id
)
1191 I915_WRITE(RING_MODE_GEN7(engine
), irqs
);
1193 /* route all GT interrupts to the host */
1194 I915_WRITE(GUC_BCS_RCS_IER
, 0);
1195 I915_WRITE(GUC_VCS2_VCS1_IER
, 0);
1196 I915_WRITE(GUC_WD_VECS_IER
, 0);
1198 dev_priv
->rps
.pm_intrmsk_mbz
|= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC
;
1199 dev_priv
->rps
.pm_intrmsk_mbz
&= ~ARAT_EXPIRED_INTRMSK
;
1202 int i915_guc_submission_enable(struct drm_i915_private
*dev_priv
)
1204 struct intel_guc
*guc
= &dev_priv
->guc
;
1205 struct i915_guc_client
*client
= guc
->execbuf_client
;
1206 struct intel_engine_cs
*engine
;
1207 enum intel_engine_id id
;
1211 client
= guc_client_alloc(dev_priv
,
1212 INTEL_INFO(dev_priv
)->ring_mask
,
1213 GUC_CLIENT_PRIORITY_KMD_NORMAL
,
1214 dev_priv
->kernel_context
);
1215 if (IS_ERR(client
)) {
1216 DRM_ERROR("Failed to create GuC client for execbuf!\n");
1217 return PTR_ERR(client
);
1220 guc
->execbuf_client
= client
;
1223 err
= intel_guc_sample_forcewake(guc
);
1225 goto err_execbuf_client
;
1227 guc_reset_wq(client
);
1229 err
= guc_init_doorbell_hw(guc
);
1231 goto err_execbuf_client
;
1233 /* Take over from manual control of ELSP (execlists) */
1234 guc_interrupts_capture(dev_priv
);
1236 for_each_engine(engine
, dev_priv
, id
) {
1237 const int wqi_size
= sizeof(struct guc_wq_item
);
1238 struct drm_i915_gem_request
*rq
;
1240 /* The tasklet was initialised by execlists, and may be in
1241 * a state of flux (across a reset) and so we just want to
1242 * take over the callback without changing any other state
1245 engine
->irq_tasklet
.func
= i915_guc_irq_handler
;
1246 clear_bit(ENGINE_IRQ_EXECLIST
, &engine
->irq_posted
);
1248 /* Replay the current set of previously submitted requests */
1249 spin_lock_irq(&engine
->timeline
->lock
);
1250 list_for_each_entry(rq
, &engine
->timeline
->requests
, link
) {
1251 guc_client_update_wq_rsvd(client
, wqi_size
);
1252 __i915_guc_submit(rq
);
1254 spin_unlock_irq(&engine
->timeline
->lock
);
1260 guc_client_free(guc
->execbuf_client
);
1261 guc
->execbuf_client
= NULL
;
1265 void i915_guc_submission_disable(struct drm_i915_private
*dev_priv
)
1267 struct intel_guc
*guc
= &dev_priv
->guc
;
1269 guc_interrupts_release(dev_priv
);
1271 /* Revert back to manual ELSP submission */
1272 intel_engines_reset_default_submission(dev_priv
);
1274 guc_client_free(guc
->execbuf_client
);
1275 guc
->execbuf_client
= NULL
;
1279 * intel_guc_suspend() - notify GuC entering suspend state
1280 * @dev_priv: i915 device private
1282 int intel_guc_suspend(struct drm_i915_private
*dev_priv
)
1284 struct intel_guc
*guc
= &dev_priv
->guc
;
1285 struct i915_gem_context
*ctx
;
1288 if (guc
->fw
.load_status
!= INTEL_UC_FIRMWARE_SUCCESS
)
1291 gen9_disable_guc_interrupts(dev_priv
);
1293 ctx
= dev_priv
->kernel_context
;
1295 data
[0] = INTEL_GUC_ACTION_ENTER_S_STATE
;
1296 /* any value greater than GUC_POWER_D0 */
1297 data
[1] = GUC_POWER_D1
;
1298 /* first page is shared data with GuC */
1299 data
[2] = guc_ggtt_offset(ctx
->engine
[RCS
].state
);
1301 return intel_guc_send(guc
, data
, ARRAY_SIZE(data
));
1305 * intel_guc_resume() - notify GuC resuming from suspend state
1306 * @dev_priv: i915 device private
1308 int intel_guc_resume(struct drm_i915_private
*dev_priv
)
1310 struct intel_guc
*guc
= &dev_priv
->guc
;
1311 struct i915_gem_context
*ctx
;
1314 if (guc
->fw
.load_status
!= INTEL_UC_FIRMWARE_SUCCESS
)
1317 if (i915
.guc_log_level
>= 0)
1318 gen9_enable_guc_interrupts(dev_priv
);
1320 ctx
= dev_priv
->kernel_context
;
1322 data
[0] = INTEL_GUC_ACTION_EXIT_S_STATE
;
1323 data
[1] = GUC_POWER_D0
;
1324 /* first page is shared data with GuC */
1325 data
[2] = guc_ggtt_offset(ctx
->engine
[RCS
].state
);
1327 return intel_guc_send(guc
, data
, ARRAY_SIZE(data
));