2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
36 struct change_domains
{
37 uint32_t invalidate_domains
;
38 uint32_t flush_domains
;
44 * Set the next domain for the specified object. This
45 * may not actually perform the necessary flushing/invaliding though,
46 * as that may want to be batched with other set_domain operations
48 * This is (we hope) the only really tricky part of gem. The goal
49 * is fairly simple -- track which caches hold bits of the object
50 * and make sure they remain coherent. A few concrete examples may
51 * help to explain how it works. For shorthand, we use the notation
52 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
53 * a pair of read and write domain masks.
55 * Case 1: the batch buffer
61 * 5. Unmapped from GTT
64 * Let's take these a step at a time
67 * Pages allocated from the kernel may still have
68 * cache contents, so we set them to (CPU, CPU) always.
69 * 2. Written by CPU (using pwrite)
70 * The pwrite function calls set_domain (CPU, CPU) and
71 * this function does nothing (as nothing changes)
73 * This function asserts that the object is not
74 * currently in any GPU-based read or write domains
76 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
77 * As write_domain is zero, this function adds in the
78 * current read domains (CPU+COMMAND, 0).
79 * flush_domains is set to CPU.
80 * invalidate_domains is set to COMMAND
81 * clflush is run to get data out of the CPU caches
82 * then i915_dev_set_domain calls i915_gem_flush to
83 * emit an MI_FLUSH and drm_agp_chipset_flush
84 * 5. Unmapped from GTT
85 * i915_gem_object_unbind calls set_domain (CPU, CPU)
86 * flush_domains and invalidate_domains end up both zero
87 * so no flushing/invalidating happens
91 * Case 2: The shared render buffer
95 * 3. Read/written by GPU
96 * 4. set_domain to (CPU,CPU)
97 * 5. Read/written by CPU
98 * 6. Read/written by GPU
101 * Same as last example, (CPU, CPU)
103 * Nothing changes (assertions find that it is not in the GPU)
104 * 3. Read/written by GPU
105 * execbuffer calls set_domain (RENDER, RENDER)
106 * flush_domains gets CPU
107 * invalidate_domains gets GPU
109 * MI_FLUSH and drm_agp_chipset_flush
110 * 4. set_domain (CPU, CPU)
111 * flush_domains gets GPU
112 * invalidate_domains gets CPU
113 * wait_rendering (obj) to make sure all drawing is complete.
114 * This will include an MI_FLUSH to get the data from GPU
116 * clflush (obj) to invalidate the CPU cache
117 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
118 * 5. Read/written by CPU
119 * cache lines are loaded and dirtied
120 * 6. Read written by GPU
121 * Same as last GPU access
123 * Case 3: The constant buffer
128 * 4. Updated (written) by CPU again
137 * flush_domains = CPU
138 * invalidate_domains = RENDER
141 * drm_agp_chipset_flush
142 * 4. Updated (written) by CPU again
144 * flush_domains = 0 (no previous write domain)
145 * invalidate_domains = 0 (no new read domains)
148 * flush_domains = CPU
149 * invalidate_domains = RENDER
152 * drm_agp_chipset_flush
155 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object
*obj
,
156 struct intel_ring_buffer
*ring
,
157 struct change_domains
*cd
)
159 uint32_t invalidate_domains
= 0, flush_domains
= 0;
162 * If the object isn't moving to a new write domain,
163 * let the object stay in multiple read domains
165 if (obj
->base
.pending_write_domain
== 0)
166 obj
->base
.pending_read_domains
|= obj
->base
.read_domains
;
169 * Flush the current write domain if
170 * the new read domains don't match. Invalidate
171 * any read domains which differ from the old
174 if (obj
->base
.write_domain
&&
175 (((obj
->base
.write_domain
!= obj
->base
.pending_read_domains
||
176 obj
->ring
!= ring
)) ||
177 (obj
->fenced_gpu_access
&& !obj
->pending_fenced_gpu_access
))) {
178 flush_domains
|= obj
->base
.write_domain
;
179 invalidate_domains
|=
180 obj
->base
.pending_read_domains
& ~obj
->base
.write_domain
;
183 * Invalidate any read caches which may have
184 * stale data. That is, any new read domains.
186 invalidate_domains
|= obj
->base
.pending_read_domains
& ~obj
->base
.read_domains
;
187 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
188 i915_gem_clflush_object(obj
);
190 if (obj
->base
.pending_write_domain
)
191 cd
->flips
|= atomic_read(&obj
->pending_flip
);
193 /* The actual obj->write_domain will be updated with
194 * pending_write_domain after we emit the accumulated flush for all
195 * of our domain changes in execbuffers (which clears objects'
196 * write_domains). So if we have a current write domain that we
197 * aren't changing, set pending_write_domain to that.
199 if (flush_domains
== 0 && obj
->base
.pending_write_domain
== 0)
200 obj
->base
.pending_write_domain
= obj
->base
.write_domain
;
202 cd
->invalidate_domains
|= invalidate_domains
;
203 cd
->flush_domains
|= flush_domains
;
204 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
205 cd
->flush_rings
|= intel_ring_flag(obj
->ring
);
206 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
207 cd
->flush_rings
|= intel_ring_flag(ring
);
212 struct hlist_head buckets
[0];
215 static struct eb_objects
*
218 struct eb_objects
*eb
;
219 int count
= PAGE_SIZE
/ sizeof(struct hlist_head
) / 2;
222 eb
= kzalloc(count
*sizeof(struct hlist_head
) +
223 sizeof(struct eb_objects
),
233 eb_reset(struct eb_objects
*eb
)
235 memset(eb
->buckets
, 0, (eb
->and+1)*sizeof(struct hlist_head
));
239 eb_add_object(struct eb_objects
*eb
, struct drm_i915_gem_object
*obj
)
241 hlist_add_head(&obj
->exec_node
,
242 &eb
->buckets
[obj
->exec_handle
& eb
->and]);
245 static struct drm_i915_gem_object
*
246 eb_get_object(struct eb_objects
*eb
, unsigned long handle
)
248 struct hlist_head
*head
;
249 struct hlist_node
*node
;
250 struct drm_i915_gem_object
*obj
;
252 head
= &eb
->buckets
[handle
& eb
->and];
253 hlist_for_each(node
, head
) {
254 obj
= hlist_entry(node
, struct drm_i915_gem_object
, exec_node
);
255 if (obj
->exec_handle
== handle
)
263 eb_destroy(struct eb_objects
*eb
)
268 static inline int use_cpu_reloc(struct drm_i915_gem_object
*obj
)
270 return (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
||
271 obj
->cache_level
!= I915_CACHE_NONE
);
275 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
276 struct eb_objects
*eb
,
277 struct drm_i915_gem_relocation_entry
*reloc
)
279 struct drm_device
*dev
= obj
->base
.dev
;
280 struct drm_gem_object
*target_obj
;
281 struct drm_i915_gem_object
*target_i915_obj
;
282 uint32_t target_offset
;
285 /* we've already hold a reference to all valid objects */
286 target_obj
= &eb_get_object(eb
, reloc
->target_handle
)->base
;
287 if (unlikely(target_obj
== NULL
))
290 target_i915_obj
= to_intel_bo(target_obj
);
291 target_offset
= target_i915_obj
->gtt_offset
;
293 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
294 * pipe_control writes because the gpu doesn't properly redirect them
295 * through the ppgtt for non_secure batchbuffers. */
296 if (unlikely(IS_GEN6(dev
) &&
297 reloc
->write_domain
== I915_GEM_DOMAIN_INSTRUCTION
&&
298 !target_i915_obj
->has_global_gtt_mapping
)) {
299 i915_gem_gtt_bind_object(target_i915_obj
,
300 target_i915_obj
->cache_level
);
303 /* The target buffer should have appeared before us in the
304 * exec_object list, so it should have a GTT space bound by now.
306 if (unlikely(target_offset
== 0)) {
307 DRM_DEBUG("No GTT space found for object %d\n",
308 reloc
->target_handle
);
312 /* Validate that the target is in a valid r/w GPU domain */
313 if (unlikely(reloc
->write_domain
& (reloc
->write_domain
- 1))) {
314 DRM_DEBUG("reloc with multiple write domains: "
315 "obj %p target %d offset %d "
316 "read %08x write %08x",
317 obj
, reloc
->target_handle
,
320 reloc
->write_domain
);
323 if (unlikely((reloc
->write_domain
| reloc
->read_domains
)
324 & ~I915_GEM_GPU_DOMAINS
)) {
325 DRM_DEBUG("reloc with read/write non-GPU domains: "
326 "obj %p target %d offset %d "
327 "read %08x write %08x",
328 obj
, reloc
->target_handle
,
331 reloc
->write_domain
);
334 if (unlikely(reloc
->write_domain
&& target_obj
->pending_write_domain
&&
335 reloc
->write_domain
!= target_obj
->pending_write_domain
)) {
336 DRM_DEBUG("Write domain conflict: "
337 "obj %p target %d offset %d "
338 "new %08x old %08x\n",
339 obj
, reloc
->target_handle
,
342 target_obj
->pending_write_domain
);
346 target_obj
->pending_read_domains
|= reloc
->read_domains
;
347 target_obj
->pending_write_domain
|= reloc
->write_domain
;
349 /* If the relocation already has the right value in it, no
350 * more work needs to be done.
352 if (target_offset
== reloc
->presumed_offset
)
355 /* Check that the relocation address is valid... */
356 if (unlikely(reloc
->offset
> obj
->base
.size
- 4)) {
357 DRM_DEBUG("Relocation beyond object bounds: "
358 "obj %p target %d offset %d size %d.\n",
359 obj
, reloc
->target_handle
,
361 (int) obj
->base
.size
);
364 if (unlikely(reloc
->offset
& 3)) {
365 DRM_DEBUG("Relocation not 4-byte aligned: "
366 "obj %p target %d offset %d.\n",
367 obj
, reloc
->target_handle
,
368 (int) reloc
->offset
);
372 /* We can't wait for rendering with pagefaults disabled */
373 if (obj
->active
&& in_atomic())
376 reloc
->delta
+= target_offset
;
377 if (use_cpu_reloc(obj
)) {
378 uint32_t page_offset
= reloc
->offset
& ~PAGE_MASK
;
381 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
385 vaddr
= kmap_atomic(obj
->pages
[reloc
->offset
>> PAGE_SHIFT
]);
386 *(uint32_t *)(vaddr
+ page_offset
) = reloc
->delta
;
387 kunmap_atomic(vaddr
);
389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
390 uint32_t __iomem
*reloc_entry
;
391 void __iomem
*reloc_page
;
393 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
397 ret
= i915_gem_object_put_fence(obj
);
401 /* Map the page containing the relocation we're going to perform. */
402 reloc
->offset
+= obj
->gtt_offset
;
403 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
404 reloc
->offset
& PAGE_MASK
);
405 reloc_entry
= (uint32_t __iomem
*)
406 (reloc_page
+ (reloc
->offset
& ~PAGE_MASK
));
407 iowrite32(reloc
->delta
, reloc_entry
);
408 io_mapping_unmap_atomic(reloc_page
);
411 /* and update the user's relocation entry */
412 reloc
->presumed_offset
= target_offset
;
418 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object
*obj
,
419 struct eb_objects
*eb
)
421 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
422 struct drm_i915_gem_relocation_entry stack_reloc
[N_RELOC(512)];
423 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
424 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
427 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
429 remain
= entry
->relocation_count
;
431 struct drm_i915_gem_relocation_entry
*r
= stack_reloc
;
433 if (count
> ARRAY_SIZE(stack_reloc
))
434 count
= ARRAY_SIZE(stack_reloc
);
437 if (__copy_from_user_inatomic(r
, user_relocs
, count
*sizeof(r
[0])))
441 u64 offset
= r
->presumed_offset
;
443 ret
= i915_gem_execbuffer_relocate_entry(obj
, eb
, r
);
447 if (r
->presumed_offset
!= offset
&&
448 __copy_to_user_inatomic(&user_relocs
->presumed_offset
,
450 sizeof(r
->presumed_offset
))) {
464 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object
*obj
,
465 struct eb_objects
*eb
,
466 struct drm_i915_gem_relocation_entry
*relocs
)
468 const struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
471 for (i
= 0; i
< entry
->relocation_count
; i
++) {
472 ret
= i915_gem_execbuffer_relocate_entry(obj
, eb
, &relocs
[i
]);
481 i915_gem_execbuffer_relocate(struct drm_device
*dev
,
482 struct eb_objects
*eb
,
483 struct list_head
*objects
)
485 struct drm_i915_gem_object
*obj
;
488 /* This is the fast path and we cannot handle a pagefault whilst
489 * holding the struct mutex lest the user pass in the relocations
490 * contained within a mmaped bo. For in such a case we, the page
491 * fault handler would call i915_gem_fault() and we would try to
492 * acquire the struct mutex again. Obviously this is bad and so
493 * lockdep complains vehemently.
496 list_for_each_entry(obj
, objects
, exec_list
) {
497 ret
= i915_gem_execbuffer_relocate_object(obj
, eb
);
506 #define __EXEC_OBJECT_HAS_FENCE (1<<31)
509 need_reloc_mappable(struct drm_i915_gem_object
*obj
)
511 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
512 return entry
->relocation_count
&& !use_cpu_reloc(obj
);
516 pin_and_fence_object(struct drm_i915_gem_object
*obj
,
517 struct intel_ring_buffer
*ring
)
519 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
520 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
521 bool need_fence
, need_mappable
;
525 has_fenced_gpu_access
&&
526 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
527 obj
->tiling_mode
!= I915_TILING_NONE
;
528 need_mappable
= need_fence
|| need_reloc_mappable(obj
);
530 ret
= i915_gem_object_pin(obj
, entry
->alignment
, need_mappable
);
534 if (has_fenced_gpu_access
) {
535 if (entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
) {
536 ret
= i915_gem_object_get_fence(obj
);
540 if (i915_gem_object_pin_fence(obj
))
541 entry
->flags
|= __EXEC_OBJECT_HAS_FENCE
;
543 obj
->pending_fenced_gpu_access
= true;
547 entry
->offset
= obj
->gtt_offset
;
551 i915_gem_object_unpin(obj
);
556 i915_gem_execbuffer_reserve(struct intel_ring_buffer
*ring
,
557 struct drm_file
*file
,
558 struct list_head
*objects
)
560 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
561 struct drm_i915_gem_object
*obj
;
563 bool has_fenced_gpu_access
= INTEL_INFO(ring
->dev
)->gen
< 4;
564 struct list_head ordered_objects
;
566 INIT_LIST_HEAD(&ordered_objects
);
567 while (!list_empty(objects
)) {
568 struct drm_i915_gem_exec_object2
*entry
;
569 bool need_fence
, need_mappable
;
571 obj
= list_first_entry(objects
,
572 struct drm_i915_gem_object
,
574 entry
= obj
->exec_entry
;
577 has_fenced_gpu_access
&&
578 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
579 obj
->tiling_mode
!= I915_TILING_NONE
;
580 need_mappable
= need_fence
|| need_reloc_mappable(obj
);
583 list_move(&obj
->exec_list
, &ordered_objects
);
585 list_move_tail(&obj
->exec_list
, &ordered_objects
);
587 obj
->base
.pending_read_domains
= 0;
588 obj
->base
.pending_write_domain
= 0;
590 list_splice(&ordered_objects
, objects
);
592 /* Attempt to pin all of the buffers into the GTT.
593 * This is done in 3 phases:
595 * 1a. Unbind all objects that do not match the GTT constraints for
596 * the execbuffer (fenceable, mappable, alignment etc).
597 * 1b. Increment pin count for already bound objects.
598 * 2. Bind new objects.
599 * 3. Decrement pin count.
601 * This avoid unnecessary unbinding of later objects in order to makr
602 * room for the earlier objects *unless* we need to defragment.
608 /* Unbind any ill-fitting objects or pin. */
609 list_for_each_entry(obj
, objects
, exec_list
) {
610 struct drm_i915_gem_exec_object2
*entry
= obj
->exec_entry
;
611 bool need_fence
, need_mappable
;
617 has_fenced_gpu_access
&&
618 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
619 obj
->tiling_mode
!= I915_TILING_NONE
;
620 need_mappable
= need_fence
|| need_reloc_mappable(obj
);
622 if ((entry
->alignment
&& obj
->gtt_offset
& (entry
->alignment
- 1)) ||
623 (need_mappable
&& !obj
->map_and_fenceable
))
624 ret
= i915_gem_object_unbind(obj
);
626 ret
= pin_and_fence_object(obj
, ring
);
631 /* Bind fresh objects */
632 list_for_each_entry(obj
, objects
, exec_list
) {
636 ret
= pin_and_fence_object(obj
, ring
);
640 /* This can potentially raise a harmless
641 * -EINVAL if we failed to bind in the above
642 * call. It cannot raise -EINTR since we know
643 * that the bo is freshly bound and so will
644 * not need to be flushed or waited upon.
646 ret_ignore
= i915_gem_object_unbind(obj
);
648 WARN_ON(obj
->gtt_space
);
653 /* Decrement pin count for bound objects */
654 list_for_each_entry(obj
, objects
, exec_list
) {
655 struct drm_i915_gem_exec_object2
*entry
;
660 entry
= obj
->exec_entry
;
661 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
) {
662 i915_gem_object_unpin_fence(obj
);
663 entry
->flags
&= ~__EXEC_OBJECT_HAS_FENCE
;
666 i915_gem_object_unpin(obj
);
668 /* ... and ensure ppgtt mapping exist if needed. */
669 if (dev_priv
->mm
.aliasing_ppgtt
&& !obj
->has_aliasing_ppgtt_mapping
) {
670 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
671 obj
, obj
->cache_level
);
673 obj
->has_aliasing_ppgtt_mapping
= 1;
677 if (ret
!= -ENOSPC
|| retry
> 1)
680 /* First attempt, just clear anything that is purgeable.
681 * Second attempt, clear the entire GTT.
683 ret
= i915_gem_evict_everything(ring
->dev
, retry
== 0);
691 list_for_each_entry_continue_reverse(obj
, objects
, exec_list
) {
692 struct drm_i915_gem_exec_object2
*entry
;
697 entry
= obj
->exec_entry
;
698 if (entry
->flags
& __EXEC_OBJECT_HAS_FENCE
) {
699 i915_gem_object_unpin_fence(obj
);
700 entry
->flags
&= ~__EXEC_OBJECT_HAS_FENCE
;
703 i915_gem_object_unpin(obj
);
710 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
711 struct drm_file
*file
,
712 struct intel_ring_buffer
*ring
,
713 struct list_head
*objects
,
714 struct eb_objects
*eb
,
715 struct drm_i915_gem_exec_object2
*exec
,
718 struct drm_i915_gem_relocation_entry
*reloc
;
719 struct drm_i915_gem_object
*obj
;
723 /* We may process another execbuffer during the unlock... */
724 while (!list_empty(objects
)) {
725 obj
= list_first_entry(objects
,
726 struct drm_i915_gem_object
,
728 list_del_init(&obj
->exec_list
);
729 drm_gem_object_unreference(&obj
->base
);
732 mutex_unlock(&dev
->struct_mutex
);
735 for (i
= 0; i
< count
; i
++)
736 total
+= exec
[i
].relocation_count
;
738 reloc_offset
= drm_malloc_ab(count
, sizeof(*reloc_offset
));
739 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
740 if (reloc
== NULL
|| reloc_offset
== NULL
) {
741 drm_free_large(reloc
);
742 drm_free_large(reloc_offset
);
743 mutex_lock(&dev
->struct_mutex
);
748 for (i
= 0; i
< count
; i
++) {
749 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
751 user_relocs
= (void __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
753 if (copy_from_user(reloc
+total
, user_relocs
,
754 exec
[i
].relocation_count
* sizeof(*reloc
))) {
756 mutex_lock(&dev
->struct_mutex
);
760 reloc_offset
[i
] = total
;
761 total
+= exec
[i
].relocation_count
;
764 ret
= i915_mutex_lock_interruptible(dev
);
766 mutex_lock(&dev
->struct_mutex
);
770 /* reacquire the objects */
772 for (i
= 0; i
< count
; i
++) {
773 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
,
775 if (&obj
->base
== NULL
) {
776 DRM_DEBUG("Invalid object handle %d at index %d\n",
782 list_add_tail(&obj
->exec_list
, objects
);
783 obj
->exec_handle
= exec
[i
].handle
;
784 obj
->exec_entry
= &exec
[i
];
785 eb_add_object(eb
, obj
);
788 ret
= i915_gem_execbuffer_reserve(ring
, file
, objects
);
792 list_for_each_entry(obj
, objects
, exec_list
) {
793 int offset
= obj
->exec_entry
- exec
;
794 ret
= i915_gem_execbuffer_relocate_object_slow(obj
, eb
,
795 reloc
+ reloc_offset
[offset
]);
800 /* Leave the user relocations as are, this is the painfully slow path,
801 * and we want to avoid the complication of dropping the lock whilst
802 * having buffers reserved in the aperture and so causing spurious
803 * ENOSPC for random operations.
807 drm_free_large(reloc
);
808 drm_free_large(reloc_offset
);
813 i915_gem_execbuffer_flush(struct drm_device
*dev
,
814 uint32_t invalidate_domains
,
815 uint32_t flush_domains
)
817 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
818 intel_gtt_chipset_flush();
820 if (flush_domains
& I915_GEM_DOMAIN_GTT
)
825 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer
*ring
, u32 flips
)
827 u32 plane
, flip_mask
;
830 /* Check for any pending flips. As we only maintain a flip queue depth
831 * of 1, we can simply insert a WAIT for the next display flip prior
832 * to executing the batch and avoid stalling the CPU.
835 for (plane
= 0; flips
>> plane
; plane
++) {
836 if (((flips
>> plane
) & 1) == 0)
840 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
842 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
844 ret
= intel_ring_begin(ring
, 2);
848 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
849 intel_ring_emit(ring
, MI_NOOP
);
850 intel_ring_advance(ring
);
858 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer
*ring
,
859 struct list_head
*objects
)
861 struct drm_i915_gem_object
*obj
;
862 struct change_domains cd
;
865 memset(&cd
, 0, sizeof(cd
));
866 list_for_each_entry(obj
, objects
, exec_list
)
867 i915_gem_object_set_to_gpu_domain(obj
, ring
, &cd
);
869 if (cd
.invalidate_domains
| cd
.flush_domains
) {
870 i915_gem_execbuffer_flush(ring
->dev
,
871 cd
.invalidate_domains
,
876 ret
= i915_gem_execbuffer_wait_for_flips(ring
, cd
.flips
);
881 list_for_each_entry(obj
, objects
, exec_list
) {
882 ret
= i915_gem_object_sync(obj
, ring
);
887 /* Unconditionally invalidate gpu caches and ensure that we do flush
888 * any residual writes from the previous batch.
890 ret
= i915_gem_flush_ring(ring
,
891 I915_GEM_GPU_DOMAINS
,
892 ring
->gpu_caches_dirty
? I915_GEM_GPU_DOMAINS
: 0);
896 ring
->gpu_caches_dirty
= false;
901 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
)
903 return ((exec
->batch_start_offset
| exec
->batch_len
) & 0x7) == 0;
907 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
912 for (i
= 0; i
< count
; i
++) {
913 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
914 int length
; /* limited by fault_in_pages_readable() */
916 /* First check for malicious input causing overflow */
917 if (exec
[i
].relocation_count
>
918 INT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
))
921 length
= exec
[i
].relocation_count
*
922 sizeof(struct drm_i915_gem_relocation_entry
);
923 if (!access_ok(VERIFY_READ
, ptr
, length
))
926 /* we may also need to update the presumed offsets */
927 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
930 if (fault_in_multipages_readable(ptr
, length
))
938 i915_gem_execbuffer_move_to_active(struct list_head
*objects
,
939 struct intel_ring_buffer
*ring
,
942 struct drm_i915_gem_object
*obj
;
944 list_for_each_entry(obj
, objects
, exec_list
) {
945 u32 old_read
= obj
->base
.read_domains
;
946 u32 old_write
= obj
->base
.write_domain
;
949 obj
->base
.read_domains
= obj
->base
.pending_read_domains
;
950 obj
->base
.write_domain
= obj
->base
.pending_write_domain
;
951 obj
->fenced_gpu_access
= obj
->pending_fenced_gpu_access
;
953 i915_gem_object_move_to_active(obj
, ring
, seqno
);
954 if (obj
->base
.write_domain
) {
956 obj
->pending_gpu_write
= true;
957 list_move_tail(&obj
->gpu_write_list
,
958 &ring
->gpu_write_list
);
959 if (obj
->pin_count
) /* check for potential scanout */
960 intel_mark_busy(ring
->dev
, obj
);
963 trace_i915_gem_object_change_domain(obj
, old_read
, old_write
);
966 intel_mark_busy(ring
->dev
, NULL
);
970 i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
971 struct drm_file
*file
,
972 struct intel_ring_buffer
*ring
)
974 struct drm_i915_gem_request
*request
;
976 /* Unconditionally force add_request to emit a full flush. */
977 ring
->gpu_caches_dirty
= true;
979 /* Add a breadcrumb for the completion of the batch buffer */
980 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
981 if (request
== NULL
|| i915_add_request(ring
, file
, request
)) {
987 i915_reset_gen7_sol_offsets(struct drm_device
*dev
,
988 struct intel_ring_buffer
*ring
)
990 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
993 if (!IS_GEN7(dev
) || ring
!= &dev_priv
->ring
[RCS
])
996 ret
= intel_ring_begin(ring
, 4 * 3);
1000 for (i
= 0; i
< 4; i
++) {
1001 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1002 intel_ring_emit(ring
, GEN7_SO_WRITE_OFFSET(i
));
1003 intel_ring_emit(ring
, 0);
1006 intel_ring_advance(ring
);
1012 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
1013 struct drm_file
*file
,
1014 struct drm_i915_gem_execbuffer2
*args
,
1015 struct drm_i915_gem_exec_object2
*exec
)
1017 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1018 struct list_head objects
;
1019 struct eb_objects
*eb
;
1020 struct drm_i915_gem_object
*batch_obj
;
1021 struct drm_clip_rect
*cliprects
= NULL
;
1022 struct intel_ring_buffer
*ring
;
1023 u32 ctx_id
= i915_execbuffer2_get_context_id(*args
);
1024 u32 exec_start
, exec_len
;
1029 if (!i915_gem_check_execbuffer(args
)) {
1030 DRM_DEBUG("execbuf with invalid offset/length\n");
1034 ret
= validate_exec_list(exec
, args
->buffer_count
);
1038 switch (args
->flags
& I915_EXEC_RING_MASK
) {
1039 case I915_EXEC_DEFAULT
:
1040 case I915_EXEC_RENDER
:
1041 ring
= &dev_priv
->ring
[RCS
];
1044 ring
= &dev_priv
->ring
[VCS
];
1046 DRM_DEBUG("Ring %s doesn't support contexts\n",
1052 ring
= &dev_priv
->ring
[BCS
];
1054 DRM_DEBUG("Ring %s doesn't support contexts\n",
1060 DRM_DEBUG("execbuf with unknown ring: %d\n",
1061 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1064 if (!intel_ring_initialized(ring
)) {
1065 DRM_DEBUG("execbuf with invalid ring: %d\n",
1066 (int)(args
->flags
& I915_EXEC_RING_MASK
));
1070 mode
= args
->flags
& I915_EXEC_CONSTANTS_MASK
;
1071 mask
= I915_EXEC_CONSTANTS_MASK
;
1073 case I915_EXEC_CONSTANTS_REL_GENERAL
:
1074 case I915_EXEC_CONSTANTS_ABSOLUTE
:
1075 case I915_EXEC_CONSTANTS_REL_SURFACE
:
1076 if (ring
== &dev_priv
->ring
[RCS
] &&
1077 mode
!= dev_priv
->relative_constants_mode
) {
1078 if (INTEL_INFO(dev
)->gen
< 4)
1081 if (INTEL_INFO(dev
)->gen
> 5 &&
1082 mode
== I915_EXEC_CONSTANTS_REL_SURFACE
)
1085 /* The HW changed the meaning on this bit on gen6 */
1086 if (INTEL_INFO(dev
)->gen
>= 6)
1087 mask
&= ~I915_EXEC_CONSTANTS_REL_SURFACE
;
1091 DRM_DEBUG("execbuf with unknown constants: %d\n", mode
);
1095 if (args
->buffer_count
< 1) {
1096 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1100 if (args
->num_cliprects
!= 0) {
1101 if (ring
!= &dev_priv
->ring
[RCS
]) {
1102 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1106 if (INTEL_INFO(dev
)->gen
>= 5) {
1107 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
1111 if (args
->num_cliprects
> UINT_MAX
/ sizeof(*cliprects
)) {
1112 DRM_DEBUG("execbuf with %u cliprects\n",
1113 args
->num_cliprects
);
1117 cliprects
= kmalloc(args
->num_cliprects
* sizeof(*cliprects
),
1119 if (cliprects
== NULL
) {
1124 if (copy_from_user(cliprects
,
1125 (struct drm_clip_rect __user
*)(uintptr_t)
1126 args
->cliprects_ptr
,
1127 sizeof(*cliprects
)*args
->num_cliprects
)) {
1133 ret
= i915_mutex_lock_interruptible(dev
);
1137 if (dev_priv
->mm
.suspended
) {
1138 mutex_unlock(&dev
->struct_mutex
);
1143 eb
= eb_create(args
->buffer_count
);
1145 mutex_unlock(&dev
->struct_mutex
);
1150 /* Look up object handles */
1151 INIT_LIST_HEAD(&objects
);
1152 for (i
= 0; i
< args
->buffer_count
; i
++) {
1153 struct drm_i915_gem_object
*obj
;
1155 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
,
1157 if (&obj
->base
== NULL
) {
1158 DRM_DEBUG("Invalid object handle %d at index %d\n",
1160 /* prevent error path from reading uninitialized data */
1165 if (!list_empty(&obj
->exec_list
)) {
1166 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
1167 obj
, exec
[i
].handle
, i
);
1172 list_add_tail(&obj
->exec_list
, &objects
);
1173 obj
->exec_handle
= exec
[i
].handle
;
1174 obj
->exec_entry
= &exec
[i
];
1175 eb_add_object(eb
, obj
);
1178 /* take note of the batch buffer before we might reorder the lists */
1179 batch_obj
= list_entry(objects
.prev
,
1180 struct drm_i915_gem_object
,
1183 /* Move the objects en-masse into the GTT, evicting if necessary. */
1184 ret
= i915_gem_execbuffer_reserve(ring
, file
, &objects
);
1188 /* The objects are in their final locations, apply the relocations. */
1189 ret
= i915_gem_execbuffer_relocate(dev
, eb
, &objects
);
1191 if (ret
== -EFAULT
) {
1192 ret
= i915_gem_execbuffer_relocate_slow(dev
, file
, ring
,
1195 args
->buffer_count
);
1196 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1202 /* Set the pending read domains for the batch buffer to COMMAND */
1203 if (batch_obj
->base
.pending_write_domain
) {
1204 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1208 batch_obj
->base
.pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
1210 ret
= i915_gem_execbuffer_move_to_gpu(ring
, &objects
);
1214 seqno
= i915_gem_next_request_seqno(ring
);
1215 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++) {
1216 if (seqno
< ring
->sync_seqno
[i
]) {
1217 /* The GPU can not handle its semaphore value wrapping,
1218 * so every billion or so execbuffers, we need to stall
1219 * the GPU in order to reset the counters.
1221 ret
= i915_gpu_idle(dev
);
1224 i915_gem_retire_requests(dev
);
1226 BUG_ON(ring
->sync_seqno
[i
]);
1230 ret
= i915_switch_context(ring
, file
, ctx_id
);
1234 if (ring
== &dev_priv
->ring
[RCS
] &&
1235 mode
!= dev_priv
->relative_constants_mode
) {
1236 ret
= intel_ring_begin(ring
, 4);
1240 intel_ring_emit(ring
, MI_NOOP
);
1241 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1242 intel_ring_emit(ring
, INSTPM
);
1243 intel_ring_emit(ring
, mask
<< 16 | mode
);
1244 intel_ring_advance(ring
);
1246 dev_priv
->relative_constants_mode
= mode
;
1249 if (args
->flags
& I915_EXEC_GEN7_SOL_RESET
) {
1250 ret
= i915_reset_gen7_sol_offsets(dev
, ring
);
1255 trace_i915_gem_ring_dispatch(ring
, seqno
);
1257 exec_start
= batch_obj
->gtt_offset
+ args
->batch_start_offset
;
1258 exec_len
= args
->batch_len
;
1260 for (i
= 0; i
< args
->num_cliprects
; i
++) {
1261 ret
= i915_emit_box(dev
, &cliprects
[i
],
1262 args
->DR1
, args
->DR4
);
1266 ret
= ring
->dispatch_execbuffer(ring
,
1267 exec_start
, exec_len
);
1272 ret
= ring
->dispatch_execbuffer(ring
, exec_start
, exec_len
);
1277 i915_gem_execbuffer_move_to_active(&objects
, ring
, seqno
);
1278 i915_gem_execbuffer_retire_commands(dev
, file
, ring
);
1282 while (!list_empty(&objects
)) {
1283 struct drm_i915_gem_object
*obj
;
1285 obj
= list_first_entry(&objects
,
1286 struct drm_i915_gem_object
,
1288 list_del_init(&obj
->exec_list
);
1289 drm_gem_object_unreference(&obj
->base
);
1292 mutex_unlock(&dev
->struct_mutex
);
1300 * Legacy execbuffer just creates an exec2 list from the original exec object
1301 * list array and passes it to the real function.
1304 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1305 struct drm_file
*file
)
1307 struct drm_i915_gem_execbuffer
*args
= data
;
1308 struct drm_i915_gem_execbuffer2 exec2
;
1309 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
1310 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1313 if (args
->buffer_count
< 1) {
1314 DRM_DEBUG("execbuf with %d buffers\n", args
->buffer_count
);
1318 /* Copy in the exec list from userland */
1319 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
1320 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
1321 if (exec_list
== NULL
|| exec2_list
== NULL
) {
1322 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1323 args
->buffer_count
);
1324 drm_free_large(exec_list
);
1325 drm_free_large(exec2_list
);
1328 ret
= copy_from_user(exec_list
,
1329 (struct drm_i915_relocation_entry __user
*)
1330 (uintptr_t) args
->buffers_ptr
,
1331 sizeof(*exec_list
) * args
->buffer_count
);
1333 DRM_DEBUG("copy %d exec entries failed %d\n",
1334 args
->buffer_count
, ret
);
1335 drm_free_large(exec_list
);
1336 drm_free_large(exec2_list
);
1340 for (i
= 0; i
< args
->buffer_count
; i
++) {
1341 exec2_list
[i
].handle
= exec_list
[i
].handle
;
1342 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
1343 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
1344 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
1345 exec2_list
[i
].offset
= exec_list
[i
].offset
;
1346 if (INTEL_INFO(dev
)->gen
< 4)
1347 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
1349 exec2_list
[i
].flags
= 0;
1352 exec2
.buffers_ptr
= args
->buffers_ptr
;
1353 exec2
.buffer_count
= args
->buffer_count
;
1354 exec2
.batch_start_offset
= args
->batch_start_offset
;
1355 exec2
.batch_len
= args
->batch_len
;
1356 exec2
.DR1
= args
->DR1
;
1357 exec2
.DR4
= args
->DR4
;
1358 exec2
.num_cliprects
= args
->num_cliprects
;
1359 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
1360 exec2
.flags
= I915_EXEC_RENDER
;
1361 i915_execbuffer2_set_context_id(exec2
, 0);
1363 ret
= i915_gem_do_execbuffer(dev
, data
, file
, &exec2
, exec2_list
);
1365 /* Copy the new buffer offsets back to the user's exec list. */
1366 for (i
= 0; i
< args
->buffer_count
; i
++)
1367 exec_list
[i
].offset
= exec2_list
[i
].offset
;
1368 /* ... and back out to userspace */
1369 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
1370 (uintptr_t) args
->buffers_ptr
,
1372 sizeof(*exec_list
) * args
->buffer_count
);
1375 DRM_DEBUG("failed to copy %d exec entries "
1376 "back to user (%d)\n",
1377 args
->buffer_count
, ret
);
1381 drm_free_large(exec_list
);
1382 drm_free_large(exec2_list
);
1387 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1388 struct drm_file
*file
)
1390 struct drm_i915_gem_execbuffer2
*args
= data
;
1391 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
1394 if (args
->buffer_count
< 1 ||
1395 args
->buffer_count
> UINT_MAX
/ sizeof(*exec2_list
)) {
1396 DRM_DEBUG("execbuf2 with %d buffers\n", args
->buffer_count
);
1400 exec2_list
= kmalloc(sizeof(*exec2_list
)*args
->buffer_count
,
1401 GFP_KERNEL
| __GFP_NOWARN
| __GFP_NORETRY
);
1402 if (exec2_list
== NULL
)
1403 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
),
1404 args
->buffer_count
);
1405 if (exec2_list
== NULL
) {
1406 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1407 args
->buffer_count
);
1410 ret
= copy_from_user(exec2_list
,
1411 (struct drm_i915_relocation_entry __user
*)
1412 (uintptr_t) args
->buffers_ptr
,
1413 sizeof(*exec2_list
) * args
->buffer_count
);
1415 DRM_DEBUG("copy %d exec entries failed %d\n",
1416 args
->buffer_count
, ret
);
1417 drm_free_large(exec2_list
);
1421 ret
= i915_gem_do_execbuffer(dev
, data
, file
, args
, exec2_list
);
1423 /* Copy the new buffer offsets back to the user's exec list. */
1424 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
1425 (uintptr_t) args
->buffers_ptr
,
1427 sizeof(*exec2_list
) * args
->buffer_count
);
1430 DRM_DEBUG("failed to copy %d exec entries "
1431 "back to user (%d)\n",
1432 args
->buffer_count
, ret
);
1436 drm_free_large(exec2_list
);