2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
42 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
44 bool map_and_fenceable
);
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
90 i915_gem_wait_for_error(struct drm_device
*dev
)
92 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 struct completion
*x
= &dev_priv
->error_completion
;
97 if (!atomic_read(&dev_priv
->mm
.wedged
))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret
= wait_for_completion_interruptible_timeout(x
, 10*HZ
);
107 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
109 } else if (ret
< 0) {
113 if (atomic_read(&dev_priv
->mm
.wedged
)) {
114 /* GPU is hung, bump the completion count to account for
115 * the token we just consumed so that we never hit zero and
116 * end up waiting upon a subsequent completion event that
119 spin_lock_irqsave(&x
->wait
.lock
, flags
);
121 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
126 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
130 ret
= i915_gem_wait_for_error(dev
);
134 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
138 WARN_ON(i915_verify_lists(dev
));
143 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
145 return obj
->gtt_space
&& !obj
->active
;
149 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
150 struct drm_file
*file
)
152 struct drm_i915_gem_init
*args
= data
;
154 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
157 if (args
->gtt_start
>= args
->gtt_end
||
158 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev
)->gen
>= 5)
165 mutex_lock(&dev
->struct_mutex
);
166 i915_gem_init_global_gtt(dev
, args
->gtt_start
,
167 args
->gtt_end
, args
->gtt_end
);
168 mutex_unlock(&dev
->struct_mutex
);
174 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
175 struct drm_file
*file
)
177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
178 struct drm_i915_gem_get_aperture
*args
= data
;
179 struct drm_i915_gem_object
*obj
;
183 mutex_lock(&dev
->struct_mutex
);
184 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
186 pinned
+= obj
->gtt_space
->size
;
187 mutex_unlock(&dev
->struct_mutex
);
189 args
->aper_size
= dev_priv
->mm
.gtt_total
;
190 args
->aper_available_size
= args
->aper_size
- pinned
;
196 i915_gem_create(struct drm_file
*file
,
197 struct drm_device
*dev
,
201 struct drm_i915_gem_object
*obj
;
205 size
= roundup(size
, PAGE_SIZE
);
209 /* Allocate the new object */
210 obj
= i915_gem_alloc_object(dev
, size
);
214 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
216 drm_gem_object_release(&obj
->base
);
217 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
222 /* drop reference from allocate - handle holds it now */
223 drm_gem_object_unreference(&obj
->base
);
224 trace_i915_gem_object_create(obj
);
231 i915_gem_dumb_create(struct drm_file
*file
,
232 struct drm_device
*dev
,
233 struct drm_mode_create_dumb
*args
)
235 /* have to work out size/pitch and return them */
236 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
237 args
->size
= args
->pitch
* args
->height
;
238 return i915_gem_create(file
, dev
,
239 args
->size
, &args
->handle
);
242 int i915_gem_dumb_destroy(struct drm_file
*file
,
243 struct drm_device
*dev
,
246 return drm_gem_handle_delete(file
, handle
);
250 * Creates a new mm object and returns a handle to it.
253 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
254 struct drm_file
*file
)
256 struct drm_i915_gem_create
*args
= data
;
258 return i915_gem_create(file
, dev
,
259 args
->size
, &args
->handle
);
262 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
264 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
266 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
267 obj
->tiling_mode
!= I915_TILING_NONE
;
271 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
272 const char *gpu_vaddr
, int gpu_offset
,
275 int ret
, cpu_offset
= 0;
278 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
279 int this_length
= min(cacheline_end
- gpu_offset
, length
);
280 int swizzled_gpu_offset
= gpu_offset
^ 64;
282 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
283 gpu_vaddr
+ swizzled_gpu_offset
,
288 cpu_offset
+= this_length
;
289 gpu_offset
+= this_length
;
290 length
-= this_length
;
297 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
298 const char __user
*cpu_vaddr
,
301 int ret
, cpu_offset
= 0;
304 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
305 int this_length
= min(cacheline_end
- gpu_offset
, length
);
306 int swizzled_gpu_offset
= gpu_offset
^ 64;
308 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
309 cpu_vaddr
+ cpu_offset
,
314 cpu_offset
+= this_length
;
315 gpu_offset
+= this_length
;
316 length
-= this_length
;
322 /* Per-page copy function for the shmem pread fastpath.
323 * Flushes invalid cachelines before reading the target if
324 * needs_clflush is set. */
326 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
327 char __user
*user_data
,
328 bool page_do_bit17_swizzling
, bool needs_clflush
)
333 if (unlikely(page_do_bit17_swizzling
))
336 vaddr
= kmap_atomic(page
);
338 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
340 ret
= __copy_to_user_inatomic(user_data
,
341 vaddr
+ shmem_page_offset
,
343 kunmap_atomic(vaddr
);
349 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
352 if (unlikely(swizzled
)) {
353 unsigned long start
= (unsigned long) addr
;
354 unsigned long end
= (unsigned long) addr
+ length
;
356 /* For swizzling simply ensure that we always flush both
357 * channels. Lame, but simple and it works. Swizzled
358 * pwrite/pread is far from a hotpath - current userspace
359 * doesn't use it at all. */
360 start
= round_down(start
, 128);
361 end
= round_up(end
, 128);
363 drm_clflush_virt_range((void *)start
, end
- start
);
365 drm_clflush_virt_range(addr
, length
);
370 /* Only difference to the fast-path function is that this can handle bit17
371 * and uses non-atomic copy and kmap functions. */
373 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
374 char __user
*user_data
,
375 bool page_do_bit17_swizzling
, bool needs_clflush
)
382 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
384 page_do_bit17_swizzling
);
386 if (page_do_bit17_swizzling
)
387 ret
= __copy_to_user_swizzled(user_data
,
388 vaddr
, shmem_page_offset
,
391 ret
= __copy_to_user(user_data
,
392 vaddr
+ shmem_page_offset
,
400 i915_gem_shmem_pread(struct drm_device
*dev
,
401 struct drm_i915_gem_object
*obj
,
402 struct drm_i915_gem_pread
*args
,
403 struct drm_file
*file
)
405 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
406 char __user
*user_data
;
409 int shmem_page_offset
, page_length
, ret
= 0;
410 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
411 int hit_slowpath
= 0;
413 int needs_clflush
= 0;
416 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
419 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
421 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
422 /* If we're not in the cpu read domain, set ourself into the gtt
423 * read domain and manually flush cachelines (if required). This
424 * optimizes for the case when the gpu will dirty the data
425 * anyway again before the next pread happens. */
426 if (obj
->cache_level
== I915_CACHE_NONE
)
428 if (obj
->gtt_space
) {
429 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
435 offset
= args
->offset
;
440 /* Operation in this page
442 * shmem_page_offset = offset within page in shmem file
443 * page_length = bytes to copy for this page
445 shmem_page_offset
= offset_in_page(offset
);
446 page_length
= remain
;
447 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
448 page_length
= PAGE_SIZE
- shmem_page_offset
;
451 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
454 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
462 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
463 (page_to_phys(page
) & (1 << 17)) != 0;
465 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
466 user_data
, page_do_bit17_swizzling
,
472 page_cache_get(page
);
473 mutex_unlock(&dev
->struct_mutex
);
476 ret
= fault_in_multipages_writeable(user_data
, remain
);
477 /* Userspace is tricking us, but we've already clobbered
478 * its pages with the prefault and promised to write the
479 * data up to the first fault. Hence ignore any errors
480 * and just continue. */
485 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
486 user_data
, page_do_bit17_swizzling
,
489 mutex_lock(&dev
->struct_mutex
);
490 page_cache_release(page
);
492 mark_page_accessed(page
);
494 page_cache_release(page
);
501 remain
-= page_length
;
502 user_data
+= page_length
;
503 offset
+= page_length
;
508 /* Fixup: Kill any reinstated backing storage pages */
509 if (obj
->madv
== __I915_MADV_PURGED
)
510 i915_gem_object_truncate(obj
);
517 * Reads data from the object referenced by handle.
519 * On error, the contents of *data are undefined.
522 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
523 struct drm_file
*file
)
525 struct drm_i915_gem_pread
*args
= data
;
526 struct drm_i915_gem_object
*obj
;
532 if (!access_ok(VERIFY_WRITE
,
533 (char __user
*)(uintptr_t)args
->data_ptr
,
537 ret
= i915_mutex_lock_interruptible(dev
);
541 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
542 if (&obj
->base
== NULL
) {
547 /* Bounds check source. */
548 if (args
->offset
> obj
->base
.size
||
549 args
->size
> obj
->base
.size
- args
->offset
) {
554 /* prime objects have no backing filp to GEM pread/pwrite
557 if (!obj
->base
.filp
) {
562 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
564 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
567 drm_gem_object_unreference(&obj
->base
);
569 mutex_unlock(&dev
->struct_mutex
);
573 /* This is the fast write path which cannot handle
574 * page faults in the source data
578 fast_user_write(struct io_mapping
*mapping
,
579 loff_t page_base
, int page_offset
,
580 char __user
*user_data
,
583 void __iomem
*vaddr_atomic
;
585 unsigned long unwritten
;
587 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
588 /* We can use the cpu mem copy function because this is X86. */
589 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
590 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
592 io_mapping_unmap_atomic(vaddr_atomic
);
597 * This is the fast pwrite path, where we copy the data directly from the
598 * user into the GTT, uncached.
601 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
602 struct drm_i915_gem_object
*obj
,
603 struct drm_i915_gem_pwrite
*args
,
604 struct drm_file
*file
)
606 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
608 loff_t offset
, page_base
;
609 char __user
*user_data
;
610 int page_offset
, page_length
, ret
;
612 ret
= i915_gem_object_pin(obj
, 0, true);
616 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
620 ret
= i915_gem_object_put_fence(obj
);
624 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
627 offset
= obj
->gtt_offset
+ args
->offset
;
630 /* Operation in this page
632 * page_base = page offset within aperture
633 * page_offset = offset within page
634 * page_length = bytes to copy for this page
636 page_base
= offset
& PAGE_MASK
;
637 page_offset
= offset_in_page(offset
);
638 page_length
= remain
;
639 if ((page_offset
+ remain
) > PAGE_SIZE
)
640 page_length
= PAGE_SIZE
- page_offset
;
642 /* If we get a fault while copying data, then (presumably) our
643 * source page isn't available. Return the error and we'll
644 * retry in the slow path.
646 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
647 page_offset
, user_data
, page_length
)) {
652 remain
-= page_length
;
653 user_data
+= page_length
;
654 offset
+= page_length
;
658 i915_gem_object_unpin(obj
);
663 /* Per-page copy function for the shmem pwrite fastpath.
664 * Flushes invalid cachelines before writing to the target if
665 * needs_clflush_before is set and flushes out any written cachelines after
666 * writing if needs_clflush is set. */
668 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
669 char __user
*user_data
,
670 bool page_do_bit17_swizzling
,
671 bool needs_clflush_before
,
672 bool needs_clflush_after
)
677 if (unlikely(page_do_bit17_swizzling
))
680 vaddr
= kmap_atomic(page
);
681 if (needs_clflush_before
)
682 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
684 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
687 if (needs_clflush_after
)
688 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
690 kunmap_atomic(vaddr
);
695 /* Only difference to the fast-path function is that this can handle bit17
696 * and uses non-atomic copy and kmap functions. */
698 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
699 char __user
*user_data
,
700 bool page_do_bit17_swizzling
,
701 bool needs_clflush_before
,
702 bool needs_clflush_after
)
708 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
709 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
711 page_do_bit17_swizzling
);
712 if (page_do_bit17_swizzling
)
713 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
717 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
720 if (needs_clflush_after
)
721 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
723 page_do_bit17_swizzling
);
730 i915_gem_shmem_pwrite(struct drm_device
*dev
,
731 struct drm_i915_gem_object
*obj
,
732 struct drm_i915_gem_pwrite
*args
,
733 struct drm_file
*file
)
735 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
738 char __user
*user_data
;
739 int shmem_page_offset
, page_length
, ret
= 0;
740 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
741 int hit_slowpath
= 0;
742 int needs_clflush_after
= 0;
743 int needs_clflush_before
= 0;
746 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
749 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
751 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
752 /* If we're not in the cpu write domain, set ourself into the gtt
753 * write domain and manually flush cachelines (if required). This
754 * optimizes for the case when the gpu will use the data
755 * right away and we therefore have to clflush anyway. */
756 if (obj
->cache_level
== I915_CACHE_NONE
)
757 needs_clflush_after
= 1;
758 if (obj
->gtt_space
) {
759 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
764 /* Same trick applies for invalidate partially written cachelines before
766 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
767 && obj
->cache_level
== I915_CACHE_NONE
)
768 needs_clflush_before
= 1;
770 offset
= args
->offset
;
775 int partial_cacheline_write
;
777 /* Operation in this page
779 * shmem_page_offset = offset within page in shmem file
780 * page_length = bytes to copy for this page
782 shmem_page_offset
= offset_in_page(offset
);
784 page_length
= remain
;
785 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
786 page_length
= PAGE_SIZE
- shmem_page_offset
;
788 /* If we don't overwrite a cacheline completely we need to be
789 * careful to have up-to-date data by first clflushing. Don't
790 * overcomplicate things and flush the entire patch. */
791 partial_cacheline_write
= needs_clflush_before
&&
792 ((shmem_page_offset
| page_length
)
793 & (boot_cpu_data
.x86_clflush_size
- 1));
796 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
799 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
807 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
808 (page_to_phys(page
) & (1 << 17)) != 0;
810 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
811 user_data
, page_do_bit17_swizzling
,
812 partial_cacheline_write
,
813 needs_clflush_after
);
818 page_cache_get(page
);
819 mutex_unlock(&dev
->struct_mutex
);
821 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
822 user_data
, page_do_bit17_swizzling
,
823 partial_cacheline_write
,
824 needs_clflush_after
);
826 mutex_lock(&dev
->struct_mutex
);
827 page_cache_release(page
);
829 set_page_dirty(page
);
830 mark_page_accessed(page
);
832 page_cache_release(page
);
839 remain
-= page_length
;
840 user_data
+= page_length
;
841 offset
+= page_length
;
846 /* Fixup: Kill any reinstated backing storage pages */
847 if (obj
->madv
== __I915_MADV_PURGED
)
848 i915_gem_object_truncate(obj
);
849 /* and flush dirty cachelines in case the object isn't in the cpu write
851 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
852 i915_gem_clflush_object(obj
);
853 intel_gtt_chipset_flush();
857 if (needs_clflush_after
)
858 intel_gtt_chipset_flush();
864 * Writes data to the object referenced by handle.
866 * On error, the contents of the buffer that were to be modified are undefined.
869 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
870 struct drm_file
*file
)
872 struct drm_i915_gem_pwrite
*args
= data
;
873 struct drm_i915_gem_object
*obj
;
879 if (!access_ok(VERIFY_READ
,
880 (char __user
*)(uintptr_t)args
->data_ptr
,
884 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
889 ret
= i915_mutex_lock_interruptible(dev
);
893 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
894 if (&obj
->base
== NULL
) {
899 /* Bounds check destination. */
900 if (args
->offset
> obj
->base
.size
||
901 args
->size
> obj
->base
.size
- args
->offset
) {
906 /* prime objects have no backing filp to GEM pread/pwrite
909 if (!obj
->base
.filp
) {
914 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
917 /* We can only do the GTT pwrite on untiled buffers, as otherwise
918 * it would end up going through the fenced access, and we'll get
919 * different detiling behavior between reading and writing.
920 * pread/pwrite currently are reading and writing from the CPU
921 * perspective, requiring manual detiling by the client.
924 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
928 if (obj
->gtt_space
&&
929 obj
->cache_level
== I915_CACHE_NONE
&&
930 obj
->tiling_mode
== I915_TILING_NONE
&&
931 obj
->map_and_fenceable
&&
932 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
933 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
934 /* Note that the gtt paths might fail with non-page-backed user
935 * pointers (e.g. gtt mappings when moving data between
936 * textures). Fallback to the shmem path in that case. */
940 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
943 drm_gem_object_unreference(&obj
->base
);
945 mutex_unlock(&dev
->struct_mutex
);
950 * Called when user space prepares to use an object with the CPU, either
951 * through the mmap ioctl's mapping or a GTT mapping.
954 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
955 struct drm_file
*file
)
957 struct drm_i915_gem_set_domain
*args
= data
;
958 struct drm_i915_gem_object
*obj
;
959 uint32_t read_domains
= args
->read_domains
;
960 uint32_t write_domain
= args
->write_domain
;
963 /* Only handle setting domains to types used by the CPU. */
964 if (write_domain
& I915_GEM_GPU_DOMAINS
)
967 if (read_domains
& I915_GEM_GPU_DOMAINS
)
970 /* Having something in the write domain implies it's in the read
971 * domain, and only that read domain. Enforce that in the request.
973 if (write_domain
!= 0 && read_domains
!= write_domain
)
976 ret
= i915_mutex_lock_interruptible(dev
);
980 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
981 if (&obj
->base
== NULL
) {
986 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
987 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
989 /* Silently promote "you're not bound, there was nothing to do"
990 * to success, since the client was just asking us to
991 * make sure everything was done.
996 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
999 drm_gem_object_unreference(&obj
->base
);
1001 mutex_unlock(&dev
->struct_mutex
);
1006 * Called when user space has done writes to this buffer
1009 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1010 struct drm_file
*file
)
1012 struct drm_i915_gem_sw_finish
*args
= data
;
1013 struct drm_i915_gem_object
*obj
;
1016 ret
= i915_mutex_lock_interruptible(dev
);
1020 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1021 if (&obj
->base
== NULL
) {
1026 /* Pinned buffers may be scanout, so flush the cache */
1028 i915_gem_object_flush_cpu_write_domain(obj
);
1030 drm_gem_object_unreference(&obj
->base
);
1032 mutex_unlock(&dev
->struct_mutex
);
1037 * Maps the contents of an object, returning the address it is mapped
1040 * While the mapping holds a reference on the contents of the object, it doesn't
1041 * imply a ref on the object itself.
1044 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1045 struct drm_file
*file
)
1047 struct drm_i915_gem_mmap
*args
= data
;
1048 struct drm_gem_object
*obj
;
1051 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1055 /* prime objects have no backing filp to GEM mmap
1059 drm_gem_object_unreference_unlocked(obj
);
1063 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1064 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1066 drm_gem_object_unreference_unlocked(obj
);
1067 if (IS_ERR((void *)addr
))
1070 args
->addr_ptr
= (uint64_t) addr
;
1076 * i915_gem_fault - fault a page into the GTT
1077 * vma: VMA in question
1080 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1081 * from userspace. The fault handler takes care of binding the object to
1082 * the GTT (if needed), allocating and programming a fence register (again,
1083 * only if needed based on whether the old reg is still valid or the object
1084 * is tiled) and inserting a new PTE into the faulting process.
1086 * Note that the faulting process may involve evicting existing objects
1087 * from the GTT and/or fence registers to make room. So performance may
1088 * suffer if the GTT working set is large or there are few fence registers
1091 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1093 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1094 struct drm_device
*dev
= obj
->base
.dev
;
1095 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1096 pgoff_t page_offset
;
1099 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1101 /* We don't use vmf->pgoff since that has the fake offset */
1102 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1105 ret
= i915_mutex_lock_interruptible(dev
);
1109 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1111 /* Now bind it into the GTT if needed */
1112 if (!obj
->map_and_fenceable
) {
1113 ret
= i915_gem_object_unbind(obj
);
1117 if (!obj
->gtt_space
) {
1118 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1122 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1127 if (!obj
->has_global_gtt_mapping
)
1128 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
1130 ret
= i915_gem_object_get_fence(obj
);
1134 if (i915_gem_object_is_inactive(obj
))
1135 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1137 obj
->fault_mappable
= true;
1139 pfn
= ((dev_priv
->mm
.gtt_base_addr
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1142 /* Finally, remap it using the new GTT offset */
1143 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1145 mutex_unlock(&dev
->struct_mutex
);
1149 /* If this -EIO is due to a gpu hang, give the reset code a
1150 * chance to clean up the mess. Otherwise return the proper
1152 if (!atomic_read(&dev_priv
->mm
.wedged
))
1153 return VM_FAULT_SIGBUS
;
1155 /* Give the error handler a chance to run and move the
1156 * objects off the GPU active list. Next time we service the
1157 * fault, we should be able to transition the page into the
1158 * GTT without touching the GPU (and so avoid further
1159 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1160 * with coherency, just lost writes.
1166 return VM_FAULT_NOPAGE
;
1168 return VM_FAULT_OOM
;
1170 return VM_FAULT_SIGBUS
;
1175 * i915_gem_release_mmap - remove physical page mappings
1176 * @obj: obj in question
1178 * Preserve the reservation of the mmapping with the DRM core code, but
1179 * relinquish ownership of the pages back to the system.
1181 * It is vital that we remove the page mapping if we have mapped a tiled
1182 * object through the GTT and then lose the fence register due to
1183 * resource pressure. Similarly if the object has been moved out of the
1184 * aperture, than pages mapped into userspace must be revoked. Removing the
1185 * mapping will then trigger a page fault on the next user access, allowing
1186 * fixup by i915_gem_fault().
1189 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1191 if (!obj
->fault_mappable
)
1194 if (obj
->base
.dev
->dev_mapping
)
1195 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1196 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1199 obj
->fault_mappable
= false;
1203 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1207 if (INTEL_INFO(dev
)->gen
>= 4 ||
1208 tiling_mode
== I915_TILING_NONE
)
1211 /* Previous chips need a power-of-two fence region when tiling */
1212 if (INTEL_INFO(dev
)->gen
== 3)
1213 gtt_size
= 1024*1024;
1215 gtt_size
= 512*1024;
1217 while (gtt_size
< size
)
1224 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1225 * @obj: object to check
1227 * Return the required GTT alignment for an object, taking into account
1228 * potential fence register mapping.
1231 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1236 * Minimum alignment is 4k (GTT page size), but might be greater
1237 * if a fence register is needed for the object.
1239 if (INTEL_INFO(dev
)->gen
>= 4 ||
1240 tiling_mode
== I915_TILING_NONE
)
1244 * Previous chips need to be aligned to the size of the smallest
1245 * fence register that can contain the object.
1247 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1251 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1254 * @size: size of the object
1255 * @tiling_mode: tiling mode of the object
1257 * Return the required GTT alignment for an object, only taking into account
1258 * unfenced tiled surface requirements.
1261 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1266 * Minimum alignment is 4k (GTT page size) for sane hw.
1268 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1269 tiling_mode
== I915_TILING_NONE
)
1272 /* Previous hardware however needs to be aligned to a power-of-two
1273 * tile height. The simplest method for determining this is to reuse
1274 * the power-of-tile object size.
1276 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1280 i915_gem_mmap_gtt(struct drm_file
*file
,
1281 struct drm_device
*dev
,
1285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1286 struct drm_i915_gem_object
*obj
;
1289 ret
= i915_mutex_lock_interruptible(dev
);
1293 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1294 if (&obj
->base
== NULL
) {
1299 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1304 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1305 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1310 if (!obj
->base
.map_list
.map
) {
1311 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1316 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1319 drm_gem_object_unreference(&obj
->base
);
1321 mutex_unlock(&dev
->struct_mutex
);
1326 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1328 * @data: GTT mapping ioctl data
1329 * @file: GEM object info
1331 * Simply returns the fake offset to userspace so it can mmap it.
1332 * The mmap call will end up in drm_gem_mmap(), which will set things
1333 * up so we can get faults in the handler above.
1335 * The fault handler will take care of binding the object into the GTT
1336 * (since it may have been evicted to make room for something), allocating
1337 * a fence register, and mapping the appropriate aperture address into
1341 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1342 struct drm_file
*file
)
1344 struct drm_i915_gem_mmap_gtt
*args
= data
;
1346 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1349 /* Immediately discard the backing storage */
1351 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1353 struct inode
*inode
;
1355 /* Our goal here is to return as much of the memory as
1356 * is possible back to the system as we are called from OOM.
1357 * To do this we must instruct the shmfs to drop all of its
1358 * backing pages, *now*.
1360 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1361 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1363 if (obj
->base
.map_list
.map
)
1364 drm_gem_free_mmap_offset(&obj
->base
);
1366 obj
->madv
= __I915_MADV_PURGED
;
1370 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1372 return obj
->madv
== I915_MADV_DONTNEED
;
1376 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1378 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1381 if (obj
->pages
== NULL
)
1384 BUG_ON(obj
->gtt_space
);
1385 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1387 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1389 /* In the event of a disaster, abandon all caches and
1390 * hope for the best.
1392 WARN_ON(ret
!= -EIO
);
1393 i915_gem_clflush_object(obj
);
1394 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1397 if (i915_gem_object_needs_bit17_swizzle(obj
))
1398 i915_gem_object_save_bit_17_swizzle(obj
);
1400 if (obj
->madv
== I915_MADV_DONTNEED
)
1403 for (i
= 0; i
< page_count
; i
++) {
1405 set_page_dirty(obj
->pages
[i
]);
1407 if (obj
->madv
== I915_MADV_WILLNEED
)
1408 mark_page_accessed(obj
->pages
[i
]);
1410 page_cache_release(obj
->pages
[i
]);
1414 drm_free_large(obj
->pages
);
1417 list_del(&obj
->gtt_list
);
1419 if (i915_gem_object_is_purgeable(obj
))
1420 i915_gem_object_truncate(obj
);
1426 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1428 struct drm_i915_gem_object
*obj
, *next
;
1431 list_for_each_entry_safe(obj
, next
,
1432 &dev_priv
->mm
.unbound_list
,
1434 if (i915_gem_object_is_purgeable(obj
) &&
1435 i915_gem_object_put_pages_gtt(obj
) == 0) {
1436 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1437 if (count
>= target
)
1442 list_for_each_entry_safe(obj
, next
,
1443 &dev_priv
->mm
.inactive_list
,
1445 if (i915_gem_object_is_purgeable(obj
) &&
1446 i915_gem_object_unbind(obj
) == 0 &&
1447 i915_gem_object_put_pages_gtt(obj
) == 0) {
1448 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1449 if (count
>= target
)
1458 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1460 struct drm_i915_gem_object
*obj
, *next
;
1462 i915_gem_evict_everything(dev_priv
->dev
);
1464 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
, gtt_list
)
1465 i915_gem_object_put_pages_gtt(obj
);
1469 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1471 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1473 struct address_space
*mapping
;
1477 if (obj
->pages
|| obj
->sg_table
)
1480 /* Assert that the object is not currently in any GPU domain. As it
1481 * wasn't in the GTT, there shouldn't be any way it could have been in
1484 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1485 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1487 /* Get the list of pages out of our struct file. They'll be pinned
1488 * at this point until we release them.
1490 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1491 obj
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1492 if (obj
->pages
== NULL
)
1495 /* Fail silently without starting the shrinker */
1496 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
1497 gfp
= mapping_gfp_mask(mapping
);
1498 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1499 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1500 for (i
= 0; i
< page_count
; i
++) {
1501 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1503 i915_gem_purge(dev_priv
, page_count
);
1504 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1507 /* We've tried hard to allocate the memory by reaping
1508 * our own buffer, now let the real VM do its job and
1509 * go down in flames if truly OOM.
1511 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1512 gfp
|= __GFP_IO
| __GFP_WAIT
;
1514 i915_gem_shrink_all(dev_priv
);
1515 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1519 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1520 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1523 obj
->pages
[i
] = page
;
1526 if (i915_gem_object_needs_bit17_swizzle(obj
))
1527 i915_gem_object_do_bit_17_swizzle(obj
);
1529 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
1534 page_cache_release(obj
->pages
[i
]);
1536 drm_free_large(obj
->pages
);
1538 return PTR_ERR(page
);
1542 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1543 struct intel_ring_buffer
*ring
,
1546 struct drm_device
*dev
= obj
->base
.dev
;
1547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1549 BUG_ON(ring
== NULL
);
1552 /* Add a reference if we're newly entering the active list. */
1554 drm_gem_object_reference(&obj
->base
);
1558 /* Move from whatever list we were on to the tail of execution. */
1559 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1560 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1562 obj
->last_read_seqno
= seqno
;
1564 if (obj
->fenced_gpu_access
) {
1565 obj
->last_fenced_seqno
= seqno
;
1567 /* Bump MRU to take account of the delayed flush */
1568 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1569 struct drm_i915_fence_reg
*reg
;
1571 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1572 list_move_tail(®
->lru_list
,
1573 &dev_priv
->mm
.fence_list
);
1579 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1581 struct drm_device
*dev
= obj
->base
.dev
;
1582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1584 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1585 BUG_ON(!obj
->active
);
1587 if (obj
->pin_count
) /* are we a framebuffer? */
1588 intel_mark_fb_idle(obj
);
1590 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1592 list_del_init(&obj
->ring_list
);
1595 obj
->last_read_seqno
= 0;
1596 obj
->last_write_seqno
= 0;
1597 obj
->base
.write_domain
= 0;
1599 obj
->last_fenced_seqno
= 0;
1600 obj
->fenced_gpu_access
= false;
1603 drm_gem_object_unreference(&obj
->base
);
1605 WARN_ON(i915_verify_lists(dev
));
1609 i915_gem_get_seqno(struct drm_device
*dev
)
1611 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1612 u32 seqno
= dev_priv
->next_seqno
;
1614 /* reserve 0 for non-seqno */
1615 if (++dev_priv
->next_seqno
== 0)
1616 dev_priv
->next_seqno
= 1;
1622 i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
)
1624 if (ring
->outstanding_lazy_request
== 0)
1625 ring
->outstanding_lazy_request
= i915_gem_get_seqno(ring
->dev
);
1627 return ring
->outstanding_lazy_request
;
1631 i915_add_request(struct intel_ring_buffer
*ring
,
1632 struct drm_file
*file
,
1633 struct drm_i915_gem_request
*request
)
1635 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1637 u32 request_ring_position
;
1642 * Emit any outstanding flushes - execbuf can fail to emit the flush
1643 * after having emitted the batchbuffer command. Hence we need to fix
1644 * things up similar to emitting the lazy request. The difference here
1645 * is that the flush _must_ happen before the next request, no matter
1648 ret
= intel_ring_flush_all_caches(ring
);
1652 if (request
== NULL
) {
1653 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
1654 if (request
== NULL
)
1658 seqno
= i915_gem_next_request_seqno(ring
);
1660 /* Record the position of the start of the request so that
1661 * should we detect the updated seqno part-way through the
1662 * GPU processing the request, we never over-estimate the
1663 * position of the head.
1665 request_ring_position
= intel_ring_get_tail(ring
);
1667 ret
= ring
->add_request(ring
, &seqno
);
1673 trace_i915_gem_request_add(ring
, seqno
);
1675 request
->seqno
= seqno
;
1676 request
->ring
= ring
;
1677 request
->tail
= request_ring_position
;
1678 request
->emitted_jiffies
= jiffies
;
1679 was_empty
= list_empty(&ring
->request_list
);
1680 list_add_tail(&request
->list
, &ring
->request_list
);
1681 request
->file_priv
= NULL
;
1684 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1686 spin_lock(&file_priv
->mm
.lock
);
1687 request
->file_priv
= file_priv
;
1688 list_add_tail(&request
->client_list
,
1689 &file_priv
->mm
.request_list
);
1690 spin_unlock(&file_priv
->mm
.lock
);
1693 ring
->outstanding_lazy_request
= 0;
1695 if (!dev_priv
->mm
.suspended
) {
1696 if (i915_enable_hangcheck
) {
1697 mod_timer(&dev_priv
->hangcheck_timer
,
1699 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1702 queue_delayed_work(dev_priv
->wq
,
1703 &dev_priv
->mm
.retire_work
, HZ
);
1704 intel_mark_busy(dev_priv
->dev
);
1712 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1714 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1719 spin_lock(&file_priv
->mm
.lock
);
1720 if (request
->file_priv
) {
1721 list_del(&request
->client_list
);
1722 request
->file_priv
= NULL
;
1724 spin_unlock(&file_priv
->mm
.lock
);
1727 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1728 struct intel_ring_buffer
*ring
)
1730 while (!list_empty(&ring
->request_list
)) {
1731 struct drm_i915_gem_request
*request
;
1733 request
= list_first_entry(&ring
->request_list
,
1734 struct drm_i915_gem_request
,
1737 list_del(&request
->list
);
1738 i915_gem_request_remove_from_client(request
);
1742 while (!list_empty(&ring
->active_list
)) {
1743 struct drm_i915_gem_object
*obj
;
1745 obj
= list_first_entry(&ring
->active_list
,
1746 struct drm_i915_gem_object
,
1749 i915_gem_object_move_to_inactive(obj
);
1753 static void i915_gem_reset_fences(struct drm_device
*dev
)
1755 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1758 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
1759 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
1761 i915_gem_write_fence(dev
, i
, NULL
);
1764 i915_gem_object_fence_lost(reg
->obj
);
1768 INIT_LIST_HEAD(®
->lru_list
);
1771 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
1774 void i915_gem_reset(struct drm_device
*dev
)
1776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1777 struct drm_i915_gem_object
*obj
;
1778 struct intel_ring_buffer
*ring
;
1781 for_each_ring(ring
, dev_priv
, i
)
1782 i915_gem_reset_ring_lists(dev_priv
, ring
);
1784 /* Move everything out of the GPU domains to ensure we do any
1785 * necessary invalidation upon reuse.
1787 list_for_each_entry(obj
,
1788 &dev_priv
->mm
.inactive_list
,
1791 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1795 /* The fence registers are invalidated so clear them out */
1796 i915_gem_reset_fences(dev
);
1800 * This function clears the request list as sequence numbers are passed.
1803 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
1808 if (list_empty(&ring
->request_list
))
1811 WARN_ON(i915_verify_lists(ring
->dev
));
1813 seqno
= ring
->get_seqno(ring
, true);
1815 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
1816 if (seqno
>= ring
->sync_seqno
[i
])
1817 ring
->sync_seqno
[i
] = 0;
1819 while (!list_empty(&ring
->request_list
)) {
1820 struct drm_i915_gem_request
*request
;
1822 request
= list_first_entry(&ring
->request_list
,
1823 struct drm_i915_gem_request
,
1826 if (!i915_seqno_passed(seqno
, request
->seqno
))
1829 trace_i915_gem_request_retire(ring
, request
->seqno
);
1830 /* We know the GPU must have read the request to have
1831 * sent us the seqno + interrupt, so use the position
1832 * of tail of the request to update the last known position
1835 ring
->last_retired_head
= request
->tail
;
1837 list_del(&request
->list
);
1838 i915_gem_request_remove_from_client(request
);
1842 /* Move any buffers on the active list that are no longer referenced
1843 * by the ringbuffer to the flushing/inactive lists as appropriate.
1845 while (!list_empty(&ring
->active_list
)) {
1846 struct drm_i915_gem_object
*obj
;
1848 obj
= list_first_entry(&ring
->active_list
,
1849 struct drm_i915_gem_object
,
1852 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
1855 i915_gem_object_move_to_inactive(obj
);
1858 if (unlikely(ring
->trace_irq_seqno
&&
1859 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
1860 ring
->irq_put(ring
);
1861 ring
->trace_irq_seqno
= 0;
1864 WARN_ON(i915_verify_lists(ring
->dev
));
1868 i915_gem_retire_requests(struct drm_device
*dev
)
1870 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1871 struct intel_ring_buffer
*ring
;
1874 for_each_ring(ring
, dev_priv
, i
)
1875 i915_gem_retire_requests_ring(ring
);
1879 i915_gem_retire_work_handler(struct work_struct
*work
)
1881 drm_i915_private_t
*dev_priv
;
1882 struct drm_device
*dev
;
1883 struct intel_ring_buffer
*ring
;
1887 dev_priv
= container_of(work
, drm_i915_private_t
,
1888 mm
.retire_work
.work
);
1889 dev
= dev_priv
->dev
;
1891 /* Come back later if the device is busy... */
1892 if (!mutex_trylock(&dev
->struct_mutex
)) {
1893 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1897 i915_gem_retire_requests(dev
);
1899 /* Send a periodic flush down the ring so we don't hold onto GEM
1900 * objects indefinitely.
1903 for_each_ring(ring
, dev_priv
, i
) {
1904 if (ring
->gpu_caches_dirty
)
1905 i915_add_request(ring
, NULL
, NULL
);
1907 idle
&= list_empty(&ring
->request_list
);
1910 if (!dev_priv
->mm
.suspended
&& !idle
)
1911 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1913 intel_mark_idle(dev
);
1915 mutex_unlock(&dev
->struct_mutex
);
1919 i915_gem_check_wedge(struct drm_i915_private
*dev_priv
,
1922 if (atomic_read(&dev_priv
->mm
.wedged
)) {
1923 struct completion
*x
= &dev_priv
->error_completion
;
1924 bool recovery_complete
;
1925 unsigned long flags
;
1927 /* Give the error handler a chance to run. */
1928 spin_lock_irqsave(&x
->wait
.lock
, flags
);
1929 recovery_complete
= x
->done
> 0;
1930 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
1932 /* Non-interruptible callers can't handle -EAGAIN, hence return
1933 * -EIO unconditionally for these. */
1937 /* Recovery complete, but still wedged means reset failure. */
1938 if (recovery_complete
)
1948 * Compare seqno against outstanding lazy request. Emit a request if they are
1952 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
1956 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1959 if (seqno
== ring
->outstanding_lazy_request
)
1960 ret
= i915_add_request(ring
, NULL
, NULL
);
1966 * __wait_seqno - wait until execution of seqno has finished
1967 * @ring: the ring expected to report seqno
1969 * @interruptible: do an interruptible wait (normally yes)
1970 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1972 * Returns 0 if the seqno was found within the alloted time. Else returns the
1973 * errno with remaining time filled in timeout argument.
1975 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
1976 bool interruptible
, struct timespec
*timeout
)
1978 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1979 struct timespec before
, now
, wait_time
={1,0};
1980 unsigned long timeout_jiffies
;
1982 bool wait_forever
= true;
1985 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1988 trace_i915_gem_request_wait_begin(ring
, seqno
);
1990 if (timeout
!= NULL
) {
1991 wait_time
= *timeout
;
1992 wait_forever
= false;
1995 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1997 if (WARN_ON(!ring
->irq_get(ring
)))
2000 /* Record current time in case interrupted by signal, or wedged * */
2001 getrawmonotonic(&before
);
2004 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
2005 atomic_read(&dev_priv->mm.wedged))
2008 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
2012 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
2015 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
2018 } while (end
== 0 && wait_forever
);
2020 getrawmonotonic(&now
);
2022 ring
->irq_put(ring
);
2023 trace_i915_gem_request_wait_end(ring
, seqno
);
2027 struct timespec sleep_time
= timespec_sub(now
, before
);
2028 *timeout
= timespec_sub(*timeout
, sleep_time
);
2033 case -EAGAIN
: /* Wedged */
2034 case -ERESTARTSYS
: /* Signal */
2036 case 0: /* Timeout */
2038 set_normalized_timespec(timeout
, 0, 0);
2040 default: /* Completed */
2041 WARN_ON(end
< 0); /* We're not aware of other errors */
2047 * Waits for a sequence number to be signaled, and cleans up the
2048 * request and object lists appropriately for that event.
2051 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
2053 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2058 ret
= i915_gem_check_wedge(dev_priv
, dev_priv
->mm
.interruptible
);
2062 ret
= i915_gem_check_olr(ring
, seqno
);
2066 ret
= __wait_seqno(ring
, seqno
, dev_priv
->mm
.interruptible
, NULL
);
2072 * Ensures that all rendering to the object has completed and the object is
2073 * safe to unbind from the GTT or access from the CPU.
2075 static __must_check
int
2076 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
2082 /* If there is rendering queued on the buffer being evicted, wait for
2086 seqno
= obj
->last_write_seqno
;
2088 seqno
= obj
->last_read_seqno
;
2092 ret
= i915_wait_seqno(obj
->ring
, seqno
);
2096 /* Manually manage the write flush as we may have not yet retired
2099 if (obj
->last_write_seqno
&&
2100 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
2101 obj
->last_write_seqno
= 0;
2102 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
2105 i915_gem_retire_requests_ring(obj
->ring
);
2110 * Ensures that an object will eventually get non-busy by flushing any required
2111 * write domains, emitting any outstanding lazy request and retiring and
2112 * completed requests.
2115 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2120 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2124 i915_gem_retire_requests_ring(obj
->ring
);
2131 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2132 * @DRM_IOCTL_ARGS: standard ioctl arguments
2134 * Returns 0 if successful, else an error is returned with the remaining time in
2135 * the timeout parameter.
2136 * -ETIME: object is still busy after timeout
2137 * -ERESTARTSYS: signal interrupted the wait
2138 * -ENONENT: object doesn't exist
2139 * Also possible, but rare:
2140 * -EAGAIN: GPU wedged
2142 * -ENODEV: Internal IRQ fail
2143 * -E?: The add request failed
2145 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2146 * non-zero timeout parameter the wait ioctl will wait for the given number of
2147 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2148 * without holding struct_mutex the object may become re-busied before this
2149 * function completes. A similar but shorter * race condition exists in the busy
2153 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2155 struct drm_i915_gem_wait
*args
= data
;
2156 struct drm_i915_gem_object
*obj
;
2157 struct intel_ring_buffer
*ring
= NULL
;
2158 struct timespec timeout_stack
, *timeout
= NULL
;
2162 if (args
->timeout_ns
>= 0) {
2163 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2164 timeout
= &timeout_stack
;
2167 ret
= i915_mutex_lock_interruptible(dev
);
2171 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2172 if (&obj
->base
== NULL
) {
2173 mutex_unlock(&dev
->struct_mutex
);
2177 /* Need to make sure the object gets inactive eventually. */
2178 ret
= i915_gem_object_flush_active(obj
);
2183 seqno
= obj
->last_read_seqno
;
2190 /* Do this after OLR check to make sure we make forward progress polling
2191 * on this IOCTL with a 0 timeout (like busy ioctl)
2193 if (!args
->timeout_ns
) {
2198 drm_gem_object_unreference(&obj
->base
);
2199 mutex_unlock(&dev
->struct_mutex
);
2201 ret
= __wait_seqno(ring
, seqno
, true, timeout
);
2203 WARN_ON(!timespec_valid(timeout
));
2204 args
->timeout_ns
= timespec_to_ns(timeout
);
2209 drm_gem_object_unreference(&obj
->base
);
2210 mutex_unlock(&dev
->struct_mutex
);
2215 * i915_gem_object_sync - sync an object to a ring.
2217 * @obj: object which may be in use on another ring.
2218 * @to: ring we wish to use the object on. May be NULL.
2220 * This code is meant to abstract object synchronization with the GPU.
2221 * Calling with NULL implies synchronizing the object with the CPU
2222 * rather than a particular GPU ring.
2224 * Returns 0 if successful, else propagates up the lower layer error.
2227 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2228 struct intel_ring_buffer
*to
)
2230 struct intel_ring_buffer
*from
= obj
->ring
;
2234 if (from
== NULL
|| to
== from
)
2237 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2238 return i915_gem_object_wait_rendering(obj
, false);
2240 idx
= intel_ring_sync_index(from
, to
);
2242 seqno
= obj
->last_read_seqno
;
2243 if (seqno
<= from
->sync_seqno
[idx
])
2246 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2250 ret
= to
->sync_to(to
, from
, seqno
);
2252 from
->sync_seqno
[idx
] = seqno
;
2257 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2259 u32 old_write_domain
, old_read_domains
;
2261 /* Act a barrier for all accesses through the GTT */
2264 /* Force a pagefault for domain tracking on next user access */
2265 i915_gem_release_mmap(obj
);
2267 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2270 old_read_domains
= obj
->base
.read_domains
;
2271 old_write_domain
= obj
->base
.write_domain
;
2273 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2274 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2276 trace_i915_gem_object_change_domain(obj
,
2282 * Unbinds an object from the GTT aperture.
2285 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2287 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2290 if (obj
->gtt_space
== NULL
)
2296 ret
= i915_gem_object_finish_gpu(obj
);
2299 /* Continue on if we fail due to EIO, the GPU is hung so we
2300 * should be safe and we need to cleanup or else we might
2301 * cause memory corruption through use-after-free.
2304 i915_gem_object_finish_gtt(obj
);
2306 /* release the fence reg _after_ flushing */
2307 ret
= i915_gem_object_put_fence(obj
);
2311 trace_i915_gem_object_unbind(obj
);
2313 if (obj
->has_global_gtt_mapping
)
2314 i915_gem_gtt_unbind_object(obj
);
2315 if (obj
->has_aliasing_ppgtt_mapping
) {
2316 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2317 obj
->has_aliasing_ppgtt_mapping
= 0;
2319 i915_gem_gtt_finish_object(obj
);
2321 list_del(&obj
->mm_list
);
2322 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
2323 /* Avoid an unnecessary call to unbind on rebind. */
2324 obj
->map_and_fenceable
= true;
2326 drm_mm_put_block(obj
->gtt_space
);
2327 obj
->gtt_space
= NULL
;
2328 obj
->gtt_offset
= 0;
2333 static int i915_ring_idle(struct intel_ring_buffer
*ring
)
2335 if (list_empty(&ring
->active_list
))
2338 return i915_wait_seqno(ring
, i915_gem_next_request_seqno(ring
));
2341 int i915_gpu_idle(struct drm_device
*dev
)
2343 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2344 struct intel_ring_buffer
*ring
;
2347 /* Flush everything onto the inactive list. */
2348 for_each_ring(ring
, dev_priv
, i
) {
2349 ret
= i915_ring_idle(ring
);
2353 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2361 static void sandybridge_write_fence_reg(struct drm_device
*dev
, int reg
,
2362 struct drm_i915_gem_object
*obj
)
2364 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2368 u32 size
= obj
->gtt_space
->size
;
2370 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2372 val
|= obj
->gtt_offset
& 0xfffff000;
2373 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2374 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2376 if (obj
->tiling_mode
== I915_TILING_Y
)
2377 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2378 val
|= I965_FENCE_REG_VALID
;
2382 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8, val
);
2383 POSTING_READ(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8);
2386 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2387 struct drm_i915_gem_object
*obj
)
2389 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2393 u32 size
= obj
->gtt_space
->size
;
2395 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2397 val
|= obj
->gtt_offset
& 0xfffff000;
2398 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2399 if (obj
->tiling_mode
== I915_TILING_Y
)
2400 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2401 val
|= I965_FENCE_REG_VALID
;
2405 I915_WRITE64(FENCE_REG_965_0
+ reg
* 8, val
);
2406 POSTING_READ(FENCE_REG_965_0
+ reg
* 8);
2409 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2410 struct drm_i915_gem_object
*obj
)
2412 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2416 u32 size
= obj
->gtt_space
->size
;
2420 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2421 (size
& -size
) != size
||
2422 (obj
->gtt_offset
& (size
- 1)),
2423 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2424 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2426 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2431 /* Note: pitch better be a power of two tile widths */
2432 pitch_val
= obj
->stride
/ tile_width
;
2433 pitch_val
= ffs(pitch_val
) - 1;
2435 val
= obj
->gtt_offset
;
2436 if (obj
->tiling_mode
== I915_TILING_Y
)
2437 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2438 val
|= I915_FENCE_SIZE_BITS(size
);
2439 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2440 val
|= I830_FENCE_REG_VALID
;
2445 reg
= FENCE_REG_830_0
+ reg
* 4;
2447 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2449 I915_WRITE(reg
, val
);
2453 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2454 struct drm_i915_gem_object
*obj
)
2456 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2460 u32 size
= obj
->gtt_space
->size
;
2463 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2464 (size
& -size
) != size
||
2465 (obj
->gtt_offset
& (size
- 1)),
2466 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2467 obj
->gtt_offset
, size
);
2469 pitch_val
= obj
->stride
/ 128;
2470 pitch_val
= ffs(pitch_val
) - 1;
2472 val
= obj
->gtt_offset
;
2473 if (obj
->tiling_mode
== I915_TILING_Y
)
2474 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2475 val
|= I830_FENCE_SIZE_BITS(size
);
2476 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2477 val
|= I830_FENCE_REG_VALID
;
2481 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2482 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2485 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2486 struct drm_i915_gem_object
*obj
)
2488 switch (INTEL_INFO(dev
)->gen
) {
2490 case 6: sandybridge_write_fence_reg(dev
, reg
, obj
); break;
2492 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2493 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2494 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2499 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2500 struct drm_i915_fence_reg
*fence
)
2502 return fence
- dev_priv
->fence_regs
;
2505 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2506 struct drm_i915_fence_reg
*fence
,
2509 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2510 int reg
= fence_number(dev_priv
, fence
);
2512 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2515 obj
->fence_reg
= reg
;
2517 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2519 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2521 list_del_init(&fence
->lru_list
);
2526 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2528 if (obj
->last_fenced_seqno
) {
2529 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2533 obj
->last_fenced_seqno
= 0;
2536 /* Ensure that all CPU reads are completed before installing a fence
2537 * and all writes before removing the fence.
2539 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2542 obj
->fenced_gpu_access
= false;
2547 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2549 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2552 ret
= i915_gem_object_flush_fence(obj
);
2556 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2559 i915_gem_object_update_fence(obj
,
2560 &dev_priv
->fence_regs
[obj
->fence_reg
],
2562 i915_gem_object_fence_lost(obj
);
2567 static struct drm_i915_fence_reg
*
2568 i915_find_fence_reg(struct drm_device
*dev
)
2570 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2571 struct drm_i915_fence_reg
*reg
, *avail
;
2574 /* First try to find a free reg */
2576 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2577 reg
= &dev_priv
->fence_regs
[i
];
2581 if (!reg
->pin_count
)
2588 /* None available, try to steal one or wait for a user to finish */
2589 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2600 * i915_gem_object_get_fence - set up fencing for an object
2601 * @obj: object to map through a fence reg
2603 * When mapping objects through the GTT, userspace wants to be able to write
2604 * to them without having to worry about swizzling if the object is tiled.
2605 * This function walks the fence regs looking for a free one for @obj,
2606 * stealing one if it can't find any.
2608 * It then sets up the reg based on the object's properties: address, pitch
2609 * and tiling format.
2611 * For an untiled surface, this removes any existing fence.
2614 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2616 struct drm_device
*dev
= obj
->base
.dev
;
2617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2618 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2619 struct drm_i915_fence_reg
*reg
;
2622 /* Have we updated the tiling parameters upon the object and so
2623 * will need to serialise the write to the associated fence register?
2625 if (obj
->fence_dirty
) {
2626 ret
= i915_gem_object_flush_fence(obj
);
2631 /* Just update our place in the LRU if our fence is getting reused. */
2632 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2633 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2634 if (!obj
->fence_dirty
) {
2635 list_move_tail(®
->lru_list
,
2636 &dev_priv
->mm
.fence_list
);
2639 } else if (enable
) {
2640 reg
= i915_find_fence_reg(dev
);
2645 struct drm_i915_gem_object
*old
= reg
->obj
;
2647 ret
= i915_gem_object_flush_fence(old
);
2651 i915_gem_object_fence_lost(old
);
2656 i915_gem_object_update_fence(obj
, reg
, enable
);
2657 obj
->fence_dirty
= false;
2662 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2663 struct drm_mm_node
*gtt_space
,
2664 unsigned long cache_level
)
2666 struct drm_mm_node
*other
;
2668 /* On non-LLC machines we have to be careful when putting differing
2669 * types of snoopable memory together to avoid the prefetcher
2670 * crossing memory domains and dieing.
2675 if (gtt_space
== NULL
)
2678 if (list_empty(>t_space
->node_list
))
2681 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2682 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2685 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2686 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2692 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2696 struct drm_i915_gem_object
*obj
;
2699 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
) {
2700 if (obj
->gtt_space
== NULL
) {
2701 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
2706 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
2707 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2708 obj
->gtt_space
->start
,
2709 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2711 obj
->gtt_space
->color
);
2716 if (!i915_gem_valid_gtt_space(dev
,
2718 obj
->cache_level
)) {
2719 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2720 obj
->gtt_space
->start
,
2721 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2733 * Finds free space in the GTT aperture and binds the object there.
2736 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2738 bool map_and_fenceable
)
2740 struct drm_device
*dev
= obj
->base
.dev
;
2741 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2742 struct drm_mm_node
*free_space
;
2743 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2744 bool mappable
, fenceable
;
2747 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2748 DRM_ERROR("Attempting to bind a purgeable object\n");
2752 fence_size
= i915_gem_get_gtt_size(dev
,
2755 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2758 unfenced_alignment
=
2759 i915_gem_get_unfenced_gtt_alignment(dev
,
2764 alignment
= map_and_fenceable
? fence_alignment
:
2766 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2767 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2771 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2773 /* If the object is bigger than the entire aperture, reject it early
2774 * before evicting everything in a vain attempt to find space.
2776 if (obj
->base
.size
>
2777 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2778 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2782 ret
= i915_gem_object_get_pages_gtt(obj
);
2787 if (map_and_fenceable
)
2789 drm_mm_search_free_in_range_color(&dev_priv
->mm
.gtt_space
,
2790 size
, alignment
, obj
->cache_level
,
2791 0, dev_priv
->mm
.gtt_mappable_end
,
2794 free_space
= drm_mm_search_free_color(&dev_priv
->mm
.gtt_space
,
2795 size
, alignment
, obj
->cache_level
,
2798 if (free_space
!= NULL
) {
2799 if (map_and_fenceable
)
2801 drm_mm_get_block_range_generic(free_space
,
2802 size
, alignment
, obj
->cache_level
,
2803 0, dev_priv
->mm
.gtt_mappable_end
,
2807 drm_mm_get_block_generic(free_space
,
2808 size
, alignment
, obj
->cache_level
,
2811 if (obj
->gtt_space
== NULL
) {
2812 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2820 if (WARN_ON(!i915_gem_valid_gtt_space(dev
,
2822 obj
->cache_level
))) {
2823 drm_mm_put_block(obj
->gtt_space
);
2824 obj
->gtt_space
= NULL
;
2829 ret
= i915_gem_gtt_prepare_object(obj
);
2831 drm_mm_put_block(obj
->gtt_space
);
2832 obj
->gtt_space
= NULL
;
2836 if (!dev_priv
->mm
.aliasing_ppgtt
)
2837 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
2839 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.bound_list
);
2840 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2842 obj
->gtt_offset
= obj
->gtt_space
->start
;
2845 obj
->gtt_space
->size
== fence_size
&&
2846 (obj
->gtt_space
->start
& (fence_alignment
- 1)) == 0;
2849 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2851 obj
->map_and_fenceable
= mappable
&& fenceable
;
2853 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2854 i915_gem_verify_gtt(dev
);
2859 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2861 /* If we don't have a page list set up, then we're not pinned
2862 * to GPU, and we can ignore the cache flush because it'll happen
2863 * again at bind time.
2865 if (obj
->pages
== NULL
)
2868 /* If the GPU is snooping the contents of the CPU cache,
2869 * we do not need to manually clear the CPU cache lines. However,
2870 * the caches are only snooped when the render cache is
2871 * flushed/invalidated. As we always have to emit invalidations
2872 * and flushes when moving into and out of the RENDER domain, correct
2873 * snooping behaviour occurs naturally as the result of our domain
2876 if (obj
->cache_level
!= I915_CACHE_NONE
)
2879 trace_i915_gem_object_clflush(obj
);
2881 drm_clflush_pages(obj
->pages
, obj
->base
.size
/ PAGE_SIZE
);
2884 /** Flushes the GTT write domain for the object if it's dirty. */
2886 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
2888 uint32_t old_write_domain
;
2890 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
2893 /* No actual flushing is required for the GTT write domain. Writes
2894 * to it immediately go to main memory as far as we know, so there's
2895 * no chipset flush. It also doesn't land in render cache.
2897 * However, we do have to enforce the order so that all writes through
2898 * the GTT land before any writes to the device, such as updates to
2903 old_write_domain
= obj
->base
.write_domain
;
2904 obj
->base
.write_domain
= 0;
2906 trace_i915_gem_object_change_domain(obj
,
2907 obj
->base
.read_domains
,
2911 /** Flushes the CPU write domain for the object if it's dirty. */
2913 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
2915 uint32_t old_write_domain
;
2917 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
2920 i915_gem_clflush_object(obj
);
2921 intel_gtt_chipset_flush();
2922 old_write_domain
= obj
->base
.write_domain
;
2923 obj
->base
.write_domain
= 0;
2925 trace_i915_gem_object_change_domain(obj
,
2926 obj
->base
.read_domains
,
2931 * Moves a single object to the GTT read, and possibly write domain.
2933 * This function returns when the move is complete, including waiting on
2937 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
2939 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2940 uint32_t old_write_domain
, old_read_domains
;
2943 /* Not valid to be called on unbound objects. */
2944 if (obj
->gtt_space
== NULL
)
2947 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
2950 ret
= i915_gem_object_wait_rendering(obj
, !write
);
2954 i915_gem_object_flush_cpu_write_domain(obj
);
2956 old_write_domain
= obj
->base
.write_domain
;
2957 old_read_domains
= obj
->base
.read_domains
;
2959 /* It should now be out of any other write domains, and we can update
2960 * the domain values for our changes.
2962 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2963 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2965 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
2966 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
2970 trace_i915_gem_object_change_domain(obj
,
2974 /* And bump the LRU for this access */
2975 if (i915_gem_object_is_inactive(obj
))
2976 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2981 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2982 enum i915_cache_level cache_level
)
2984 struct drm_device
*dev
= obj
->base
.dev
;
2985 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2988 if (obj
->cache_level
== cache_level
)
2991 if (obj
->pin_count
) {
2992 DRM_DEBUG("can not change the cache level of pinned objects\n");
2996 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
2997 ret
= i915_gem_object_unbind(obj
);
3002 if (obj
->gtt_space
) {
3003 ret
= i915_gem_object_finish_gpu(obj
);
3007 i915_gem_object_finish_gtt(obj
);
3009 /* Before SandyBridge, you could not use tiling or fence
3010 * registers with snooped memory, so relinquish any fences
3011 * currently pointing to our region in the aperture.
3013 if (INTEL_INFO(dev
)->gen
< 6) {
3014 ret
= i915_gem_object_put_fence(obj
);
3019 if (obj
->has_global_gtt_mapping
)
3020 i915_gem_gtt_bind_object(obj
, cache_level
);
3021 if (obj
->has_aliasing_ppgtt_mapping
)
3022 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3025 obj
->gtt_space
->color
= cache_level
;
3028 if (cache_level
== I915_CACHE_NONE
) {
3029 u32 old_read_domains
, old_write_domain
;
3031 /* If we're coming from LLC cached, then we haven't
3032 * actually been tracking whether the data is in the
3033 * CPU cache or not, since we only allow one bit set
3034 * in obj->write_domain and have been skipping the clflushes.
3035 * Just set it to the CPU cache for now.
3037 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3038 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3040 old_read_domains
= obj
->base
.read_domains
;
3041 old_write_domain
= obj
->base
.write_domain
;
3043 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3044 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3046 trace_i915_gem_object_change_domain(obj
,
3051 obj
->cache_level
= cache_level
;
3052 i915_gem_verify_gtt(dev
);
3056 int i915_gem_get_cacheing_ioctl(struct drm_device
*dev
, void *data
,
3057 struct drm_file
*file
)
3059 struct drm_i915_gem_cacheing
*args
= data
;
3060 struct drm_i915_gem_object
*obj
;
3063 ret
= i915_mutex_lock_interruptible(dev
);
3067 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3068 if (&obj
->base
== NULL
) {
3073 args
->cacheing
= obj
->cache_level
!= I915_CACHE_NONE
;
3075 drm_gem_object_unreference(&obj
->base
);
3077 mutex_unlock(&dev
->struct_mutex
);
3081 int i915_gem_set_cacheing_ioctl(struct drm_device
*dev
, void *data
,
3082 struct drm_file
*file
)
3084 struct drm_i915_gem_cacheing
*args
= data
;
3085 struct drm_i915_gem_object
*obj
;
3086 enum i915_cache_level level
;
3089 ret
= i915_mutex_lock_interruptible(dev
);
3093 switch (args
->cacheing
) {
3094 case I915_CACHEING_NONE
:
3095 level
= I915_CACHE_NONE
;
3097 case I915_CACHEING_CACHED
:
3098 level
= I915_CACHE_LLC
;
3104 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3105 if (&obj
->base
== NULL
) {
3110 ret
= i915_gem_object_set_cache_level(obj
, level
);
3112 drm_gem_object_unreference(&obj
->base
);
3114 mutex_unlock(&dev
->struct_mutex
);
3119 * Prepare buffer for display plane (scanout, cursors, etc).
3120 * Can be called from an uninterruptible phase (modesetting) and allows
3121 * any flushes to be pipelined (for pageflips).
3124 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3126 struct intel_ring_buffer
*pipelined
)
3128 u32 old_read_domains
, old_write_domain
;
3131 if (pipelined
!= obj
->ring
) {
3132 ret
= i915_gem_object_sync(obj
, pipelined
);
3137 /* The display engine is not coherent with the LLC cache on gen6. As
3138 * a result, we make sure that the pinning that is about to occur is
3139 * done with uncached PTEs. This is lowest common denominator for all
3142 * However for gen6+, we could do better by using the GFDT bit instead
3143 * of uncaching, which would allow us to flush all the LLC-cached data
3144 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3146 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3150 /* As the user may map the buffer once pinned in the display plane
3151 * (e.g. libkms for the bootup splash), we have to ensure that we
3152 * always use map_and_fenceable for all scanout buffers.
3154 ret
= i915_gem_object_pin(obj
, alignment
, true);
3158 i915_gem_object_flush_cpu_write_domain(obj
);
3160 old_write_domain
= obj
->base
.write_domain
;
3161 old_read_domains
= obj
->base
.read_domains
;
3163 /* It should now be out of any other write domains, and we can update
3164 * the domain values for our changes.
3166 obj
->base
.write_domain
= 0;
3167 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3169 trace_i915_gem_object_change_domain(obj
,
3177 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3181 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3184 ret
= i915_gem_object_wait_rendering(obj
, false);
3188 /* Ensure that we invalidate the GPU's caches and TLBs. */
3189 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3194 * Moves a single object to the CPU read, and possibly write domain.
3196 * This function returns when the move is complete, including waiting on
3200 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3202 uint32_t old_write_domain
, old_read_domains
;
3205 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3208 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3212 i915_gem_object_flush_gtt_write_domain(obj
);
3214 old_write_domain
= obj
->base
.write_domain
;
3215 old_read_domains
= obj
->base
.read_domains
;
3217 /* Flush the CPU cache if it's still invalid. */
3218 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3219 i915_gem_clflush_object(obj
);
3221 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3224 /* It should now be out of any other write domains, and we can update
3225 * the domain values for our changes.
3227 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3229 /* If we're writing through the CPU, then the GPU read domains will
3230 * need to be invalidated at next use.
3233 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3234 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3237 trace_i915_gem_object_change_domain(obj
,
3244 /* Throttle our rendering by waiting until the ring has completed our requests
3245 * emitted over 20 msec ago.
3247 * Note that if we were to use the current jiffies each time around the loop,
3248 * we wouldn't escape the function with any frames outstanding if the time to
3249 * render a frame was over 20ms.
3251 * This should get us reasonable parallelism between CPU and GPU but also
3252 * relatively low latency when blocking on a particular request to finish.
3255 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3258 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3259 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3260 struct drm_i915_gem_request
*request
;
3261 struct intel_ring_buffer
*ring
= NULL
;
3265 if (atomic_read(&dev_priv
->mm
.wedged
))
3268 spin_lock(&file_priv
->mm
.lock
);
3269 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3270 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3273 ring
= request
->ring
;
3274 seqno
= request
->seqno
;
3276 spin_unlock(&file_priv
->mm
.lock
);
3281 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
3283 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3289 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3291 bool map_and_fenceable
)
3295 BUG_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3297 if (obj
->gtt_space
!= NULL
) {
3298 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3299 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3300 WARN(obj
->pin_count
,
3301 "bo is already pinned with incorrect alignment:"
3302 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3303 " obj->map_and_fenceable=%d\n",
3304 obj
->gtt_offset
, alignment
,
3306 obj
->map_and_fenceable
);
3307 ret
= i915_gem_object_unbind(obj
);
3313 if (obj
->gtt_space
== NULL
) {
3314 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3320 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3321 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3324 obj
->pin_mappable
|= map_and_fenceable
;
3330 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3332 BUG_ON(obj
->pin_count
== 0);
3333 BUG_ON(obj
->gtt_space
== NULL
);
3335 if (--obj
->pin_count
== 0)
3336 obj
->pin_mappable
= false;
3340 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3341 struct drm_file
*file
)
3343 struct drm_i915_gem_pin
*args
= data
;
3344 struct drm_i915_gem_object
*obj
;
3347 ret
= i915_mutex_lock_interruptible(dev
);
3351 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3352 if (&obj
->base
== NULL
) {
3357 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3358 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3363 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3364 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3370 obj
->user_pin_count
++;
3371 obj
->pin_filp
= file
;
3372 if (obj
->user_pin_count
== 1) {
3373 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
3378 /* XXX - flush the CPU caches for pinned objects
3379 * as the X server doesn't manage domains yet
3381 i915_gem_object_flush_cpu_write_domain(obj
);
3382 args
->offset
= obj
->gtt_offset
;
3384 drm_gem_object_unreference(&obj
->base
);
3386 mutex_unlock(&dev
->struct_mutex
);
3391 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3392 struct drm_file
*file
)
3394 struct drm_i915_gem_pin
*args
= data
;
3395 struct drm_i915_gem_object
*obj
;
3398 ret
= i915_mutex_lock_interruptible(dev
);
3402 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3403 if (&obj
->base
== NULL
) {
3408 if (obj
->pin_filp
!= file
) {
3409 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3414 obj
->user_pin_count
--;
3415 if (obj
->user_pin_count
== 0) {
3416 obj
->pin_filp
= NULL
;
3417 i915_gem_object_unpin(obj
);
3421 drm_gem_object_unreference(&obj
->base
);
3423 mutex_unlock(&dev
->struct_mutex
);
3428 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3429 struct drm_file
*file
)
3431 struct drm_i915_gem_busy
*args
= data
;
3432 struct drm_i915_gem_object
*obj
;
3435 ret
= i915_mutex_lock_interruptible(dev
);
3439 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3440 if (&obj
->base
== NULL
) {
3445 /* Count all active objects as busy, even if they are currently not used
3446 * by the gpu. Users of this interface expect objects to eventually
3447 * become non-busy without any further actions, therefore emit any
3448 * necessary flushes here.
3450 ret
= i915_gem_object_flush_active(obj
);
3452 args
->busy
= obj
->active
;
3454 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3455 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3458 drm_gem_object_unreference(&obj
->base
);
3460 mutex_unlock(&dev
->struct_mutex
);
3465 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3466 struct drm_file
*file_priv
)
3468 return i915_gem_ring_throttle(dev
, file_priv
);
3472 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3473 struct drm_file
*file_priv
)
3475 struct drm_i915_gem_madvise
*args
= data
;
3476 struct drm_i915_gem_object
*obj
;
3479 switch (args
->madv
) {
3480 case I915_MADV_DONTNEED
:
3481 case I915_MADV_WILLNEED
:
3487 ret
= i915_mutex_lock_interruptible(dev
);
3491 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3492 if (&obj
->base
== NULL
) {
3497 if (obj
->pin_count
) {
3502 if (obj
->madv
!= __I915_MADV_PURGED
)
3503 obj
->madv
= args
->madv
;
3505 /* if the object is no longer attached, discard its backing storage */
3506 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3507 i915_gem_object_truncate(obj
);
3509 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3512 drm_gem_object_unreference(&obj
->base
);
3514 mutex_unlock(&dev
->struct_mutex
);
3518 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3522 struct drm_i915_gem_object
*obj
;
3523 struct address_space
*mapping
;
3526 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3530 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3535 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3536 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3537 /* 965gm cannot relocate objects above 4GiB. */
3538 mask
&= ~__GFP_HIGHMEM
;
3539 mask
|= __GFP_DMA32
;
3542 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3543 mapping_set_gfp_mask(mapping
, mask
);
3545 i915_gem_info_add_obj(dev_priv
, size
);
3547 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3548 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3551 /* On some devices, we can have the GPU use the LLC (the CPU
3552 * cache) for about a 10% performance improvement
3553 * compared to uncached. Graphics requests other than
3554 * display scanout are coherent with the CPU in
3555 * accessing this cache. This means in this mode we
3556 * don't need to clflush on the CPU side, and on the
3557 * GPU side we only need to flush internal caches to
3558 * get data visible to the CPU.
3560 * However, we maintain the display planes as UC, and so
3561 * need to rebind when first used as such.
3563 obj
->cache_level
= I915_CACHE_LLC
;
3565 obj
->cache_level
= I915_CACHE_NONE
;
3567 obj
->base
.driver_private
= NULL
;
3568 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3569 INIT_LIST_HEAD(&obj
->mm_list
);
3570 INIT_LIST_HEAD(&obj
->gtt_list
);
3571 INIT_LIST_HEAD(&obj
->ring_list
);
3572 INIT_LIST_HEAD(&obj
->exec_list
);
3573 obj
->madv
= I915_MADV_WILLNEED
;
3574 /* Avoid an unnecessary call to unbind on the first bind. */
3575 obj
->map_and_fenceable
= true;
3580 int i915_gem_init_object(struct drm_gem_object
*obj
)
3587 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3589 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3590 struct drm_device
*dev
= obj
->base
.dev
;
3591 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3593 trace_i915_gem_object_destroy(obj
);
3595 if (gem_obj
->import_attach
)
3596 drm_prime_gem_destroy(gem_obj
, obj
->sg_table
);
3599 i915_gem_detach_phys_object(dev
, obj
);
3602 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3603 bool was_interruptible
;
3605 was_interruptible
= dev_priv
->mm
.interruptible
;
3606 dev_priv
->mm
.interruptible
= false;
3608 WARN_ON(i915_gem_object_unbind(obj
));
3610 dev_priv
->mm
.interruptible
= was_interruptible
;
3613 i915_gem_object_put_pages_gtt(obj
);
3614 if (obj
->base
.map_list
.map
)
3615 drm_gem_free_mmap_offset(&obj
->base
);
3617 drm_gem_object_release(&obj
->base
);
3618 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3625 i915_gem_idle(struct drm_device
*dev
)
3627 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3630 mutex_lock(&dev
->struct_mutex
);
3632 if (dev_priv
->mm
.suspended
) {
3633 mutex_unlock(&dev
->struct_mutex
);
3637 ret
= i915_gpu_idle(dev
);
3639 mutex_unlock(&dev
->struct_mutex
);
3642 i915_gem_retire_requests(dev
);
3644 /* Under UMS, be paranoid and evict. */
3645 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3646 i915_gem_evict_everything(dev
);
3648 i915_gem_reset_fences(dev
);
3650 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3651 * We need to replace this with a semaphore, or something.
3652 * And not confound mm.suspended!
3654 dev_priv
->mm
.suspended
= 1;
3655 del_timer_sync(&dev_priv
->hangcheck_timer
);
3657 i915_kernel_lost_context(dev
);
3658 i915_gem_cleanup_ringbuffer(dev
);
3660 mutex_unlock(&dev
->struct_mutex
);
3662 /* Cancel the retire work handler, which should be idle now. */
3663 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3668 void i915_gem_l3_remap(struct drm_device
*dev
)
3670 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3674 if (!IS_IVYBRIDGE(dev
))
3677 if (!dev_priv
->mm
.l3_remap_info
)
3680 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3681 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3682 POSTING_READ(GEN7_MISCCPCTL
);
3684 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3685 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3686 if (remap
&& remap
!= dev_priv
->mm
.l3_remap_info
[i
/4])
3687 DRM_DEBUG("0x%x was already programmed to %x\n",
3688 GEN7_L3LOG_BASE
+ i
, remap
);
3689 if (remap
&& !dev_priv
->mm
.l3_remap_info
[i
/4])
3690 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3691 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->mm
.l3_remap_info
[i
/4]);
3694 /* Make sure all the writes land before disabling dop clock gating */
3695 POSTING_READ(GEN7_L3LOG_BASE
);
3697 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3700 void i915_gem_init_swizzling(struct drm_device
*dev
)
3702 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3704 if (INTEL_INFO(dev
)->gen
< 5 ||
3705 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3708 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3709 DISP_TILE_SURFACE_SWIZZLING
);
3714 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3716 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3718 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3721 void i915_gem_init_ppgtt(struct drm_device
*dev
)
3723 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3725 struct intel_ring_buffer
*ring
;
3726 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3727 uint32_t __iomem
*pd_addr
;
3731 if (!dev_priv
->mm
.aliasing_ppgtt
)
3735 pd_addr
= dev_priv
->mm
.gtt
->gtt
+ ppgtt
->pd_offset
/sizeof(uint32_t);
3736 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
3739 if (dev_priv
->mm
.gtt
->needs_dmar
)
3740 pt_addr
= ppgtt
->pt_dma_addr
[i
];
3742 pt_addr
= page_to_phys(ppgtt
->pt_pages
[i
]);
3744 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
3745 pd_entry
|= GEN6_PDE_VALID
;
3747 writel(pd_entry
, pd_addr
+ i
);
3751 pd_offset
= ppgtt
->pd_offset
;
3752 pd_offset
/= 64; /* in cachelines, */
3755 if (INTEL_INFO(dev
)->gen
== 6) {
3756 uint32_t ecochk
, gab_ctl
, ecobits
;
3758 ecobits
= I915_READ(GAC_ECO_BITS
);
3759 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
3761 gab_ctl
= I915_READ(GAB_CTL
);
3762 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
3764 ecochk
= I915_READ(GAM_ECOCHK
);
3765 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
3766 ECOCHK_PPGTT_CACHE64B
);
3767 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3768 } else if (INTEL_INFO(dev
)->gen
>= 7) {
3769 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
3770 /* GFX_MODE is per-ring on gen7+ */
3773 for_each_ring(ring
, dev_priv
, i
) {
3774 if (INTEL_INFO(dev
)->gen
>= 7)
3775 I915_WRITE(RING_MODE_GEN7(ring
),
3776 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3778 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
3779 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
3784 intel_enable_blt(struct drm_device
*dev
)
3789 /* The blitter was dysfunctional on early prototypes */
3790 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3791 DRM_INFO("BLT not supported on this pre-production hardware;"
3792 " graphics performance will be degraded.\n");
3800 i915_gem_init_hw(struct drm_device
*dev
)
3802 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3805 if (!intel_enable_gtt())
3808 i915_gem_l3_remap(dev
);
3810 i915_gem_init_swizzling(dev
);
3812 ret
= intel_init_render_ring_buffer(dev
);
3817 ret
= intel_init_bsd_ring_buffer(dev
);
3819 goto cleanup_render_ring
;
3822 if (intel_enable_blt(dev
)) {
3823 ret
= intel_init_blt_ring_buffer(dev
);
3825 goto cleanup_bsd_ring
;
3828 dev_priv
->next_seqno
= 1;
3831 * XXX: There was some w/a described somewhere suggesting loading
3832 * contexts before PPGTT.
3834 i915_gem_context_init(dev
);
3835 i915_gem_init_ppgtt(dev
);
3840 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3841 cleanup_render_ring
:
3842 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3847 intel_enable_ppgtt(struct drm_device
*dev
)
3849 if (i915_enable_ppgtt
>= 0)
3850 return i915_enable_ppgtt
;
3852 #ifdef CONFIG_INTEL_IOMMU
3853 /* Disable ppgtt on SNB if VT-d is on. */
3854 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
3861 int i915_gem_init(struct drm_device
*dev
)
3863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3864 unsigned long gtt_size
, mappable_size
;
3867 gtt_size
= dev_priv
->mm
.gtt
->gtt_total_entries
<< PAGE_SHIFT
;
3868 mappable_size
= dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
3870 mutex_lock(&dev
->struct_mutex
);
3871 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
3872 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3873 * aperture accordingly when using aliasing ppgtt. */
3874 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
3876 i915_gem_init_global_gtt(dev
, 0, mappable_size
, gtt_size
);
3878 ret
= i915_gem_init_aliasing_ppgtt(dev
);
3880 mutex_unlock(&dev
->struct_mutex
);
3884 /* Let GEM Manage all of the aperture.
3886 * However, leave one page at the end still bound to the scratch
3887 * page. There are a number of places where the hardware
3888 * apparently prefetches past the end of the object, and we've
3889 * seen multiple hangs with the GPU head pointer stuck in a
3890 * batchbuffer bound at the last page of the aperture. One page
3891 * should be enough to keep any prefetching inside of the
3894 i915_gem_init_global_gtt(dev
, 0, mappable_size
,
3898 ret
= i915_gem_init_hw(dev
);
3899 mutex_unlock(&dev
->struct_mutex
);
3901 i915_gem_cleanup_aliasing_ppgtt(dev
);
3905 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3906 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3907 dev_priv
->dri1
.allow_batchbuffer
= 1;
3912 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3914 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3915 struct intel_ring_buffer
*ring
;
3918 for_each_ring(ring
, dev_priv
, i
)
3919 intel_cleanup_ring_buffer(ring
);
3923 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3924 struct drm_file
*file_priv
)
3926 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3929 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3932 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3933 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3934 atomic_set(&dev_priv
->mm
.wedged
, 0);
3937 mutex_lock(&dev
->struct_mutex
);
3938 dev_priv
->mm
.suspended
= 0;
3940 ret
= i915_gem_init_hw(dev
);
3942 mutex_unlock(&dev
->struct_mutex
);
3946 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3947 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3948 mutex_unlock(&dev
->struct_mutex
);
3950 ret
= drm_irq_install(dev
);
3952 goto cleanup_ringbuffer
;
3957 mutex_lock(&dev
->struct_mutex
);
3958 i915_gem_cleanup_ringbuffer(dev
);
3959 dev_priv
->mm
.suspended
= 1;
3960 mutex_unlock(&dev
->struct_mutex
);
3966 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3967 struct drm_file
*file_priv
)
3969 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3972 drm_irq_uninstall(dev
);
3973 return i915_gem_idle(dev
);
3977 i915_gem_lastclose(struct drm_device
*dev
)
3981 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3984 ret
= i915_gem_idle(dev
);
3986 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3990 init_ring_lists(struct intel_ring_buffer
*ring
)
3992 INIT_LIST_HEAD(&ring
->active_list
);
3993 INIT_LIST_HEAD(&ring
->request_list
);
3997 i915_gem_load(struct drm_device
*dev
)
4000 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4002 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4003 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4004 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4005 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4006 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4007 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4008 init_ring_lists(&dev_priv
->ring
[i
]);
4009 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4010 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4011 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4012 i915_gem_retire_work_handler
);
4013 init_completion(&dev_priv
->error_completion
);
4015 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4017 I915_WRITE(MI_ARB_STATE
,
4018 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4021 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4023 /* Old X drivers will take 0-2 for front, back, depth buffers */
4024 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4025 dev_priv
->fence_reg_start
= 3;
4027 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4028 dev_priv
->num_fence_regs
= 16;
4030 dev_priv
->num_fence_regs
= 8;
4032 /* Initialize fence registers to zero */
4033 i915_gem_reset_fences(dev
);
4035 i915_gem_detect_bit_6_swizzle(dev
);
4036 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4038 dev_priv
->mm
.interruptible
= true;
4040 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4041 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4042 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4046 * Create a physically contiguous memory object for this object
4047 * e.g. for cursor + overlay regs
4049 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4050 int id
, int size
, int align
)
4052 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4053 struct drm_i915_gem_phys_object
*phys_obj
;
4056 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4059 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4065 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4066 if (!phys_obj
->handle
) {
4071 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4074 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4082 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4084 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4085 struct drm_i915_gem_phys_object
*phys_obj
;
4087 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4090 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4091 if (phys_obj
->cur_obj
) {
4092 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4096 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4098 drm_pci_free(dev
, phys_obj
->handle
);
4100 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4103 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4107 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4108 i915_gem_free_phys_object(dev
, i
);
4111 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4112 struct drm_i915_gem_object
*obj
)
4114 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4121 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4123 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4124 for (i
= 0; i
< page_count
; i
++) {
4125 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4126 if (!IS_ERR(page
)) {
4127 char *dst
= kmap_atomic(page
);
4128 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4131 drm_clflush_pages(&page
, 1);
4133 set_page_dirty(page
);
4134 mark_page_accessed(page
);
4135 page_cache_release(page
);
4138 intel_gtt_chipset_flush();
4140 obj
->phys_obj
->cur_obj
= NULL
;
4141 obj
->phys_obj
= NULL
;
4145 i915_gem_attach_phys_object(struct drm_device
*dev
,
4146 struct drm_i915_gem_object
*obj
,
4150 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4151 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4156 if (id
> I915_MAX_PHYS_OBJECT
)
4159 if (obj
->phys_obj
) {
4160 if (obj
->phys_obj
->id
== id
)
4162 i915_gem_detach_phys_object(dev
, obj
);
4165 /* create a new object */
4166 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4167 ret
= i915_gem_init_phys_object(dev
, id
,
4168 obj
->base
.size
, align
);
4170 DRM_ERROR("failed to init phys object %d size: %zu\n",
4171 id
, obj
->base
.size
);
4176 /* bind to the object */
4177 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4178 obj
->phys_obj
->cur_obj
= obj
;
4180 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4182 for (i
= 0; i
< page_count
; i
++) {
4186 page
= shmem_read_mapping_page(mapping
, i
);
4188 return PTR_ERR(page
);
4190 src
= kmap_atomic(page
);
4191 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4192 memcpy(dst
, src
, PAGE_SIZE
);
4195 mark_page_accessed(page
);
4196 page_cache_release(page
);
4203 i915_gem_phys_pwrite(struct drm_device
*dev
,
4204 struct drm_i915_gem_object
*obj
,
4205 struct drm_i915_gem_pwrite
*args
,
4206 struct drm_file
*file_priv
)
4208 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4209 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4211 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4212 unsigned long unwritten
;
4214 /* The physical object once assigned is fixed for the lifetime
4215 * of the obj, so we can safely drop the lock and continue
4218 mutex_unlock(&dev
->struct_mutex
);
4219 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4220 mutex_lock(&dev
->struct_mutex
);
4225 intel_gtt_chipset_flush();
4229 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4231 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4233 /* Clean up our request list when the client is going away, so that
4234 * later retire_requests won't dereference our soon-to-be-gone
4237 spin_lock(&file_priv
->mm
.lock
);
4238 while (!list_empty(&file_priv
->mm
.request_list
)) {
4239 struct drm_i915_gem_request
*request
;
4241 request
= list_first_entry(&file_priv
->mm
.request_list
,
4242 struct drm_i915_gem_request
,
4244 list_del(&request
->client_list
);
4245 request
->file_priv
= NULL
;
4247 spin_unlock(&file_priv
->mm
.lock
);
4251 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4253 struct drm_i915_private
*dev_priv
=
4254 container_of(shrinker
,
4255 struct drm_i915_private
,
4256 mm
.inactive_shrinker
);
4257 struct drm_device
*dev
= dev_priv
->dev
;
4258 struct drm_i915_gem_object
*obj
;
4259 int nr_to_scan
= sc
->nr_to_scan
;
4262 if (!mutex_trylock(&dev
->struct_mutex
))
4266 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4268 i915_gem_shrink_all(dev_priv
);
4272 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, gtt_list
)
4273 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4274 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
4275 if (obj
->pin_count
== 0)
4276 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4278 mutex_unlock(&dev
->struct_mutex
);