2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
43 static __must_check
int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
46 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
47 struct drm_i915_gem_object
*obj
,
48 struct drm_i915_gem_pwrite
*args
,
49 struct drm_file
*file
);
51 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
52 struct drm_i915_gem_object
*obj
);
53 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
54 struct drm_i915_fence_reg
*fence
,
57 static unsigned long i915_gem_inactive_count(struct shrinker
*shrinker
,
58 struct shrink_control
*sc
);
59 static unsigned long i915_gem_inactive_scan(struct shrinker
*shrinker
,
60 struct shrink_control
*sc
);
61 static unsigned long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
62 static unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
63 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
64 static void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
66 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
67 enum i915_cache_level level
)
69 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
74 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
77 return obj
->pin_display
;
80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
83 i915_gem_release_mmap(obj
);
85 /* As we do not have an associated fence register, we will force
86 * a tiling change if we ever need to acquire one.
88 obj
->fence_dirty
= false;
89 obj
->fence_reg
= I915_FENCE_REG_NONE
;
92 /* some bookkeeping */
93 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
96 spin_lock(&dev_priv
->mm
.object_stat_lock
);
97 dev_priv
->mm
.object_count
++;
98 dev_priv
->mm
.object_memory
+= size
;
99 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
102 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
105 spin_lock(&dev_priv
->mm
.object_stat_lock
);
106 dev_priv
->mm
.object_count
--;
107 dev_priv
->mm
.object_memory
-= size
;
108 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
112 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
116 #define EXIT_COND (!i915_reset_in_progress(error) || \
117 i915_terminally_wedged(error))
122 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
123 * userspace. If it takes that long something really bad is going on and
124 * we should simply try to bail out and fail as gracefully as possible.
126 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
130 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
132 } else if (ret
< 0) {
140 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
145 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
149 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
153 WARN_ON(i915_verify_lists(dev
));
158 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
160 return i915_gem_obj_bound_any(obj
) && !obj
->active
;
164 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
165 struct drm_file
*file
)
167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
168 struct drm_i915_gem_init
*args
= data
;
170 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
173 if (args
->gtt_start
>= args
->gtt_end
||
174 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
177 /* GEM with user mode setting was never supported on ilk and later. */
178 if (INTEL_INFO(dev
)->gen
>= 5)
181 mutex_lock(&dev
->struct_mutex
);
182 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
184 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
185 mutex_unlock(&dev
->struct_mutex
);
191 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
192 struct drm_file
*file
)
194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
195 struct drm_i915_gem_get_aperture
*args
= data
;
196 struct drm_i915_gem_object
*obj
;
200 mutex_lock(&dev
->struct_mutex
);
201 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
202 if (i915_gem_obj_is_pinned(obj
))
203 pinned
+= i915_gem_obj_ggtt_size(obj
);
204 mutex_unlock(&dev
->struct_mutex
);
206 args
->aper_size
= dev_priv
->gtt
.base
.total
;
207 args
->aper_available_size
= args
->aper_size
- pinned
;
212 void *i915_gem_object_alloc(struct drm_device
*dev
)
214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
215 return kmem_cache_zalloc(dev_priv
->slab
, GFP_KERNEL
);
218 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
220 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
221 kmem_cache_free(dev_priv
->slab
, obj
);
225 i915_gem_create(struct drm_file
*file
,
226 struct drm_device
*dev
,
230 struct drm_i915_gem_object
*obj
;
234 size
= roundup(size
, PAGE_SIZE
);
238 /* Allocate the new object */
239 obj
= i915_gem_alloc_object(dev
, size
);
243 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
244 /* drop reference from allocate - handle holds it now */
245 drm_gem_object_unreference_unlocked(&obj
->base
);
254 i915_gem_dumb_create(struct drm_file
*file
,
255 struct drm_device
*dev
,
256 struct drm_mode_create_dumb
*args
)
258 /* have to work out size/pitch and return them */
259 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
260 args
->size
= args
->pitch
* args
->height
;
261 return i915_gem_create(file
, dev
,
262 args
->size
, &args
->handle
);
266 * Creates a new mm object and returns a handle to it.
269 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
270 struct drm_file
*file
)
272 struct drm_i915_gem_create
*args
= data
;
274 return i915_gem_create(file
, dev
,
275 args
->size
, &args
->handle
);
279 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
280 const char *gpu_vaddr
, int gpu_offset
,
283 int ret
, cpu_offset
= 0;
286 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
287 int this_length
= min(cacheline_end
- gpu_offset
, length
);
288 int swizzled_gpu_offset
= gpu_offset
^ 64;
290 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
291 gpu_vaddr
+ swizzled_gpu_offset
,
296 cpu_offset
+= this_length
;
297 gpu_offset
+= this_length
;
298 length
-= this_length
;
305 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
306 const char __user
*cpu_vaddr
,
309 int ret
, cpu_offset
= 0;
312 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
313 int this_length
= min(cacheline_end
- gpu_offset
, length
);
314 int swizzled_gpu_offset
= gpu_offset
^ 64;
316 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
317 cpu_vaddr
+ cpu_offset
,
322 cpu_offset
+= this_length
;
323 gpu_offset
+= this_length
;
324 length
-= this_length
;
331 * Pins the specified object's pages and synchronizes the object with
332 * GPU accesses. Sets needs_clflush to non-zero if the caller should
333 * flush the object from the CPU cache.
335 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
345 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
346 /* If we're not in the cpu read domain, set ourself into the gtt
347 * read domain and manually flush cachelines (if required). This
348 * optimizes for the case when the gpu will dirty the data
349 * anyway again before the next pread happens. */
350 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
352 ret
= i915_gem_object_wait_rendering(obj
, true);
357 ret
= i915_gem_object_get_pages(obj
);
361 i915_gem_object_pin_pages(obj
);
366 /* Per-page copy function for the shmem pread fastpath.
367 * Flushes invalid cachelines before reading the target if
368 * needs_clflush is set. */
370 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
371 char __user
*user_data
,
372 bool page_do_bit17_swizzling
, bool needs_clflush
)
377 if (unlikely(page_do_bit17_swizzling
))
380 vaddr
= kmap_atomic(page
);
382 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
384 ret
= __copy_to_user_inatomic(user_data
,
385 vaddr
+ shmem_page_offset
,
387 kunmap_atomic(vaddr
);
389 return ret
? -EFAULT
: 0;
393 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
396 if (unlikely(swizzled
)) {
397 unsigned long start
= (unsigned long) addr
;
398 unsigned long end
= (unsigned long) addr
+ length
;
400 /* For swizzling simply ensure that we always flush both
401 * channels. Lame, but simple and it works. Swizzled
402 * pwrite/pread is far from a hotpath - current userspace
403 * doesn't use it at all. */
404 start
= round_down(start
, 128);
405 end
= round_up(end
, 128);
407 drm_clflush_virt_range((void *)start
, end
- start
);
409 drm_clflush_virt_range(addr
, length
);
414 /* Only difference to the fast-path function is that this can handle bit17
415 * and uses non-atomic copy and kmap functions. */
417 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
418 char __user
*user_data
,
419 bool page_do_bit17_swizzling
, bool needs_clflush
)
426 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
428 page_do_bit17_swizzling
);
430 if (page_do_bit17_swizzling
)
431 ret
= __copy_to_user_swizzled(user_data
,
432 vaddr
, shmem_page_offset
,
435 ret
= __copy_to_user(user_data
,
436 vaddr
+ shmem_page_offset
,
440 return ret
? - EFAULT
: 0;
444 i915_gem_shmem_pread(struct drm_device
*dev
,
445 struct drm_i915_gem_object
*obj
,
446 struct drm_i915_gem_pread
*args
,
447 struct drm_file
*file
)
449 char __user
*user_data
;
452 int shmem_page_offset
, page_length
, ret
= 0;
453 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
455 int needs_clflush
= 0;
456 struct sg_page_iter sg_iter
;
458 user_data
= to_user_ptr(args
->data_ptr
);
461 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
463 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
467 offset
= args
->offset
;
469 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
470 offset
>> PAGE_SHIFT
) {
471 struct page
*page
= sg_page_iter_page(&sg_iter
);
476 /* Operation in this page
478 * shmem_page_offset = offset within page in shmem file
479 * page_length = bytes to copy for this page
481 shmem_page_offset
= offset_in_page(offset
);
482 page_length
= remain
;
483 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
484 page_length
= PAGE_SIZE
- shmem_page_offset
;
486 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
487 (page_to_phys(page
) & (1 << 17)) != 0;
489 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
490 user_data
, page_do_bit17_swizzling
,
495 mutex_unlock(&dev
->struct_mutex
);
497 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
498 ret
= fault_in_multipages_writeable(user_data
, remain
);
499 /* Userspace is tricking us, but we've already clobbered
500 * its pages with the prefault and promised to write the
501 * data up to the first fault. Hence ignore any errors
502 * and just continue. */
507 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
508 user_data
, page_do_bit17_swizzling
,
511 mutex_lock(&dev
->struct_mutex
);
517 remain
-= page_length
;
518 user_data
+= page_length
;
519 offset
+= page_length
;
523 i915_gem_object_unpin_pages(obj
);
529 * Reads data from the object referenced by handle.
531 * On error, the contents of *data are undefined.
534 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
535 struct drm_file
*file
)
537 struct drm_i915_gem_pread
*args
= data
;
538 struct drm_i915_gem_object
*obj
;
544 if (!access_ok(VERIFY_WRITE
,
545 to_user_ptr(args
->data_ptr
),
549 ret
= i915_mutex_lock_interruptible(dev
);
553 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
554 if (&obj
->base
== NULL
) {
559 /* Bounds check source. */
560 if (args
->offset
> obj
->base
.size
||
561 args
->size
> obj
->base
.size
- args
->offset
) {
566 /* prime objects have no backing filp to GEM pread/pwrite
569 if (!obj
->base
.filp
) {
574 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
576 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
579 drm_gem_object_unreference(&obj
->base
);
581 mutex_unlock(&dev
->struct_mutex
);
585 /* This is the fast write path which cannot handle
586 * page faults in the source data
590 fast_user_write(struct io_mapping
*mapping
,
591 loff_t page_base
, int page_offset
,
592 char __user
*user_data
,
595 void __iomem
*vaddr_atomic
;
597 unsigned long unwritten
;
599 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
600 /* We can use the cpu mem copy function because this is X86. */
601 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
602 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
604 io_mapping_unmap_atomic(vaddr_atomic
);
609 * This is the fast pwrite path, where we copy the data directly from the
610 * user into the GTT, uncached.
613 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
614 struct drm_i915_gem_object
*obj
,
615 struct drm_i915_gem_pwrite
*args
,
616 struct drm_file
*file
)
618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
620 loff_t offset
, page_base
;
621 char __user
*user_data
;
622 int page_offset
, page_length
, ret
;
624 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
628 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
632 ret
= i915_gem_object_put_fence(obj
);
636 user_data
= to_user_ptr(args
->data_ptr
);
639 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
642 /* Operation in this page
644 * page_base = page offset within aperture
645 * page_offset = offset within page
646 * page_length = bytes to copy for this page
648 page_base
= offset
& PAGE_MASK
;
649 page_offset
= offset_in_page(offset
);
650 page_length
= remain
;
651 if ((page_offset
+ remain
) > PAGE_SIZE
)
652 page_length
= PAGE_SIZE
- page_offset
;
654 /* If we get a fault while copying data, then (presumably) our
655 * source page isn't available. Return the error and we'll
656 * retry in the slow path.
658 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
659 page_offset
, user_data
, page_length
)) {
664 remain
-= page_length
;
665 user_data
+= page_length
;
666 offset
+= page_length
;
670 i915_gem_object_ggtt_unpin(obj
);
675 /* Per-page copy function for the shmem pwrite fastpath.
676 * Flushes invalid cachelines before writing to the target if
677 * needs_clflush_before is set and flushes out any written cachelines after
678 * writing if needs_clflush is set. */
680 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
681 char __user
*user_data
,
682 bool page_do_bit17_swizzling
,
683 bool needs_clflush_before
,
684 bool needs_clflush_after
)
689 if (unlikely(page_do_bit17_swizzling
))
692 vaddr
= kmap_atomic(page
);
693 if (needs_clflush_before
)
694 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
696 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
697 user_data
, page_length
);
698 if (needs_clflush_after
)
699 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
701 kunmap_atomic(vaddr
);
703 return ret
? -EFAULT
: 0;
706 /* Only difference to the fast-path function is that this can handle bit17
707 * and uses non-atomic copy and kmap functions. */
709 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
710 char __user
*user_data
,
711 bool page_do_bit17_swizzling
,
712 bool needs_clflush_before
,
713 bool needs_clflush_after
)
719 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
720 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
722 page_do_bit17_swizzling
);
723 if (page_do_bit17_swizzling
)
724 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
728 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
731 if (needs_clflush_after
)
732 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
734 page_do_bit17_swizzling
);
737 return ret
? -EFAULT
: 0;
741 i915_gem_shmem_pwrite(struct drm_device
*dev
,
742 struct drm_i915_gem_object
*obj
,
743 struct drm_i915_gem_pwrite
*args
,
744 struct drm_file
*file
)
748 char __user
*user_data
;
749 int shmem_page_offset
, page_length
, ret
= 0;
750 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
751 int hit_slowpath
= 0;
752 int needs_clflush_after
= 0;
753 int needs_clflush_before
= 0;
754 struct sg_page_iter sg_iter
;
756 user_data
= to_user_ptr(args
->data_ptr
);
759 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
761 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
762 /* If we're not in the cpu write domain, set ourself into the gtt
763 * write domain and manually flush cachelines (if required). This
764 * optimizes for the case when the gpu will use the data
765 * right away and we therefore have to clflush anyway. */
766 needs_clflush_after
= cpu_write_needs_clflush(obj
);
767 ret
= i915_gem_object_wait_rendering(obj
, false);
771 /* Same trick applies to invalidate partially written cachelines read
773 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
774 needs_clflush_before
=
775 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
777 ret
= i915_gem_object_get_pages(obj
);
781 i915_gem_object_pin_pages(obj
);
783 offset
= args
->offset
;
786 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
787 offset
>> PAGE_SHIFT
) {
788 struct page
*page
= sg_page_iter_page(&sg_iter
);
789 int partial_cacheline_write
;
794 /* Operation in this page
796 * shmem_page_offset = offset within page in shmem file
797 * page_length = bytes to copy for this page
799 shmem_page_offset
= offset_in_page(offset
);
801 page_length
= remain
;
802 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
803 page_length
= PAGE_SIZE
- shmem_page_offset
;
805 /* If we don't overwrite a cacheline completely we need to be
806 * careful to have up-to-date data by first clflushing. Don't
807 * overcomplicate things and flush the entire patch. */
808 partial_cacheline_write
= needs_clflush_before
&&
809 ((shmem_page_offset
| page_length
)
810 & (boot_cpu_data
.x86_clflush_size
- 1));
812 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
813 (page_to_phys(page
) & (1 << 17)) != 0;
815 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
816 user_data
, page_do_bit17_swizzling
,
817 partial_cacheline_write
,
818 needs_clflush_after
);
823 mutex_unlock(&dev
->struct_mutex
);
824 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
825 user_data
, page_do_bit17_swizzling
,
826 partial_cacheline_write
,
827 needs_clflush_after
);
829 mutex_lock(&dev
->struct_mutex
);
835 remain
-= page_length
;
836 user_data
+= page_length
;
837 offset
+= page_length
;
841 i915_gem_object_unpin_pages(obj
);
845 * Fixup: Flush cpu caches in case we didn't flush the dirty
846 * cachelines in-line while writing and the object moved
847 * out of the cpu write domain while we've dropped the lock.
849 if (!needs_clflush_after
&&
850 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
851 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
852 i915_gem_chipset_flush(dev
);
856 if (needs_clflush_after
)
857 i915_gem_chipset_flush(dev
);
863 * Writes data to the object referenced by handle.
865 * On error, the contents of the buffer that were to be modified are undefined.
868 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
869 struct drm_file
*file
)
871 struct drm_i915_gem_pwrite
*args
= data
;
872 struct drm_i915_gem_object
*obj
;
878 if (!access_ok(VERIFY_READ
,
879 to_user_ptr(args
->data_ptr
),
883 if (likely(!i915
.prefault_disable
)) {
884 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
890 ret
= i915_mutex_lock_interruptible(dev
);
894 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
895 if (&obj
->base
== NULL
) {
900 /* Bounds check destination. */
901 if (args
->offset
> obj
->base
.size
||
902 args
->size
> obj
->base
.size
- args
->offset
) {
907 /* prime objects have no backing filp to GEM pread/pwrite
910 if (!obj
->base
.filp
) {
915 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
918 /* We can only do the GTT pwrite on untiled buffers, as otherwise
919 * it would end up going through the fenced access, and we'll get
920 * different detiling behavior between reading and writing.
921 * pread/pwrite currently are reading and writing from the CPU
922 * perspective, requiring manual detiling by the client.
925 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
929 if (obj
->tiling_mode
== I915_TILING_NONE
&&
930 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
931 cpu_write_needs_clflush(obj
)) {
932 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
933 /* Note that the gtt paths might fail with non-page-backed user
934 * pointers (e.g. gtt mappings when moving data between
935 * textures). Fallback to the shmem path in that case. */
938 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
939 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
942 drm_gem_object_unreference(&obj
->base
);
944 mutex_unlock(&dev
->struct_mutex
);
949 i915_gem_check_wedge(struct i915_gpu_error
*error
,
952 if (i915_reset_in_progress(error
)) {
953 /* Non-interruptible callers can't handle -EAGAIN, hence return
954 * -EIO unconditionally for these. */
958 /* Recovery complete, but the reset failed ... */
959 if (i915_terminally_wedged(error
))
969 * Compare seqno against outstanding lazy request. Emit a request if they are
973 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
977 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
980 if (seqno
== ring
->outstanding_lazy_seqno
)
981 ret
= i915_add_request(ring
, NULL
);
986 static void fake_irq(unsigned long data
)
988 wake_up_process((struct task_struct
*)data
);
991 static bool missed_irq(struct drm_i915_private
*dev_priv
,
992 struct intel_ring_buffer
*ring
)
994 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
997 static bool can_wait_boost(struct drm_i915_file_private
*file_priv
)
999 if (file_priv
== NULL
)
1002 return !atomic_xchg(&file_priv
->rps_wait_boost
, true);
1006 * __wait_seqno - wait until execution of seqno has finished
1007 * @ring: the ring expected to report seqno
1009 * @reset_counter: reset sequence associated with the given seqno
1010 * @interruptible: do an interruptible wait (normally yes)
1011 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1013 * Note: It is of utmost importance that the passed in seqno and reset_counter
1014 * values have been read by the caller in an smp safe manner. Where read-side
1015 * locks are involved, it is sufficient to read the reset_counter before
1016 * unlocking the lock that protects the seqno. For lockless tricks, the
1017 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1020 * Returns 0 if the seqno was found within the alloted time. Else returns the
1021 * errno with remaining time filled in timeout argument.
1023 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
1024 unsigned reset_counter
,
1026 struct timespec
*timeout
,
1027 struct drm_i915_file_private
*file_priv
)
1029 struct drm_device
*dev
= ring
->dev
;
1030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1031 const bool irq_test_in_progress
=
1032 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1033 struct timespec before
, now
;
1035 unsigned long timeout_expire
;
1038 WARN(dev_priv
->pm
.irqs_disabled
, "IRQs disabled\n");
1040 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1043 timeout_expire
= timeout
? jiffies
+ timespec_to_jiffies_timeout(timeout
) : 0;
1045 if (INTEL_INFO(dev
)->gen
>= 6 && can_wait_boost(file_priv
)) {
1046 gen6_rps_boost(dev_priv
);
1048 mod_delayed_work(dev_priv
->wq
,
1049 &file_priv
->mm
.idle_work
,
1050 msecs_to_jiffies(100));
1053 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
)))
1056 /* Record current time in case interrupted by signal, or wedged */
1057 trace_i915_gem_request_wait_begin(ring
, seqno
);
1058 getrawmonotonic(&before
);
1060 struct timer_list timer
;
1062 prepare_to_wait(&ring
->irq_queue
, &wait
,
1063 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1065 /* We need to check whether any gpu reset happened in between
1066 * the caller grabbing the seqno and now ... */
1067 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1068 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1069 * is truely gone. */
1070 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1076 if (i915_seqno_passed(ring
->get_seqno(ring
, false), seqno
)) {
1081 if (interruptible
&& signal_pending(current
)) {
1086 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1091 timer
.function
= NULL
;
1092 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1093 unsigned long expire
;
1095 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1096 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1097 mod_timer(&timer
, expire
);
1102 if (timer
.function
) {
1103 del_singleshot_timer_sync(&timer
);
1104 destroy_timer_on_stack(&timer
);
1107 getrawmonotonic(&now
);
1108 trace_i915_gem_request_wait_end(ring
, seqno
);
1110 if (!irq_test_in_progress
)
1111 ring
->irq_put(ring
);
1113 finish_wait(&ring
->irq_queue
, &wait
);
1116 struct timespec sleep_time
= timespec_sub(now
, before
);
1117 *timeout
= timespec_sub(*timeout
, sleep_time
);
1118 if (!timespec_valid(timeout
)) /* i.e. negative time remains */
1119 set_normalized_timespec(timeout
, 0, 0);
1126 * Waits for a sequence number to be signaled, and cleans up the
1127 * request and object lists appropriately for that event.
1130 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1132 struct drm_device
*dev
= ring
->dev
;
1133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1134 bool interruptible
= dev_priv
->mm
.interruptible
;
1137 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1140 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1144 ret
= i915_gem_check_olr(ring
, seqno
);
1148 return __wait_seqno(ring
, seqno
,
1149 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1150 interruptible
, NULL
, NULL
);
1154 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
,
1155 struct intel_ring_buffer
*ring
)
1157 i915_gem_retire_requests_ring(ring
);
1159 /* Manually manage the write flush as we may have not yet
1160 * retired the buffer.
1162 * Note that the last_write_seqno is always the earlier of
1163 * the two (read/write) seqno, so if we haved successfully waited,
1164 * we know we have passed the last write.
1166 obj
->last_write_seqno
= 0;
1167 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1173 * Ensures that all rendering to the object has completed and the object is
1174 * safe to unbind from the GTT or access from the CPU.
1176 static __must_check
int
1177 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1180 struct intel_ring_buffer
*ring
= obj
->ring
;
1184 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1188 ret
= i915_wait_seqno(ring
, seqno
);
1192 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1195 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1196 * as the object state may change during this call.
1198 static __must_check
int
1199 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1200 struct drm_i915_file_private
*file_priv
,
1203 struct drm_device
*dev
= obj
->base
.dev
;
1204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1205 struct intel_ring_buffer
*ring
= obj
->ring
;
1206 unsigned reset_counter
;
1210 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1211 BUG_ON(!dev_priv
->mm
.interruptible
);
1213 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1217 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1221 ret
= i915_gem_check_olr(ring
, seqno
);
1225 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1226 mutex_unlock(&dev
->struct_mutex
);
1227 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
, file_priv
);
1228 mutex_lock(&dev
->struct_mutex
);
1232 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1236 * Called when user space prepares to use an object with the CPU, either
1237 * through the mmap ioctl's mapping or a GTT mapping.
1240 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1241 struct drm_file
*file
)
1243 struct drm_i915_gem_set_domain
*args
= data
;
1244 struct drm_i915_gem_object
*obj
;
1245 uint32_t read_domains
= args
->read_domains
;
1246 uint32_t write_domain
= args
->write_domain
;
1249 /* Only handle setting domains to types used by the CPU. */
1250 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1253 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1256 /* Having something in the write domain implies it's in the read
1257 * domain, and only that read domain. Enforce that in the request.
1259 if (write_domain
!= 0 && read_domains
!= write_domain
)
1262 ret
= i915_mutex_lock_interruptible(dev
);
1266 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1267 if (&obj
->base
== NULL
) {
1272 /* Try to flush the object off the GPU without holding the lock.
1273 * We will repeat the flush holding the lock in the normal manner
1274 * to catch cases where we are gazumped.
1276 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1282 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1283 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1285 /* Silently promote "you're not bound, there was nothing to do"
1286 * to success, since the client was just asking us to
1287 * make sure everything was done.
1292 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1296 drm_gem_object_unreference(&obj
->base
);
1298 mutex_unlock(&dev
->struct_mutex
);
1303 * Called when user space has done writes to this buffer
1306 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1307 struct drm_file
*file
)
1309 struct drm_i915_gem_sw_finish
*args
= data
;
1310 struct drm_i915_gem_object
*obj
;
1313 ret
= i915_mutex_lock_interruptible(dev
);
1317 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1318 if (&obj
->base
== NULL
) {
1323 /* Pinned buffers may be scanout, so flush the cache */
1324 if (obj
->pin_display
)
1325 i915_gem_object_flush_cpu_write_domain(obj
, true);
1327 drm_gem_object_unreference(&obj
->base
);
1329 mutex_unlock(&dev
->struct_mutex
);
1334 * Maps the contents of an object, returning the address it is mapped
1337 * While the mapping holds a reference on the contents of the object, it doesn't
1338 * imply a ref on the object itself.
1341 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1342 struct drm_file
*file
)
1344 struct drm_i915_gem_mmap
*args
= data
;
1345 struct drm_gem_object
*obj
;
1348 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1352 /* prime objects have no backing filp to GEM mmap
1356 drm_gem_object_unreference_unlocked(obj
);
1360 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1361 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1363 drm_gem_object_unreference_unlocked(obj
);
1364 if (IS_ERR((void *)addr
))
1367 args
->addr_ptr
= (uint64_t) addr
;
1373 * i915_gem_fault - fault a page into the GTT
1374 * vma: VMA in question
1377 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1378 * from userspace. The fault handler takes care of binding the object to
1379 * the GTT (if needed), allocating and programming a fence register (again,
1380 * only if needed based on whether the old reg is still valid or the object
1381 * is tiled) and inserting a new PTE into the faulting process.
1383 * Note that the faulting process may involve evicting existing objects
1384 * from the GTT and/or fence registers to make room. So performance may
1385 * suffer if the GTT working set is large or there are few fence registers
1388 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1390 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1391 struct drm_device
*dev
= obj
->base
.dev
;
1392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1393 pgoff_t page_offset
;
1396 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1398 intel_runtime_pm_get(dev_priv
);
1400 /* We don't use vmf->pgoff since that has the fake offset */
1401 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1404 ret
= i915_mutex_lock_interruptible(dev
);
1408 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1410 /* Try to flush the object off the GPU first without holding the lock.
1411 * Upon reacquiring the lock, we will perform our sanity checks and then
1412 * repeat the flush holding the lock in the normal manner to catch cases
1413 * where we are gazumped.
1415 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1419 /* Access to snoopable pages through the GTT is incoherent. */
1420 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1425 /* Now bind it into the GTT if needed */
1426 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
1430 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1434 ret
= i915_gem_object_get_fence(obj
);
1438 obj
->fault_mappable
= true;
1440 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1444 /* Finally, remap it using the new GTT offset */
1445 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1447 i915_gem_object_ggtt_unpin(obj
);
1449 mutex_unlock(&dev
->struct_mutex
);
1453 /* If this -EIO is due to a gpu hang, give the reset code a
1454 * chance to clean up the mess. Otherwise return the proper
1456 if (i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1457 ret
= VM_FAULT_SIGBUS
;
1462 * EAGAIN means the gpu is hung and we'll wait for the error
1463 * handler to reset everything when re-faulting in
1464 * i915_mutex_lock_interruptible.
1471 * EBUSY is ok: this just means that another thread
1472 * already did the job.
1474 ret
= VM_FAULT_NOPAGE
;
1481 ret
= VM_FAULT_SIGBUS
;
1484 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1485 ret
= VM_FAULT_SIGBUS
;
1489 intel_runtime_pm_put(dev_priv
);
1493 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1495 struct i915_vma
*vma
;
1498 * Only the global gtt is relevant for gtt memory mappings, so restrict
1499 * list traversal to objects bound into the global address space. Note
1500 * that the active list should be empty, but better safe than sorry.
1502 WARN_ON(!list_empty(&dev_priv
->gtt
.base
.active_list
));
1503 list_for_each_entry(vma
, &dev_priv
->gtt
.base
.active_list
, mm_list
)
1504 i915_gem_release_mmap(vma
->obj
);
1505 list_for_each_entry(vma
, &dev_priv
->gtt
.base
.inactive_list
, mm_list
)
1506 i915_gem_release_mmap(vma
->obj
);
1510 * i915_gem_release_mmap - remove physical page mappings
1511 * @obj: obj in question
1513 * Preserve the reservation of the mmapping with the DRM core code, but
1514 * relinquish ownership of the pages back to the system.
1516 * It is vital that we remove the page mapping if we have mapped a tiled
1517 * object through the GTT and then lose the fence register due to
1518 * resource pressure. Similarly if the object has been moved out of the
1519 * aperture, than pages mapped into userspace must be revoked. Removing the
1520 * mapping will then trigger a page fault on the next user access, allowing
1521 * fixup by i915_gem_fault().
1524 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1526 if (!obj
->fault_mappable
)
1529 drm_vma_node_unmap(&obj
->base
.vma_node
,
1530 obj
->base
.dev
->anon_inode
->i_mapping
);
1531 obj
->fault_mappable
= false;
1535 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1539 if (INTEL_INFO(dev
)->gen
>= 4 ||
1540 tiling_mode
== I915_TILING_NONE
)
1543 /* Previous chips need a power-of-two fence region when tiling */
1544 if (INTEL_INFO(dev
)->gen
== 3)
1545 gtt_size
= 1024*1024;
1547 gtt_size
= 512*1024;
1549 while (gtt_size
< size
)
1556 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1557 * @obj: object to check
1559 * Return the required GTT alignment for an object, taking into account
1560 * potential fence register mapping.
1563 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1564 int tiling_mode
, bool fenced
)
1567 * Minimum alignment is 4k (GTT page size), but might be greater
1568 * if a fence register is needed for the object.
1570 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1571 tiling_mode
== I915_TILING_NONE
)
1575 * Previous chips need to be aligned to the size of the smallest
1576 * fence register that can contain the object.
1578 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1581 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1583 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1586 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1589 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1591 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1595 /* Badly fragmented mmap space? The only way we can recover
1596 * space is by destroying unwanted objects. We can't randomly release
1597 * mmap_offsets as userspace expects them to be persistent for the
1598 * lifetime of the objects. The closest we can is to release the
1599 * offsets on purgeable objects by truncating it and marking it purged,
1600 * which prevents userspace from ever using that object again.
1602 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1603 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1607 i915_gem_shrink_all(dev_priv
);
1608 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1610 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1615 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1617 drm_gem_free_mmap_offset(&obj
->base
);
1621 i915_gem_mmap_gtt(struct drm_file
*file
,
1622 struct drm_device
*dev
,
1626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1627 struct drm_i915_gem_object
*obj
;
1630 ret
= i915_mutex_lock_interruptible(dev
);
1634 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1635 if (&obj
->base
== NULL
) {
1640 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1645 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1646 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1651 ret
= i915_gem_object_create_mmap_offset(obj
);
1655 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1658 drm_gem_object_unreference(&obj
->base
);
1660 mutex_unlock(&dev
->struct_mutex
);
1665 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1667 * @data: GTT mapping ioctl data
1668 * @file: GEM object info
1670 * Simply returns the fake offset to userspace so it can mmap it.
1671 * The mmap call will end up in drm_gem_mmap(), which will set things
1672 * up so we can get faults in the handler above.
1674 * The fault handler will take care of binding the object into the GTT
1675 * (since it may have been evicted to make room for something), allocating
1676 * a fence register, and mapping the appropriate aperture address into
1680 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1681 struct drm_file
*file
)
1683 struct drm_i915_gem_mmap_gtt
*args
= data
;
1685 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1688 /* Immediately discard the backing storage */
1690 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1692 struct inode
*inode
;
1694 i915_gem_object_free_mmap_offset(obj
);
1696 if (obj
->base
.filp
== NULL
)
1699 /* Our goal here is to return as much of the memory as
1700 * is possible back to the system as we are called from OOM.
1701 * To do this we must instruct the shmfs to drop all of its
1702 * backing pages, *now*.
1704 inode
= file_inode(obj
->base
.filp
);
1705 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1707 obj
->madv
= __I915_MADV_PURGED
;
1711 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1713 return obj
->madv
== I915_MADV_DONTNEED
;
1717 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1719 struct sg_page_iter sg_iter
;
1722 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1724 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1726 /* In the event of a disaster, abandon all caches and
1727 * hope for the best.
1729 WARN_ON(ret
!= -EIO
);
1730 i915_gem_clflush_object(obj
, true);
1731 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1734 if (i915_gem_object_needs_bit17_swizzle(obj
))
1735 i915_gem_object_save_bit_17_swizzle(obj
);
1737 if (obj
->madv
== I915_MADV_DONTNEED
)
1740 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1741 struct page
*page
= sg_page_iter_page(&sg_iter
);
1744 set_page_dirty(page
);
1746 if (obj
->madv
== I915_MADV_WILLNEED
)
1747 mark_page_accessed(page
);
1749 page_cache_release(page
);
1753 sg_free_table(obj
->pages
);
1758 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1760 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1762 if (obj
->pages
== NULL
)
1765 if (obj
->pages_pin_count
)
1768 BUG_ON(i915_gem_obj_bound_any(obj
));
1770 /* ->put_pages might need to allocate memory for the bit17 swizzle
1771 * array, hence protect them from being reaped by removing them from gtt
1773 list_del(&obj
->global_list
);
1775 ops
->put_pages(obj
);
1778 if (i915_gem_object_is_purgeable(obj
))
1779 i915_gem_object_truncate(obj
);
1784 static unsigned long
1785 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1786 bool purgeable_only
)
1788 struct list_head still_bound_list
;
1789 struct drm_i915_gem_object
*obj
, *next
;
1790 unsigned long count
= 0;
1792 list_for_each_entry_safe(obj
, next
,
1793 &dev_priv
->mm
.unbound_list
,
1795 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1796 i915_gem_object_put_pages(obj
) == 0) {
1797 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1798 if (count
>= target
)
1804 * As we may completely rewrite the bound list whilst unbinding
1805 * (due to retiring requests) we have to strictly process only
1806 * one element of the list at the time, and recheck the list
1807 * on every iteration.
1809 INIT_LIST_HEAD(&still_bound_list
);
1810 while (count
< target
&& !list_empty(&dev_priv
->mm
.bound_list
)) {
1811 struct i915_vma
*vma
, *v
;
1813 obj
= list_first_entry(&dev_priv
->mm
.bound_list
,
1814 typeof(*obj
), global_list
);
1815 list_move_tail(&obj
->global_list
, &still_bound_list
);
1817 if (!i915_gem_object_is_purgeable(obj
) && purgeable_only
)
1821 * Hold a reference whilst we unbind this object, as we may
1822 * end up waiting for and retiring requests. This might
1823 * release the final reference (held by the active list)
1824 * and result in the object being freed from under us.
1825 * in this object being freed.
1827 * Note 1: Shrinking the bound list is special since only active
1828 * (and hence bound objects) can contain such limbo objects, so
1829 * we don't need special tricks for shrinking the unbound list.
1830 * The only other place where we have to be careful with active
1831 * objects suddenly disappearing due to retiring requests is the
1834 * Note 2: Even though the bound list doesn't hold a reference
1835 * to the object we can safely grab one here: The final object
1836 * unreferencing and the bound_list are both protected by the
1837 * dev->struct_mutex and so we won't ever be able to observe an
1838 * object on the bound_list with a reference count equals 0.
1840 drm_gem_object_reference(&obj
->base
);
1842 list_for_each_entry_safe(vma
, v
, &obj
->vma_list
, vma_link
)
1843 if (i915_vma_unbind(vma
))
1846 if (i915_gem_object_put_pages(obj
) == 0)
1847 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1849 drm_gem_object_unreference(&obj
->base
);
1851 list_splice(&still_bound_list
, &dev_priv
->mm
.bound_list
);
1856 static unsigned long
1857 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1859 return __i915_gem_shrink(dev_priv
, target
, true);
1862 static unsigned long
1863 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1865 struct drm_i915_gem_object
*obj
, *next
;
1868 i915_gem_evict_everything(dev_priv
->dev
);
1870 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
1872 if (i915_gem_object_put_pages(obj
) == 0)
1873 freed
+= obj
->base
.size
>> PAGE_SHIFT
;
1879 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1881 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1883 struct address_space
*mapping
;
1884 struct sg_table
*st
;
1885 struct scatterlist
*sg
;
1886 struct sg_page_iter sg_iter
;
1888 unsigned long last_pfn
= 0; /* suppress gcc warning */
1891 /* Assert that the object is not currently in any GPU domain. As it
1892 * wasn't in the GTT, there shouldn't be any way it could have been in
1895 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1896 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1898 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1902 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1903 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1908 /* Get the list of pages out of our struct file. They'll be pinned
1909 * at this point until we release them.
1911 * Fail silently without starting the shrinker
1913 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
1914 gfp
= mapping_gfp_mask(mapping
);
1915 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1916 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1919 for (i
= 0; i
< page_count
; i
++) {
1920 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1922 i915_gem_purge(dev_priv
, page_count
);
1923 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1926 /* We've tried hard to allocate the memory by reaping
1927 * our own buffer, now let the real VM do its job and
1928 * go down in flames if truly OOM.
1930 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1931 gfp
|= __GFP_IO
| __GFP_WAIT
;
1933 i915_gem_shrink_all(dev_priv
);
1934 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1938 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1939 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1941 #ifdef CONFIG_SWIOTLB
1942 if (swiotlb_nr_tbl()) {
1944 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1949 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
1953 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1955 sg
->length
+= PAGE_SIZE
;
1957 last_pfn
= page_to_pfn(page
);
1959 /* Check that the i965g/gm workaround works. */
1960 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
1962 #ifdef CONFIG_SWIOTLB
1963 if (!swiotlb_nr_tbl())
1968 if (i915_gem_object_needs_bit17_swizzle(obj
))
1969 i915_gem_object_do_bit_17_swizzle(obj
);
1975 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
1976 page_cache_release(sg_page_iter_page(&sg_iter
));
1979 return PTR_ERR(page
);
1982 /* Ensure that the associated pages are gathered from the backing storage
1983 * and pinned into our object. i915_gem_object_get_pages() may be called
1984 * multiple times before they are released by a single call to
1985 * i915_gem_object_put_pages() - once the pages are no longer referenced
1986 * either as a result of memory pressure (reaping pages under the shrinker)
1987 * or as the object is itself released.
1990 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1992 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1993 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1999 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2000 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2004 BUG_ON(obj
->pages_pin_count
);
2006 ret
= ops
->get_pages(obj
);
2010 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2015 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2016 struct intel_ring_buffer
*ring
)
2018 struct drm_device
*dev
= obj
->base
.dev
;
2019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2020 u32 seqno
= intel_ring_get_seqno(ring
);
2022 BUG_ON(ring
== NULL
);
2023 if (obj
->ring
!= ring
&& obj
->last_write_seqno
) {
2024 /* Keep the seqno relative to the current ring */
2025 obj
->last_write_seqno
= seqno
;
2029 /* Add a reference if we're newly entering the active list. */
2031 drm_gem_object_reference(&obj
->base
);
2035 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2037 obj
->last_read_seqno
= seqno
;
2039 if (obj
->fenced_gpu_access
) {
2040 obj
->last_fenced_seqno
= seqno
;
2042 /* Bump MRU to take account of the delayed flush */
2043 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2044 struct drm_i915_fence_reg
*reg
;
2046 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2047 list_move_tail(®
->lru_list
,
2048 &dev_priv
->mm
.fence_list
);
2053 void i915_vma_move_to_active(struct i915_vma
*vma
,
2054 struct intel_ring_buffer
*ring
)
2056 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2057 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2061 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2063 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2064 struct i915_address_space
*vm
;
2065 struct i915_vma
*vma
;
2067 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2068 BUG_ON(!obj
->active
);
2070 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2071 vma
= i915_gem_obj_to_vma(obj
, vm
);
2072 if (vma
&& !list_empty(&vma
->mm_list
))
2073 list_move_tail(&vma
->mm_list
, &vm
->inactive_list
);
2076 list_del_init(&obj
->ring_list
);
2079 obj
->last_read_seqno
= 0;
2080 obj
->last_write_seqno
= 0;
2081 obj
->base
.write_domain
= 0;
2083 obj
->last_fenced_seqno
= 0;
2084 obj
->fenced_gpu_access
= false;
2087 drm_gem_object_unreference(&obj
->base
);
2089 WARN_ON(i915_verify_lists(dev
));
2093 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2096 struct intel_ring_buffer
*ring
;
2099 /* Carefully retire all requests without writing to the rings */
2100 for_each_ring(ring
, dev_priv
, i
) {
2101 ret
= intel_ring_idle(ring
);
2105 i915_gem_retire_requests(dev
);
2107 /* Finally reset hw state */
2108 for_each_ring(ring
, dev_priv
, i
) {
2109 intel_ring_init_seqno(ring
, seqno
);
2111 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
2112 ring
->sync_seqno
[j
] = 0;
2118 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2126 /* HWS page needs to be set less than what we
2127 * will inject to ring
2129 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2133 /* Carefully set the last_seqno value so that wrap
2134 * detection still works
2136 dev_priv
->next_seqno
= seqno
;
2137 dev_priv
->last_seqno
= seqno
- 1;
2138 if (dev_priv
->last_seqno
== 0)
2139 dev_priv
->last_seqno
--;
2145 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2149 /* reserve 0 for non-seqno */
2150 if (dev_priv
->next_seqno
== 0) {
2151 int ret
= i915_gem_init_seqno(dev
, 0);
2155 dev_priv
->next_seqno
= 1;
2158 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2162 int __i915_add_request(struct intel_ring_buffer
*ring
,
2163 struct drm_file
*file
,
2164 struct drm_i915_gem_object
*obj
,
2167 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2168 struct drm_i915_gem_request
*request
;
2169 u32 request_ring_position
, request_start
;
2172 request_start
= intel_ring_get_tail(ring
);
2174 * Emit any outstanding flushes - execbuf can fail to emit the flush
2175 * after having emitted the batchbuffer command. Hence we need to fix
2176 * things up similar to emitting the lazy request. The difference here
2177 * is that the flush _must_ happen before the next request, no matter
2180 ret
= intel_ring_flush_all_caches(ring
);
2184 request
= ring
->preallocated_lazy_request
;
2185 if (WARN_ON(request
== NULL
))
2188 /* Record the position of the start of the request so that
2189 * should we detect the updated seqno part-way through the
2190 * GPU processing the request, we never over-estimate the
2191 * position of the head.
2193 request_ring_position
= intel_ring_get_tail(ring
);
2195 ret
= ring
->add_request(ring
);
2199 request
->seqno
= intel_ring_get_seqno(ring
);
2200 request
->ring
= ring
;
2201 request
->head
= request_start
;
2202 request
->tail
= request_ring_position
;
2204 /* Whilst this request exists, batch_obj will be on the
2205 * active_list, and so will hold the active reference. Only when this
2206 * request is retired will the the batch_obj be moved onto the
2207 * inactive_list and lose its active reference. Hence we do not need
2208 * to explicitly hold another reference here.
2210 request
->batch_obj
= obj
;
2212 /* Hold a reference to the current context so that we can inspect
2213 * it later in case a hangcheck error event fires.
2215 request
->ctx
= ring
->last_context
;
2217 i915_gem_context_reference(request
->ctx
);
2219 request
->emitted_jiffies
= jiffies
;
2220 list_add_tail(&request
->list
, &ring
->request_list
);
2221 request
->file_priv
= NULL
;
2224 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2226 spin_lock(&file_priv
->mm
.lock
);
2227 request
->file_priv
= file_priv
;
2228 list_add_tail(&request
->client_list
,
2229 &file_priv
->mm
.request_list
);
2230 spin_unlock(&file_priv
->mm
.lock
);
2233 trace_i915_gem_request_add(ring
, request
->seqno
);
2234 ring
->outstanding_lazy_seqno
= 0;
2235 ring
->preallocated_lazy_request
= NULL
;
2237 if (!dev_priv
->ums
.mm_suspended
) {
2238 i915_queue_hangcheck(ring
->dev
);
2240 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
2241 queue_delayed_work(dev_priv
->wq
,
2242 &dev_priv
->mm
.retire_work
,
2243 round_jiffies_up_relative(HZ
));
2244 intel_mark_busy(dev_priv
->dev
);
2248 *out_seqno
= request
->seqno
;
2253 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2255 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2260 spin_lock(&file_priv
->mm
.lock
);
2261 list_del(&request
->client_list
);
2262 request
->file_priv
= NULL
;
2263 spin_unlock(&file_priv
->mm
.lock
);
2266 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2267 const struct i915_hw_context
*ctx
)
2269 unsigned long elapsed
;
2271 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2273 if (ctx
->hang_stats
.banned
)
2276 if (elapsed
<= DRM_I915_CTX_BAN_PERIOD
) {
2277 if (!i915_gem_context_is_default(ctx
)) {
2278 DRM_DEBUG("context hanging too fast, banning!\n");
2280 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2281 if (i915_stop_ring_allow_warn(dev_priv
))
2282 DRM_ERROR("gpu hanging too fast, banning!\n");
2290 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2291 struct i915_hw_context
*ctx
,
2294 struct i915_ctx_hang_stats
*hs
;
2299 hs
= &ctx
->hang_stats
;
2302 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2304 hs
->guilty_ts
= get_seconds();
2306 hs
->batch_pending
++;
2310 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2312 list_del(&request
->list
);
2313 i915_gem_request_remove_from_client(request
);
2316 i915_gem_context_unreference(request
->ctx
);
2321 struct drm_i915_gem_request
*
2322 i915_gem_find_active_request(struct intel_ring_buffer
*ring
)
2324 struct drm_i915_gem_request
*request
;
2325 u32 completed_seqno
;
2327 completed_seqno
= ring
->get_seqno(ring
, false);
2329 list_for_each_entry(request
, &ring
->request_list
, list
) {
2330 if (i915_seqno_passed(completed_seqno
, request
->seqno
))
2339 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2340 struct intel_ring_buffer
*ring
)
2342 struct drm_i915_gem_request
*request
;
2345 request
= i915_gem_find_active_request(ring
);
2347 if (request
== NULL
)
2350 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2352 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2354 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2355 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2358 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2359 struct intel_ring_buffer
*ring
)
2361 while (!list_empty(&ring
->active_list
)) {
2362 struct drm_i915_gem_object
*obj
;
2364 obj
= list_first_entry(&ring
->active_list
,
2365 struct drm_i915_gem_object
,
2368 i915_gem_object_move_to_inactive(obj
);
2372 * We must free the requests after all the corresponding objects have
2373 * been moved off active lists. Which is the same order as the normal
2374 * retire_requests function does. This is important if object hold
2375 * implicit references on things like e.g. ppgtt address spaces through
2378 while (!list_empty(&ring
->request_list
)) {
2379 struct drm_i915_gem_request
*request
;
2381 request
= list_first_entry(&ring
->request_list
,
2382 struct drm_i915_gem_request
,
2385 i915_gem_free_request(request
);
2389 void i915_gem_restore_fences(struct drm_device
*dev
)
2391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2394 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2395 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2398 * Commit delayed tiling changes if we have an object still
2399 * attached to the fence, otherwise just clear the fence.
2402 i915_gem_object_update_fence(reg
->obj
, reg
,
2403 reg
->obj
->tiling_mode
);
2405 i915_gem_write_fence(dev
, i
, NULL
);
2410 void i915_gem_reset(struct drm_device
*dev
)
2412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2413 struct intel_ring_buffer
*ring
;
2417 * Before we free the objects from the requests, we need to inspect
2418 * them for finding the guilty party. As the requests only borrow
2419 * their reference to the objects, the inspection must be done first.
2421 for_each_ring(ring
, dev_priv
, i
)
2422 i915_gem_reset_ring_status(dev_priv
, ring
);
2424 for_each_ring(ring
, dev_priv
, i
)
2425 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2427 i915_gem_cleanup_ringbuffer(dev
);
2429 i915_gem_context_reset(dev
);
2431 i915_gem_restore_fences(dev
);
2435 * This function clears the request list as sequence numbers are passed.
2438 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2442 if (list_empty(&ring
->request_list
))
2445 WARN_ON(i915_verify_lists(ring
->dev
));
2447 seqno
= ring
->get_seqno(ring
, true);
2449 /* Move any buffers on the active list that are no longer referenced
2450 * by the ringbuffer to the flushing/inactive lists as appropriate,
2451 * before we free the context associated with the requests.
2453 while (!list_empty(&ring
->active_list
)) {
2454 struct drm_i915_gem_object
*obj
;
2456 obj
= list_first_entry(&ring
->active_list
,
2457 struct drm_i915_gem_object
,
2460 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2463 i915_gem_object_move_to_inactive(obj
);
2467 while (!list_empty(&ring
->request_list
)) {
2468 struct drm_i915_gem_request
*request
;
2470 request
= list_first_entry(&ring
->request_list
,
2471 struct drm_i915_gem_request
,
2474 if (!i915_seqno_passed(seqno
, request
->seqno
))
2477 trace_i915_gem_request_retire(ring
, request
->seqno
);
2478 /* We know the GPU must have read the request to have
2479 * sent us the seqno + interrupt, so use the position
2480 * of tail of the request to update the last known position
2483 ring
->last_retired_head
= request
->tail
;
2485 i915_gem_free_request(request
);
2488 if (unlikely(ring
->trace_irq_seqno
&&
2489 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2490 ring
->irq_put(ring
);
2491 ring
->trace_irq_seqno
= 0;
2494 WARN_ON(i915_verify_lists(ring
->dev
));
2498 i915_gem_retire_requests(struct drm_device
*dev
)
2500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2501 struct intel_ring_buffer
*ring
;
2505 for_each_ring(ring
, dev_priv
, i
) {
2506 i915_gem_retire_requests_ring(ring
);
2507 idle
&= list_empty(&ring
->request_list
);
2511 mod_delayed_work(dev_priv
->wq
,
2512 &dev_priv
->mm
.idle_work
,
2513 msecs_to_jiffies(100));
2519 i915_gem_retire_work_handler(struct work_struct
*work
)
2521 struct drm_i915_private
*dev_priv
=
2522 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2523 struct drm_device
*dev
= dev_priv
->dev
;
2526 /* Come back later if the device is busy... */
2528 if (mutex_trylock(&dev
->struct_mutex
)) {
2529 idle
= i915_gem_retire_requests(dev
);
2530 mutex_unlock(&dev
->struct_mutex
);
2533 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2534 round_jiffies_up_relative(HZ
));
2538 i915_gem_idle_work_handler(struct work_struct
*work
)
2540 struct drm_i915_private
*dev_priv
=
2541 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2543 intel_mark_idle(dev_priv
->dev
);
2547 * Ensures that an object will eventually get non-busy by flushing any required
2548 * write domains, emitting any outstanding lazy request and retiring and
2549 * completed requests.
2552 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2557 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2561 i915_gem_retire_requests_ring(obj
->ring
);
2568 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2569 * @DRM_IOCTL_ARGS: standard ioctl arguments
2571 * Returns 0 if successful, else an error is returned with the remaining time in
2572 * the timeout parameter.
2573 * -ETIME: object is still busy after timeout
2574 * -ERESTARTSYS: signal interrupted the wait
2575 * -ENONENT: object doesn't exist
2576 * Also possible, but rare:
2577 * -EAGAIN: GPU wedged
2579 * -ENODEV: Internal IRQ fail
2580 * -E?: The add request failed
2582 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2583 * non-zero timeout parameter the wait ioctl will wait for the given number of
2584 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2585 * without holding struct_mutex the object may become re-busied before this
2586 * function completes. A similar but shorter * race condition exists in the busy
2590 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2593 struct drm_i915_gem_wait
*args
= data
;
2594 struct drm_i915_gem_object
*obj
;
2595 struct intel_ring_buffer
*ring
= NULL
;
2596 struct timespec timeout_stack
, *timeout
= NULL
;
2597 unsigned reset_counter
;
2601 if (args
->timeout_ns
>= 0) {
2602 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2603 timeout
= &timeout_stack
;
2606 ret
= i915_mutex_lock_interruptible(dev
);
2610 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2611 if (&obj
->base
== NULL
) {
2612 mutex_unlock(&dev
->struct_mutex
);
2616 /* Need to make sure the object gets inactive eventually. */
2617 ret
= i915_gem_object_flush_active(obj
);
2622 seqno
= obj
->last_read_seqno
;
2629 /* Do this after OLR check to make sure we make forward progress polling
2630 * on this IOCTL with a 0 timeout (like busy ioctl)
2632 if (!args
->timeout_ns
) {
2637 drm_gem_object_unreference(&obj
->base
);
2638 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2639 mutex_unlock(&dev
->struct_mutex
);
2641 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
, file
->driver_priv
);
2643 args
->timeout_ns
= timespec_to_ns(timeout
);
2647 drm_gem_object_unreference(&obj
->base
);
2648 mutex_unlock(&dev
->struct_mutex
);
2653 * i915_gem_object_sync - sync an object to a ring.
2655 * @obj: object which may be in use on another ring.
2656 * @to: ring we wish to use the object on. May be NULL.
2658 * This code is meant to abstract object synchronization with the GPU.
2659 * Calling with NULL implies synchronizing the object with the CPU
2660 * rather than a particular GPU ring.
2662 * Returns 0 if successful, else propagates up the lower layer error.
2665 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2666 struct intel_ring_buffer
*to
)
2668 struct intel_ring_buffer
*from
= obj
->ring
;
2672 if (from
== NULL
|| to
== from
)
2675 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2676 return i915_gem_object_wait_rendering(obj
, false);
2678 idx
= intel_ring_sync_index(from
, to
);
2680 seqno
= obj
->last_read_seqno
;
2681 if (seqno
<= from
->sync_seqno
[idx
])
2684 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2688 trace_i915_gem_ring_sync_to(from
, to
, seqno
);
2689 ret
= to
->sync_to(to
, from
, seqno
);
2691 /* We use last_read_seqno because sync_to()
2692 * might have just caused seqno wrap under
2695 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2700 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2702 u32 old_write_domain
, old_read_domains
;
2704 /* Force a pagefault for domain tracking on next user access */
2705 i915_gem_release_mmap(obj
);
2707 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2710 /* Wait for any direct GTT access to complete */
2713 old_read_domains
= obj
->base
.read_domains
;
2714 old_write_domain
= obj
->base
.write_domain
;
2716 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2717 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2719 trace_i915_gem_object_change_domain(obj
,
2724 int i915_vma_unbind(struct i915_vma
*vma
)
2726 struct drm_i915_gem_object
*obj
= vma
->obj
;
2727 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2730 if (list_empty(&vma
->vma_link
))
2733 if (!drm_mm_node_allocated(&vma
->node
)) {
2734 i915_gem_vma_destroy(vma
);
2741 BUG_ON(obj
->pages
== NULL
);
2743 ret
= i915_gem_object_finish_gpu(obj
);
2746 /* Continue on if we fail due to EIO, the GPU is hung so we
2747 * should be safe and we need to cleanup or else we might
2748 * cause memory corruption through use-after-free.
2751 i915_gem_object_finish_gtt(obj
);
2753 /* release the fence reg _after_ flushing */
2754 ret
= i915_gem_object_put_fence(obj
);
2758 trace_i915_vma_unbind(vma
);
2760 vma
->unbind_vma(vma
);
2762 i915_gem_gtt_finish_object(obj
);
2764 list_del_init(&vma
->mm_list
);
2765 /* Avoid an unnecessary call to unbind on rebind. */
2766 if (i915_is_ggtt(vma
->vm
))
2767 obj
->map_and_fenceable
= true;
2769 drm_mm_remove_node(&vma
->node
);
2770 i915_gem_vma_destroy(vma
);
2772 /* Since the unbound list is global, only move to that list if
2773 * no more VMAs exist. */
2774 if (list_empty(&obj
->vma_list
))
2775 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2777 /* And finally now the object is completely decoupled from this vma,
2778 * we can drop its hold on the backing storage and allow it to be
2779 * reaped by the shrinker.
2781 i915_gem_object_unpin_pages(obj
);
2786 int i915_gpu_idle(struct drm_device
*dev
)
2788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2789 struct intel_ring_buffer
*ring
;
2792 /* Flush everything onto the inactive list. */
2793 for_each_ring(ring
, dev_priv
, i
) {
2794 ret
= i915_switch_context(ring
, ring
->default_context
);
2798 ret
= intel_ring_idle(ring
);
2806 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2807 struct drm_i915_gem_object
*obj
)
2809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2811 int fence_pitch_shift
;
2813 if (INTEL_INFO(dev
)->gen
>= 6) {
2814 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2815 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2817 fence_reg
= FENCE_REG_965_0
;
2818 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2821 fence_reg
+= reg
* 8;
2823 /* To w/a incoherency with non-atomic 64-bit register updates,
2824 * we split the 64-bit update into two 32-bit writes. In order
2825 * for a partial fence not to be evaluated between writes, we
2826 * precede the update with write to turn off the fence register,
2827 * and only enable the fence as the last step.
2829 * For extra levels of paranoia, we make sure each step lands
2830 * before applying the next step.
2832 I915_WRITE(fence_reg
, 0);
2833 POSTING_READ(fence_reg
);
2836 u32 size
= i915_gem_obj_ggtt_size(obj
);
2839 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
2841 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
2842 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2843 if (obj
->tiling_mode
== I915_TILING_Y
)
2844 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2845 val
|= I965_FENCE_REG_VALID
;
2847 I915_WRITE(fence_reg
+ 4, val
>> 32);
2848 POSTING_READ(fence_reg
+ 4);
2850 I915_WRITE(fence_reg
+ 0, val
);
2851 POSTING_READ(fence_reg
);
2853 I915_WRITE(fence_reg
+ 4, 0);
2854 POSTING_READ(fence_reg
+ 4);
2858 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2859 struct drm_i915_gem_object
*obj
)
2861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2865 u32 size
= i915_gem_obj_ggtt_size(obj
);
2869 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
2870 (size
& -size
) != size
||
2871 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2872 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2873 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
2875 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2880 /* Note: pitch better be a power of two tile widths */
2881 pitch_val
= obj
->stride
/ tile_width
;
2882 pitch_val
= ffs(pitch_val
) - 1;
2884 val
= i915_gem_obj_ggtt_offset(obj
);
2885 if (obj
->tiling_mode
== I915_TILING_Y
)
2886 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2887 val
|= I915_FENCE_SIZE_BITS(size
);
2888 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2889 val
|= I830_FENCE_REG_VALID
;
2894 reg
= FENCE_REG_830_0
+ reg
* 4;
2896 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2898 I915_WRITE(reg
, val
);
2902 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2903 struct drm_i915_gem_object
*obj
)
2905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2909 u32 size
= i915_gem_obj_ggtt_size(obj
);
2912 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
2913 (size
& -size
) != size
||
2914 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2915 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2916 i915_gem_obj_ggtt_offset(obj
), size
);
2918 pitch_val
= obj
->stride
/ 128;
2919 pitch_val
= ffs(pitch_val
) - 1;
2921 val
= i915_gem_obj_ggtt_offset(obj
);
2922 if (obj
->tiling_mode
== I915_TILING_Y
)
2923 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2924 val
|= I830_FENCE_SIZE_BITS(size
);
2925 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2926 val
|= I830_FENCE_REG_VALID
;
2930 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2931 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2934 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
2936 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
2939 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2940 struct drm_i915_gem_object
*obj
)
2942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2944 /* Ensure that all CPU reads are completed before installing a fence
2945 * and all writes before removing the fence.
2947 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
2950 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
2951 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2952 obj
->stride
, obj
->tiling_mode
);
2954 switch (INTEL_INFO(dev
)->gen
) {
2959 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2960 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2961 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2965 /* And similarly be paranoid that no direct access to this region
2966 * is reordered to before the fence is installed.
2968 if (i915_gem_object_needs_mb(obj
))
2972 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2973 struct drm_i915_fence_reg
*fence
)
2975 return fence
- dev_priv
->fence_regs
;
2978 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2979 struct drm_i915_fence_reg
*fence
,
2982 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2983 int reg
= fence_number(dev_priv
, fence
);
2985 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2988 obj
->fence_reg
= reg
;
2990 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2992 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2994 list_del_init(&fence
->lru_list
);
2996 obj
->fence_dirty
= false;
3000 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3002 if (obj
->last_fenced_seqno
) {
3003 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
3007 obj
->last_fenced_seqno
= 0;
3010 obj
->fenced_gpu_access
= false;
3015 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3017 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3018 struct drm_i915_fence_reg
*fence
;
3021 ret
= i915_gem_object_wait_fence(obj
);
3025 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3028 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3030 i915_gem_object_fence_lost(obj
);
3031 i915_gem_object_update_fence(obj
, fence
, false);
3036 static struct drm_i915_fence_reg
*
3037 i915_find_fence_reg(struct drm_device
*dev
)
3039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3040 struct drm_i915_fence_reg
*reg
, *avail
;
3043 /* First try to find a free reg */
3045 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3046 reg
= &dev_priv
->fence_regs
[i
];
3050 if (!reg
->pin_count
)
3057 /* None available, try to steal one or wait for a user to finish */
3058 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3066 /* Wait for completion of pending flips which consume fences */
3067 if (intel_has_pending_fb_unpin(dev
))
3068 return ERR_PTR(-EAGAIN
);
3070 return ERR_PTR(-EDEADLK
);
3074 * i915_gem_object_get_fence - set up fencing for an object
3075 * @obj: object to map through a fence reg
3077 * When mapping objects through the GTT, userspace wants to be able to write
3078 * to them without having to worry about swizzling if the object is tiled.
3079 * This function walks the fence regs looking for a free one for @obj,
3080 * stealing one if it can't find any.
3082 * It then sets up the reg based on the object's properties: address, pitch
3083 * and tiling format.
3085 * For an untiled surface, this removes any existing fence.
3088 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3090 struct drm_device
*dev
= obj
->base
.dev
;
3091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3092 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3093 struct drm_i915_fence_reg
*reg
;
3096 /* Have we updated the tiling parameters upon the object and so
3097 * will need to serialise the write to the associated fence register?
3099 if (obj
->fence_dirty
) {
3100 ret
= i915_gem_object_wait_fence(obj
);
3105 /* Just update our place in the LRU if our fence is getting reused. */
3106 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3107 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3108 if (!obj
->fence_dirty
) {
3109 list_move_tail(®
->lru_list
,
3110 &dev_priv
->mm
.fence_list
);
3113 } else if (enable
) {
3114 reg
= i915_find_fence_reg(dev
);
3116 return PTR_ERR(reg
);
3119 struct drm_i915_gem_object
*old
= reg
->obj
;
3121 ret
= i915_gem_object_wait_fence(old
);
3125 i915_gem_object_fence_lost(old
);
3130 i915_gem_object_update_fence(obj
, reg
, enable
);
3135 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
3136 struct drm_mm_node
*gtt_space
,
3137 unsigned long cache_level
)
3139 struct drm_mm_node
*other
;
3141 /* On non-LLC machines we have to be careful when putting differing
3142 * types of snoopable memory together to avoid the prefetcher
3143 * crossing memory domains and dying.
3148 if (!drm_mm_node_allocated(gtt_space
))
3151 if (list_empty(>t_space
->node_list
))
3154 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3155 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3158 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3159 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3165 static void i915_gem_verify_gtt(struct drm_device
*dev
)
3168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3169 struct drm_i915_gem_object
*obj
;
3172 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, global_list
) {
3173 if (obj
->gtt_space
== NULL
) {
3174 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
3179 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
3180 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3181 i915_gem_obj_ggtt_offset(obj
),
3182 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3184 obj
->gtt_space
->color
);
3189 if (!i915_gem_valid_gtt_space(dev
,
3191 obj
->cache_level
)) {
3192 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3193 i915_gem_obj_ggtt_offset(obj
),
3194 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3206 * Finds free space in the GTT aperture and binds the object there.
3208 static struct i915_vma
*
3209 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3210 struct i915_address_space
*vm
,
3214 struct drm_device
*dev
= obj
->base
.dev
;
3215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3216 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3218 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3219 struct i915_vma
*vma
;
3222 fence_size
= i915_gem_get_gtt_size(dev
,
3225 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3227 obj
->tiling_mode
, true);
3228 unfenced_alignment
=
3229 i915_gem_get_gtt_alignment(dev
,
3231 obj
->tiling_mode
, false);
3234 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3236 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3237 DRM_DEBUG("Invalid object alignment requested %u\n", alignment
);
3238 return ERR_PTR(-EINVAL
);
3241 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3243 /* If the object is bigger than the entire aperture, reject it early
3244 * before evicting everything in a vain attempt to find space.
3246 if (obj
->base
.size
> gtt_max
) {
3247 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3249 flags
& PIN_MAPPABLE
? "mappable" : "total",
3251 return ERR_PTR(-E2BIG
);
3254 ret
= i915_gem_object_get_pages(obj
);
3256 return ERR_PTR(ret
);
3258 i915_gem_object_pin_pages(obj
);
3260 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3265 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3267 obj
->cache_level
, 0, gtt_max
,
3268 DRM_MM_SEARCH_DEFAULT
,
3269 DRM_MM_CREATE_DEFAULT
);
3271 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3272 obj
->cache_level
, flags
);
3278 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, &vma
->node
,
3279 obj
->cache_level
))) {
3281 goto err_remove_node
;
3284 ret
= i915_gem_gtt_prepare_object(obj
);
3286 goto err_remove_node
;
3288 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3289 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3291 if (i915_is_ggtt(vm
)) {
3292 bool mappable
, fenceable
;
3294 fenceable
= (vma
->node
.size
== fence_size
&&
3295 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
3297 mappable
= (vma
->node
.start
+ obj
->base
.size
<=
3298 dev_priv
->gtt
.mappable_end
);
3300 obj
->map_and_fenceable
= mappable
&& fenceable
;
3303 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
3305 trace_i915_vma_bind(vma
, flags
);
3306 vma
->bind_vma(vma
, obj
->cache_level
,
3307 flags
& (PIN_MAPPABLE
| PIN_GLOBAL
) ? GLOBAL_BIND
: 0);
3309 i915_gem_verify_gtt(dev
);
3313 drm_mm_remove_node(&vma
->node
);
3315 i915_gem_vma_destroy(vma
);
3318 i915_gem_object_unpin_pages(obj
);
3323 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3326 /* If we don't have a page list set up, then we're not pinned
3327 * to GPU, and we can ignore the cache flush because it'll happen
3328 * again at bind time.
3330 if (obj
->pages
== NULL
)
3334 * Stolen memory is always coherent with the GPU as it is explicitly
3335 * marked as wc by the system, or the system is cache-coherent.
3340 /* If the GPU is snooping the contents of the CPU cache,
3341 * we do not need to manually clear the CPU cache lines. However,
3342 * the caches are only snooped when the render cache is
3343 * flushed/invalidated. As we always have to emit invalidations
3344 * and flushes when moving into and out of the RENDER domain, correct
3345 * snooping behaviour occurs naturally as the result of our domain
3348 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3351 trace_i915_gem_object_clflush(obj
);
3352 drm_clflush_sg(obj
->pages
);
3357 /** Flushes the GTT write domain for the object if it's dirty. */
3359 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3361 uint32_t old_write_domain
;
3363 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3366 /* No actual flushing is required for the GTT write domain. Writes
3367 * to it immediately go to main memory as far as we know, so there's
3368 * no chipset flush. It also doesn't land in render cache.
3370 * However, we do have to enforce the order so that all writes through
3371 * the GTT land before any writes to the device, such as updates to
3376 old_write_domain
= obj
->base
.write_domain
;
3377 obj
->base
.write_domain
= 0;
3379 trace_i915_gem_object_change_domain(obj
,
3380 obj
->base
.read_domains
,
3384 /** Flushes the CPU write domain for the object if it's dirty. */
3386 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
3389 uint32_t old_write_domain
;
3391 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3394 if (i915_gem_clflush_object(obj
, force
))
3395 i915_gem_chipset_flush(obj
->base
.dev
);
3397 old_write_domain
= obj
->base
.write_domain
;
3398 obj
->base
.write_domain
= 0;
3400 trace_i915_gem_object_change_domain(obj
,
3401 obj
->base
.read_domains
,
3406 * Moves a single object to the GTT read, and possibly write domain.
3408 * This function returns when the move is complete, including waiting on
3412 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3414 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3415 uint32_t old_write_domain
, old_read_domains
;
3418 /* Not valid to be called on unbound objects. */
3419 if (!i915_gem_obj_bound_any(obj
))
3422 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3425 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3429 i915_gem_object_flush_cpu_write_domain(obj
, false);
3431 /* Serialise direct access to this object with the barriers for
3432 * coherent writes from the GPU, by effectively invalidating the
3433 * GTT domain upon first access.
3435 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3438 old_write_domain
= obj
->base
.write_domain
;
3439 old_read_domains
= obj
->base
.read_domains
;
3441 /* It should now be out of any other write domains, and we can update
3442 * the domain values for our changes.
3444 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3445 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3447 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3448 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3452 trace_i915_gem_object_change_domain(obj
,
3456 /* And bump the LRU for this access */
3457 if (i915_gem_object_is_inactive(obj
)) {
3458 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
3460 list_move_tail(&vma
->mm_list
,
3461 &dev_priv
->gtt
.base
.inactive_list
);
3468 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3469 enum i915_cache_level cache_level
)
3471 struct drm_device
*dev
= obj
->base
.dev
;
3472 struct i915_vma
*vma
, *next
;
3475 if (obj
->cache_level
== cache_level
)
3478 if (i915_gem_obj_is_pinned(obj
)) {
3479 DRM_DEBUG("can not change the cache level of pinned objects\n");
3483 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3484 if (!i915_gem_valid_gtt_space(dev
, &vma
->node
, cache_level
)) {
3485 ret
= i915_vma_unbind(vma
);
3491 if (i915_gem_obj_bound_any(obj
)) {
3492 ret
= i915_gem_object_finish_gpu(obj
);
3496 i915_gem_object_finish_gtt(obj
);
3498 /* Before SandyBridge, you could not use tiling or fence
3499 * registers with snooped memory, so relinquish any fences
3500 * currently pointing to our region in the aperture.
3502 if (INTEL_INFO(dev
)->gen
< 6) {
3503 ret
= i915_gem_object_put_fence(obj
);
3508 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3509 if (drm_mm_node_allocated(&vma
->node
))
3510 vma
->bind_vma(vma
, cache_level
,
3511 obj
->has_global_gtt_mapping
? GLOBAL_BIND
: 0);
3514 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3515 vma
->node
.color
= cache_level
;
3516 obj
->cache_level
= cache_level
;
3518 if (cpu_write_needs_clflush(obj
)) {
3519 u32 old_read_domains
, old_write_domain
;
3521 /* If we're coming from LLC cached, then we haven't
3522 * actually been tracking whether the data is in the
3523 * CPU cache or not, since we only allow one bit set
3524 * in obj->write_domain and have been skipping the clflushes.
3525 * Just set it to the CPU cache for now.
3527 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3529 old_read_domains
= obj
->base
.read_domains
;
3530 old_write_domain
= obj
->base
.write_domain
;
3532 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3533 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3535 trace_i915_gem_object_change_domain(obj
,
3540 i915_gem_verify_gtt(dev
);
3544 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3545 struct drm_file
*file
)
3547 struct drm_i915_gem_caching
*args
= data
;
3548 struct drm_i915_gem_object
*obj
;
3551 ret
= i915_mutex_lock_interruptible(dev
);
3555 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3556 if (&obj
->base
== NULL
) {
3561 switch (obj
->cache_level
) {
3562 case I915_CACHE_LLC
:
3563 case I915_CACHE_L3_LLC
:
3564 args
->caching
= I915_CACHING_CACHED
;
3568 args
->caching
= I915_CACHING_DISPLAY
;
3572 args
->caching
= I915_CACHING_NONE
;
3576 drm_gem_object_unreference(&obj
->base
);
3578 mutex_unlock(&dev
->struct_mutex
);
3582 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3583 struct drm_file
*file
)
3585 struct drm_i915_gem_caching
*args
= data
;
3586 struct drm_i915_gem_object
*obj
;
3587 enum i915_cache_level level
;
3590 switch (args
->caching
) {
3591 case I915_CACHING_NONE
:
3592 level
= I915_CACHE_NONE
;
3594 case I915_CACHING_CACHED
:
3595 level
= I915_CACHE_LLC
;
3597 case I915_CACHING_DISPLAY
:
3598 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3604 ret
= i915_mutex_lock_interruptible(dev
);
3608 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3609 if (&obj
->base
== NULL
) {
3614 ret
= i915_gem_object_set_cache_level(obj
, level
);
3616 drm_gem_object_unreference(&obj
->base
);
3618 mutex_unlock(&dev
->struct_mutex
);
3622 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3624 /* There are 3 sources that pin objects:
3625 * 1. The display engine (scanouts, sprites, cursors);
3626 * 2. Reservations for execbuffer;
3629 * We can ignore reservations as we hold the struct_mutex and
3630 * are only called outside of the reservation path. The user
3631 * can only increment pin_count once, and so if after
3632 * subtracting the potential reference by the user, any pin_count
3633 * remains, it must be due to another use by the display engine.
3635 return i915_gem_obj_to_ggtt(obj
)->pin_count
- !!obj
->user_pin_count
;
3639 * Prepare buffer for display plane (scanout, cursors, etc).
3640 * Can be called from an uninterruptible phase (modesetting) and allows
3641 * any flushes to be pipelined (for pageflips).
3644 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3646 struct intel_ring_buffer
*pipelined
)
3648 u32 old_read_domains
, old_write_domain
;
3651 if (pipelined
!= obj
->ring
) {
3652 ret
= i915_gem_object_sync(obj
, pipelined
);
3657 /* Mark the pin_display early so that we account for the
3658 * display coherency whilst setting up the cache domains.
3660 obj
->pin_display
= true;
3662 /* The display engine is not coherent with the LLC cache on gen6. As
3663 * a result, we make sure that the pinning that is about to occur is
3664 * done with uncached PTEs. This is lowest common denominator for all
3667 * However for gen6+, we could do better by using the GFDT bit instead
3668 * of uncaching, which would allow us to flush all the LLC-cached data
3669 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3671 ret
= i915_gem_object_set_cache_level(obj
,
3672 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3674 goto err_unpin_display
;
3676 /* As the user may map the buffer once pinned in the display plane
3677 * (e.g. libkms for the bootup splash), we have to ensure that we
3678 * always use map_and_fenceable for all scanout buffers.
3680 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, PIN_MAPPABLE
);
3682 goto err_unpin_display
;
3684 i915_gem_object_flush_cpu_write_domain(obj
, true);
3686 old_write_domain
= obj
->base
.write_domain
;
3687 old_read_domains
= obj
->base
.read_domains
;
3689 /* It should now be out of any other write domains, and we can update
3690 * the domain values for our changes.
3692 obj
->base
.write_domain
= 0;
3693 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3695 trace_i915_gem_object_change_domain(obj
,
3702 obj
->pin_display
= is_pin_display(obj
);
3707 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
)
3709 i915_gem_object_ggtt_unpin(obj
);
3710 obj
->pin_display
= is_pin_display(obj
);
3714 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3718 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3721 ret
= i915_gem_object_wait_rendering(obj
, false);
3725 /* Ensure that we invalidate the GPU's caches and TLBs. */
3726 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3731 * Moves a single object to the CPU read, and possibly write domain.
3733 * This function returns when the move is complete, including waiting on
3737 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3739 uint32_t old_write_domain
, old_read_domains
;
3742 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3745 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3749 i915_gem_object_flush_gtt_write_domain(obj
);
3751 old_write_domain
= obj
->base
.write_domain
;
3752 old_read_domains
= obj
->base
.read_domains
;
3754 /* Flush the CPU cache if it's still invalid. */
3755 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3756 i915_gem_clflush_object(obj
, false);
3758 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3761 /* It should now be out of any other write domains, and we can update
3762 * the domain values for our changes.
3764 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3766 /* If we're writing through the CPU, then the GPU read domains will
3767 * need to be invalidated at next use.
3770 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3771 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3774 trace_i915_gem_object_change_domain(obj
,
3781 /* Throttle our rendering by waiting until the ring has completed our requests
3782 * emitted over 20 msec ago.
3784 * Note that if we were to use the current jiffies each time around the loop,
3785 * we wouldn't escape the function with any frames outstanding if the time to
3786 * render a frame was over 20ms.
3788 * This should get us reasonable parallelism between CPU and GPU but also
3789 * relatively low latency when blocking on a particular request to finish.
3792 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3795 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3796 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3797 struct drm_i915_gem_request
*request
;
3798 struct intel_ring_buffer
*ring
= NULL
;
3799 unsigned reset_counter
;
3803 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3807 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3811 spin_lock(&file_priv
->mm
.lock
);
3812 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3813 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3816 ring
= request
->ring
;
3817 seqno
= request
->seqno
;
3819 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3820 spin_unlock(&file_priv
->mm
.lock
);
3825 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
, NULL
);
3827 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3833 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3834 struct i915_address_space
*vm
,
3838 struct i915_vma
*vma
;
3841 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
3844 vma
= i915_gem_obj_to_vma(obj
, vm
);
3846 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3850 vma
->node
.start
& (alignment
- 1)) ||
3851 (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)) {
3852 WARN(vma
->pin_count
,
3853 "bo is already pinned with incorrect alignment:"
3854 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3855 " obj->map_and_fenceable=%d\n",
3856 i915_gem_obj_offset(obj
, vm
), alignment
,
3857 flags
& PIN_MAPPABLE
,
3858 obj
->map_and_fenceable
);
3859 ret
= i915_vma_unbind(vma
);
3867 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
3868 vma
= i915_gem_object_bind_to_vm(obj
, vm
, alignment
, flags
);
3870 return PTR_ERR(vma
);
3873 if (flags
& PIN_GLOBAL
&& !obj
->has_global_gtt_mapping
)
3874 vma
->bind_vma(vma
, obj
->cache_level
, GLOBAL_BIND
);
3877 if (flags
& PIN_MAPPABLE
)
3878 obj
->pin_mappable
|= true;
3884 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3886 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
3889 BUG_ON(vma
->pin_count
== 0);
3890 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
3892 if (--vma
->pin_count
== 0)
3893 obj
->pin_mappable
= false;
3897 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3898 struct drm_file
*file
)
3900 struct drm_i915_gem_pin
*args
= data
;
3901 struct drm_i915_gem_object
*obj
;
3904 if (INTEL_INFO(dev
)->gen
>= 6)
3907 ret
= i915_mutex_lock_interruptible(dev
);
3911 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3912 if (&obj
->base
== NULL
) {
3917 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3918 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
3923 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3924 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
3930 if (obj
->user_pin_count
== ULONG_MAX
) {
3935 if (obj
->user_pin_count
== 0) {
3936 ret
= i915_gem_obj_ggtt_pin(obj
, args
->alignment
, PIN_MAPPABLE
);
3941 obj
->user_pin_count
++;
3942 obj
->pin_filp
= file
;
3944 args
->offset
= i915_gem_obj_ggtt_offset(obj
);
3946 drm_gem_object_unreference(&obj
->base
);
3948 mutex_unlock(&dev
->struct_mutex
);
3953 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3954 struct drm_file
*file
)
3956 struct drm_i915_gem_pin
*args
= data
;
3957 struct drm_i915_gem_object
*obj
;
3960 ret
= i915_mutex_lock_interruptible(dev
);
3964 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3965 if (&obj
->base
== NULL
) {
3970 if (obj
->pin_filp
!= file
) {
3971 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3976 obj
->user_pin_count
--;
3977 if (obj
->user_pin_count
== 0) {
3978 obj
->pin_filp
= NULL
;
3979 i915_gem_object_ggtt_unpin(obj
);
3983 drm_gem_object_unreference(&obj
->base
);
3985 mutex_unlock(&dev
->struct_mutex
);
3990 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3991 struct drm_file
*file
)
3993 struct drm_i915_gem_busy
*args
= data
;
3994 struct drm_i915_gem_object
*obj
;
3997 ret
= i915_mutex_lock_interruptible(dev
);
4001 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4002 if (&obj
->base
== NULL
) {
4007 /* Count all active objects as busy, even if they are currently not used
4008 * by the gpu. Users of this interface expect objects to eventually
4009 * become non-busy without any further actions, therefore emit any
4010 * necessary flushes here.
4012 ret
= i915_gem_object_flush_active(obj
);
4014 args
->busy
= obj
->active
;
4016 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4017 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
4020 drm_gem_object_unreference(&obj
->base
);
4022 mutex_unlock(&dev
->struct_mutex
);
4027 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4028 struct drm_file
*file_priv
)
4030 return i915_gem_ring_throttle(dev
, file_priv
);
4034 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4035 struct drm_file
*file_priv
)
4037 struct drm_i915_gem_madvise
*args
= data
;
4038 struct drm_i915_gem_object
*obj
;
4041 switch (args
->madv
) {
4042 case I915_MADV_DONTNEED
:
4043 case I915_MADV_WILLNEED
:
4049 ret
= i915_mutex_lock_interruptible(dev
);
4053 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4054 if (&obj
->base
== NULL
) {
4059 if (i915_gem_obj_is_pinned(obj
)) {
4064 if (obj
->madv
!= __I915_MADV_PURGED
)
4065 obj
->madv
= args
->madv
;
4067 /* if the object is no longer attached, discard its backing storage */
4068 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
4069 i915_gem_object_truncate(obj
);
4071 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4074 drm_gem_object_unreference(&obj
->base
);
4076 mutex_unlock(&dev
->struct_mutex
);
4080 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4081 const struct drm_i915_gem_object_ops
*ops
)
4083 INIT_LIST_HEAD(&obj
->global_list
);
4084 INIT_LIST_HEAD(&obj
->ring_list
);
4085 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4086 INIT_LIST_HEAD(&obj
->vma_list
);
4090 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4091 obj
->madv
= I915_MADV_WILLNEED
;
4092 /* Avoid an unnecessary call to unbind on the first bind. */
4093 obj
->map_and_fenceable
= true;
4095 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4098 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4099 .get_pages
= i915_gem_object_get_pages_gtt
,
4100 .put_pages
= i915_gem_object_put_pages_gtt
,
4103 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4106 struct drm_i915_gem_object
*obj
;
4107 struct address_space
*mapping
;
4110 obj
= i915_gem_object_alloc(dev
);
4114 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4115 i915_gem_object_free(obj
);
4119 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4120 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4121 /* 965gm cannot relocate objects above 4GiB. */
4122 mask
&= ~__GFP_HIGHMEM
;
4123 mask
|= __GFP_DMA32
;
4126 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4127 mapping_set_gfp_mask(mapping
, mask
);
4129 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4131 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4132 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4135 /* On some devices, we can have the GPU use the LLC (the CPU
4136 * cache) for about a 10% performance improvement
4137 * compared to uncached. Graphics requests other than
4138 * display scanout are coherent with the CPU in
4139 * accessing this cache. This means in this mode we
4140 * don't need to clflush on the CPU side, and on the
4141 * GPU side we only need to flush internal caches to
4142 * get data visible to the CPU.
4144 * However, we maintain the display planes as UC, and so
4145 * need to rebind when first used as such.
4147 obj
->cache_level
= I915_CACHE_LLC
;
4149 obj
->cache_level
= I915_CACHE_NONE
;
4151 trace_i915_gem_object_create(obj
);
4156 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4158 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4159 struct drm_device
*dev
= obj
->base
.dev
;
4160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4161 struct i915_vma
*vma
, *next
;
4163 intel_runtime_pm_get(dev_priv
);
4165 trace_i915_gem_object_destroy(obj
);
4168 i915_gem_detach_phys_object(dev
, obj
);
4170 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4174 ret
= i915_vma_unbind(vma
);
4175 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4176 bool was_interruptible
;
4178 was_interruptible
= dev_priv
->mm
.interruptible
;
4179 dev_priv
->mm
.interruptible
= false;
4181 WARN_ON(i915_vma_unbind(vma
));
4183 dev_priv
->mm
.interruptible
= was_interruptible
;
4187 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4188 * before progressing. */
4190 i915_gem_object_unpin_pages(obj
);
4192 if (WARN_ON(obj
->pages_pin_count
))
4193 obj
->pages_pin_count
= 0;
4194 i915_gem_object_put_pages(obj
);
4195 i915_gem_object_free_mmap_offset(obj
);
4196 i915_gem_object_release_stolen(obj
);
4200 if (obj
->base
.import_attach
)
4201 drm_prime_gem_destroy(&obj
->base
, NULL
);
4203 drm_gem_object_release(&obj
->base
);
4204 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4207 i915_gem_object_free(obj
);
4209 intel_runtime_pm_put(dev_priv
);
4212 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4213 struct i915_address_space
*vm
)
4215 struct i915_vma
*vma
;
4216 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4223 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4225 WARN_ON(vma
->node
.allocated
);
4227 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4228 if (!list_empty(&vma
->exec_list
))
4231 list_del(&vma
->vma_link
);
4237 i915_gem_suspend(struct drm_device
*dev
)
4239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4242 mutex_lock(&dev
->struct_mutex
);
4243 if (dev_priv
->ums
.mm_suspended
)
4246 ret
= i915_gpu_idle(dev
);
4250 i915_gem_retire_requests(dev
);
4252 /* Under UMS, be paranoid and evict. */
4253 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4254 i915_gem_evict_everything(dev
);
4256 i915_kernel_lost_context(dev
);
4257 i915_gem_cleanup_ringbuffer(dev
);
4259 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4260 * We need to replace this with a semaphore, or something.
4261 * And not confound ums.mm_suspended!
4263 dev_priv
->ums
.mm_suspended
= !drm_core_check_feature(dev
,
4265 mutex_unlock(&dev
->struct_mutex
);
4267 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4268 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4269 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
4274 mutex_unlock(&dev
->struct_mutex
);
4278 int i915_gem_l3_remap(struct intel_ring_buffer
*ring
, int slice
)
4280 struct drm_device
*dev
= ring
->dev
;
4281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4282 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4283 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4286 if (!HAS_L3_DPF(dev
) || !remap_info
)
4289 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4294 * Note: We do not worry about the concurrent register cacheline hang
4295 * here because no other code should access these registers other than
4296 * at initialization time.
4298 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4299 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4300 intel_ring_emit(ring
, reg_base
+ i
);
4301 intel_ring_emit(ring
, remap_info
[i
/4]);
4304 intel_ring_advance(ring
);
4309 void i915_gem_init_swizzling(struct drm_device
*dev
)
4311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4313 if (INTEL_INFO(dev
)->gen
< 5 ||
4314 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4317 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4318 DISP_TILE_SURFACE_SWIZZLING
);
4323 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4325 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4326 else if (IS_GEN7(dev
))
4327 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4328 else if (IS_GEN8(dev
))
4329 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4335 intel_enable_blt(struct drm_device
*dev
)
4340 /* The blitter was dysfunctional on early prototypes */
4341 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4342 DRM_INFO("BLT not supported on this pre-production hardware;"
4343 " graphics performance will be degraded.\n");
4350 static int i915_gem_init_rings(struct drm_device
*dev
)
4352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4355 ret
= intel_init_render_ring_buffer(dev
);
4360 ret
= intel_init_bsd_ring_buffer(dev
);
4362 goto cleanup_render_ring
;
4365 if (intel_enable_blt(dev
)) {
4366 ret
= intel_init_blt_ring_buffer(dev
);
4368 goto cleanup_bsd_ring
;
4371 if (HAS_VEBOX(dev
)) {
4372 ret
= intel_init_vebox_ring_buffer(dev
);
4374 goto cleanup_blt_ring
;
4378 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4380 goto cleanup_vebox_ring
;
4385 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4387 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4389 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4390 cleanup_render_ring
:
4391 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4397 i915_gem_init_hw(struct drm_device
*dev
)
4399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4402 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4405 if (dev_priv
->ellc_size
)
4406 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4408 if (IS_HASWELL(dev
))
4409 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4410 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4412 if (HAS_PCH_NOP(dev
)) {
4413 if (IS_IVYBRIDGE(dev
)) {
4414 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4415 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4416 I915_WRITE(GEN7_MSG_CTL
, temp
);
4417 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4418 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4419 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4420 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4424 i915_gem_init_swizzling(dev
);
4426 ret
= i915_gem_init_rings(dev
);
4430 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4431 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4434 * XXX: Contexts should only be initialized once. Doing a switch to the
4435 * default context switch however is something we'd like to do after
4436 * reset or thaw (the latter may not actually be necessary for HW, but
4437 * goes with our code better). Context switching requires rings (for
4438 * the do_switch), but before enabling PPGTT. So don't move this.
4440 ret
= i915_gem_context_enable(dev_priv
);
4442 DRM_ERROR("Context enable failed %d\n", ret
);
4449 i915_gem_cleanup_ringbuffer(dev
);
4453 int i915_gem_init(struct drm_device
*dev
)
4455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4458 mutex_lock(&dev
->struct_mutex
);
4460 if (IS_VALLEYVIEW(dev
)) {
4461 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4462 I915_WRITE(VLV_GTLC_WAKE_CTRL
, 1);
4463 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) & 1) == 1, 10))
4464 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4467 i915_gem_init_global_gtt(dev
);
4469 ret
= i915_gem_context_init(dev
);
4471 mutex_unlock(&dev
->struct_mutex
);
4475 ret
= i915_gem_init_hw(dev
);
4476 mutex_unlock(&dev
->struct_mutex
);
4478 WARN_ON(dev_priv
->mm
.aliasing_ppgtt
);
4479 i915_gem_context_fini(dev
);
4480 drm_mm_takedown(&dev_priv
->gtt
.base
.mm
);
4484 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4485 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4486 dev_priv
->dri1
.allow_batchbuffer
= 1;
4491 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4494 struct intel_ring_buffer
*ring
;
4497 for_each_ring(ring
, dev_priv
, i
)
4498 intel_cleanup_ring_buffer(ring
);
4502 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4503 struct drm_file
*file_priv
)
4505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4508 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4511 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4512 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4513 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4516 mutex_lock(&dev
->struct_mutex
);
4517 dev_priv
->ums
.mm_suspended
= 0;
4519 ret
= i915_gem_init_hw(dev
);
4521 mutex_unlock(&dev
->struct_mutex
);
4525 BUG_ON(!list_empty(&dev_priv
->gtt
.base
.active_list
));
4526 mutex_unlock(&dev
->struct_mutex
);
4528 ret
= drm_irq_install(dev
);
4530 goto cleanup_ringbuffer
;
4535 mutex_lock(&dev
->struct_mutex
);
4536 i915_gem_cleanup_ringbuffer(dev
);
4537 dev_priv
->ums
.mm_suspended
= 1;
4538 mutex_unlock(&dev
->struct_mutex
);
4544 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4545 struct drm_file
*file_priv
)
4547 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4550 drm_irq_uninstall(dev
);
4552 return i915_gem_suspend(dev
);
4556 i915_gem_lastclose(struct drm_device
*dev
)
4560 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4563 ret
= i915_gem_suspend(dev
);
4565 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4569 init_ring_lists(struct intel_ring_buffer
*ring
)
4571 INIT_LIST_HEAD(&ring
->active_list
);
4572 INIT_LIST_HEAD(&ring
->request_list
);
4575 void i915_init_vm(struct drm_i915_private
*dev_priv
,
4576 struct i915_address_space
*vm
)
4578 if (!i915_is_ggtt(vm
))
4579 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
4580 vm
->dev
= dev_priv
->dev
;
4581 INIT_LIST_HEAD(&vm
->active_list
);
4582 INIT_LIST_HEAD(&vm
->inactive_list
);
4583 INIT_LIST_HEAD(&vm
->global_link
);
4584 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
4588 i915_gem_load(struct drm_device
*dev
)
4590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4594 kmem_cache_create("i915_gem_object",
4595 sizeof(struct drm_i915_gem_object
), 0,
4599 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4600 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
4602 INIT_LIST_HEAD(&dev_priv
->context_list
);
4603 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4604 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4605 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4606 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4607 init_ring_lists(&dev_priv
->ring
[i
]);
4608 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4609 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4610 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4611 i915_gem_retire_work_handler
);
4612 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
4613 i915_gem_idle_work_handler
);
4614 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4616 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4618 I915_WRITE(MI_ARB_STATE
,
4619 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4622 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4624 /* Old X drivers will take 0-2 for front, back, depth buffers */
4625 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4626 dev_priv
->fence_reg_start
= 3;
4628 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4629 dev_priv
->num_fence_regs
= 32;
4630 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4631 dev_priv
->num_fence_regs
= 16;
4633 dev_priv
->num_fence_regs
= 8;
4635 /* Initialize fence registers to zero */
4636 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4637 i915_gem_restore_fences(dev
);
4639 i915_gem_detect_bit_6_swizzle(dev
);
4640 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4642 dev_priv
->mm
.interruptible
= true;
4644 dev_priv
->mm
.inactive_shrinker
.scan_objects
= i915_gem_inactive_scan
;
4645 dev_priv
->mm
.inactive_shrinker
.count_objects
= i915_gem_inactive_count
;
4646 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4647 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4651 * Create a physically contiguous memory object for this object
4652 * e.g. for cursor + overlay regs
4654 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4655 int id
, int size
, int align
)
4657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4658 struct drm_i915_gem_phys_object
*phys_obj
;
4661 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4664 phys_obj
= kzalloc(sizeof(*phys_obj
), GFP_KERNEL
);
4670 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4671 if (!phys_obj
->handle
) {
4676 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4679 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4687 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4690 struct drm_i915_gem_phys_object
*phys_obj
;
4692 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4695 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4696 if (phys_obj
->cur_obj
) {
4697 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4701 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4703 drm_pci_free(dev
, phys_obj
->handle
);
4705 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4708 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4712 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4713 i915_gem_free_phys_object(dev
, i
);
4716 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4717 struct drm_i915_gem_object
*obj
)
4719 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4726 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4728 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4729 for (i
= 0; i
< page_count
; i
++) {
4730 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4731 if (!IS_ERR(page
)) {
4732 char *dst
= kmap_atomic(page
);
4733 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4736 drm_clflush_pages(&page
, 1);
4738 set_page_dirty(page
);
4739 mark_page_accessed(page
);
4740 page_cache_release(page
);
4743 i915_gem_chipset_flush(dev
);
4745 obj
->phys_obj
->cur_obj
= NULL
;
4746 obj
->phys_obj
= NULL
;
4750 i915_gem_attach_phys_object(struct drm_device
*dev
,
4751 struct drm_i915_gem_object
*obj
,
4755 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4761 if (id
> I915_MAX_PHYS_OBJECT
)
4764 if (obj
->phys_obj
) {
4765 if (obj
->phys_obj
->id
== id
)
4767 i915_gem_detach_phys_object(dev
, obj
);
4770 /* create a new object */
4771 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4772 ret
= i915_gem_init_phys_object(dev
, id
,
4773 obj
->base
.size
, align
);
4775 DRM_ERROR("failed to init phys object %d size: %zu\n",
4776 id
, obj
->base
.size
);
4781 /* bind to the object */
4782 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4783 obj
->phys_obj
->cur_obj
= obj
;
4785 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4787 for (i
= 0; i
< page_count
; i
++) {
4791 page
= shmem_read_mapping_page(mapping
, i
);
4793 return PTR_ERR(page
);
4795 src
= kmap_atomic(page
);
4796 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4797 memcpy(dst
, src
, PAGE_SIZE
);
4800 mark_page_accessed(page
);
4801 page_cache_release(page
);
4808 i915_gem_phys_pwrite(struct drm_device
*dev
,
4809 struct drm_i915_gem_object
*obj
,
4810 struct drm_i915_gem_pwrite
*args
,
4811 struct drm_file
*file_priv
)
4813 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4814 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
4816 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4817 unsigned long unwritten
;
4819 /* The physical object once assigned is fixed for the lifetime
4820 * of the obj, so we can safely drop the lock and continue
4823 mutex_unlock(&dev
->struct_mutex
);
4824 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4825 mutex_lock(&dev
->struct_mutex
);
4830 i915_gem_chipset_flush(dev
);
4834 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4836 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4838 cancel_delayed_work_sync(&file_priv
->mm
.idle_work
);
4840 /* Clean up our request list when the client is going away, so that
4841 * later retire_requests won't dereference our soon-to-be-gone
4844 spin_lock(&file_priv
->mm
.lock
);
4845 while (!list_empty(&file_priv
->mm
.request_list
)) {
4846 struct drm_i915_gem_request
*request
;
4848 request
= list_first_entry(&file_priv
->mm
.request_list
,
4849 struct drm_i915_gem_request
,
4851 list_del(&request
->client_list
);
4852 request
->file_priv
= NULL
;
4854 spin_unlock(&file_priv
->mm
.lock
);
4858 i915_gem_file_idle_work_handler(struct work_struct
*work
)
4860 struct drm_i915_file_private
*file_priv
=
4861 container_of(work
, typeof(*file_priv
), mm
.idle_work
.work
);
4863 atomic_set(&file_priv
->rps_wait_boost
, false);
4866 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
4868 struct drm_i915_file_private
*file_priv
;
4871 DRM_DEBUG_DRIVER("\n");
4873 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
4877 file
->driver_priv
= file_priv
;
4878 file_priv
->dev_priv
= dev
->dev_private
;
4879 file_priv
->file
= file
;
4881 spin_lock_init(&file_priv
->mm
.lock
);
4882 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
4883 INIT_DELAYED_WORK(&file_priv
->mm
.idle_work
,
4884 i915_gem_file_idle_work_handler
);
4886 ret
= i915_gem_context_open(dev
, file
);
4893 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4895 if (!mutex_is_locked(mutex
))
4898 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4899 return mutex
->owner
== task
;
4901 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4906 static unsigned long
4907 i915_gem_inactive_count(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4909 struct drm_i915_private
*dev_priv
=
4910 container_of(shrinker
,
4911 struct drm_i915_private
,
4912 mm
.inactive_shrinker
);
4913 struct drm_device
*dev
= dev_priv
->dev
;
4914 struct drm_i915_gem_object
*obj
;
4916 unsigned long count
;
4918 if (!mutex_trylock(&dev
->struct_mutex
)) {
4919 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4922 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4929 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
4930 if (obj
->pages_pin_count
== 0)
4931 count
+= obj
->base
.size
>> PAGE_SHIFT
;
4933 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
4937 if (!i915_gem_obj_is_pinned(obj
) && obj
->pages_pin_count
== 0)
4938 count
+= obj
->base
.size
>> PAGE_SHIFT
;
4942 mutex_unlock(&dev
->struct_mutex
);
4947 /* All the new VM stuff */
4948 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
4949 struct i915_address_space
*vm
)
4951 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4952 struct i915_vma
*vma
;
4954 if (!dev_priv
->mm
.aliasing_ppgtt
||
4955 vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
4956 vm
= &dev_priv
->gtt
.base
;
4958 BUG_ON(list_empty(&o
->vma_list
));
4959 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
4961 return vma
->node
.start
;
4967 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
4968 struct i915_address_space
*vm
)
4970 struct i915_vma
*vma
;
4972 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
4973 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
4979 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
4981 struct i915_vma
*vma
;
4983 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
4984 if (drm_mm_node_allocated(&vma
->node
))
4990 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
4991 struct i915_address_space
*vm
)
4993 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4994 struct i915_vma
*vma
;
4996 if (!dev_priv
->mm
.aliasing_ppgtt
||
4997 vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
4998 vm
= &dev_priv
->gtt
.base
;
5000 BUG_ON(list_empty(&o
->vma_list
));
5002 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5004 return vma
->node
.size
;
5009 static unsigned long
5010 i915_gem_inactive_scan(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5012 struct drm_i915_private
*dev_priv
=
5013 container_of(shrinker
,
5014 struct drm_i915_private
,
5015 mm
.inactive_shrinker
);
5016 struct drm_device
*dev
= dev_priv
->dev
;
5017 unsigned long freed
;
5020 if (!mutex_trylock(&dev
->struct_mutex
)) {
5021 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
5024 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
5030 freed
= i915_gem_purge(dev_priv
, sc
->nr_to_scan
);
5031 if (freed
< sc
->nr_to_scan
)
5032 freed
+= __i915_gem_shrink(dev_priv
,
5033 sc
->nr_to_scan
- freed
,
5035 if (freed
< sc
->nr_to_scan
)
5036 freed
+= i915_gem_shrink_all(dev_priv
);
5039 mutex_unlock(&dev
->struct_mutex
);
5044 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
5046 struct i915_vma
*vma
;
5048 if (WARN_ON(list_empty(&obj
->vma_list
)))
5051 vma
= list_first_entry(&obj
->vma_list
, typeof(*vma
), vma_link
);
5052 if (vma
->vm
!= obj_to_ggtt(obj
))