1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/drm_atomic_helper.h>
47 #include <drm/i915_drm.h>
50 #include "i915_trace.h"
51 #include "i915_vgpu.h"
52 #include "intel_drv.h"
55 static struct drm_driver driver
;
57 static unsigned int i915_load_fail_count
;
59 bool __i915_inject_load_failure(const char *func
, int line
)
61 if (i915_load_fail_count
>= i915
.inject_load_failure
)
64 if (++i915_load_fail_count
== i915
.inject_load_failure
) {
65 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
66 i915
.inject_load_failure
, func
, line
);
73 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
74 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
75 "providing the dmesg log by booting with drm.debug=0xf"
78 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
81 static bool shown_bug_once
;
82 struct device
*kdev
= dev_priv
->drm
.dev
;
83 bool is_error
= level
[1] <= KERN_ERR
[1];
84 bool is_debug
= level
[1] == KERN_DEBUG
[1];
88 if (is_debug
&& !(drm_debug
& DRM_UT_DRIVER
))
96 dev_printk(level
, kdev
, "[" DRM_NAME
":%ps] %pV",
97 __builtin_return_address(0), &vaf
);
99 if (is_error
&& !shown_bug_once
) {
100 dev_notice(kdev
, "%s", FDO_BUG_MSG
);
101 shown_bug_once
= true;
107 static bool i915_error_injected(struct drm_i915_private
*dev_priv
)
109 return i915
.inject_load_failure
&&
110 i915_load_fail_count
== i915
.inject_load_failure
;
113 #define i915_load_error(dev_priv, fmt, ...) \
114 __i915_printk(dev_priv, \
115 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
119 static enum intel_pch
intel_virt_detect_pch(struct drm_i915_private
*dev_priv
)
121 enum intel_pch ret
= PCH_NOP
;
124 * In a virtualized passthrough environment we can be in a
125 * setup where the ISA bridge is not able to be passed through.
126 * In this case, a south bridge can be emulated and we have to
127 * make an educated guess as to which PCH is really there.
130 if (IS_GEN5(dev_priv
)) {
132 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
133 } else if (IS_GEN6(dev_priv
) || IS_IVYBRIDGE(dev_priv
)) {
135 DRM_DEBUG_KMS("Assuming CougarPoint PCH\n");
136 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
138 if (IS_HSW_ULT(dev_priv
) || IS_BDW_ULT(dev_priv
))
139 dev_priv
->pch_id
= INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
;
141 dev_priv
->pch_id
= INTEL_PCH_LPT_DEVICE_ID_TYPE
;
142 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
143 } else if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
145 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
146 } else if (IS_COFFEELAKE(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
148 DRM_DEBUG_KMS("Assuming CannonPoint PCH\n");
154 static void intel_detect_pch(struct drm_i915_private
*dev_priv
)
156 struct pci_dev
*pch
= NULL
;
158 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
159 * (which really amounts to a PCH but no South Display).
161 if (INTEL_INFO(dev_priv
)->num_pipes
== 0) {
162 dev_priv
->pch_type
= PCH_NOP
;
167 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
168 * make graphics device passthrough work easy for VMM, that only
169 * need to expose ISA bridge to let driver know the real hardware
170 * underneath. This is a requirement from virtualization team.
172 * In some virtualized environments (e.g. XEN), there is irrelevant
173 * ISA bridge in the system. To work reliably, we should scan trhough
174 * all the ISA bridge devices and check for the first match, instead
175 * of only checking the first one.
177 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
178 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
179 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
181 dev_priv
->pch_id
= id
;
183 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
184 dev_priv
->pch_type
= PCH_IBX
;
185 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
186 WARN_ON(!IS_GEN5(dev_priv
));
187 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
188 dev_priv
->pch_type
= PCH_CPT
;
189 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
190 WARN_ON(!IS_GEN6(dev_priv
) &&
191 !IS_IVYBRIDGE(dev_priv
));
192 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
193 /* PantherPoint is CPT compatible */
194 dev_priv
->pch_type
= PCH_CPT
;
195 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
196 WARN_ON(!IS_GEN6(dev_priv
) &&
197 !IS_IVYBRIDGE(dev_priv
));
198 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
199 dev_priv
->pch_type
= PCH_LPT
;
200 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
201 WARN_ON(!IS_HASWELL(dev_priv
) &&
202 !IS_BROADWELL(dev_priv
));
203 WARN_ON(IS_HSW_ULT(dev_priv
) ||
204 IS_BDW_ULT(dev_priv
));
205 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
206 dev_priv
->pch_type
= PCH_LPT
;
207 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
208 WARN_ON(!IS_HASWELL(dev_priv
) &&
209 !IS_BROADWELL(dev_priv
));
210 WARN_ON(!IS_HSW_ULT(dev_priv
) &&
211 !IS_BDW_ULT(dev_priv
));
212 } else if (id
== INTEL_PCH_WPT_DEVICE_ID_TYPE
) {
213 /* WildcatPoint is LPT compatible */
214 dev_priv
->pch_type
= PCH_LPT
;
215 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
216 WARN_ON(!IS_HASWELL(dev_priv
) &&
217 !IS_BROADWELL(dev_priv
));
218 WARN_ON(IS_HSW_ULT(dev_priv
) ||
219 IS_BDW_ULT(dev_priv
));
220 } else if (id
== INTEL_PCH_WPT_LP_DEVICE_ID_TYPE
) {
221 /* WildcatPoint is LPT compatible */
222 dev_priv
->pch_type
= PCH_LPT
;
223 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
224 WARN_ON(!IS_HASWELL(dev_priv
) &&
225 !IS_BROADWELL(dev_priv
));
226 WARN_ON(!IS_HSW_ULT(dev_priv
) &&
227 !IS_BDW_ULT(dev_priv
));
228 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
229 dev_priv
->pch_type
= PCH_SPT
;
230 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
231 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
232 !IS_KABYLAKE(dev_priv
));
233 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
234 dev_priv
->pch_type
= PCH_SPT
;
235 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
236 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
237 !IS_KABYLAKE(dev_priv
));
238 } else if (id
== INTEL_PCH_KBP_DEVICE_ID_TYPE
) {
239 dev_priv
->pch_type
= PCH_KBP
;
240 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
241 WARN_ON(!IS_SKYLAKE(dev_priv
) &&
242 !IS_KABYLAKE(dev_priv
));
243 } else if (id
== INTEL_PCH_CNP_DEVICE_ID_TYPE
) {
244 dev_priv
->pch_type
= PCH_CNP
;
245 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
246 WARN_ON(!IS_CANNONLAKE(dev_priv
) &&
247 !IS_COFFEELAKE(dev_priv
));
248 } else if (id
== INTEL_PCH_CNP_LP_DEVICE_ID_TYPE
) {
249 dev_priv
->pch_type
= PCH_CNP
;
250 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
251 WARN_ON(!IS_CANNONLAKE(dev_priv
) &&
252 !IS_COFFEELAKE(dev_priv
));
253 } else if (id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
||
254 id
== INTEL_PCH_P3X_DEVICE_ID_TYPE
||
255 (id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
&&
256 pch
->subsystem_vendor
==
257 PCI_SUBVENDOR_ID_REDHAT_QUMRANET
&&
258 pch
->subsystem_device
==
259 PCI_SUBDEVICE_ID_QEMU
)) {
261 intel_virt_detect_pch(dev_priv
);
269 DRM_DEBUG_KMS("No PCH found.\n");
274 static int i915_getparam(struct drm_device
*dev
, void *data
,
275 struct drm_file
*file_priv
)
277 struct drm_i915_private
*dev_priv
= to_i915(dev
);
278 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
279 drm_i915_getparam_t
*param
= data
;
282 switch (param
->param
) {
283 case I915_PARAM_IRQ_ACTIVE
:
284 case I915_PARAM_ALLOW_BATCHBUFFER
:
285 case I915_PARAM_LAST_DISPATCH
:
286 case I915_PARAM_HAS_EXEC_CONSTANTS
:
287 /* Reject all old ums/dri params. */
289 case I915_PARAM_CHIPSET_ID
:
290 value
= pdev
->device
;
292 case I915_PARAM_REVISION
:
293 value
= pdev
->revision
;
295 case I915_PARAM_NUM_FENCES_AVAIL
:
296 value
= dev_priv
->num_fence_regs
;
298 case I915_PARAM_HAS_OVERLAY
:
299 value
= dev_priv
->overlay
? 1 : 0;
301 case I915_PARAM_HAS_BSD
:
302 value
= !!dev_priv
->engine
[VCS
];
304 case I915_PARAM_HAS_BLT
:
305 value
= !!dev_priv
->engine
[BCS
];
307 case I915_PARAM_HAS_VEBOX
:
308 value
= !!dev_priv
->engine
[VECS
];
310 case I915_PARAM_HAS_BSD2
:
311 value
= !!dev_priv
->engine
[VCS2
];
313 case I915_PARAM_HAS_LLC
:
314 value
= HAS_LLC(dev_priv
);
316 case I915_PARAM_HAS_WT
:
317 value
= HAS_WT(dev_priv
);
319 case I915_PARAM_HAS_ALIASING_PPGTT
:
320 value
= USES_PPGTT(dev_priv
);
322 case I915_PARAM_HAS_SEMAPHORES
:
323 value
= i915
.semaphores
;
325 case I915_PARAM_HAS_SECURE_BATCHES
:
326 value
= capable(CAP_SYS_ADMIN
);
328 case I915_PARAM_CMD_PARSER_VERSION
:
329 value
= i915_cmd_parser_get_version(dev_priv
);
331 case I915_PARAM_SUBSLICE_TOTAL
:
332 value
= sseu_subslice_total(&INTEL_INFO(dev_priv
)->sseu
);
336 case I915_PARAM_EU_TOTAL
:
337 value
= INTEL_INFO(dev_priv
)->sseu
.eu_total
;
341 case I915_PARAM_HAS_GPU_RESET
:
342 value
= i915
.enable_hangcheck
&& intel_has_gpu_reset(dev_priv
);
343 if (value
&& intel_has_reset_engine(dev_priv
))
346 case I915_PARAM_HAS_RESOURCE_STREAMER
:
347 value
= HAS_RESOURCE_STREAMER(dev_priv
);
349 case I915_PARAM_HAS_POOLED_EU
:
350 value
= HAS_POOLED_EU(dev_priv
);
352 case I915_PARAM_MIN_EU_IN_POOL
:
353 value
= INTEL_INFO(dev_priv
)->sseu
.min_eu_in_pool
;
355 case I915_PARAM_HUC_STATUS
:
356 intel_runtime_pm_get(dev_priv
);
357 value
= I915_READ(HUC_STATUS2
) & HUC_FW_VERIFIED
;
358 intel_runtime_pm_put(dev_priv
);
360 case I915_PARAM_MMAP_GTT_VERSION
:
361 /* Though we've started our numbering from 1, and so class all
362 * earlier versions as 0, in effect their value is undefined as
363 * the ioctl will report EINVAL for the unknown param!
365 value
= i915_gem_mmap_gtt_version();
367 case I915_PARAM_HAS_SCHEDULER
:
368 value
= dev_priv
->engine
[RCS
] &&
369 dev_priv
->engine
[RCS
]->schedule
;
371 case I915_PARAM_MMAP_VERSION
:
372 /* Remember to bump this if the version changes! */
373 case I915_PARAM_HAS_GEM
:
374 case I915_PARAM_HAS_PAGEFLIPPING
:
375 case I915_PARAM_HAS_EXECBUF2
: /* depends on GEM */
376 case I915_PARAM_HAS_RELAXED_FENCING
:
377 case I915_PARAM_HAS_COHERENT_RINGS
:
378 case I915_PARAM_HAS_RELAXED_DELTA
:
379 case I915_PARAM_HAS_GEN7_SOL_RESET
:
380 case I915_PARAM_HAS_WAIT_TIMEOUT
:
381 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
382 case I915_PARAM_HAS_PINNED_BATCHES
:
383 case I915_PARAM_HAS_EXEC_NO_RELOC
:
384 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
385 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
386 case I915_PARAM_HAS_EXEC_SOFTPIN
:
387 case I915_PARAM_HAS_EXEC_ASYNC
:
388 case I915_PARAM_HAS_EXEC_FENCE
:
389 case I915_PARAM_HAS_EXEC_CAPTURE
:
390 case I915_PARAM_HAS_EXEC_BATCH_FIRST
:
391 case I915_PARAM_HAS_EXEC_FENCE_ARRAY
:
392 /* For the time being all of these are always true;
393 * if some supported hardware does not have one of these
394 * features this value needs to be provided from
395 * INTEL_INFO(), a feature macro, or similar.
399 case I915_PARAM_SLICE_MASK
:
400 value
= INTEL_INFO(dev_priv
)->sseu
.slice_mask
;
404 case I915_PARAM_SUBSLICE_MASK
:
405 value
= INTEL_INFO(dev_priv
)->sseu
.subslice_mask
;
410 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
414 if (put_user(value
, param
->value
))
420 static int i915_get_bridge_dev(struct drm_i915_private
*dev_priv
)
422 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
423 if (!dev_priv
->bridge_dev
) {
424 DRM_ERROR("bridge device not found\n");
430 /* Allocate space for the MCH regs if needed, return nonzero on error */
432 intel_alloc_mchbar_resource(struct drm_i915_private
*dev_priv
)
434 int reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
435 u32 temp_lo
, temp_hi
= 0;
439 if (INTEL_GEN(dev_priv
) >= 4)
440 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
441 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
442 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
444 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
447 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
451 /* Get some space for it */
452 dev_priv
->mch_res
.name
= "i915 MCHBAR";
453 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
454 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
456 MCHBAR_SIZE
, MCHBAR_SIZE
,
458 0, pcibios_align_resource
,
459 dev_priv
->bridge_dev
);
461 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
462 dev_priv
->mch_res
.start
= 0;
466 if (INTEL_GEN(dev_priv
) >= 4)
467 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
468 upper_32_bits(dev_priv
->mch_res
.start
));
470 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
471 lower_32_bits(dev_priv
->mch_res
.start
));
475 /* Setup MCHBAR if possible, return true if we should disable it again */
477 intel_setup_mchbar(struct drm_i915_private
*dev_priv
)
479 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
483 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
486 dev_priv
->mchbar_need_disable
= false;
488 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
489 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
, &temp
);
490 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
492 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
496 /* If it's already enabled, don't have to do anything */
500 if (intel_alloc_mchbar_resource(dev_priv
))
503 dev_priv
->mchbar_need_disable
= true;
505 /* Space is allocated or reserved, so enable it. */
506 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
507 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
508 temp
| DEVEN_MCHBAR_EN
);
510 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
511 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
516 intel_teardown_mchbar(struct drm_i915_private
*dev_priv
)
518 int mchbar_reg
= INTEL_GEN(dev_priv
) >= 4 ? MCHBAR_I965
: MCHBAR_I915
;
520 if (dev_priv
->mchbar_need_disable
) {
521 if (IS_I915G(dev_priv
) || IS_I915GM(dev_priv
)) {
524 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
,
526 deven_val
&= ~DEVEN_MCHBAR_EN
;
527 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
532 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
535 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
540 if (dev_priv
->mch_res
.start
)
541 release_resource(&dev_priv
->mch_res
);
544 /* true = enable decode, false = disable decoder */
545 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
547 struct drm_i915_private
*dev_priv
= cookie
;
549 intel_modeset_vga_set_state(dev_priv
, state
);
551 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
552 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
554 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
557 static int i915_resume_switcheroo(struct drm_device
*dev
);
558 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
560 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
562 struct drm_device
*dev
= pci_get_drvdata(pdev
);
563 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
565 if (state
== VGA_SWITCHEROO_ON
) {
566 pr_info("switched on\n");
567 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
568 /* i915 resume handler doesn't set to D0 */
569 pci_set_power_state(pdev
, PCI_D0
);
570 i915_resume_switcheroo(dev
);
571 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
573 pr_info("switched off\n");
574 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
575 i915_suspend_switcheroo(dev
, pmm
);
576 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
580 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
582 struct drm_device
*dev
= pci_get_drvdata(pdev
);
585 * FIXME: open_count is protected by drm_global_mutex but that would lead to
586 * locking inversion with the driver load path. And the access here is
587 * completely racy anyway. So don't bother with locking for now.
589 return dev
->open_count
== 0;
592 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
593 .set_gpu_state
= i915_switcheroo_set_state
,
595 .can_switch
= i915_switcheroo_can_switch
,
598 static void i915_gem_fini(struct drm_i915_private
*dev_priv
)
600 /* Flush any outstanding unpin_work. */
601 i915_gem_drain_workqueue(dev_priv
);
603 mutex_lock(&dev_priv
->drm
.struct_mutex
);
604 intel_uc_fini_hw(dev_priv
);
605 i915_gem_cleanup_engines(dev_priv
);
606 i915_gem_contexts_fini(dev_priv
);
607 i915_gem_cleanup_userptr(dev_priv
);
608 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
610 i915_gem_drain_freed_objects(dev_priv
);
612 WARN_ON(!list_empty(&dev_priv
->contexts
.list
));
615 static int i915_load_modeset_init(struct drm_device
*dev
)
617 struct drm_i915_private
*dev_priv
= to_i915(dev
);
618 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
621 if (i915_inject_load_failure())
624 intel_bios_init(dev_priv
);
626 /* If we have > 1 VGA cards, then we need to arbitrate access
627 * to the common VGA resources.
629 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
630 * then we do not take part in VGA arbitration and the
631 * vga_client_register() fails with -ENODEV.
633 ret
= vga_client_register(pdev
, dev_priv
, NULL
, i915_vga_set_decode
);
634 if (ret
&& ret
!= -ENODEV
)
637 intel_register_dsm_handler();
639 ret
= vga_switcheroo_register_client(pdev
, &i915_switcheroo_ops
, false);
641 goto cleanup_vga_client
;
643 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
644 intel_update_rawclk(dev_priv
);
646 intel_power_domains_init_hw(dev_priv
, false);
648 intel_csr_ucode_init(dev_priv
);
650 ret
= intel_irq_install(dev_priv
);
654 intel_setup_gmbus(dev_priv
);
656 /* Important: The output setup functions called by modeset_init need
657 * working irqs for e.g. gmbus and dp aux transfers. */
658 ret
= intel_modeset_init(dev
);
662 intel_uc_init_fw(dev_priv
);
664 ret
= i915_gem_init(dev_priv
);
668 intel_modeset_gem_init(dev
);
670 if (INTEL_INFO(dev_priv
)->num_pipes
== 0)
673 ret
= intel_fbdev_init(dev
);
677 /* Only enable hotplug handling once the fbdev is fully set up. */
678 intel_hpd_init(dev_priv
);
680 drm_kms_helper_poll_init(dev
);
685 if (i915_gem_suspend(dev_priv
))
686 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
687 i915_gem_fini(dev_priv
);
689 intel_uc_fini_fw(dev_priv
);
691 drm_irq_uninstall(dev
);
692 intel_teardown_gmbus(dev_priv
);
694 intel_csr_ucode_fini(dev_priv
);
695 intel_power_domains_fini(dev_priv
);
696 vga_switcheroo_unregister_client(pdev
);
698 vga_client_register(pdev
, NULL
, NULL
, NULL
);
703 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
705 struct apertures_struct
*ap
;
706 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
707 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
711 ap
= alloc_apertures(1);
715 ap
->ranges
[0].base
= ggtt
->mappable_base
;
716 ap
->ranges
[0].size
= ggtt
->mappable_end
;
719 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
721 ret
= drm_fb_helper_remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
728 #if !defined(CONFIG_VGA_CONSOLE)
729 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
733 #elif !defined(CONFIG_DUMMY_CONSOLE)
734 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
739 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
743 DRM_INFO("Replacing VGA console driver\n");
746 if (con_is_bound(&vga_con
))
747 ret
= do_take_over_console(&dummy_con
, 0, MAX_NR_CONSOLES
- 1, 1);
749 ret
= do_unregister_con_driver(&vga_con
);
751 /* Ignore "already unregistered". */
761 static void intel_init_dpio(struct drm_i915_private
*dev_priv
)
764 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
765 * CHV x1 PHY (DP/HDMI D)
766 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
768 if (IS_CHERRYVIEW(dev_priv
)) {
769 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
770 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
771 } else if (IS_VALLEYVIEW(dev_priv
)) {
772 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
776 static int i915_workqueues_init(struct drm_i915_private
*dev_priv
)
779 * The i915 workqueue is primarily used for batched retirement of
780 * requests (and thus managing bo) once the task has been completed
781 * by the GPU. i915_gem_retire_requests() is called directly when we
782 * need high-priority retirement, such as waiting for an explicit
785 * It is also used for periodic low-priority events, such as
786 * idle-timers and recording error state.
788 * All tasks on the workqueue are expected to acquire the dev mutex
789 * so there is no point in running more than one instance of the
790 * workqueue at any time. Use an ordered one.
792 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
793 if (dev_priv
->wq
== NULL
)
796 dev_priv
->hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
797 if (dev_priv
->hotplug
.dp_wq
== NULL
)
803 destroy_workqueue(dev_priv
->wq
);
805 DRM_ERROR("Failed to allocate workqueues.\n");
810 static void i915_engines_cleanup(struct drm_i915_private
*i915
)
812 struct intel_engine_cs
*engine
;
813 enum intel_engine_id id
;
815 for_each_engine(engine
, i915
, id
)
819 static void i915_workqueues_cleanup(struct drm_i915_private
*dev_priv
)
821 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
822 destroy_workqueue(dev_priv
->wq
);
826 * We don't keep the workarounds for pre-production hardware, so we expect our
827 * driver to fail on these machines in one way or another. A little warning on
828 * dmesg may help both the user and the bug triagers.
830 static void intel_detect_preproduction_hw(struct drm_i915_private
*dev_priv
)
834 pre
|= IS_HSW_EARLY_SDV(dev_priv
);
835 pre
|= IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
);
836 pre
|= IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B_LAST
);
839 DRM_ERROR("This is a pre-production stepping. "
840 "It may not be fully functional.\n");
841 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_STILL_OK
);
846 * i915_driver_init_early - setup state not requiring device access
847 * @dev_priv: device private
849 * Initialize everything that is a "SW-only" state, that is state not
850 * requiring accessing the device or exposing the driver via kernel internal
851 * or userspace interfaces. Example steps belonging here: lock initialization,
852 * system memory allocation, setting up device specific attributes and
853 * function hooks not requiring accessing the device.
855 static int i915_driver_init_early(struct drm_i915_private
*dev_priv
,
856 const struct pci_device_id
*ent
)
858 const struct intel_device_info
*match_info
=
859 (struct intel_device_info
*)ent
->driver_data
;
860 struct intel_device_info
*device_info
;
863 if (i915_inject_load_failure())
866 /* Setup the write-once "constant" device info */
867 device_info
= mkwrite_device_info(dev_priv
);
868 memcpy(device_info
, match_info
, sizeof(*device_info
));
869 device_info
->device_id
= dev_priv
->drm
.pdev
->device
;
871 BUG_ON(device_info
->gen
> sizeof(device_info
->gen_mask
) * BITS_PER_BYTE
);
872 device_info
->gen_mask
= BIT(device_info
->gen
- 1);
874 spin_lock_init(&dev_priv
->irq_lock
);
875 spin_lock_init(&dev_priv
->gpu_error
.lock
);
876 mutex_init(&dev_priv
->backlight_lock
);
877 spin_lock_init(&dev_priv
->uncore
.lock
);
879 spin_lock_init(&dev_priv
->mm
.object_stat_lock
);
880 mutex_init(&dev_priv
->sb_lock
);
881 mutex_init(&dev_priv
->av_mutex
);
882 mutex_init(&dev_priv
->wm
.wm_mutex
);
883 mutex_init(&dev_priv
->pps_mutex
);
885 intel_uc_init_early(dev_priv
);
886 i915_memcpy_init_early(dev_priv
);
888 ret
= i915_workqueues_init(dev_priv
);
892 /* This must be called before any calls to HAS_PCH_* */
893 intel_detect_pch(dev_priv
);
895 intel_pm_setup(dev_priv
);
896 intel_init_dpio(dev_priv
);
897 intel_power_domains_init(dev_priv
);
898 intel_irq_init(dev_priv
);
899 intel_hangcheck_init(dev_priv
);
900 intel_init_display_hooks(dev_priv
);
901 intel_init_clock_gating_hooks(dev_priv
);
902 intel_init_audio_hooks(dev_priv
);
903 ret
= i915_gem_load_init(dev_priv
);
907 intel_display_crc_init(dev_priv
);
909 intel_device_info_dump(dev_priv
);
911 intel_detect_preproduction_hw(dev_priv
);
913 i915_perf_init(dev_priv
);
918 intel_irq_fini(dev_priv
);
919 i915_workqueues_cleanup(dev_priv
);
921 i915_engines_cleanup(dev_priv
);
926 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
927 * @dev_priv: device private
929 static void i915_driver_cleanup_early(struct drm_i915_private
*dev_priv
)
931 i915_perf_fini(dev_priv
);
932 i915_gem_load_cleanup(dev_priv
);
933 intel_irq_fini(dev_priv
);
934 i915_workqueues_cleanup(dev_priv
);
935 i915_engines_cleanup(dev_priv
);
938 static int i915_mmio_setup(struct drm_i915_private
*dev_priv
)
940 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
944 mmio_bar
= IS_GEN2(dev_priv
) ? 1 : 0;
946 * Before gen4, the registers and the GTT are behind different BARs.
947 * However, from gen4 onwards, the registers and the GTT are shared
948 * in the same BAR, so we want to restrict this ioremap from
949 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
950 * the register BAR remains the same size for all the earlier
951 * generations up to Ironlake.
953 if (INTEL_GEN(dev_priv
) < 5)
954 mmio_size
= 512 * 1024;
956 mmio_size
= 2 * 1024 * 1024;
957 dev_priv
->regs
= pci_iomap(pdev
, mmio_bar
, mmio_size
);
958 if (dev_priv
->regs
== NULL
) {
959 DRM_ERROR("failed to map registers\n");
964 /* Try to make sure MCHBAR is enabled before poking at it */
965 intel_setup_mchbar(dev_priv
);
970 static void i915_mmio_cleanup(struct drm_i915_private
*dev_priv
)
972 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
974 intel_teardown_mchbar(dev_priv
);
975 pci_iounmap(pdev
, dev_priv
->regs
);
979 * i915_driver_init_mmio - setup device MMIO
980 * @dev_priv: device private
982 * Setup minimal device state necessary for MMIO accesses later in the
983 * initialization sequence. The setup here should avoid any other device-wide
984 * side effects or exposing the driver via kernel internal or user space
987 static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv
)
991 if (i915_inject_load_failure())
994 if (i915_get_bridge_dev(dev_priv
))
997 ret
= i915_mmio_setup(dev_priv
);
1001 intel_uncore_init(dev_priv
);
1003 ret
= intel_engines_init_mmio(dev_priv
);
1007 i915_gem_init_mmio(dev_priv
);
1012 intel_uncore_fini(dev_priv
);
1014 pci_dev_put(dev_priv
->bridge_dev
);
1020 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1021 * @dev_priv: device private
1023 static void i915_driver_cleanup_mmio(struct drm_i915_private
*dev_priv
)
1025 intel_uncore_fini(dev_priv
);
1026 i915_mmio_cleanup(dev_priv
);
1027 pci_dev_put(dev_priv
->bridge_dev
);
1030 static void intel_sanitize_options(struct drm_i915_private
*dev_priv
)
1032 i915
.enable_execlists
=
1033 intel_sanitize_enable_execlists(dev_priv
,
1034 i915
.enable_execlists
);
1037 * i915.enable_ppgtt is read-only, so do an early pass to validate the
1038 * user's requested state against the hardware/driver capabilities. We
1039 * do this now so that we can print out any log messages once rather
1040 * than every time we check intel_enable_ppgtt().
1043 intel_sanitize_enable_ppgtt(dev_priv
, i915
.enable_ppgtt
);
1044 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
1046 i915
.semaphores
= intel_sanitize_semaphores(dev_priv
, i915
.semaphores
);
1047 DRM_DEBUG_DRIVER("use GPU semaphores? %s\n", yesno(i915
.semaphores
));
1049 intel_uc_sanitize_options(dev_priv
);
1051 intel_gvt_sanitize_options(dev_priv
);
1055 * i915_driver_init_hw - setup state requiring device access
1056 * @dev_priv: device private
1058 * Setup state that requires accessing the device, but doesn't require
1059 * exposing the driver via kernel internal or userspace interfaces.
1061 static int i915_driver_init_hw(struct drm_i915_private
*dev_priv
)
1063 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1066 if (i915_inject_load_failure())
1069 intel_device_info_runtime_init(dev_priv
);
1071 intel_sanitize_options(dev_priv
);
1073 ret
= i915_ggtt_probe_hw(dev_priv
);
1077 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1078 * otherwise the vga fbdev driver falls over. */
1079 ret
= i915_kick_out_firmware_fb(dev_priv
);
1081 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1085 ret
= i915_kick_out_vgacon(dev_priv
);
1087 DRM_ERROR("failed to remove conflicting VGA console\n");
1091 ret
= i915_ggtt_init_hw(dev_priv
);
1095 ret
= i915_ggtt_enable_hw(dev_priv
);
1097 DRM_ERROR("failed to enable GGTT\n");
1101 pci_set_master(pdev
);
1103 /* overlay on gen2 is broken and can't address above 1G */
1104 if (IS_GEN2(dev_priv
)) {
1105 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(30));
1107 DRM_ERROR("failed to set DMA mask\n");
1113 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1114 * using 32bit addressing, overwriting memory if HWS is located
1117 * The documentation also mentions an issue with undefined
1118 * behaviour if any general state is accessed within a page above 4GB,
1119 * which also needs to be handled carefully.
1121 if (IS_I965G(dev_priv
) || IS_I965GM(dev_priv
)) {
1122 ret
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(32));
1125 DRM_ERROR("failed to set DMA mask\n");
1131 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
,
1132 PM_QOS_DEFAULT_VALUE
);
1134 intel_uncore_sanitize(dev_priv
);
1136 intel_opregion_setup(dev_priv
);
1138 i915_gem_load_init_fences(dev_priv
);
1140 /* On the 945G/GM, the chipset reports the MSI capability on the
1141 * integrated graphics even though the support isn't actually there
1142 * according to the published specs. It doesn't appear to function
1143 * correctly in testing on 945G.
1144 * This may be a side effect of MSI having been made available for PEG
1145 * and the registers being closely associated.
1147 * According to chipset errata, on the 965GM, MSI interrupts may
1148 * be lost or delayed, and was defeatured. MSI interrupts seem to
1149 * get lost on g4x as well, and interrupt delivery seems to stay
1150 * properly dead afterwards. So we'll just disable them for all
1151 * pre-gen5 chipsets.
1153 if (INTEL_GEN(dev_priv
) >= 5) {
1154 if (pci_enable_msi(pdev
) < 0)
1155 DRM_DEBUG_DRIVER("can't enable MSI");
1158 ret
= intel_gvt_init(dev_priv
);
1165 i915_ggtt_cleanup_hw(dev_priv
);
1171 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1172 * @dev_priv: device private
1174 static void i915_driver_cleanup_hw(struct drm_i915_private
*dev_priv
)
1176 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1178 if (pdev
->msi_enabled
)
1179 pci_disable_msi(pdev
);
1181 pm_qos_remove_request(&dev_priv
->pm_qos
);
1182 i915_ggtt_cleanup_hw(dev_priv
);
1186 * i915_driver_register - register the driver with the rest of the system
1187 * @dev_priv: device private
1189 * Perform any steps necessary to make the driver available via kernel
1190 * internal or userspace interfaces.
1192 static void i915_driver_register(struct drm_i915_private
*dev_priv
)
1194 struct drm_device
*dev
= &dev_priv
->drm
;
1196 i915_gem_shrinker_init(dev_priv
);
1199 * Notify a valid surface after modesetting,
1200 * when running inside a VM.
1202 if (intel_vgpu_active(dev_priv
))
1203 I915_WRITE(vgtif_reg(display_ready
), VGT_DRV_DISPLAY_READY
);
1205 /* Reveal our presence to userspace */
1206 if (drm_dev_register(dev
, 0) == 0) {
1207 i915_debugfs_register(dev_priv
);
1208 i915_guc_log_register(dev_priv
);
1209 i915_setup_sysfs(dev_priv
);
1211 /* Depends on sysfs having been initialized */
1212 i915_perf_register(dev_priv
);
1214 DRM_ERROR("Failed to register driver for userspace access!\n");
1216 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1217 /* Must be done after probing outputs */
1218 intel_opregion_register(dev_priv
);
1219 acpi_video_register();
1222 if (IS_GEN5(dev_priv
))
1223 intel_gpu_ips_init(dev_priv
);
1225 intel_audio_init(dev_priv
);
1228 * Some ports require correctly set-up hpd registers for detection to
1229 * work properly (leading to ghost connected connector status), e.g. VGA
1230 * on gm45. Hence we can only set up the initial fbdev config after hpd
1231 * irqs are fully enabled. We do it last so that the async config
1232 * cannot run before the connectors are registered.
1234 intel_fbdev_initial_config_async(dev
);
1238 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1239 * @dev_priv: device private
1241 static void i915_driver_unregister(struct drm_i915_private
*dev_priv
)
1243 intel_fbdev_unregister(dev_priv
);
1244 intel_audio_deinit(dev_priv
);
1246 intel_gpu_ips_teardown();
1247 acpi_video_unregister();
1248 intel_opregion_unregister(dev_priv
);
1250 i915_perf_unregister(dev_priv
);
1252 i915_teardown_sysfs(dev_priv
);
1253 i915_guc_log_unregister(dev_priv
);
1254 drm_dev_unregister(&dev_priv
->drm
);
1256 i915_gem_shrinker_cleanup(dev_priv
);
1260 * i915_driver_load - setup chip and create an initial config
1262 * @ent: matching PCI ID entry
1264 * The driver load routine has to do several things:
1265 * - drive output discovery via intel_modeset_init()
1266 * - initialize the memory manager
1267 * - allocate initial config memory
1268 * - setup the DRM framebuffer with the allocated memory
1270 int i915_driver_load(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1272 const struct intel_device_info
*match_info
=
1273 (struct intel_device_info
*)ent
->driver_data
;
1274 struct drm_i915_private
*dev_priv
;
1277 /* Enable nuclear pageflip on ILK+ */
1278 if (!i915
.nuclear_pageflip
&& match_info
->gen
< 5)
1279 driver
.driver_features
&= ~DRIVER_ATOMIC
;
1282 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
1284 ret
= drm_dev_init(&dev_priv
->drm
, &driver
, &pdev
->dev
);
1286 DRM_DEV_ERROR(&pdev
->dev
, "allocation failed\n");
1290 dev_priv
->drm
.pdev
= pdev
;
1291 dev_priv
->drm
.dev_private
= dev_priv
;
1293 ret
= pci_enable_device(pdev
);
1297 pci_set_drvdata(pdev
, &dev_priv
->drm
);
1299 * Disable the system suspend direct complete optimization, which can
1300 * leave the device suspended skipping the driver's suspend handlers
1301 * if the device was already runtime suspended. This is needed due to
1302 * the difference in our runtime and system suspend sequence and
1303 * becaue the HDA driver may require us to enable the audio power
1304 * domain during system suspend.
1306 pdev
->dev_flags
|= PCI_DEV_FLAGS_NEEDS_RESUME
;
1308 ret
= i915_driver_init_early(dev_priv
, ent
);
1310 goto out_pci_disable
;
1312 intel_runtime_pm_get(dev_priv
);
1314 ret
= i915_driver_init_mmio(dev_priv
);
1316 goto out_runtime_pm_put
;
1318 ret
= i915_driver_init_hw(dev_priv
);
1320 goto out_cleanup_mmio
;
1323 * TODO: move the vblank init and parts of modeset init steps into one
1324 * of the i915_driver_init_/i915_driver_register functions according
1325 * to the role/effect of the given init step.
1327 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1328 ret
= drm_vblank_init(&dev_priv
->drm
,
1329 INTEL_INFO(dev_priv
)->num_pipes
);
1331 goto out_cleanup_hw
;
1334 ret
= i915_load_modeset_init(&dev_priv
->drm
);
1336 goto out_cleanup_hw
;
1338 i915_driver_register(dev_priv
);
1340 intel_runtime_pm_enable(dev_priv
);
1342 dev_priv
->ipc_enabled
= false;
1344 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG
))
1345 DRM_INFO("DRM_I915_DEBUG enabled\n");
1346 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM
))
1347 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1349 intel_runtime_pm_put(dev_priv
);
1354 i915_driver_cleanup_hw(dev_priv
);
1356 i915_driver_cleanup_mmio(dev_priv
);
1358 intel_runtime_pm_put(dev_priv
);
1359 i915_driver_cleanup_early(dev_priv
);
1361 pci_disable_device(pdev
);
1363 i915_load_error(dev_priv
, "Device initialization failed (%d)\n", ret
);
1364 drm_dev_fini(&dev_priv
->drm
);
1370 void i915_driver_unload(struct drm_device
*dev
)
1372 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1373 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1375 i915_driver_unregister(dev_priv
);
1377 if (i915_gem_suspend(dev_priv
))
1378 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1380 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
1382 drm_atomic_helper_shutdown(dev
);
1384 intel_gvt_cleanup(dev_priv
);
1386 intel_modeset_cleanup(dev
);
1389 * free the memory space allocated for the child device
1390 * config parsed from VBT
1392 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
1393 kfree(dev_priv
->vbt
.child_dev
);
1394 dev_priv
->vbt
.child_dev
= NULL
;
1395 dev_priv
->vbt
.child_dev_num
= 0;
1397 kfree(dev_priv
->vbt
.sdvo_lvds_vbt_mode
);
1398 dev_priv
->vbt
.sdvo_lvds_vbt_mode
= NULL
;
1399 kfree(dev_priv
->vbt
.lfp_lvds_vbt_mode
);
1400 dev_priv
->vbt
.lfp_lvds_vbt_mode
= NULL
;
1402 vga_switcheroo_unregister_client(pdev
);
1403 vga_client_register(pdev
, NULL
, NULL
, NULL
);
1405 intel_csr_ucode_fini(dev_priv
);
1407 /* Free error state after interrupts are fully disabled. */
1408 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1409 i915_reset_error_state(dev_priv
);
1411 i915_gem_fini(dev_priv
);
1412 intel_uc_fini_fw(dev_priv
);
1413 intel_fbc_cleanup_cfb(dev_priv
);
1415 intel_power_domains_fini(dev_priv
);
1417 i915_driver_cleanup_hw(dev_priv
);
1418 i915_driver_cleanup_mmio(dev_priv
);
1420 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
1423 static void i915_driver_release(struct drm_device
*dev
)
1425 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1427 i915_driver_cleanup_early(dev_priv
);
1428 drm_dev_fini(&dev_priv
->drm
);
1433 static int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1435 struct drm_i915_private
*i915
= to_i915(dev
);
1438 ret
= i915_gem_open(i915
, file
);
1446 * i915_driver_lastclose - clean up after all DRM clients have exited
1449 * Take care of cleaning up after all DRM clients have exited. In the
1450 * mode setting case, we want to restore the kernel's initial mode (just
1451 * in case the last client left us in a bad state).
1453 * Additionally, in the non-mode setting case, we'll tear down the GTT
1454 * and DMA structures, since the kernel won't be using them, and clea
1457 static void i915_driver_lastclose(struct drm_device
*dev
)
1459 intel_fbdev_restore_mode(dev
);
1460 vga_switcheroo_process_delayed_switch();
1463 static void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1465 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1467 mutex_lock(&dev
->struct_mutex
);
1468 i915_gem_context_close(file
);
1469 i915_gem_release(dev
, file
);
1470 mutex_unlock(&dev
->struct_mutex
);
1475 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
1477 struct drm_device
*dev
= &dev_priv
->drm
;
1478 struct intel_encoder
*encoder
;
1480 drm_modeset_lock_all(dev
);
1481 for_each_intel_encoder(dev
, encoder
)
1482 if (encoder
->suspend
)
1483 encoder
->suspend(encoder
);
1484 drm_modeset_unlock_all(dev
);
1487 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1489 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
);
1491 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
1493 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1494 if (acpi_target_system_state() < ACPI_STATE_S3
)
1500 static int i915_drm_suspend(struct drm_device
*dev
)
1502 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1503 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1504 pci_power_t opregion_target_state
;
1507 disable_rpm_wakeref_asserts(dev_priv
);
1509 /* We do a lot of poking in a lot of registers, make sure they work
1511 intel_display_set_init_power(dev_priv
, true);
1513 drm_kms_helper_poll_disable(dev
);
1515 pci_save_state(pdev
);
1517 error
= i915_gem_suspend(dev_priv
);
1520 "GEM idle failed, resume might fail\n");
1524 intel_display_suspend(dev
);
1526 intel_dp_mst_suspend(dev
);
1528 intel_runtime_pm_disable_interrupts(dev_priv
);
1529 intel_hpd_cancel_work(dev_priv
);
1531 intel_suspend_encoders(dev_priv
);
1533 intel_suspend_hw(dev_priv
);
1535 i915_gem_suspend_gtt_mappings(dev_priv
);
1537 i915_save_state(dev_priv
);
1539 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
1540 intel_opregion_notify_adapter(dev_priv
, opregion_target_state
);
1542 intel_uncore_suspend(dev_priv
);
1543 intel_opregion_unregister(dev_priv
);
1545 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
1547 dev_priv
->suspend_count
++;
1549 intel_csr_ucode_suspend(dev_priv
);
1552 enable_rpm_wakeref_asserts(dev_priv
);
1557 static int i915_drm_suspend_late(struct drm_device
*dev
, bool hibernation
)
1559 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1560 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1564 disable_rpm_wakeref_asserts(dev_priv
);
1566 intel_display_set_init_power(dev_priv
, false);
1568 fw_csr
= !IS_GEN9_LP(dev_priv
) &&
1569 suspend_to_idle(dev_priv
) && dev_priv
->csr
.dmc_payload
;
1571 * In case of firmware assisted context save/restore don't manually
1572 * deinit the power domains. This also means the CSR/DMC firmware will
1573 * stay active, it will power down any HW resources as required and
1574 * also enable deeper system power states that would be blocked if the
1575 * firmware was inactive.
1578 intel_power_domains_suspend(dev_priv
);
1581 if (IS_GEN9_LP(dev_priv
))
1582 bxt_enable_dc9(dev_priv
);
1583 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1584 hsw_enable_pc8(dev_priv
);
1585 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1586 ret
= vlv_suspend_complete(dev_priv
);
1589 DRM_ERROR("Suspend complete failed: %d\n", ret
);
1591 intel_power_domains_init_hw(dev_priv
, true);
1596 pci_disable_device(pdev
);
1598 * During hibernation on some platforms the BIOS may try to access
1599 * the device even though it's already in D3 and hang the machine. So
1600 * leave the device in D0 on those platforms and hope the BIOS will
1601 * power down the device properly. The issue was seen on multiple old
1602 * GENs with different BIOS vendors, so having an explicit blacklist
1603 * is inpractical; apply the workaround on everything pre GEN6. The
1604 * platforms where the issue was seen:
1605 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1609 if (!(hibernation
&& INTEL_GEN(dev_priv
) < 6))
1610 pci_set_power_state(pdev
, PCI_D3hot
);
1612 dev_priv
->suspended_to_idle
= suspend_to_idle(dev_priv
);
1615 enable_rpm_wakeref_asserts(dev_priv
);
1620 static int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
1625 DRM_ERROR("dev: %p\n", dev
);
1626 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1630 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
1631 state
.event
!= PM_EVENT_FREEZE
))
1634 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1637 error
= i915_drm_suspend(dev
);
1641 return i915_drm_suspend_late(dev
, false);
1644 static int i915_drm_resume(struct drm_device
*dev
)
1646 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1649 disable_rpm_wakeref_asserts(dev_priv
);
1650 intel_sanitize_gt_powersave(dev_priv
);
1652 ret
= i915_ggtt_enable_hw(dev_priv
);
1654 DRM_ERROR("failed to re-enable GGTT\n");
1656 intel_csr_ucode_resume(dev_priv
);
1658 i915_gem_resume(dev_priv
);
1660 i915_restore_state(dev_priv
);
1661 intel_pps_unlock_regs_wa(dev_priv
);
1662 intel_opregion_setup(dev_priv
);
1664 intel_init_pch_refclk(dev_priv
);
1667 * Interrupts have to be enabled before any batches are run. If not the
1668 * GPU will hang. i915_gem_init_hw() will initiate batches to
1669 * update/restore the context.
1671 * drm_mode_config_reset() needs AUX interrupts.
1673 * Modeset enabling in intel_modeset_init_hw() also needs working
1676 intel_runtime_pm_enable_interrupts(dev_priv
);
1678 drm_mode_config_reset(dev
);
1680 mutex_lock(&dev
->struct_mutex
);
1681 if (i915_gem_init_hw(dev_priv
)) {
1682 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1683 i915_gem_set_wedged(dev_priv
);
1685 mutex_unlock(&dev
->struct_mutex
);
1687 intel_guc_resume(dev_priv
);
1689 intel_modeset_init_hw(dev
);
1690 intel_init_clock_gating(dev_priv
);
1692 spin_lock_irq(&dev_priv
->irq_lock
);
1693 if (dev_priv
->display
.hpd_irq_setup
)
1694 dev_priv
->display
.hpd_irq_setup(dev_priv
);
1695 spin_unlock_irq(&dev_priv
->irq_lock
);
1697 intel_dp_mst_resume(dev
);
1699 intel_display_resume(dev
);
1701 drm_kms_helper_poll_enable(dev
);
1704 * ... but also need to make sure that hotplug processing
1705 * doesn't cause havoc. Like in the driver load code we don't
1706 * bother with the tiny race here where we might loose hotplug
1709 intel_hpd_init(dev_priv
);
1711 intel_opregion_register(dev_priv
);
1713 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
1715 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
1717 intel_autoenable_gt_powersave(dev_priv
);
1719 enable_rpm_wakeref_asserts(dev_priv
);
1724 static int i915_drm_resume_early(struct drm_device
*dev
)
1726 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1727 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1731 * We have a resume ordering issue with the snd-hda driver also
1732 * requiring our device to be power up. Due to the lack of a
1733 * parent/child relationship we currently solve this with an early
1736 * FIXME: This should be solved with a special hdmi sink device or
1737 * similar so that power domains can be employed.
1741 * Note that we need to set the power state explicitly, since we
1742 * powered off the device during freeze and the PCI core won't power
1743 * it back up for us during thaw. Powering off the device during
1744 * freeze is not a hard requirement though, and during the
1745 * suspend/resume phases the PCI core makes sure we get here with the
1746 * device powered on. So in case we change our freeze logic and keep
1747 * the device powered we can also remove the following set power state
1750 ret
= pci_set_power_state(pdev
, PCI_D0
);
1752 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
1757 * Note that pci_enable_device() first enables any parent bridge
1758 * device and only then sets the power state for this device. The
1759 * bridge enabling is a nop though, since bridge devices are resumed
1760 * first. The order of enabling power and enabling the device is
1761 * imposed by the PCI core as described above, so here we preserve the
1762 * same order for the freeze/thaw phases.
1764 * TODO: eventually we should remove pci_disable_device() /
1765 * pci_enable_enable_device() from suspend/resume. Due to how they
1766 * depend on the device enable refcount we can't anyway depend on them
1767 * disabling/enabling the device.
1769 if (pci_enable_device(pdev
)) {
1774 pci_set_master(pdev
);
1776 disable_rpm_wakeref_asserts(dev_priv
);
1778 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1779 ret
= vlv_resume_prepare(dev_priv
, false);
1781 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1784 intel_uncore_resume_early(dev_priv
);
1786 if (IS_GEN9_LP(dev_priv
)) {
1787 if (!dev_priv
->suspended_to_idle
)
1788 gen9_sanitize_dc_state(dev_priv
);
1789 bxt_disable_dc9(dev_priv
);
1790 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1791 hsw_disable_pc8(dev_priv
);
1794 intel_uncore_sanitize(dev_priv
);
1796 if (IS_GEN9_LP(dev_priv
) ||
1797 !(dev_priv
->suspended_to_idle
&& dev_priv
->csr
.dmc_payload
))
1798 intel_power_domains_init_hw(dev_priv
, true);
1800 intel_display_set_init_power(dev_priv
, true);
1802 i915_gem_sanitize(dev_priv
);
1804 enable_rpm_wakeref_asserts(dev_priv
);
1807 dev_priv
->suspended_to_idle
= false;
1812 static int i915_resume_switcheroo(struct drm_device
*dev
)
1816 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1819 ret
= i915_drm_resume_early(dev
);
1823 return i915_drm_resume(dev
);
1827 * i915_reset - reset chip after a hang
1828 * @i915: #drm_i915_private to reset
1829 * @flags: Instructions
1831 * Reset the chip. Useful if a hang is detected. Marks the device as wedged
1834 * Caller must hold the struct_mutex.
1836 * Procedure is fairly simple:
1837 * - reset the chip using the reset reg
1838 * - re-init context state
1839 * - re-init hardware status page
1840 * - re-init ring buffer
1841 * - re-init interrupt state
1844 void i915_reset(struct drm_i915_private
*i915
, unsigned int flags
)
1846 struct i915_gpu_error
*error
= &i915
->gpu_error
;
1849 lockdep_assert_held(&i915
->drm
.struct_mutex
);
1850 GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF
, &error
->flags
));
1852 if (!test_bit(I915_RESET_HANDOFF
, &error
->flags
))
1855 /* Clear any previous failed attempts at recovery. Time to try again. */
1856 if (!i915_gem_unset_wedged(i915
))
1859 if (!(flags
& I915_RESET_QUIET
))
1860 dev_notice(i915
->drm
.dev
, "Resetting chip after gpu hang\n");
1861 error
->reset_count
++;
1863 disable_irq(i915
->drm
.irq
);
1864 ret
= i915_gem_reset_prepare(i915
);
1866 DRM_ERROR("GPU recovery failed\n");
1867 intel_gpu_reset(i915
, ALL_ENGINES
);
1871 ret
= intel_gpu_reset(i915
, ALL_ENGINES
);
1874 DRM_ERROR("Failed to reset chip: %i\n", ret
);
1876 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1880 i915_gem_reset(i915
);
1881 intel_overlay_reset(i915
);
1883 /* Ok, now get things going again... */
1886 * Everything depends on having the GTT running, so we need to start
1889 ret
= i915_ggtt_enable_hw(i915
);
1891 DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret
);
1896 * Next we need to restore the context, but we don't use those
1899 * Ring buffer needs to be re-initialized in the KMS case, or if X
1900 * was running at the time of the reset (i.e. we weren't VT
1903 ret
= i915_gem_init_hw(i915
);
1905 DRM_ERROR("Failed hw init on reset %d\n", ret
);
1909 i915_queue_hangcheck(i915
);
1912 i915_gem_reset_finish(i915
);
1913 enable_irq(i915
->drm
.irq
);
1916 clear_bit(I915_RESET_HANDOFF
, &error
->flags
);
1917 wake_up_bit(&error
->flags
, I915_RESET_HANDOFF
);
1921 i915_gem_set_wedged(i915
);
1922 i915_gem_retire_requests(i915
);
1927 * i915_reset_engine - reset GPU engine to recover from a hang
1928 * @engine: engine to reset
1931 * Reset a specific GPU engine. Useful if a hang is detected.
1932 * Returns zero on successful reset or otherwise an error code.
1935 * - identifies the request that caused the hang and it is dropped
1936 * - reset engine (which will force the engine to idle)
1937 * - re-init/configure engine
1939 int i915_reset_engine(struct intel_engine_cs
*engine
, unsigned int flags
)
1941 struct i915_gpu_error
*error
= &engine
->i915
->gpu_error
;
1942 struct drm_i915_gem_request
*active_request
;
1945 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE
+ engine
->id
, &error
->flags
));
1947 if (!(flags
& I915_RESET_QUIET
)) {
1948 dev_notice(engine
->i915
->drm
.dev
,
1949 "Resetting %s after gpu hang\n", engine
->name
);
1951 error
->reset_engine_count
[engine
->id
]++;
1953 active_request
= i915_gem_reset_prepare_engine(engine
);
1954 if (IS_ERR(active_request
)) {
1955 DRM_DEBUG_DRIVER("Previous reset failed, promote to full reset\n");
1956 ret
= PTR_ERR(active_request
);
1960 ret
= intel_gpu_reset(engine
->i915
, intel_engine_flag(engine
));
1962 /* If we fail here, we expect to fallback to a global reset */
1963 DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n",
1969 * The request that caused the hang is stuck on elsp, we know the
1970 * active request and can drop it, adjust head to skip the offending
1971 * request to resume executing remaining requests in the queue.
1973 i915_gem_reset_engine(engine
, active_request
);
1976 * The engine and its registers (and workarounds in case of render)
1977 * have been reset to their default values. Follow the init_ring
1978 * process to program RING_MODE, HWSP and re-enable submission.
1980 ret
= engine
->init_hw(engine
);
1985 i915_gem_reset_finish_engine(engine
);
1989 static int i915_pm_suspend(struct device
*kdev
)
1991 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1992 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1995 dev_err(kdev
, "DRM not initialized, aborting suspend.\n");
1999 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2002 return i915_drm_suspend(dev
);
2005 static int i915_pm_suspend_late(struct device
*kdev
)
2007 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2010 * We have a suspend ordering issue with the snd-hda driver also
2011 * requiring our device to be power up. Due to the lack of a
2012 * parent/child relationship we currently solve this with an late
2015 * FIXME: This should be solved with a special hdmi sink device or
2016 * similar so that power domains can be employed.
2018 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2021 return i915_drm_suspend_late(dev
, false);
2024 static int i915_pm_poweroff_late(struct device
*kdev
)
2026 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2028 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2031 return i915_drm_suspend_late(dev
, true);
2034 static int i915_pm_resume_early(struct device
*kdev
)
2036 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2038 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2041 return i915_drm_resume_early(dev
);
2044 static int i915_pm_resume(struct device
*kdev
)
2046 struct drm_device
*dev
= &kdev_to_i915(kdev
)->drm
;
2048 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
2051 return i915_drm_resume(dev
);
2054 /* freeze: before creating the hibernation_image */
2055 static int i915_pm_freeze(struct device
*kdev
)
2059 ret
= i915_pm_suspend(kdev
);
2063 ret
= i915_gem_freeze(kdev_to_i915(kdev
));
2070 static int i915_pm_freeze_late(struct device
*kdev
)
2074 ret
= i915_pm_suspend_late(kdev
);
2078 ret
= i915_gem_freeze_late(kdev_to_i915(kdev
));
2085 /* thaw: called after creating the hibernation image, but before turning off. */
2086 static int i915_pm_thaw_early(struct device
*kdev
)
2088 return i915_pm_resume_early(kdev
);
2091 static int i915_pm_thaw(struct device
*kdev
)
2093 return i915_pm_resume(kdev
);
2096 /* restore: called after loading the hibernation image. */
2097 static int i915_pm_restore_early(struct device
*kdev
)
2099 return i915_pm_resume_early(kdev
);
2102 static int i915_pm_restore(struct device
*kdev
)
2104 return i915_pm_resume(kdev
);
2108 * Save all Gunit registers that may be lost after a D3 and a subsequent
2109 * S0i[R123] transition. The list of registers needing a save/restore is
2110 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2111 * registers in the following way:
2112 * - Driver: saved/restored by the driver
2113 * - Punit : saved/restored by the Punit firmware
2114 * - No, w/o marking: no need to save/restore, since the register is R/O or
2115 * used internally by the HW in a way that doesn't depend
2116 * keeping the content across a suspend/resume.
2117 * - Debug : used for debugging
2119 * We save/restore all registers marked with 'Driver', with the following
2121 * - Registers out of use, including also registers marked with 'Debug'.
2122 * These have no effect on the driver's operation, so we don't save/restore
2123 * them to reduce the overhead.
2124 * - Registers that are fully setup by an initialization function called from
2125 * the resume path. For example many clock gating and RPS/RC6 registers.
2126 * - Registers that provide the right functionality with their reset defaults.
2128 * TODO: Except for registers that based on the above 3 criteria can be safely
2129 * ignored, we save/restore all others, practically treating the HW context as
2130 * a black-box for the driver. Further investigation is needed to reduce the
2131 * saved/restored registers even further, by following the same 3 criteria.
2133 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2135 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2138 /* GAM 0x4000-0x4770 */
2139 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
2140 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
2141 s
->arb_mode
= I915_READ(ARB_MODE
);
2142 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
2143 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
2145 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2146 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
2148 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
2149 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
2151 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
2152 s
->ecochk
= I915_READ(GAM_ECOCHK
);
2153 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
2154 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
2156 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
2158 /* MBC 0x9024-0x91D0, 0x8500 */
2159 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
2160 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
2161 s
->mbctl
= I915_READ(GEN6_MBCTL
);
2163 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2164 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
2165 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
2166 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
2167 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
2168 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
2169 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
2171 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2172 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
2173 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
2174 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
2175 s
->ecobus
= I915_READ(ECOBUS
);
2176 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
2177 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
2178 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
2179 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
2180 s
->rcedata
= I915_READ(VLV_RCEDATA
);
2181 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
2183 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2184 s
->gt_imr
= I915_READ(GTIMR
);
2185 s
->gt_ier
= I915_READ(GTIER
);
2186 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
2187 s
->pm_ier
= I915_READ(GEN6_PMIER
);
2189 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2190 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
2192 /* GT SA CZ domain, 0x100000-0x138124 */
2193 s
->tilectl
= I915_READ(TILECTL
);
2194 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
2195 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2196 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2197 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
2199 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2200 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
2201 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
2202 s
->pcbr
= I915_READ(VLV_PCBR
);
2203 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
2206 * Not saving any of:
2207 * DFT, 0x9800-0x9EC0
2208 * SARB, 0xB000-0xB1FC
2209 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2214 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2216 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2220 /* GAM 0x4000-0x4770 */
2221 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
2222 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
2223 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
2224 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
2225 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
2227 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2228 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
2230 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
2231 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
2233 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
2234 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
2235 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
2236 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
2238 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
2240 /* MBC 0x9024-0x91D0, 0x8500 */
2241 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
2242 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
2243 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
2245 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2246 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
2247 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
2248 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
2249 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
2250 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
2251 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
2253 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2254 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
2255 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
2256 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
2257 I915_WRITE(ECOBUS
, s
->ecobus
);
2258 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
2259 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
2260 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
2261 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
2262 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
2263 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
2265 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2266 I915_WRITE(GTIMR
, s
->gt_imr
);
2267 I915_WRITE(GTIER
, s
->gt_ier
);
2268 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
2269 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
2271 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2272 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
2274 /* GT SA CZ domain, 0x100000-0x138124 */
2275 I915_WRITE(TILECTL
, s
->tilectl
);
2276 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
2278 * Preserve the GT allow wake and GFX force clock bit, they are not
2279 * be restored, as they are used to control the s0ix suspend/resume
2280 * sequence by the caller.
2282 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2283 val
&= VLV_GTLC_ALLOWWAKEREQ
;
2284 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
2285 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2287 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2288 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
2289 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
2290 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2292 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
2294 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2295 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
2296 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
2297 I915_WRITE(VLV_PCBR
, s
->pcbr
);
2298 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
2301 static int vlv_wait_for_pw_status(struct drm_i915_private
*dev_priv
,
2304 /* The HW does not like us polling for PW_STATUS frequently, so
2305 * use the sleeping loop rather than risk the busy spin within
2306 * intel_wait_for_register().
2308 * Transitioning between RC6 states should be at most 2ms (see
2309 * valleyview_enable_rps) so use a 3ms timeout.
2311 return wait_for((I915_READ_NOTRACE(VLV_GTLC_PW_STATUS
) & mask
) == val
,
2315 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
2320 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2321 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
2323 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
2324 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2329 err
= intel_wait_for_register(dev_priv
,
2330 VLV_GTLC_SURVIVABILITY_REG
,
2331 VLV_GFX_CLK_STATUS_BIT
,
2332 VLV_GFX_CLK_STATUS_BIT
,
2335 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2336 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
2341 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
2347 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2348 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
2350 val
|= VLV_GTLC_ALLOWWAKEREQ
;
2351 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2352 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
2354 mask
= VLV_GTLC_ALLOWWAKEACK
;
2355 val
= allow
? mask
: 0;
2357 err
= vlv_wait_for_pw_status(dev_priv
, mask
, val
);
2359 DRM_ERROR("timeout disabling GT waking\n");
2364 static void vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
2370 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
2371 val
= wait_for_on
? mask
: 0;
2374 * RC6 transitioning can be delayed up to 2 msec (see
2375 * valleyview_enable_rps), use 3 msec for safety.
2377 if (vlv_wait_for_pw_status(dev_priv
, mask
, val
))
2378 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2379 onoff(wait_for_on
));
2382 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
2384 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
2387 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2388 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
2391 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
2397 * Bspec defines the following GT well on flags as debug only, so
2398 * don't treat them as hard failures.
2400 vlv_wait_for_gt_wells(dev_priv
, false);
2402 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
2403 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
2405 vlv_check_no_gt_access(dev_priv
);
2407 err
= vlv_force_gfx_clock(dev_priv
, true);
2411 err
= vlv_allow_gt_wake(dev_priv
, false);
2415 if (!IS_CHERRYVIEW(dev_priv
))
2416 vlv_save_gunit_s0ix_state(dev_priv
);
2418 err
= vlv_force_gfx_clock(dev_priv
, false);
2425 /* For safety always re-enable waking and disable gfx clock forcing */
2426 vlv_allow_gt_wake(dev_priv
, true);
2428 vlv_force_gfx_clock(dev_priv
, false);
2433 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
2440 * If any of the steps fail just try to continue, that's the best we
2441 * can do at this point. Return the first error code (which will also
2442 * leave RPM permanently disabled).
2444 ret
= vlv_force_gfx_clock(dev_priv
, true);
2446 if (!IS_CHERRYVIEW(dev_priv
))
2447 vlv_restore_gunit_s0ix_state(dev_priv
);
2449 err
= vlv_allow_gt_wake(dev_priv
, true);
2453 err
= vlv_force_gfx_clock(dev_priv
, false);
2457 vlv_check_no_gt_access(dev_priv
);
2460 intel_init_clock_gating(dev_priv
);
2465 static int intel_runtime_suspend(struct device
*kdev
)
2467 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2468 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2469 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2472 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6())))
2475 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2478 DRM_DEBUG_KMS("Suspending device\n");
2480 disable_rpm_wakeref_asserts(dev_priv
);
2483 * We are safe here against re-faults, since the fault handler takes
2486 i915_gem_runtime_suspend(dev_priv
);
2488 intel_guc_suspend(dev_priv
);
2490 intel_runtime_pm_disable_interrupts(dev_priv
);
2493 if (IS_GEN9_LP(dev_priv
)) {
2494 bxt_display_core_uninit(dev_priv
);
2495 bxt_enable_dc9(dev_priv
);
2496 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2497 hsw_enable_pc8(dev_priv
);
2498 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2499 ret
= vlv_suspend_complete(dev_priv
);
2503 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
2504 intel_runtime_pm_enable_interrupts(dev_priv
);
2506 enable_rpm_wakeref_asserts(dev_priv
);
2511 intel_uncore_suspend(dev_priv
);
2513 enable_rpm_wakeref_asserts(dev_priv
);
2514 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2516 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv
))
2517 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2519 dev_priv
->pm
.suspended
= true;
2522 * FIXME: We really should find a document that references the arguments
2525 if (IS_BROADWELL(dev_priv
)) {
2527 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2528 * being detected, and the call we do at intel_runtime_resume()
2529 * won't be able to restore them. Since PCI_D3hot matches the
2530 * actual specification and appears to be working, use it.
2532 intel_opregion_notify_adapter(dev_priv
, PCI_D3hot
);
2535 * current versions of firmware which depend on this opregion
2536 * notification have repurposed the D1 definition to mean
2537 * "runtime suspended" vs. what you would normally expect (D3)
2538 * to distinguish it from notifications that might be sent via
2541 intel_opregion_notify_adapter(dev_priv
, PCI_D1
);
2544 assert_forcewakes_inactive(dev_priv
);
2546 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2547 intel_hpd_poll_init(dev_priv
);
2549 DRM_DEBUG_KMS("Device suspended\n");
2553 static int intel_runtime_resume(struct device
*kdev
)
2555 struct pci_dev
*pdev
= to_pci_dev(kdev
);
2556 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2557 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2560 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv
)))
2563 DRM_DEBUG_KMS("Resuming device\n");
2565 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2566 disable_rpm_wakeref_asserts(dev_priv
);
2568 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
2569 dev_priv
->pm
.suspended
= false;
2570 if (intel_uncore_unclaimed_mmio(dev_priv
))
2571 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2573 intel_guc_resume(dev_priv
);
2575 if (IS_GEN9_LP(dev_priv
)) {
2576 bxt_disable_dc9(dev_priv
);
2577 bxt_display_core_init(dev_priv
, true);
2578 if (dev_priv
->csr
.dmc_payload
&&
2579 (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC5
))
2580 gen9_enable_dc5(dev_priv
);
2581 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2582 hsw_disable_pc8(dev_priv
);
2583 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2584 ret
= vlv_resume_prepare(dev_priv
, true);
2587 intel_uncore_runtime_resume(dev_priv
);
2590 * No point of rolling back things in case of an error, as the best
2591 * we can do is to hope that things will still work (and disable RPM).
2593 i915_gem_init_swizzling(dev_priv
);
2594 i915_gem_restore_fences(dev_priv
);
2596 intel_runtime_pm_enable_interrupts(dev_priv
);
2599 * On VLV/CHV display interrupts are part of the display
2600 * power well, so hpd is reinitialized from there. For
2601 * everyone else do it here.
2603 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2604 intel_hpd_init(dev_priv
);
2606 enable_rpm_wakeref_asserts(dev_priv
);
2609 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
2611 DRM_DEBUG_KMS("Device resumed\n");
2616 const struct dev_pm_ops i915_pm_ops
= {
2618 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2621 .suspend
= i915_pm_suspend
,
2622 .suspend_late
= i915_pm_suspend_late
,
2623 .resume_early
= i915_pm_resume_early
,
2624 .resume
= i915_pm_resume
,
2628 * @freeze, @freeze_late : called (1) before creating the
2629 * hibernation image [PMSG_FREEZE] and
2630 * (2) after rebooting, before restoring
2631 * the image [PMSG_QUIESCE]
2632 * @thaw, @thaw_early : called (1) after creating the hibernation
2633 * image, before writing it [PMSG_THAW]
2634 * and (2) after failing to create or
2635 * restore the image [PMSG_RECOVER]
2636 * @poweroff, @poweroff_late: called after writing the hibernation
2637 * image, before rebooting [PMSG_HIBERNATE]
2638 * @restore, @restore_early : called after rebooting and restoring the
2639 * hibernation image [PMSG_RESTORE]
2641 .freeze
= i915_pm_freeze
,
2642 .freeze_late
= i915_pm_freeze_late
,
2643 .thaw_early
= i915_pm_thaw_early
,
2644 .thaw
= i915_pm_thaw
,
2645 .poweroff
= i915_pm_suspend
,
2646 .poweroff_late
= i915_pm_poweroff_late
,
2647 .restore_early
= i915_pm_restore_early
,
2648 .restore
= i915_pm_restore
,
2650 /* S0ix (via runtime suspend) event handlers */
2651 .runtime_suspend
= intel_runtime_suspend
,
2652 .runtime_resume
= intel_runtime_resume
,
2655 static const struct vm_operations_struct i915_gem_vm_ops
= {
2656 .fault
= i915_gem_fault
,
2657 .open
= drm_gem_vm_open
,
2658 .close
= drm_gem_vm_close
,
2661 static const struct file_operations i915_driver_fops
= {
2662 .owner
= THIS_MODULE
,
2664 .release
= drm_release
,
2665 .unlocked_ioctl
= drm_ioctl
,
2666 .mmap
= drm_gem_mmap
,
2669 .compat_ioctl
= i915_compat_ioctl
,
2670 .llseek
= noop_llseek
,
2674 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
2675 struct drm_file
*file
)
2680 static const struct drm_ioctl_desc i915_ioctls
[] = {
2681 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2682 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
2683 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
2684 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
2685 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
2686 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
2687 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2688 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2689 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
2690 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
2691 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2692 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
2693 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2694 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2695 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
2696 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
2697 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2698 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2699 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
),
2700 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2701 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2702 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2703 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2704 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_RENDER_ALLOW
),
2705 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_RENDER_ALLOW
),
2706 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2707 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2708 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2709 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_RENDER_ALLOW
),
2710 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_RENDER_ALLOW
),
2711 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_RENDER_ALLOW
),
2712 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_RENDER_ALLOW
),
2713 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_RENDER_ALLOW
),
2714 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_RENDER_ALLOW
),
2715 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_RENDER_ALLOW
),
2716 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling_ioctl
, DRM_RENDER_ALLOW
),
2717 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling_ioctl
, DRM_RENDER_ALLOW
),
2718 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_RENDER_ALLOW
),
2719 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, 0),
2720 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_RENDER_ALLOW
),
2721 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2722 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2723 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2724 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2725 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2726 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_RENDER_ALLOW
),
2727 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_RENDER_ALLOW
),
2728 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_RENDER_ALLOW
),
2729 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_gem_context_reset_stats_ioctl
, DRM_RENDER_ALLOW
),
2730 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_RENDER_ALLOW
),
2731 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_RENDER_ALLOW
),
2732 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_RENDER_ALLOW
),
2733 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN
, i915_perf_open_ioctl
, DRM_RENDER_ALLOW
),
2734 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG
, i915_perf_add_config_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
2735 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG
, i915_perf_remove_config_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
2738 static struct drm_driver driver
= {
2739 /* Don't use MTRRs here; the Xserver or userspace app should
2740 * deal with them for Intel hardware.
2743 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
2744 DRIVER_RENDER
| DRIVER_MODESET
| DRIVER_ATOMIC
| DRIVER_SYNCOBJ
,
2745 .release
= i915_driver_release
,
2746 .open
= i915_driver_open
,
2747 .lastclose
= i915_driver_lastclose
,
2748 .postclose
= i915_driver_postclose
,
2750 .gem_close_object
= i915_gem_close_object
,
2751 .gem_free_object_unlocked
= i915_gem_free_object
,
2752 .gem_vm_ops
= &i915_gem_vm_ops
,
2754 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
2755 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
2756 .gem_prime_export
= i915_gem_prime_export
,
2757 .gem_prime_import
= i915_gem_prime_import
,
2759 .dumb_create
= i915_gem_dumb_create
,
2760 .dumb_map_offset
= i915_gem_mmap_gtt
,
2761 .ioctls
= i915_ioctls
,
2762 .num_ioctls
= ARRAY_SIZE(i915_ioctls
),
2763 .fops
= &i915_driver_fops
,
2764 .name
= DRIVER_NAME
,
2765 .desc
= DRIVER_DESC
,
2766 .date
= DRIVER_DATE
,
2767 .major
= DRIVER_MAJOR
,
2768 .minor
= DRIVER_MINOR
,
2769 .patchlevel
= DRIVER_PATCHLEVEL
,
2772 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2773 #include "selftests/mock_drm.c"