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UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/device.h>
31 #include <drm/drmP.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
40
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
46
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
49
50 int i915_panel_ignore_lid __read_mostly = 0;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect [default], 1=lid open, "
54 "-1=lid closed)");
55
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
60
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
65
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
74
75 int i915_enable_fbc __read_mostly = -1;
76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
80
81 unsigned int i915_lvds_downclock __read_mostly = 0;
82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
86
87 int i915_lvds_channel_mode __read_mostly;
88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
93 int i915_panel_use_ssc __read_mostly = -1;
94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
98
99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
104
105 static bool i915_try_reset __read_mostly = true;
106 module_param_named(reset, i915_try_reset, bool, 0600);
107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
108
109 bool i915_enable_hangcheck __read_mostly = true;
110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
115
116 int i915_enable_ppgtt __read_mostly = -1;
117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
121 static struct drm_driver driver;
122 extern int intel_agp_enabled;
123
124 #define INTEL_VGA_DEVICE(id, info) { \
125 .class = PCI_BASE_CLASS_DISPLAY << 16, \
126 .class_mask = 0xff0000, \
127 .vendor = 0x8086, \
128 .device = id, \
129 .subvendor = PCI_ANY_ID, \
130 .subdevice = PCI_ANY_ID, \
131 .driver_data = (unsigned long) info }
132
133 static const struct intel_device_info intel_i830_info = {
134 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
135 .has_overlay = 1, .overlay_needs_physical = 1,
136 };
137
138 static const struct intel_device_info intel_845g_info = {
139 .gen = 2,
140 .has_overlay = 1, .overlay_needs_physical = 1,
141 };
142
143 static const struct intel_device_info intel_i85x_info = {
144 .gen = 2, .is_i85x = 1, .is_mobile = 1,
145 .cursor_needs_physical = 1,
146 .has_overlay = 1, .overlay_needs_physical = 1,
147 };
148
149 static const struct intel_device_info intel_i865g_info = {
150 .gen = 2,
151 .has_overlay = 1, .overlay_needs_physical = 1,
152 };
153
154 static const struct intel_device_info intel_i915g_info = {
155 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
156 .has_overlay = 1, .overlay_needs_physical = 1,
157 };
158 static const struct intel_device_info intel_i915gm_info = {
159 .gen = 3, .is_mobile = 1,
160 .cursor_needs_physical = 1,
161 .has_overlay = 1, .overlay_needs_physical = 1,
162 .supports_tv = 1,
163 };
164 static const struct intel_device_info intel_i945g_info = {
165 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
166 .has_overlay = 1, .overlay_needs_physical = 1,
167 };
168 static const struct intel_device_info intel_i945gm_info = {
169 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
170 .has_hotplug = 1, .cursor_needs_physical = 1,
171 .has_overlay = 1, .overlay_needs_physical = 1,
172 .supports_tv = 1,
173 };
174
175 static const struct intel_device_info intel_i965g_info = {
176 .gen = 4, .is_broadwater = 1,
177 .has_hotplug = 1,
178 .has_overlay = 1,
179 };
180
181 static const struct intel_device_info intel_i965gm_info = {
182 .gen = 4, .is_crestline = 1,
183 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
184 .has_overlay = 1,
185 .supports_tv = 1,
186 };
187
188 static const struct intel_device_info intel_g33_info = {
189 .gen = 3, .is_g33 = 1,
190 .need_gfx_hws = 1, .has_hotplug = 1,
191 .has_overlay = 1,
192 };
193
194 static const struct intel_device_info intel_g45_info = {
195 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
196 .has_pipe_cxsr = 1, .has_hotplug = 1,
197 .has_bsd_ring = 1,
198 };
199
200 static const struct intel_device_info intel_gm45_info = {
201 .gen = 4, .is_g4x = 1,
202 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
203 .has_pipe_cxsr = 1, .has_hotplug = 1,
204 .supports_tv = 1,
205 .has_bsd_ring = 1,
206 };
207
208 static const struct intel_device_info intel_pineview_info = {
209 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
210 .need_gfx_hws = 1, .has_hotplug = 1,
211 .has_overlay = 1,
212 };
213
214 static const struct intel_device_info intel_ironlake_d_info = {
215 .gen = 5,
216 .need_gfx_hws = 1, .has_hotplug = 1,
217 .has_bsd_ring = 1,
218 };
219
220 static const struct intel_device_info intel_ironlake_m_info = {
221 .gen = 5, .is_mobile = 1,
222 .need_gfx_hws = 1, .has_hotplug = 1,
223 .has_fbc = 1,
224 .has_bsd_ring = 1,
225 };
226
227 static const struct intel_device_info intel_sandybridge_d_info = {
228 .gen = 6,
229 .need_gfx_hws = 1, .has_hotplug = 1,
230 .has_bsd_ring = 1,
231 .has_blt_ring = 1,
232 .has_llc = 1,
233 .has_force_wake = 1,
234 };
235
236 static const struct intel_device_info intel_sandybridge_m_info = {
237 .gen = 6, .is_mobile = 1,
238 .need_gfx_hws = 1, .has_hotplug = 1,
239 .has_fbc = 1,
240 .has_bsd_ring = 1,
241 .has_blt_ring = 1,
242 .has_llc = 1,
243 .has_force_wake = 1,
244 };
245
246 static const struct intel_device_info intel_ivybridge_d_info = {
247 .is_ivybridge = 1, .gen = 7,
248 .need_gfx_hws = 1, .has_hotplug = 1,
249 .has_bsd_ring = 1,
250 .has_blt_ring = 1,
251 .has_llc = 1,
252 .has_force_wake = 1,
253 };
254
255 static const struct intel_device_info intel_ivybridge_m_info = {
256 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
257 .need_gfx_hws = 1, .has_hotplug = 1,
258 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
259 .has_bsd_ring = 1,
260 .has_blt_ring = 1,
261 .has_llc = 1,
262 .has_force_wake = 1,
263 };
264
265 static const struct intel_device_info intel_valleyview_m_info = {
266 .gen = 7, .is_mobile = 1,
267 .need_gfx_hws = 1, .has_hotplug = 1,
268 .has_fbc = 0,
269 .has_bsd_ring = 1,
270 .has_blt_ring = 1,
271 .is_valleyview = 1,
272 };
273
274 static const struct intel_device_info intel_valleyview_d_info = {
275 .gen = 7,
276 .need_gfx_hws = 1, .has_hotplug = 1,
277 .has_fbc = 0,
278 .has_bsd_ring = 1,
279 .has_blt_ring = 1,
280 .is_valleyview = 1,
281 };
282
283 static const struct intel_device_info intel_haswell_d_info = {
284 .is_haswell = 1, .gen = 7,
285 .need_gfx_hws = 1, .has_hotplug = 1,
286 .has_bsd_ring = 1,
287 .has_blt_ring = 1,
288 .has_llc = 1,
289 .has_force_wake = 1,
290 };
291
292 static const struct intel_device_info intel_haswell_m_info = {
293 .is_haswell = 1, .gen = 7, .is_mobile = 1,
294 .need_gfx_hws = 1, .has_hotplug = 1,
295 .has_bsd_ring = 1,
296 .has_blt_ring = 1,
297 .has_llc = 1,
298 .has_force_wake = 1,
299 };
300
301 static const struct pci_device_id pciidlist[] = { /* aka */
302 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
303 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
304 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
305 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
306 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
307 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
308 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
309 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
310 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
311 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
312 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
313 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
314 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
315 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
316 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
317 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
318 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
319 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
320 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
321 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
322 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
323 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
324 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
325 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
326 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
327 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
328 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
329 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
330 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
331 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
332 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
333 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
334 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
335 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
336 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
337 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
338 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
339 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
340 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
341 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
342 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
343 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
344 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
345 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
346 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
347 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
348 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
349 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
350 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
351 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
352 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
353 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
354 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
355 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
356 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
357 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
358 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
359 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
360 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
361 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
362 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
363 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
364 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
365 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
366 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
367 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
368 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
369 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
370 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
371 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
372 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
373 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
374 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
375 INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
376 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
377 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
378 INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
379 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
380 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
381 INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
382 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
383 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
384 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
385 {0, 0, 0}
386 };
387
388 #if defined(CONFIG_DRM_I915_KMS)
389 MODULE_DEVICE_TABLE(pci, pciidlist);
390 #endif
391
392 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
393 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
394 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
395 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
396 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
397
398 void intel_detect_pch(struct drm_device *dev)
399 {
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 struct pci_dev *pch;
402
403 /*
404 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
405 * make graphics device passthrough work easy for VMM, that only
406 * need to expose ISA bridge to let driver know the real hardware
407 * underneath. This is a requirement from virtualization team.
408 */
409 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
410 if (pch) {
411 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
412 int id;
413 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
414
415 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
416 dev_priv->pch_type = PCH_IBX;
417 dev_priv->num_pch_pll = 2;
418 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
419 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
420 dev_priv->pch_type = PCH_CPT;
421 dev_priv->num_pch_pll = 2;
422 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
423 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
424 /* PantherPoint is CPT compatible */
425 dev_priv->pch_type = PCH_CPT;
426 dev_priv->num_pch_pll = 2;
427 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
428 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
429 dev_priv->pch_type = PCH_LPT;
430 dev_priv->num_pch_pll = 0;
431 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
432 }
433 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
434 }
435 pci_dev_put(pch);
436 }
437 }
438
439 bool i915_semaphore_is_enabled(struct drm_device *dev)
440 {
441 if (INTEL_INFO(dev)->gen < 6)
442 return 0;
443
444 if (i915_semaphores >= 0)
445 return i915_semaphores;
446
447 #ifdef CONFIG_INTEL_IOMMU
448 /* Enable semaphores on SNB when IO remapping is off */
449 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
450 return false;
451 #endif
452
453 return 1;
454 }
455
456 static int i915_drm_freeze(struct drm_device *dev)
457 {
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 drm_kms_helper_poll_disable(dev);
461
462 pci_save_state(dev->pdev);
463
464 /* If KMS is active, we do the leavevt stuff here */
465 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
466 int error = i915_gem_idle(dev);
467 if (error) {
468 dev_err(&dev->pdev->dev,
469 "GEM idle failed, resume might fail\n");
470 return error;
471 }
472 drm_irq_uninstall(dev);
473 }
474
475 i915_save_state(dev);
476
477 intel_opregion_fini(dev);
478
479 /* Modeset on resume, not lid events */
480 dev_priv->modeset_on_lid = 0;
481
482 console_lock();
483 intel_fbdev_set_suspend(dev, 1);
484 console_unlock();
485
486 return 0;
487 }
488
489 int i915_suspend(struct drm_device *dev, pm_message_t state)
490 {
491 int error;
492
493 if (!dev || !dev->dev_private) {
494 DRM_ERROR("dev: %p\n", dev);
495 DRM_ERROR("DRM not initialized, aborting suspend.\n");
496 return -ENODEV;
497 }
498
499 if (state.event == PM_EVENT_PRETHAW)
500 return 0;
501
502
503 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
504 return 0;
505
506 error = i915_drm_freeze(dev);
507 if (error)
508 return error;
509
510 if (state.event == PM_EVENT_SUSPEND) {
511 /* Shut down the device */
512 pci_disable_device(dev->pdev);
513 pci_set_power_state(dev->pdev, PCI_D3hot);
514 }
515
516 return 0;
517 }
518
519 static int i915_drm_thaw(struct drm_device *dev)
520 {
521 struct drm_i915_private *dev_priv = dev->dev_private;
522 int error = 0;
523
524 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
525 mutex_lock(&dev->struct_mutex);
526 i915_gem_restore_gtt_mappings(dev);
527 mutex_unlock(&dev->struct_mutex);
528 }
529
530 i915_restore_state(dev);
531 intel_opregion_setup(dev);
532
533 /* KMS EnterVT equivalent */
534 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
535 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
536 ironlake_init_pch_refclk(dev);
537
538 mutex_lock(&dev->struct_mutex);
539 dev_priv->mm.suspended = 0;
540
541 error = i915_gem_init_hw(dev);
542 mutex_unlock(&dev->struct_mutex);
543
544 intel_modeset_init_hw(dev);
545 drm_mode_config_reset(dev);
546 drm_irq_install(dev);
547
548 /* Resume the modeset for every activated CRTC */
549 mutex_lock(&dev->mode_config.mutex);
550 drm_helper_resume_force_mode(dev);
551 mutex_unlock(&dev->mode_config.mutex);
552 }
553
554 intel_opregion_init(dev);
555
556 dev_priv->modeset_on_lid = 0;
557
558 console_lock();
559 intel_fbdev_set_suspend(dev, 0);
560 console_unlock();
561 return error;
562 }
563
564 int i915_resume(struct drm_device *dev)
565 {
566 int ret;
567
568 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
569 return 0;
570
571 if (pci_enable_device(dev->pdev))
572 return -EIO;
573
574 pci_set_master(dev->pdev);
575
576 ret = i915_drm_thaw(dev);
577 if (ret)
578 return ret;
579
580 drm_kms_helper_poll_enable(dev);
581 return 0;
582 }
583
584 static int i8xx_do_reset(struct drm_device *dev)
585 {
586 struct drm_i915_private *dev_priv = dev->dev_private;
587
588 if (IS_I85X(dev))
589 return -ENODEV;
590
591 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
592 POSTING_READ(D_STATE);
593
594 if (IS_I830(dev) || IS_845G(dev)) {
595 I915_WRITE(DEBUG_RESET_I830,
596 DEBUG_RESET_DISPLAY |
597 DEBUG_RESET_RENDER |
598 DEBUG_RESET_FULL);
599 POSTING_READ(DEBUG_RESET_I830);
600 msleep(1);
601
602 I915_WRITE(DEBUG_RESET_I830, 0);
603 POSTING_READ(DEBUG_RESET_I830);
604 }
605
606 msleep(1);
607
608 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
609 POSTING_READ(D_STATE);
610
611 return 0;
612 }
613
614 static int i965_reset_complete(struct drm_device *dev)
615 {
616 u8 gdrst;
617 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
618 return (gdrst & GRDOM_RESET_ENABLE) == 0;
619 }
620
621 static int i965_do_reset(struct drm_device *dev)
622 {
623 int ret;
624 u8 gdrst;
625
626 /*
627 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
628 * well as the reset bit (GR/bit 0). Setting the GR bit
629 * triggers the reset; when done, the hardware will clear it.
630 */
631 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
632 pci_write_config_byte(dev->pdev, I965_GDRST,
633 gdrst | GRDOM_RENDER |
634 GRDOM_RESET_ENABLE);
635 ret = wait_for(i965_reset_complete(dev), 500);
636 if (ret)
637 return ret;
638
639 /* We can't reset render&media without also resetting display ... */
640 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
641 pci_write_config_byte(dev->pdev, I965_GDRST,
642 gdrst | GRDOM_MEDIA |
643 GRDOM_RESET_ENABLE);
644
645 return wait_for(i965_reset_complete(dev), 500);
646 }
647
648 static int ironlake_do_reset(struct drm_device *dev)
649 {
650 struct drm_i915_private *dev_priv = dev->dev_private;
651 u32 gdrst;
652 int ret;
653
654 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
655 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
656 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
657 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
658 if (ret)
659 return ret;
660
661 /* We can't reset render&media without also resetting display ... */
662 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
663 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
664 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
665 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
666 }
667
668 static int gen6_do_reset(struct drm_device *dev)
669 {
670 struct drm_i915_private *dev_priv = dev->dev_private;
671 int ret;
672 unsigned long irqflags;
673
674 /* Hold gt_lock across reset to prevent any register access
675 * with forcewake not set correctly
676 */
677 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
678
679 /* Reset the chip */
680
681 /* GEN6_GDRST is not in the gt power well, no need to check
682 * for fifo space for the write or forcewake the chip for
683 * the read
684 */
685 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
686
687 /* Spin waiting for the device to ack the reset request */
688 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
689
690 /* If reset with a user forcewake, try to restore, otherwise turn it off */
691 if (dev_priv->forcewake_count)
692 dev_priv->gt.force_wake_get(dev_priv);
693 else
694 dev_priv->gt.force_wake_put(dev_priv);
695
696 /* Restore fifo count */
697 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
698
699 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
700 return ret;
701 }
702
703 int intel_gpu_reset(struct drm_device *dev)
704 {
705 struct drm_i915_private *dev_priv = dev->dev_private;
706 int ret = -ENODEV;
707
708 switch (INTEL_INFO(dev)->gen) {
709 case 7:
710 case 6:
711 ret = gen6_do_reset(dev);
712 break;
713 case 5:
714 ret = ironlake_do_reset(dev);
715 break;
716 case 4:
717 ret = i965_do_reset(dev);
718 break;
719 case 2:
720 ret = i8xx_do_reset(dev);
721 break;
722 }
723
724 /* Also reset the gpu hangman. */
725 if (dev_priv->stop_rings) {
726 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
727 dev_priv->stop_rings = 0;
728 if (ret == -ENODEV) {
729 DRM_ERROR("Reset not implemented, but ignoring "
730 "error for simulated gpu hangs\n");
731 ret = 0;
732 }
733 }
734
735 return ret;
736 }
737
738 /**
739 * i915_reset - reset chip after a hang
740 * @dev: drm device to reset
741 *
742 * Reset the chip. Useful if a hang is detected. Returns zero on successful
743 * reset or otherwise an error code.
744 *
745 * Procedure is fairly simple:
746 * - reset the chip using the reset reg
747 * - re-init context state
748 * - re-init hardware status page
749 * - re-init ring buffer
750 * - re-init interrupt state
751 * - re-init display
752 */
753 int i915_reset(struct drm_device *dev)
754 {
755 drm_i915_private_t *dev_priv = dev->dev_private;
756 int ret;
757
758 if (!i915_try_reset)
759 return 0;
760
761 mutex_lock(&dev->struct_mutex);
762
763 i915_gem_reset(dev);
764
765 ret = -ENODEV;
766 if (get_seconds() - dev_priv->last_gpu_reset < 5)
767 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
768 else
769 ret = intel_gpu_reset(dev);
770
771 dev_priv->last_gpu_reset = get_seconds();
772 if (ret) {
773 DRM_ERROR("Failed to reset chip.\n");
774 mutex_unlock(&dev->struct_mutex);
775 return ret;
776 }
777
778 /* Ok, now get things going again... */
779
780 /*
781 * Everything depends on having the GTT running, so we need to start
782 * there. Fortunately we don't need to do this unless we reset the
783 * chip at a PCI level.
784 *
785 * Next we need to restore the context, but we don't use those
786 * yet either...
787 *
788 * Ring buffer needs to be re-initialized in the KMS case, or if X
789 * was running at the time of the reset (i.e. we weren't VT
790 * switched away).
791 */
792 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
793 !dev_priv->mm.suspended) {
794 struct intel_ring_buffer *ring;
795 int i;
796
797 dev_priv->mm.suspended = 0;
798
799 i915_gem_init_swizzling(dev);
800
801 for_each_ring(ring, dev_priv, i)
802 ring->init(ring);
803
804 i915_gem_context_init(dev);
805 i915_gem_init_ppgtt(dev);
806
807 /*
808 * It would make sense to re-init all the other hw state, at
809 * least the rps/rc6/emon init done within modeset_init_hw. For
810 * some unknown reason, this blows up my ilk, so don't.
811 */
812
813 mutex_unlock(&dev->struct_mutex);
814
815 drm_irq_uninstall(dev);
816 drm_irq_install(dev);
817 } else {
818 mutex_unlock(&dev->struct_mutex);
819 }
820
821 return 0;
822 }
823
824 static int __devinit
825 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
826 {
827 struct intel_device_info *intel_info =
828 (struct intel_device_info *) ent->driver_data;
829
830 /* Only bind to function 0 of the device. Early generations
831 * used function 1 as a placeholder for multi-head. This causes
832 * us confusion instead, especially on the systems where both
833 * functions have the same PCI-ID!
834 */
835 if (PCI_FUNC(pdev->devfn))
836 return -ENODEV;
837
838 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
839 * implementation for gen3 (and only gen3) that used legacy drm maps
840 * (gasp!) to share buffers between X and the client. Hence we need to
841 * keep around the fake agp stuff for gen3, even when kms is enabled. */
842 if (intel_info->gen != 3) {
843 driver.driver_features &=
844 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
845 } else if (!intel_agp_enabled) {
846 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
847 return -ENODEV;
848 }
849
850 return drm_get_pci_dev(pdev, ent, &driver);
851 }
852
853 static void
854 i915_pci_remove(struct pci_dev *pdev)
855 {
856 struct drm_device *dev = pci_get_drvdata(pdev);
857
858 drm_put_dev(dev);
859 }
860
861 static int i915_pm_suspend(struct device *dev)
862 {
863 struct pci_dev *pdev = to_pci_dev(dev);
864 struct drm_device *drm_dev = pci_get_drvdata(pdev);
865 int error;
866
867 if (!drm_dev || !drm_dev->dev_private) {
868 dev_err(dev, "DRM not initialized, aborting suspend.\n");
869 return -ENODEV;
870 }
871
872 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
873 return 0;
874
875 error = i915_drm_freeze(drm_dev);
876 if (error)
877 return error;
878
879 pci_disable_device(pdev);
880 pci_set_power_state(pdev, PCI_D3hot);
881
882 return 0;
883 }
884
885 static int i915_pm_resume(struct device *dev)
886 {
887 struct pci_dev *pdev = to_pci_dev(dev);
888 struct drm_device *drm_dev = pci_get_drvdata(pdev);
889
890 return i915_resume(drm_dev);
891 }
892
893 static int i915_pm_freeze(struct device *dev)
894 {
895 struct pci_dev *pdev = to_pci_dev(dev);
896 struct drm_device *drm_dev = pci_get_drvdata(pdev);
897
898 if (!drm_dev || !drm_dev->dev_private) {
899 dev_err(dev, "DRM not initialized, aborting suspend.\n");
900 return -ENODEV;
901 }
902
903 return i915_drm_freeze(drm_dev);
904 }
905
906 static int i915_pm_thaw(struct device *dev)
907 {
908 struct pci_dev *pdev = to_pci_dev(dev);
909 struct drm_device *drm_dev = pci_get_drvdata(pdev);
910
911 return i915_drm_thaw(drm_dev);
912 }
913
914 static int i915_pm_poweroff(struct device *dev)
915 {
916 struct pci_dev *pdev = to_pci_dev(dev);
917 struct drm_device *drm_dev = pci_get_drvdata(pdev);
918
919 return i915_drm_freeze(drm_dev);
920 }
921
922 static const struct dev_pm_ops i915_pm_ops = {
923 .suspend = i915_pm_suspend,
924 .resume = i915_pm_resume,
925 .freeze = i915_pm_freeze,
926 .thaw = i915_pm_thaw,
927 .poweroff = i915_pm_poweroff,
928 .restore = i915_pm_resume,
929 };
930
931 static const struct vm_operations_struct i915_gem_vm_ops = {
932 .fault = i915_gem_fault,
933 .open = drm_gem_vm_open,
934 .close = drm_gem_vm_close,
935 };
936
937 static const struct file_operations i915_driver_fops = {
938 .owner = THIS_MODULE,
939 .open = drm_open,
940 .release = drm_release,
941 .unlocked_ioctl = drm_ioctl,
942 .mmap = drm_gem_mmap,
943 .poll = drm_poll,
944 .fasync = drm_fasync,
945 .read = drm_read,
946 #ifdef CONFIG_COMPAT
947 .compat_ioctl = i915_compat_ioctl,
948 #endif
949 .llseek = noop_llseek,
950 };
951
952 static struct drm_driver driver = {
953 /* Don't use MTRRs here; the Xserver or userspace app should
954 * deal with them for Intel hardware.
955 */
956 .driver_features =
957 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
958 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
959 .load = i915_driver_load,
960 .unload = i915_driver_unload,
961 .open = i915_driver_open,
962 .lastclose = i915_driver_lastclose,
963 .preclose = i915_driver_preclose,
964 .postclose = i915_driver_postclose,
965
966 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
967 .suspend = i915_suspend,
968 .resume = i915_resume,
969
970 .device_is_agp = i915_driver_device_is_agp,
971 .master_create = i915_master_create,
972 .master_destroy = i915_master_destroy,
973 #if defined(CONFIG_DEBUG_FS)
974 .debugfs_init = i915_debugfs_init,
975 .debugfs_cleanup = i915_debugfs_cleanup,
976 #endif
977 .gem_init_object = i915_gem_init_object,
978 .gem_free_object = i915_gem_free_object,
979 .gem_vm_ops = &i915_gem_vm_ops,
980
981 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
982 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
983 .gem_prime_export = i915_gem_prime_export,
984 .gem_prime_import = i915_gem_prime_import,
985
986 .dumb_create = i915_gem_dumb_create,
987 .dumb_map_offset = i915_gem_mmap_gtt,
988 .dumb_destroy = i915_gem_dumb_destroy,
989 .ioctls = i915_ioctls,
990 .fops = &i915_driver_fops,
991 .name = DRIVER_NAME,
992 .desc = DRIVER_DESC,
993 .date = DRIVER_DATE,
994 .major = DRIVER_MAJOR,
995 .minor = DRIVER_MINOR,
996 .patchlevel = DRIVER_PATCHLEVEL,
997 };
998
999 static struct pci_driver i915_pci_driver = {
1000 .name = DRIVER_NAME,
1001 .id_table = pciidlist,
1002 .probe = i915_pci_probe,
1003 .remove = i915_pci_remove,
1004 .driver.pm = &i915_pm_ops,
1005 };
1006
1007 static int __init i915_init(void)
1008 {
1009 driver.num_ioctls = i915_max_ioctl;
1010
1011 /*
1012 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1013 * explicitly disabled with the module pararmeter.
1014 *
1015 * Otherwise, just follow the parameter (defaulting to off).
1016 *
1017 * Allow optional vga_text_mode_force boot option to override
1018 * the default behavior.
1019 */
1020 #if defined(CONFIG_DRM_I915_KMS)
1021 if (i915_modeset != 0)
1022 driver.driver_features |= DRIVER_MODESET;
1023 #endif
1024 if (i915_modeset == 1)
1025 driver.driver_features |= DRIVER_MODESET;
1026
1027 #ifdef CONFIG_VGA_CONSOLE
1028 if (vgacon_text_force() && i915_modeset == -1)
1029 driver.driver_features &= ~DRIVER_MODESET;
1030 #endif
1031
1032 if (!(driver.driver_features & DRIVER_MODESET))
1033 driver.get_vblank_timestamp = NULL;
1034
1035 return drm_pci_init(&driver, &i915_pci_driver);
1036 }
1037
1038 static void __exit i915_exit(void)
1039 {
1040 drm_pci_exit(&driver, &i915_pci_driver);
1041 }
1042
1043 module_init(i915_init);
1044 module_exit(i915_exit);
1045
1046 MODULE_AUTHOR(DRIVER_AUTHOR);
1047 MODULE_DESCRIPTION(DRIVER_DESC);
1048 MODULE_LICENSE("GPL and additional rights");
1049
1050 /* We give fast paths for the really cool registers */
1051 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1052 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1053 ((reg) < 0x40000) && \
1054 ((reg) != FORCEWAKE))
1055
1056 static bool IS_DISPLAYREG(u32 reg)
1057 {
1058 /*
1059 * This should make it easier to transition modules over to the
1060 * new register block scheme, since we can do it incrementally.
1061 */
1062 if (reg >= 0x180000)
1063 return false;
1064
1065 if (reg >= RENDER_RING_BASE &&
1066 reg < RENDER_RING_BASE + 0xff)
1067 return false;
1068 if (reg >= GEN6_BSD_RING_BASE &&
1069 reg < GEN6_BSD_RING_BASE + 0xff)
1070 return false;
1071 if (reg >= BLT_RING_BASE &&
1072 reg < BLT_RING_BASE + 0xff)
1073 return false;
1074
1075 if (reg == PGTBL_ER)
1076 return false;
1077
1078 if (reg >= IPEIR_I965 &&
1079 reg < HWSTAM)
1080 return false;
1081
1082 if (reg == MI_MODE)
1083 return false;
1084
1085 if (reg == GFX_MODE_GEN7)
1086 return false;
1087
1088 if (reg == RENDER_HWS_PGA_GEN7 ||
1089 reg == BSD_HWS_PGA_GEN7 ||
1090 reg == BLT_HWS_PGA_GEN7)
1091 return false;
1092
1093 if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1094 reg == GEN6_BSD_RNCID)
1095 return false;
1096
1097 if (reg == GEN6_BLITTER_ECOSKPD)
1098 return false;
1099
1100 if (reg >= 0x4000c &&
1101 reg <= 0x4002c)
1102 return false;
1103
1104 if (reg >= 0x4f000 &&
1105 reg <= 0x4f08f)
1106 return false;
1107
1108 if (reg >= 0x4f100 &&
1109 reg <= 0x4f11f)
1110 return false;
1111
1112 if (reg >= VLV_MASTER_IER &&
1113 reg <= GEN6_PMIER)
1114 return false;
1115
1116 if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1117 reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1118 return false;
1119
1120 if (reg >= VLV_IIR_RW &&
1121 reg <= VLV_ISR)
1122 return false;
1123
1124 if (reg == FORCEWAKE_VLV ||
1125 reg == FORCEWAKE_ACK_VLV)
1126 return false;
1127
1128 if (reg == GEN6_GDRST)
1129 return false;
1130
1131 return true;
1132 }
1133
1134 #define __i915_read(x, y) \
1135 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1136 u##x val = 0; \
1137 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1138 unsigned long irqflags; \
1139 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1140 if (dev_priv->forcewake_count == 0) \
1141 dev_priv->gt.force_wake_get(dev_priv); \
1142 val = read##y(dev_priv->regs + reg); \
1143 if (dev_priv->forcewake_count == 0) \
1144 dev_priv->gt.force_wake_put(dev_priv); \
1145 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1146 } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1147 val = read##y(dev_priv->regs + reg + 0x180000); \
1148 } else { \
1149 val = read##y(dev_priv->regs + reg); \
1150 } \
1151 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1152 return val; \
1153 }
1154
1155 __i915_read(8, b)
1156 __i915_read(16, w)
1157 __i915_read(32, l)
1158 __i915_read(64, q)
1159 #undef __i915_read
1160
1161 #define __i915_write(x, y) \
1162 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1163 u32 __fifo_ret = 0; \
1164 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1165 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1166 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1167 } \
1168 if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1169 write##y(val, dev_priv->regs + reg + 0x180000); \
1170 } else { \
1171 write##y(val, dev_priv->regs + reg); \
1172 } \
1173 if (unlikely(__fifo_ret)) { \
1174 gen6_gt_check_fifodbg(dev_priv); \
1175 } \
1176 }
1177 __i915_write(8, b)
1178 __i915_write(16, w)
1179 __i915_write(32, l)
1180 __i915_write(64, q)
1181 #undef __i915_write
kernel source for telekom puls (alcatel/mediatek)